1//===--- Targets.cpp - Implement -arch option and targets -----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements construction of a TargetInfo object from a
11// target triple.
12//
13//===----------------------------------------------------------------------===//
14
15#include "clang/Basic/TargetInfo.h"
16#include "clang/Basic/Builtins.h"
17#include "clang/Basic/Diagnostic.h"
18#include "clang/Basic/LangOptions.h"
19#include "clang/Basic/MacroBuilder.h"
20#include "clang/Basic/TargetBuiltins.h"
21#include "clang/Basic/TargetOptions.h"
22#include "llvm/ADT/APFloat.h"
23#include "llvm/ADT/STLExtras.h"
24#include "llvm/ADT/StringExtras.h"
25#include "llvm/ADT/StringRef.h"
26#include "llvm/ADT/StringSwitch.h"
27#include "llvm/ADT/Triple.h"
28#include "llvm/IR/Type.h"
29#include "llvm/MC/MCSectionMachO.h"
30#include "llvm/Support/ErrorHandling.h"
31#include <algorithm>
32#include <memory>
33using namespace clang;
34
35//===----------------------------------------------------------------------===//
36// Common code shared among targets.
37//===----------------------------------------------------------------------===//
38
39/// DefineStd - Define a macro name and standard variants. For example if
40/// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
41/// when in GNU mode.
42static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
43 const LangOptions &Opts) {
44 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
45
46 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
47 // in the user's namespace.
48 if (Opts.GNUMode)
49 Builder.defineMacro(MacroName);
50
51 // Define __unix.
52 Builder.defineMacro("__" + MacroName);
53
54 // Define __unix__.
55 Builder.defineMacro("__" + MacroName + "__");
56}
57
58static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
59 bool Tuning = true) {
60 Builder.defineMacro("__" + CPUName);
61 Builder.defineMacro("__" + CPUName + "__");
62 if (Tuning)
63 Builder.defineMacro("__tune_" + CPUName + "__");
64}
65
66//===----------------------------------------------------------------------===//
67// Defines specific to certain operating systems.
68//===----------------------------------------------------------------------===//
69
70namespace {
71template<typename TgtInfo>
72class OSTargetInfo : public TgtInfo {
73protected:
74 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
75 MacroBuilder &Builder) const=0;
76public:
77 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
78 void getTargetDefines(const LangOptions &Opts,
79 MacroBuilder &Builder) const override {
80 TgtInfo::getTargetDefines(Opts, Builder);
81 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
82 }
83
84};
85} // end anonymous namespace
86
87
88static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
89 const llvm::Triple &Triple,
90 StringRef &PlatformName,
91 VersionTuple &PlatformMinVersion) {
92 Builder.defineMacro("__APPLE_CC__", "6000");
93 Builder.defineMacro("__APPLE__");
94 Builder.defineMacro("OBJC_NEW_PROPERTIES");
95 // AddressSanitizer doesn't play well with source fortification, which is on
96 // by default on Darwin.
97 if (Opts.Sanitize.has(SanitizerKind::Address))
98 Builder.defineMacro("_FORTIFY_SOURCE", "0");
99
100 if (!Opts.ObjCAutoRefCount) {
101 // __weak is always defined, for use in blocks and with objc pointers.
102 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
103
104 // Darwin defines __strong even in C mode (just to nothing).
105 if (Opts.getGC() != LangOptions::NonGC)
106 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
107 else
108 Builder.defineMacro("__strong", "");
109
110 // __unsafe_unretained is defined to nothing in non-ARC mode. We even
111 // allow this in C, since one might have block pointers in structs that
112 // are used in pure C code and in Objective-C ARC.
113 Builder.defineMacro("__unsafe_unretained", "");
114 }
115
116 if (Opts.Static)
117 Builder.defineMacro("__STATIC__");
118 else
119 Builder.defineMacro("__DYNAMIC__");
120
121 if (Opts.POSIXThreads)
122 Builder.defineMacro("_REENTRANT");
123
124 // Get the platform type and version number from the triple.
125 unsigned Maj, Min, Rev;
126 if (Triple.isMacOSX()) {
127 Triple.getMacOSXVersion(Maj, Min, Rev);
128 PlatformName = "macosx";
129 } else {
130 Triple.getOSVersion(Maj, Min, Rev);
131 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
132 }
133
134 // If -target arch-pc-win32-macho option specified, we're
135 // generating code for Win32 ABI. No need to emit
136 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
137 if (PlatformName == "win32") {
138 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
139 return;
140 }
141
142 // Set the appropriate OS version define.
143 if (Triple.isiOS()) {
144 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
145 char Str[6];
146 Str[0] = '0' + Maj;
147 Str[1] = '0' + (Min / 10);
148 Str[2] = '0' + (Min % 10);
149 Str[3] = '0' + (Rev / 10);
150 Str[4] = '0' + (Rev % 10);
151 Str[5] = '\0';
152 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
153 Str);
154 } else if (Triple.isMacOSX()) {
155 // Note that the Driver allows versions which aren't representable in the
156 // define (because we only get a single digit for the minor and micro
157 // revision numbers). So, we limit them to the maximum representable
158 // version.
159 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
160 char Str[7];
161 if (Maj < 10 || (Maj == 10 && Min < 10)) {
162 Str[0] = '0' + (Maj / 10);
163 Str[1] = '0' + (Maj % 10);
164 Str[2] = '0' + std::min(Min, 9U);
165 Str[3] = '0' + std::min(Rev, 9U);
166 Str[4] = '\0';
167 } else {
168 // Handle versions > 10.9.
169 Str[0] = '0' + (Maj / 10);
170 Str[1] = '0' + (Maj % 10);
171 Str[2] = '0' + (Min / 10);
172 Str[3] = '0' + (Min % 10);
173 Str[4] = '0' + (Rev / 10);
174 Str[5] = '0' + (Rev % 10);
175 Str[6] = '\0';
176 }
177 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
178 }
179
180 // Tell users about the kernel if there is one.
181 if (Triple.isOSDarwin())
182 Builder.defineMacro("__MACH__");
183
184 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
185}
186
187namespace {
188template<typename Target>
189class DarwinTargetInfo : public OSTargetInfo<Target> {
190protected:
191 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
192 MacroBuilder &Builder) const override {
193 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
194 this->PlatformMinVersion);
195 }
196
197public:
198 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
199 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
200 this->MCountName = "\01mcount";
201 }
202
203 std::string isValidSectionSpecifier(StringRef SR) const override {
204 // Let MCSectionMachO validate this.
205 StringRef Segment, Section;
206 unsigned TAA, StubSize;
207 bool HasTAA;
208 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
209 TAA, HasTAA, StubSize);
210 }
211
212 const char *getStaticInitSectionSpecifier() const override {
213 // FIXME: We should return 0 when building kexts.
214 return "__TEXT,__StaticInit,regular,pure_instructions";
215 }
216
217 /// Darwin does not support protected visibility. Darwin's "default"
218 /// is very similar to ELF's "protected"; Darwin requires a "weak"
219 /// attribute on declarations that can be dynamically replaced.
220 bool hasProtectedVisibility() const override {
221 return false;
222 }
223};
224
225
226// DragonFlyBSD Target
227template<typename Target>
228class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
229protected:
230 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
231 MacroBuilder &Builder) const override {
232 // DragonFly defines; list based off of gcc output
233 Builder.defineMacro("__DragonFly__");
234 Builder.defineMacro("__DragonFly_cc_version", "100001");
235 Builder.defineMacro("__ELF__");
236 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
237 Builder.defineMacro("__tune_i386__");
238 DefineStd(Builder, "unix", Opts);
239 }
240public:
241 DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
242 : OSTargetInfo<Target>(Triple) {
243 this->UserLabelPrefix = "";
244
245 switch (Triple.getArch()) {
246 default:
247 case llvm::Triple::x86:
248 case llvm::Triple::x86_64:
249 this->MCountName = ".mcount";
250 break;
251 }
252 }
253};
254
255// FreeBSD Target
256template<typename Target>
257class FreeBSDTargetInfo : public OSTargetInfo<Target> {
258protected:
259 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
260 MacroBuilder &Builder) const override {
261 // FreeBSD defines; list based off of gcc output
262
263 unsigned Release = Triple.getOSMajorVersion();
264 if (Release == 0U)
265 Release = 8;
266
267 Builder.defineMacro("__FreeBSD__", Twine(Release));
268 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
269 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
270 DefineStd(Builder, "unix", Opts);
271 Builder.defineMacro("__ELF__");
272
273 // On FreeBSD, wchar_t contains the number of the code point as
274 // used by the character set of the locale. These character sets are
275 // not necessarily a superset of ASCII.
276 //
277 // FIXME: This is wrong; the macro refers to the numerical values
278 // of wchar_t *literals*, which are not locale-dependent. However,
279 // FreeBSD systems apparently depend on us getting this wrong, and
280 // setting this to 1 is conforming even if all the basic source
281 // character literals have the same encoding as char and wchar_t.
282 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
283 }
284public:
285 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
286 this->UserLabelPrefix = "";
287
288 switch (Triple.getArch()) {
289 default:
290 case llvm::Triple::x86:
291 case llvm::Triple::x86_64:
292 this->MCountName = ".mcount";
293 break;
294 case llvm::Triple::mips:
295 case llvm::Triple::mipsel:
296 case llvm::Triple::ppc:
297 case llvm::Triple::ppc64:
298 case llvm::Triple::ppc64le:
299 this->MCountName = "_mcount";
300 break;
301 case llvm::Triple::arm:
302 this->MCountName = "__mcount";
303 break;
304 }
305 }
306};
307
308// GNU/kFreeBSD Target
309template<typename Target>
310class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
311protected:
312 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
313 MacroBuilder &Builder) const override {
314 // GNU/kFreeBSD defines; list based off of gcc output
315
316 DefineStd(Builder, "unix", Opts);
317 Builder.defineMacro("__FreeBSD_kernel__");
318 Builder.defineMacro("__GLIBC__");
319 Builder.defineMacro("__ELF__");
320 if (Opts.POSIXThreads)
321 Builder.defineMacro("_REENTRANT");
322 if (Opts.CPlusPlus)
323 Builder.defineMacro("_GNU_SOURCE");
324 }
325public:
326 KFreeBSDTargetInfo(const llvm::Triple &Triple)
327 : OSTargetInfo<Target>(Triple) {
328 this->UserLabelPrefix = "";
329 }
330};
331
332// Minix Target
333template<typename Target>
334class MinixTargetInfo : public OSTargetInfo<Target> {
335protected:
336 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
337 MacroBuilder &Builder) const override {
338 // Minix defines
339
340 Builder.defineMacro("__minix", "3");
341 Builder.defineMacro("_EM_WSIZE", "4");
342 Builder.defineMacro("_EM_PSIZE", "4");
343 Builder.defineMacro("_EM_SSIZE", "2");
344 Builder.defineMacro("_EM_LSIZE", "4");
345 Builder.defineMacro("_EM_FSIZE", "4");
346 Builder.defineMacro("_EM_DSIZE", "8");
347 Builder.defineMacro("__ELF__");
348 DefineStd(Builder, "unix", Opts);
349 }
350public:
351 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
352 this->UserLabelPrefix = "";
353 }
354};
355
356// Linux target
357template<typename Target>
358class LinuxTargetInfo : public OSTargetInfo<Target> {
359protected:
360 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
361 MacroBuilder &Builder) const override {
362 // Linux defines; list based off of gcc output
363 DefineStd(Builder, "unix", Opts);
364 DefineStd(Builder, "linux", Opts);
365 Builder.defineMacro("__gnu_linux__");
366 Builder.defineMacro("__ELF__");
367 if (Triple.getEnvironment() == llvm::Triple::Android)
368 Builder.defineMacro("__ANDROID__", "1");
369 if (Opts.POSIXThreads)
370 Builder.defineMacro("_REENTRANT");
371 if (Opts.CPlusPlus)
372 Builder.defineMacro("_GNU_SOURCE");
373 }
374public:
375 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
376 this->UserLabelPrefix = "";
377 this->WIntType = TargetInfo::UnsignedInt;
378
379 switch (Triple.getArch()) {
380 default:
381 break;
382 case llvm::Triple::ppc:
383 case llvm::Triple::ppc64:
384 case llvm::Triple::ppc64le:
385 this->MCountName = "_mcount";
386 break;
387 }
388 }
389
390 const char *getStaticInitSectionSpecifier() const override {
391 return ".text.startup";
392 }
393};
394
395// NetBSD Target
396template<typename Target>
397class NetBSDTargetInfo : public OSTargetInfo<Target> {
398protected:
399 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
400 MacroBuilder &Builder) const override {
401 // NetBSD defines; list based off of gcc output
402 Builder.defineMacro("__NetBSD__");
403 Builder.defineMacro("__unix__");
404 Builder.defineMacro("__ELF__");
405 if (Opts.POSIXThreads)
406 Builder.defineMacro("_POSIX_THREADS");
407
408 switch (Triple.getArch()) {
409 default:
410 break;
411 case llvm::Triple::arm:
412 case llvm::Triple::armeb:
413 case llvm::Triple::thumb:
414 case llvm::Triple::thumbeb:
415 Builder.defineMacro("__ARM_DWARF_EH__");
416 break;
417 }
418 }
419public:
420 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
421 this->UserLabelPrefix = "";
| 1//===--- Targets.cpp - Implement -arch option and targets -----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements construction of a TargetInfo object from a
11// target triple.
12//
13//===----------------------------------------------------------------------===//
14
15#include "clang/Basic/TargetInfo.h"
16#include "clang/Basic/Builtins.h"
17#include "clang/Basic/Diagnostic.h"
18#include "clang/Basic/LangOptions.h"
19#include "clang/Basic/MacroBuilder.h"
20#include "clang/Basic/TargetBuiltins.h"
21#include "clang/Basic/TargetOptions.h"
22#include "llvm/ADT/APFloat.h"
23#include "llvm/ADT/STLExtras.h"
24#include "llvm/ADT/StringExtras.h"
25#include "llvm/ADT/StringRef.h"
26#include "llvm/ADT/StringSwitch.h"
27#include "llvm/ADT/Triple.h"
28#include "llvm/IR/Type.h"
29#include "llvm/MC/MCSectionMachO.h"
30#include "llvm/Support/ErrorHandling.h"
31#include <algorithm>
32#include <memory>
33using namespace clang;
34
35//===----------------------------------------------------------------------===//
36// Common code shared among targets.
37//===----------------------------------------------------------------------===//
38
39/// DefineStd - Define a macro name and standard variants. For example if
40/// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
41/// when in GNU mode.
42static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
43 const LangOptions &Opts) {
44 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
45
46 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
47 // in the user's namespace.
48 if (Opts.GNUMode)
49 Builder.defineMacro(MacroName);
50
51 // Define __unix.
52 Builder.defineMacro("__" + MacroName);
53
54 // Define __unix__.
55 Builder.defineMacro("__" + MacroName + "__");
56}
57
58static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
59 bool Tuning = true) {
60 Builder.defineMacro("__" + CPUName);
61 Builder.defineMacro("__" + CPUName + "__");
62 if (Tuning)
63 Builder.defineMacro("__tune_" + CPUName + "__");
64}
65
66//===----------------------------------------------------------------------===//
67// Defines specific to certain operating systems.
68//===----------------------------------------------------------------------===//
69
70namespace {
71template<typename TgtInfo>
72class OSTargetInfo : public TgtInfo {
73protected:
74 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
75 MacroBuilder &Builder) const=0;
76public:
77 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
78 void getTargetDefines(const LangOptions &Opts,
79 MacroBuilder &Builder) const override {
80 TgtInfo::getTargetDefines(Opts, Builder);
81 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
82 }
83
84};
85} // end anonymous namespace
86
87
88static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
89 const llvm::Triple &Triple,
90 StringRef &PlatformName,
91 VersionTuple &PlatformMinVersion) {
92 Builder.defineMacro("__APPLE_CC__", "6000");
93 Builder.defineMacro("__APPLE__");
94 Builder.defineMacro("OBJC_NEW_PROPERTIES");
95 // AddressSanitizer doesn't play well with source fortification, which is on
96 // by default on Darwin.
97 if (Opts.Sanitize.has(SanitizerKind::Address))
98 Builder.defineMacro("_FORTIFY_SOURCE", "0");
99
100 if (!Opts.ObjCAutoRefCount) {
101 // __weak is always defined, for use in blocks and with objc pointers.
102 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
103
104 // Darwin defines __strong even in C mode (just to nothing).
105 if (Opts.getGC() != LangOptions::NonGC)
106 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
107 else
108 Builder.defineMacro("__strong", "");
109
110 // __unsafe_unretained is defined to nothing in non-ARC mode. We even
111 // allow this in C, since one might have block pointers in structs that
112 // are used in pure C code and in Objective-C ARC.
113 Builder.defineMacro("__unsafe_unretained", "");
114 }
115
116 if (Opts.Static)
117 Builder.defineMacro("__STATIC__");
118 else
119 Builder.defineMacro("__DYNAMIC__");
120
121 if (Opts.POSIXThreads)
122 Builder.defineMacro("_REENTRANT");
123
124 // Get the platform type and version number from the triple.
125 unsigned Maj, Min, Rev;
126 if (Triple.isMacOSX()) {
127 Triple.getMacOSXVersion(Maj, Min, Rev);
128 PlatformName = "macosx";
129 } else {
130 Triple.getOSVersion(Maj, Min, Rev);
131 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
132 }
133
134 // If -target arch-pc-win32-macho option specified, we're
135 // generating code for Win32 ABI. No need to emit
136 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
137 if (PlatformName == "win32") {
138 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
139 return;
140 }
141
142 // Set the appropriate OS version define.
143 if (Triple.isiOS()) {
144 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
145 char Str[6];
146 Str[0] = '0' + Maj;
147 Str[1] = '0' + (Min / 10);
148 Str[2] = '0' + (Min % 10);
149 Str[3] = '0' + (Rev / 10);
150 Str[4] = '0' + (Rev % 10);
151 Str[5] = '\0';
152 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
153 Str);
154 } else if (Triple.isMacOSX()) {
155 // Note that the Driver allows versions which aren't representable in the
156 // define (because we only get a single digit for the minor and micro
157 // revision numbers). So, we limit them to the maximum representable
158 // version.
159 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
160 char Str[7];
161 if (Maj < 10 || (Maj == 10 && Min < 10)) {
162 Str[0] = '0' + (Maj / 10);
163 Str[1] = '0' + (Maj % 10);
164 Str[2] = '0' + std::min(Min, 9U);
165 Str[3] = '0' + std::min(Rev, 9U);
166 Str[4] = '\0';
167 } else {
168 // Handle versions > 10.9.
169 Str[0] = '0' + (Maj / 10);
170 Str[1] = '0' + (Maj % 10);
171 Str[2] = '0' + (Min / 10);
172 Str[3] = '0' + (Min % 10);
173 Str[4] = '0' + (Rev / 10);
174 Str[5] = '0' + (Rev % 10);
175 Str[6] = '\0';
176 }
177 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
178 }
179
180 // Tell users about the kernel if there is one.
181 if (Triple.isOSDarwin())
182 Builder.defineMacro("__MACH__");
183
184 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
185}
186
187namespace {
188template<typename Target>
189class DarwinTargetInfo : public OSTargetInfo<Target> {
190protected:
191 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
192 MacroBuilder &Builder) const override {
193 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
194 this->PlatformMinVersion);
195 }
196
197public:
198 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
199 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
200 this->MCountName = "\01mcount";
201 }
202
203 std::string isValidSectionSpecifier(StringRef SR) const override {
204 // Let MCSectionMachO validate this.
205 StringRef Segment, Section;
206 unsigned TAA, StubSize;
207 bool HasTAA;
208 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
209 TAA, HasTAA, StubSize);
210 }
211
212 const char *getStaticInitSectionSpecifier() const override {
213 // FIXME: We should return 0 when building kexts.
214 return "__TEXT,__StaticInit,regular,pure_instructions";
215 }
216
217 /// Darwin does not support protected visibility. Darwin's "default"
218 /// is very similar to ELF's "protected"; Darwin requires a "weak"
219 /// attribute on declarations that can be dynamically replaced.
220 bool hasProtectedVisibility() const override {
221 return false;
222 }
223};
224
225
226// DragonFlyBSD Target
227template<typename Target>
228class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
229protected:
230 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
231 MacroBuilder &Builder) const override {
232 // DragonFly defines; list based off of gcc output
233 Builder.defineMacro("__DragonFly__");
234 Builder.defineMacro("__DragonFly_cc_version", "100001");
235 Builder.defineMacro("__ELF__");
236 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
237 Builder.defineMacro("__tune_i386__");
238 DefineStd(Builder, "unix", Opts);
239 }
240public:
241 DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
242 : OSTargetInfo<Target>(Triple) {
243 this->UserLabelPrefix = "";
244
245 switch (Triple.getArch()) {
246 default:
247 case llvm::Triple::x86:
248 case llvm::Triple::x86_64:
249 this->MCountName = ".mcount";
250 break;
251 }
252 }
253};
254
255// FreeBSD Target
256template<typename Target>
257class FreeBSDTargetInfo : public OSTargetInfo<Target> {
258protected:
259 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
260 MacroBuilder &Builder) const override {
261 // FreeBSD defines; list based off of gcc output
262
263 unsigned Release = Triple.getOSMajorVersion();
264 if (Release == 0U)
265 Release = 8;
266
267 Builder.defineMacro("__FreeBSD__", Twine(Release));
268 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
269 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
270 DefineStd(Builder, "unix", Opts);
271 Builder.defineMacro("__ELF__");
272
273 // On FreeBSD, wchar_t contains the number of the code point as
274 // used by the character set of the locale. These character sets are
275 // not necessarily a superset of ASCII.
276 //
277 // FIXME: This is wrong; the macro refers to the numerical values
278 // of wchar_t *literals*, which are not locale-dependent. However,
279 // FreeBSD systems apparently depend on us getting this wrong, and
280 // setting this to 1 is conforming even if all the basic source
281 // character literals have the same encoding as char and wchar_t.
282 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
283 }
284public:
285 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
286 this->UserLabelPrefix = "";
287
288 switch (Triple.getArch()) {
289 default:
290 case llvm::Triple::x86:
291 case llvm::Triple::x86_64:
292 this->MCountName = ".mcount";
293 break;
294 case llvm::Triple::mips:
295 case llvm::Triple::mipsel:
296 case llvm::Triple::ppc:
297 case llvm::Triple::ppc64:
298 case llvm::Triple::ppc64le:
299 this->MCountName = "_mcount";
300 break;
301 case llvm::Triple::arm:
302 this->MCountName = "__mcount";
303 break;
304 }
305 }
306};
307
308// GNU/kFreeBSD Target
309template<typename Target>
310class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
311protected:
312 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
313 MacroBuilder &Builder) const override {
314 // GNU/kFreeBSD defines; list based off of gcc output
315
316 DefineStd(Builder, "unix", Opts);
317 Builder.defineMacro("__FreeBSD_kernel__");
318 Builder.defineMacro("__GLIBC__");
319 Builder.defineMacro("__ELF__");
320 if (Opts.POSIXThreads)
321 Builder.defineMacro("_REENTRANT");
322 if (Opts.CPlusPlus)
323 Builder.defineMacro("_GNU_SOURCE");
324 }
325public:
326 KFreeBSDTargetInfo(const llvm::Triple &Triple)
327 : OSTargetInfo<Target>(Triple) {
328 this->UserLabelPrefix = "";
329 }
330};
331
332// Minix Target
333template<typename Target>
334class MinixTargetInfo : public OSTargetInfo<Target> {
335protected:
336 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
337 MacroBuilder &Builder) const override {
338 // Minix defines
339
340 Builder.defineMacro("__minix", "3");
341 Builder.defineMacro("_EM_WSIZE", "4");
342 Builder.defineMacro("_EM_PSIZE", "4");
343 Builder.defineMacro("_EM_SSIZE", "2");
344 Builder.defineMacro("_EM_LSIZE", "4");
345 Builder.defineMacro("_EM_FSIZE", "4");
346 Builder.defineMacro("_EM_DSIZE", "8");
347 Builder.defineMacro("__ELF__");
348 DefineStd(Builder, "unix", Opts);
349 }
350public:
351 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
352 this->UserLabelPrefix = "";
353 }
354};
355
356// Linux target
357template<typename Target>
358class LinuxTargetInfo : public OSTargetInfo<Target> {
359protected:
360 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
361 MacroBuilder &Builder) const override {
362 // Linux defines; list based off of gcc output
363 DefineStd(Builder, "unix", Opts);
364 DefineStd(Builder, "linux", Opts);
365 Builder.defineMacro("__gnu_linux__");
366 Builder.defineMacro("__ELF__");
367 if (Triple.getEnvironment() == llvm::Triple::Android)
368 Builder.defineMacro("__ANDROID__", "1");
369 if (Opts.POSIXThreads)
370 Builder.defineMacro("_REENTRANT");
371 if (Opts.CPlusPlus)
372 Builder.defineMacro("_GNU_SOURCE");
373 }
374public:
375 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
376 this->UserLabelPrefix = "";
377 this->WIntType = TargetInfo::UnsignedInt;
378
379 switch (Triple.getArch()) {
380 default:
381 break;
382 case llvm::Triple::ppc:
383 case llvm::Triple::ppc64:
384 case llvm::Triple::ppc64le:
385 this->MCountName = "_mcount";
386 break;
387 }
388 }
389
390 const char *getStaticInitSectionSpecifier() const override {
391 return ".text.startup";
392 }
393};
394
395// NetBSD Target
396template<typename Target>
397class NetBSDTargetInfo : public OSTargetInfo<Target> {
398protected:
399 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
400 MacroBuilder &Builder) const override {
401 // NetBSD defines; list based off of gcc output
402 Builder.defineMacro("__NetBSD__");
403 Builder.defineMacro("__unix__");
404 Builder.defineMacro("__ELF__");
405 if (Opts.POSIXThreads)
406 Builder.defineMacro("_POSIX_THREADS");
407
408 switch (Triple.getArch()) {
409 default:
410 break;
411 case llvm::Triple::arm:
412 case llvm::Triple::armeb:
413 case llvm::Triple::thumb:
414 case llvm::Triple::thumbeb:
415 Builder.defineMacro("__ARM_DWARF_EH__");
416 break;
417 }
418 }
419public:
420 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
421 this->UserLabelPrefix = "";
|
| 422 this->MCountName = "_mcount";
|
422 }
423};
424
425// OpenBSD Target
426template<typename Target>
427class OpenBSDTargetInfo : public OSTargetInfo<Target> {
428protected:
429 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
430 MacroBuilder &Builder) const override {
431 // OpenBSD defines; list based off of gcc output
432
433 Builder.defineMacro("__OpenBSD__");
434 DefineStd(Builder, "unix", Opts);
435 Builder.defineMacro("__ELF__");
436 if (Opts.POSIXThreads)
437 Builder.defineMacro("_REENTRANT");
438 }
439public:
440 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
441 this->UserLabelPrefix = "";
442 this->TLSSupported = false;
443
444 switch (Triple.getArch()) {
445 default:
446 case llvm::Triple::x86:
447 case llvm::Triple::x86_64:
448 case llvm::Triple::arm:
449 case llvm::Triple::sparc:
450 this->MCountName = "__mcount";
451 break;
452 case llvm::Triple::mips64:
453 case llvm::Triple::mips64el:
454 case llvm::Triple::ppc:
455 case llvm::Triple::sparcv9:
456 this->MCountName = "_mcount";
457 break;
458 }
459 }
460};
461
462// Bitrig Target
463template<typename Target>
464class BitrigTargetInfo : public OSTargetInfo<Target> {
465protected:
466 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
467 MacroBuilder &Builder) const override {
468 // Bitrig defines; list based off of gcc output
469
470 Builder.defineMacro("__Bitrig__");
471 DefineStd(Builder, "unix", Opts);
472 Builder.defineMacro("__ELF__");
473 if (Opts.POSIXThreads)
474 Builder.defineMacro("_REENTRANT");
475 }
476public:
477 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
478 this->UserLabelPrefix = "";
479 this->MCountName = "__mcount";
480 }
481};
482
483// PSP Target
484template<typename Target>
485class PSPTargetInfo : public OSTargetInfo<Target> {
486protected:
487 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
488 MacroBuilder &Builder) const override {
489 // PSP defines; list based on the output of the pspdev gcc toolchain.
490 Builder.defineMacro("PSP");
491 Builder.defineMacro("_PSP");
492 Builder.defineMacro("__psp__");
493 Builder.defineMacro("__ELF__");
494 }
495public:
496 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
497 this->UserLabelPrefix = "";
498 }
499};
500
501// PS3 PPU Target
502template<typename Target>
503class PS3PPUTargetInfo : public OSTargetInfo<Target> {
504protected:
505 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
506 MacroBuilder &Builder) const override {
507 // PS3 PPU defines.
508 Builder.defineMacro("__PPC__");
509 Builder.defineMacro("__PPU__");
510 Builder.defineMacro("__CELLOS_LV2__");
511 Builder.defineMacro("__ELF__");
512 Builder.defineMacro("__LP32__");
513 Builder.defineMacro("_ARCH_PPC64");
514 Builder.defineMacro("__powerpc64__");
515 }
516public:
517 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
518 this->UserLabelPrefix = "";
519 this->LongWidth = this->LongAlign = 32;
520 this->PointerWidth = this->PointerAlign = 32;
521 this->IntMaxType = TargetInfo::SignedLongLong;
522 this->Int64Type = TargetInfo::SignedLongLong;
523 this->SizeType = TargetInfo::UnsignedInt;
524 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64";
525 }
526};
527
528// Solaris target
529template<typename Target>
530class SolarisTargetInfo : public OSTargetInfo<Target> {
531protected:
532 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
533 MacroBuilder &Builder) const override {
534 DefineStd(Builder, "sun", Opts);
535 DefineStd(Builder, "unix", Opts);
536 Builder.defineMacro("__ELF__");
537 Builder.defineMacro("__svr4__");
538 Builder.defineMacro("__SVR4");
539 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
540 // newer, but to 500 for everything else. feature_test.h has a check to
541 // ensure that you are not using C99 with an old version of X/Open or C89
542 // with a new version.
543 if (Opts.C99)
544 Builder.defineMacro("_XOPEN_SOURCE", "600");
545 else
546 Builder.defineMacro("_XOPEN_SOURCE", "500");
547 if (Opts.CPlusPlus)
548 Builder.defineMacro("__C99FEATURES__");
549 Builder.defineMacro("_LARGEFILE_SOURCE");
550 Builder.defineMacro("_LARGEFILE64_SOURCE");
551 Builder.defineMacro("__EXTENSIONS__");
552 Builder.defineMacro("_REENTRANT");
553 }
554public:
555 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
556 this->UserLabelPrefix = "";
557 this->WCharType = this->SignedInt;
558 // FIXME: WIntType should be SignedLong
559 }
560};
561
562// Windows target
563template<typename Target>
564class WindowsTargetInfo : public OSTargetInfo<Target> {
565protected:
566 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
567 MacroBuilder &Builder) const override {
568 Builder.defineMacro("_WIN32");
569 }
570 void getVisualStudioDefines(const LangOptions &Opts,
571 MacroBuilder &Builder) const {
572 if (Opts.CPlusPlus) {
573 if (Opts.RTTIData)
574 Builder.defineMacro("_CPPRTTI");
575
576 if (Opts.Exceptions)
577 Builder.defineMacro("_CPPUNWIND");
578 }
579
580 if (!Opts.CharIsSigned)
581 Builder.defineMacro("_CHAR_UNSIGNED");
582
583 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
584 // but it works for now.
585 if (Opts.POSIXThreads)
586 Builder.defineMacro("_MT");
587
588 if (Opts.MSCompatibilityVersion) {
589 Builder.defineMacro("_MSC_VER",
590 Twine(Opts.MSCompatibilityVersion / 100000));
591 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
592 // FIXME We cannot encode the revision information into 32-bits
593 Builder.defineMacro("_MSC_BUILD", Twine(1));
594 }
595
596 if (Opts.MicrosoftExt) {
597 Builder.defineMacro("_MSC_EXTENSIONS");
598
599 if (Opts.CPlusPlus11) {
600 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
601 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
602 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
603 }
604 }
605
606 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
607 }
608
609public:
610 WindowsTargetInfo(const llvm::Triple &Triple)
611 : OSTargetInfo<Target>(Triple) {}
612};
613
614template <typename Target>
615class NaClTargetInfo : public OSTargetInfo<Target> {
616protected:
617 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
618 MacroBuilder &Builder) const override {
619 if (Opts.POSIXThreads)
620 Builder.defineMacro("_REENTRANT");
621 if (Opts.CPlusPlus)
622 Builder.defineMacro("_GNU_SOURCE");
623
624 DefineStd(Builder, "unix", Opts);
625 Builder.defineMacro("__ELF__");
626 Builder.defineMacro("__native_client__");
627 }
628
629public:
630 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
631 this->UserLabelPrefix = "";
632 this->LongAlign = 32;
633 this->LongWidth = 32;
634 this->PointerAlign = 32;
635 this->PointerWidth = 32;
636 this->IntMaxType = TargetInfo::SignedLongLong;
637 this->Int64Type = TargetInfo::SignedLongLong;
638 this->DoubleAlign = 64;
639 this->LongDoubleWidth = 64;
640 this->LongDoubleAlign = 64;
641 this->LongLongWidth = 64;
642 this->LongLongAlign = 64;
643 this->SizeType = TargetInfo::UnsignedInt;
644 this->PtrDiffType = TargetInfo::SignedInt;
645 this->IntPtrType = TargetInfo::SignedInt;
646 // RegParmMax is inherited from the underlying architecture
647 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
648 if (Triple.getArch() == llvm::Triple::arm) {
649 this->DescriptionString =
650 "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
651 } else if (Triple.getArch() == llvm::Triple::x86) {
652 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
653 } else if (Triple.getArch() == llvm::Triple::x86_64) {
654 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
655 } else if (Triple.getArch() == llvm::Triple::mipsel) {
656 // Handled on mips' setDescriptionString.
657 } else {
658 assert(Triple.getArch() == llvm::Triple::le32);
659 this->DescriptionString = "e-p:32:32-i64:64";
660 }
661 }
662 typename Target::CallingConvCheckResult checkCallingConvention(
663 CallingConv CC) const override {
664 return CC == CC_PnaclCall ? Target::CCCR_OK :
665 Target::checkCallingConvention(CC);
666 }
667};
668} // end anonymous namespace.
669
670//===----------------------------------------------------------------------===//
671// Specific target implementations.
672//===----------------------------------------------------------------------===//
673
674namespace {
675// PPC abstract base class
676class PPCTargetInfo : public TargetInfo {
677 static const Builtin::Info BuiltinInfo[];
678 static const char * const GCCRegNames[];
679 static const TargetInfo::GCCRegAlias GCCRegAliases[];
680 std::string CPU;
681
682 // Target cpu features.
683 bool HasVSX;
684 bool HasP8Vector;
685
686protected:
687 std::string ABI;
688
689public:
690 PPCTargetInfo(const llvm::Triple &Triple)
691 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false) {
692 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
693 LongDoubleWidth = LongDoubleAlign = 128;
694 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
695 }
696
697 /// \brief Flags for architecture specific defines.
698 typedef enum {
699 ArchDefineNone = 0,
700 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
701 ArchDefinePpcgr = 1 << 1,
702 ArchDefinePpcsq = 1 << 2,
703 ArchDefine440 = 1 << 3,
704 ArchDefine603 = 1 << 4,
705 ArchDefine604 = 1 << 5,
706 ArchDefinePwr4 = 1 << 6,
707 ArchDefinePwr5 = 1 << 7,
708 ArchDefinePwr5x = 1 << 8,
709 ArchDefinePwr6 = 1 << 9,
710 ArchDefinePwr6x = 1 << 10,
711 ArchDefinePwr7 = 1 << 11,
712 ArchDefinePwr8 = 1 << 12,
713 ArchDefineA2 = 1 << 13,
714 ArchDefineA2q = 1 << 14
715 } ArchDefineTypes;
716
717 // Note: GCC recognizes the following additional cpus:
718 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
719 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
720 // titan, rs64.
721 bool setCPU(const std::string &Name) override {
722 bool CPUKnown = llvm::StringSwitch<bool>(Name)
723 .Case("generic", true)
724 .Case("440", true)
725 .Case("450", true)
726 .Case("601", true)
727 .Case("602", true)
728 .Case("603", true)
729 .Case("603e", true)
730 .Case("603ev", true)
731 .Case("604", true)
732 .Case("604e", true)
733 .Case("620", true)
734 .Case("630", true)
735 .Case("g3", true)
736 .Case("7400", true)
737 .Case("g4", true)
738 .Case("7450", true)
739 .Case("g4+", true)
740 .Case("750", true)
741 .Case("970", true)
742 .Case("g5", true)
743 .Case("a2", true)
744 .Case("a2q", true)
745 .Case("e500mc", true)
746 .Case("e5500", true)
747 .Case("power3", true)
748 .Case("pwr3", true)
749 .Case("power4", true)
750 .Case("pwr4", true)
751 .Case("power5", true)
752 .Case("pwr5", true)
753 .Case("power5x", true)
754 .Case("pwr5x", true)
755 .Case("power6", true)
756 .Case("pwr6", true)
757 .Case("power6x", true)
758 .Case("pwr6x", true)
759 .Case("power7", true)
760 .Case("pwr7", true)
761 .Case("power8", true)
762 .Case("pwr8", true)
763 .Case("powerpc", true)
764 .Case("ppc", true)
765 .Case("powerpc64", true)
766 .Case("ppc64", true)
767 .Case("powerpc64le", true)
768 .Case("ppc64le", true)
769 .Default(false);
770
771 if (CPUKnown)
772 CPU = Name;
773
774 return CPUKnown;
775 }
776
777
778 StringRef getABI() const override { return ABI; }
779
780 void getTargetBuiltins(const Builtin::Info *&Records,
781 unsigned &NumRecords) const override {
782 Records = BuiltinInfo;
783 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
784 }
785
786 bool isCLZForZeroUndef() const override { return false; }
787
788 void getTargetDefines(const LangOptions &Opts,
789 MacroBuilder &Builder) const override;
790
791 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
792
793 bool handleTargetFeatures(std::vector<std::string> &Features,
794 DiagnosticsEngine &Diags) override;
795 bool hasFeature(StringRef Feature) const override;
796
797 void getGCCRegNames(const char * const *&Names,
798 unsigned &NumNames) const override;
799 void getGCCRegAliases(const GCCRegAlias *&Aliases,
800 unsigned &NumAliases) const override;
801 bool validateAsmConstraint(const char *&Name,
802 TargetInfo::ConstraintInfo &Info) const override {
803 switch (*Name) {
804 default: return false;
805 case 'O': // Zero
806 break;
807 case 'b': // Base register
808 case 'f': // Floating point register
809 Info.setAllowsRegister();
810 break;
811 // FIXME: The following are added to allow parsing.
812 // I just took a guess at what the actions should be.
813 // Also, is more specific checking needed? I.e. specific registers?
814 case 'd': // Floating point register (containing 64-bit value)
815 case 'v': // Altivec vector register
816 Info.setAllowsRegister();
817 break;
818 case 'w':
819 switch (Name[1]) {
820 case 'd':// VSX vector register to hold vector double data
821 case 'f':// VSX vector register to hold vector float data
822 case 's':// VSX vector register to hold scalar float data
823 case 'a':// Any VSX register
824 case 'c':// An individual CR bit
825 break;
826 default:
827 return false;
828 }
829 Info.setAllowsRegister();
830 Name++; // Skip over 'w'.
831 break;
832 case 'h': // `MQ', `CTR', or `LINK' register
833 case 'q': // `MQ' register
834 case 'c': // `CTR' register
835 case 'l': // `LINK' register
836 case 'x': // `CR' register (condition register) number 0
837 case 'y': // `CR' register (condition register)
838 case 'z': // `XER[CA]' carry bit (part of the XER register)
839 Info.setAllowsRegister();
840 break;
841 case 'I': // Signed 16-bit constant
842 case 'J': // Unsigned 16-bit constant shifted left 16 bits
843 // (use `L' instead for SImode constants)
844 case 'K': // Unsigned 16-bit constant
845 case 'L': // Signed 16-bit constant shifted left 16 bits
846 case 'M': // Constant larger than 31
847 case 'N': // Exact power of 2
848 case 'P': // Constant whose negation is a signed 16-bit constant
849 case 'G': // Floating point constant that can be loaded into a
850 // register with one instruction per word
851 case 'H': // Integer/Floating point constant that can be loaded
852 // into a register using three instructions
853 break;
854 case 'm': // Memory operand. Note that on PowerPC targets, m can
855 // include addresses that update the base register. It
856 // is therefore only safe to use `m' in an asm statement
857 // if that asm statement accesses the operand exactly once.
858 // The asm statement must also use `%U<opno>' as a
859 // placeholder for the "update" flag in the corresponding
860 // load or store instruction. For example:
861 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
862 // is correct but:
863 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
864 // is not. Use es rather than m if you don't want the base
865 // register to be updated.
866 case 'e':
867 if (Name[1] != 's')
868 return false;
869 // es: A "stable" memory operand; that is, one which does not
870 // include any automodification of the base register. Unlike
871 // `m', this constraint can be used in asm statements that
872 // might access the operand several times, or that might not
873 // access it at all.
874 Info.setAllowsMemory();
875 Name++; // Skip over 'e'.
876 break;
877 case 'Q': // Memory operand that is an offset from a register (it is
878 // usually better to use `m' or `es' in asm statements)
879 case 'Z': // Memory operand that is an indexed or indirect from a
880 // register (it is usually better to use `m' or `es' in
881 // asm statements)
882 Info.setAllowsMemory();
883 Info.setAllowsRegister();
884 break;
885 case 'R': // AIX TOC entry
886 case 'a': // Address operand that is an indexed or indirect from a
887 // register (`p' is preferable for asm statements)
888 case 'S': // Constant suitable as a 64-bit mask operand
889 case 'T': // Constant suitable as a 32-bit mask operand
890 case 'U': // System V Release 4 small data area reference
891 case 't': // AND masks that can be performed by two rldic{l, r}
892 // instructions
893 case 'W': // Vector constant that does not require memory
894 case 'j': // Vector constant that is all zeros.
895 break;
896 // End FIXME.
897 }
898 return true;
899 }
900 std::string convertConstraint(const char *&Constraint) const override {
901 std::string R;
902 switch (*Constraint) {
903 case 'e':
904 case 'w':
905 // Two-character constraint; add "^" hint for later parsing.
906 R = std::string("^") + std::string(Constraint, 2);
907 Constraint++;
908 break;
909 default:
910 return TargetInfo::convertConstraint(Constraint);
911 }
912 return R;
913 }
914 const char *getClobbers() const override {
915 return "";
916 }
917 int getEHDataRegisterNumber(unsigned RegNo) const override {
918 if (RegNo == 0) return 3;
919 if (RegNo == 1) return 4;
920 return -1;
921 }
| 423 }
424};
425
426// OpenBSD Target
427template<typename Target>
428class OpenBSDTargetInfo : public OSTargetInfo<Target> {
429protected:
430 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
431 MacroBuilder &Builder) const override {
432 // OpenBSD defines; list based off of gcc output
433
434 Builder.defineMacro("__OpenBSD__");
435 DefineStd(Builder, "unix", Opts);
436 Builder.defineMacro("__ELF__");
437 if (Opts.POSIXThreads)
438 Builder.defineMacro("_REENTRANT");
439 }
440public:
441 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
442 this->UserLabelPrefix = "";
443 this->TLSSupported = false;
444
445 switch (Triple.getArch()) {
446 default:
447 case llvm::Triple::x86:
448 case llvm::Triple::x86_64:
449 case llvm::Triple::arm:
450 case llvm::Triple::sparc:
451 this->MCountName = "__mcount";
452 break;
453 case llvm::Triple::mips64:
454 case llvm::Triple::mips64el:
455 case llvm::Triple::ppc:
456 case llvm::Triple::sparcv9:
457 this->MCountName = "_mcount";
458 break;
459 }
460 }
461};
462
463// Bitrig Target
464template<typename Target>
465class BitrigTargetInfo : public OSTargetInfo<Target> {
466protected:
467 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
468 MacroBuilder &Builder) const override {
469 // Bitrig defines; list based off of gcc output
470
471 Builder.defineMacro("__Bitrig__");
472 DefineStd(Builder, "unix", Opts);
473 Builder.defineMacro("__ELF__");
474 if (Opts.POSIXThreads)
475 Builder.defineMacro("_REENTRANT");
476 }
477public:
478 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
479 this->UserLabelPrefix = "";
480 this->MCountName = "__mcount";
481 }
482};
483
484// PSP Target
485template<typename Target>
486class PSPTargetInfo : public OSTargetInfo<Target> {
487protected:
488 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
489 MacroBuilder &Builder) const override {
490 // PSP defines; list based on the output of the pspdev gcc toolchain.
491 Builder.defineMacro("PSP");
492 Builder.defineMacro("_PSP");
493 Builder.defineMacro("__psp__");
494 Builder.defineMacro("__ELF__");
495 }
496public:
497 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
498 this->UserLabelPrefix = "";
499 }
500};
501
502// PS3 PPU Target
503template<typename Target>
504class PS3PPUTargetInfo : public OSTargetInfo<Target> {
505protected:
506 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
507 MacroBuilder &Builder) const override {
508 // PS3 PPU defines.
509 Builder.defineMacro("__PPC__");
510 Builder.defineMacro("__PPU__");
511 Builder.defineMacro("__CELLOS_LV2__");
512 Builder.defineMacro("__ELF__");
513 Builder.defineMacro("__LP32__");
514 Builder.defineMacro("_ARCH_PPC64");
515 Builder.defineMacro("__powerpc64__");
516 }
517public:
518 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
519 this->UserLabelPrefix = "";
520 this->LongWidth = this->LongAlign = 32;
521 this->PointerWidth = this->PointerAlign = 32;
522 this->IntMaxType = TargetInfo::SignedLongLong;
523 this->Int64Type = TargetInfo::SignedLongLong;
524 this->SizeType = TargetInfo::UnsignedInt;
525 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64";
526 }
527};
528
529// Solaris target
530template<typename Target>
531class SolarisTargetInfo : public OSTargetInfo<Target> {
532protected:
533 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
534 MacroBuilder &Builder) const override {
535 DefineStd(Builder, "sun", Opts);
536 DefineStd(Builder, "unix", Opts);
537 Builder.defineMacro("__ELF__");
538 Builder.defineMacro("__svr4__");
539 Builder.defineMacro("__SVR4");
540 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
541 // newer, but to 500 for everything else. feature_test.h has a check to
542 // ensure that you are not using C99 with an old version of X/Open or C89
543 // with a new version.
544 if (Opts.C99)
545 Builder.defineMacro("_XOPEN_SOURCE", "600");
546 else
547 Builder.defineMacro("_XOPEN_SOURCE", "500");
548 if (Opts.CPlusPlus)
549 Builder.defineMacro("__C99FEATURES__");
550 Builder.defineMacro("_LARGEFILE_SOURCE");
551 Builder.defineMacro("_LARGEFILE64_SOURCE");
552 Builder.defineMacro("__EXTENSIONS__");
553 Builder.defineMacro("_REENTRANT");
554 }
555public:
556 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
557 this->UserLabelPrefix = "";
558 this->WCharType = this->SignedInt;
559 // FIXME: WIntType should be SignedLong
560 }
561};
562
563// Windows target
564template<typename Target>
565class WindowsTargetInfo : public OSTargetInfo<Target> {
566protected:
567 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
568 MacroBuilder &Builder) const override {
569 Builder.defineMacro("_WIN32");
570 }
571 void getVisualStudioDefines(const LangOptions &Opts,
572 MacroBuilder &Builder) const {
573 if (Opts.CPlusPlus) {
574 if (Opts.RTTIData)
575 Builder.defineMacro("_CPPRTTI");
576
577 if (Opts.Exceptions)
578 Builder.defineMacro("_CPPUNWIND");
579 }
580
581 if (!Opts.CharIsSigned)
582 Builder.defineMacro("_CHAR_UNSIGNED");
583
584 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
585 // but it works for now.
586 if (Opts.POSIXThreads)
587 Builder.defineMacro("_MT");
588
589 if (Opts.MSCompatibilityVersion) {
590 Builder.defineMacro("_MSC_VER",
591 Twine(Opts.MSCompatibilityVersion / 100000));
592 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
593 // FIXME We cannot encode the revision information into 32-bits
594 Builder.defineMacro("_MSC_BUILD", Twine(1));
595 }
596
597 if (Opts.MicrosoftExt) {
598 Builder.defineMacro("_MSC_EXTENSIONS");
599
600 if (Opts.CPlusPlus11) {
601 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
602 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
603 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
604 }
605 }
606
607 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
608 }
609
610public:
611 WindowsTargetInfo(const llvm::Triple &Triple)
612 : OSTargetInfo<Target>(Triple) {}
613};
614
615template <typename Target>
616class NaClTargetInfo : public OSTargetInfo<Target> {
617protected:
618 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
619 MacroBuilder &Builder) const override {
620 if (Opts.POSIXThreads)
621 Builder.defineMacro("_REENTRANT");
622 if (Opts.CPlusPlus)
623 Builder.defineMacro("_GNU_SOURCE");
624
625 DefineStd(Builder, "unix", Opts);
626 Builder.defineMacro("__ELF__");
627 Builder.defineMacro("__native_client__");
628 }
629
630public:
631 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
632 this->UserLabelPrefix = "";
633 this->LongAlign = 32;
634 this->LongWidth = 32;
635 this->PointerAlign = 32;
636 this->PointerWidth = 32;
637 this->IntMaxType = TargetInfo::SignedLongLong;
638 this->Int64Type = TargetInfo::SignedLongLong;
639 this->DoubleAlign = 64;
640 this->LongDoubleWidth = 64;
641 this->LongDoubleAlign = 64;
642 this->LongLongWidth = 64;
643 this->LongLongAlign = 64;
644 this->SizeType = TargetInfo::UnsignedInt;
645 this->PtrDiffType = TargetInfo::SignedInt;
646 this->IntPtrType = TargetInfo::SignedInt;
647 // RegParmMax is inherited from the underlying architecture
648 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
649 if (Triple.getArch() == llvm::Triple::arm) {
650 this->DescriptionString =
651 "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
652 } else if (Triple.getArch() == llvm::Triple::x86) {
653 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
654 } else if (Triple.getArch() == llvm::Triple::x86_64) {
655 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
656 } else if (Triple.getArch() == llvm::Triple::mipsel) {
657 // Handled on mips' setDescriptionString.
658 } else {
659 assert(Triple.getArch() == llvm::Triple::le32);
660 this->DescriptionString = "e-p:32:32-i64:64";
661 }
662 }
663 typename Target::CallingConvCheckResult checkCallingConvention(
664 CallingConv CC) const override {
665 return CC == CC_PnaclCall ? Target::CCCR_OK :
666 Target::checkCallingConvention(CC);
667 }
668};
669} // end anonymous namespace.
670
671//===----------------------------------------------------------------------===//
672// Specific target implementations.
673//===----------------------------------------------------------------------===//
674
675namespace {
676// PPC abstract base class
677class PPCTargetInfo : public TargetInfo {
678 static const Builtin::Info BuiltinInfo[];
679 static const char * const GCCRegNames[];
680 static const TargetInfo::GCCRegAlias GCCRegAliases[];
681 std::string CPU;
682
683 // Target cpu features.
684 bool HasVSX;
685 bool HasP8Vector;
686
687protected:
688 std::string ABI;
689
690public:
691 PPCTargetInfo(const llvm::Triple &Triple)
692 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false) {
693 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
694 LongDoubleWidth = LongDoubleAlign = 128;
695 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
696 }
697
698 /// \brief Flags for architecture specific defines.
699 typedef enum {
700 ArchDefineNone = 0,
701 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
702 ArchDefinePpcgr = 1 << 1,
703 ArchDefinePpcsq = 1 << 2,
704 ArchDefine440 = 1 << 3,
705 ArchDefine603 = 1 << 4,
706 ArchDefine604 = 1 << 5,
707 ArchDefinePwr4 = 1 << 6,
708 ArchDefinePwr5 = 1 << 7,
709 ArchDefinePwr5x = 1 << 8,
710 ArchDefinePwr6 = 1 << 9,
711 ArchDefinePwr6x = 1 << 10,
712 ArchDefinePwr7 = 1 << 11,
713 ArchDefinePwr8 = 1 << 12,
714 ArchDefineA2 = 1 << 13,
715 ArchDefineA2q = 1 << 14
716 } ArchDefineTypes;
717
718 // Note: GCC recognizes the following additional cpus:
719 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
720 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
721 // titan, rs64.
722 bool setCPU(const std::string &Name) override {
723 bool CPUKnown = llvm::StringSwitch<bool>(Name)
724 .Case("generic", true)
725 .Case("440", true)
726 .Case("450", true)
727 .Case("601", true)
728 .Case("602", true)
729 .Case("603", true)
730 .Case("603e", true)
731 .Case("603ev", true)
732 .Case("604", true)
733 .Case("604e", true)
734 .Case("620", true)
735 .Case("630", true)
736 .Case("g3", true)
737 .Case("7400", true)
738 .Case("g4", true)
739 .Case("7450", true)
740 .Case("g4+", true)
741 .Case("750", true)
742 .Case("970", true)
743 .Case("g5", true)
744 .Case("a2", true)
745 .Case("a2q", true)
746 .Case("e500mc", true)
747 .Case("e5500", true)
748 .Case("power3", true)
749 .Case("pwr3", true)
750 .Case("power4", true)
751 .Case("pwr4", true)
752 .Case("power5", true)
753 .Case("pwr5", true)
754 .Case("power5x", true)
755 .Case("pwr5x", true)
756 .Case("power6", true)
757 .Case("pwr6", true)
758 .Case("power6x", true)
759 .Case("pwr6x", true)
760 .Case("power7", true)
761 .Case("pwr7", true)
762 .Case("power8", true)
763 .Case("pwr8", true)
764 .Case("powerpc", true)
765 .Case("ppc", true)
766 .Case("powerpc64", true)
767 .Case("ppc64", true)
768 .Case("powerpc64le", true)
769 .Case("ppc64le", true)
770 .Default(false);
771
772 if (CPUKnown)
773 CPU = Name;
774
775 return CPUKnown;
776 }
777
778
779 StringRef getABI() const override { return ABI; }
780
781 void getTargetBuiltins(const Builtin::Info *&Records,
782 unsigned &NumRecords) const override {
783 Records = BuiltinInfo;
784 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
785 }
786
787 bool isCLZForZeroUndef() const override { return false; }
788
789 void getTargetDefines(const LangOptions &Opts,
790 MacroBuilder &Builder) const override;
791
792 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
793
794 bool handleTargetFeatures(std::vector<std::string> &Features,
795 DiagnosticsEngine &Diags) override;
796 bool hasFeature(StringRef Feature) const override;
797
798 void getGCCRegNames(const char * const *&Names,
799 unsigned &NumNames) const override;
800 void getGCCRegAliases(const GCCRegAlias *&Aliases,
801 unsigned &NumAliases) const override;
802 bool validateAsmConstraint(const char *&Name,
803 TargetInfo::ConstraintInfo &Info) const override {
804 switch (*Name) {
805 default: return false;
806 case 'O': // Zero
807 break;
808 case 'b': // Base register
809 case 'f': // Floating point register
810 Info.setAllowsRegister();
811 break;
812 // FIXME: The following are added to allow parsing.
813 // I just took a guess at what the actions should be.
814 // Also, is more specific checking needed? I.e. specific registers?
815 case 'd': // Floating point register (containing 64-bit value)
816 case 'v': // Altivec vector register
817 Info.setAllowsRegister();
818 break;
819 case 'w':
820 switch (Name[1]) {
821 case 'd':// VSX vector register to hold vector double data
822 case 'f':// VSX vector register to hold vector float data
823 case 's':// VSX vector register to hold scalar float data
824 case 'a':// Any VSX register
825 case 'c':// An individual CR bit
826 break;
827 default:
828 return false;
829 }
830 Info.setAllowsRegister();
831 Name++; // Skip over 'w'.
832 break;
833 case 'h': // `MQ', `CTR', or `LINK' register
834 case 'q': // `MQ' register
835 case 'c': // `CTR' register
836 case 'l': // `LINK' register
837 case 'x': // `CR' register (condition register) number 0
838 case 'y': // `CR' register (condition register)
839 case 'z': // `XER[CA]' carry bit (part of the XER register)
840 Info.setAllowsRegister();
841 break;
842 case 'I': // Signed 16-bit constant
843 case 'J': // Unsigned 16-bit constant shifted left 16 bits
844 // (use `L' instead for SImode constants)
845 case 'K': // Unsigned 16-bit constant
846 case 'L': // Signed 16-bit constant shifted left 16 bits
847 case 'M': // Constant larger than 31
848 case 'N': // Exact power of 2
849 case 'P': // Constant whose negation is a signed 16-bit constant
850 case 'G': // Floating point constant that can be loaded into a
851 // register with one instruction per word
852 case 'H': // Integer/Floating point constant that can be loaded
853 // into a register using three instructions
854 break;
855 case 'm': // Memory operand. Note that on PowerPC targets, m can
856 // include addresses that update the base register. It
857 // is therefore only safe to use `m' in an asm statement
858 // if that asm statement accesses the operand exactly once.
859 // The asm statement must also use `%U<opno>' as a
860 // placeholder for the "update" flag in the corresponding
861 // load or store instruction. For example:
862 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
863 // is correct but:
864 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
865 // is not. Use es rather than m if you don't want the base
866 // register to be updated.
867 case 'e':
868 if (Name[1] != 's')
869 return false;
870 // es: A "stable" memory operand; that is, one which does not
871 // include any automodification of the base register. Unlike
872 // `m', this constraint can be used in asm statements that
873 // might access the operand several times, or that might not
874 // access it at all.
875 Info.setAllowsMemory();
876 Name++; // Skip over 'e'.
877 break;
878 case 'Q': // Memory operand that is an offset from a register (it is
879 // usually better to use `m' or `es' in asm statements)
880 case 'Z': // Memory operand that is an indexed or indirect from a
881 // register (it is usually better to use `m' or `es' in
882 // asm statements)
883 Info.setAllowsMemory();
884 Info.setAllowsRegister();
885 break;
886 case 'R': // AIX TOC entry
887 case 'a': // Address operand that is an indexed or indirect from a
888 // register (`p' is preferable for asm statements)
889 case 'S': // Constant suitable as a 64-bit mask operand
890 case 'T': // Constant suitable as a 32-bit mask operand
891 case 'U': // System V Release 4 small data area reference
892 case 't': // AND masks that can be performed by two rldic{l, r}
893 // instructions
894 case 'W': // Vector constant that does not require memory
895 case 'j': // Vector constant that is all zeros.
896 break;
897 // End FIXME.
898 }
899 return true;
900 }
901 std::string convertConstraint(const char *&Constraint) const override {
902 std::string R;
903 switch (*Constraint) {
904 case 'e':
905 case 'w':
906 // Two-character constraint; add "^" hint for later parsing.
907 R = std::string("^") + std::string(Constraint, 2);
908 Constraint++;
909 break;
910 default:
911 return TargetInfo::convertConstraint(Constraint);
912 }
913 return R;
914 }
915 const char *getClobbers() const override {
916 return "";
917 }
918 int getEHDataRegisterNumber(unsigned RegNo) const override {
919 if (RegNo == 0) return 3;
920 if (RegNo == 1) return 4;
921 return -1;
922 }
|
| 923
924 bool hasSjLjLowering() const override {
925 return true;
926 }
|
922};
923
924const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
925#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
926#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
927 ALL_LANGUAGES },
928#include "clang/Basic/BuiltinsPPC.def"
929};
930
931/// handleTargetFeatures - Perform initialization based on the user
932/// configured set of features.
933bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
934 DiagnosticsEngine &Diags) {
935 for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
936 // Ignore disabled features.
937 if (Features[i][0] == '-')
938 continue;
939
940 StringRef Feature = StringRef(Features[i]).substr(1);
941
942 if (Feature == "vsx") {
943 HasVSX = true;
944 continue;
945 }
946
947 if (Feature == "power8-vector") {
948 HasP8Vector = true;
949 continue;
950 }
951
952 // TODO: Finish this list and add an assert that we've handled them
953 // all.
954 }
955
956 return true;
957}
958
959/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
960/// #defines that are not tied to a specific subtarget.
961void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
962 MacroBuilder &Builder) const {
963 // Target identification.
964 Builder.defineMacro("__ppc__");
965 Builder.defineMacro("__PPC__");
966 Builder.defineMacro("_ARCH_PPC");
967 Builder.defineMacro("__powerpc__");
968 Builder.defineMacro("__POWERPC__");
969 if (PointerWidth == 64) {
970 Builder.defineMacro("_ARCH_PPC64");
971 Builder.defineMacro("__powerpc64__");
972 Builder.defineMacro("__ppc64__");
973 Builder.defineMacro("__PPC64__");
974 }
975
976 // Target properties.
977 if (getTriple().getArch() == llvm::Triple::ppc64le) {
978 Builder.defineMacro("_LITTLE_ENDIAN");
979 } else {
980 if (getTriple().getOS() != llvm::Triple::NetBSD &&
981 getTriple().getOS() != llvm::Triple::OpenBSD)
982 Builder.defineMacro("_BIG_ENDIAN");
983 }
984
985 // ABI options.
986 if (ABI == "elfv1")
987 Builder.defineMacro("_CALL_ELF", "1");
988 if (ABI == "elfv2")
989 Builder.defineMacro("_CALL_ELF", "2");
990
991 // Subtarget options.
992 Builder.defineMacro("__NATURAL_ALIGNMENT__");
993 Builder.defineMacro("__REGISTER_PREFIX__", "");
994
995 // FIXME: Should be controlled by command line option.
996 if (LongDoubleWidth == 128)
997 Builder.defineMacro("__LONG_DOUBLE_128__");
998
999 if (Opts.AltiVec) {
1000 Builder.defineMacro("__VEC__", "10206");
1001 Builder.defineMacro("__ALTIVEC__");
1002 }
1003
1004 // CPU identification.
1005 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1006 .Case("440", ArchDefineName)
1007 .Case("450", ArchDefineName | ArchDefine440)
1008 .Case("601", ArchDefineName)
1009 .Case("602", ArchDefineName | ArchDefinePpcgr)
1010 .Case("603", ArchDefineName | ArchDefinePpcgr)
1011 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1012 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1013 .Case("604", ArchDefineName | ArchDefinePpcgr)
1014 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1015 .Case("620", ArchDefineName | ArchDefinePpcgr)
1016 .Case("630", ArchDefineName | ArchDefinePpcgr)
1017 .Case("7400", ArchDefineName | ArchDefinePpcgr)
1018 .Case("7450", ArchDefineName | ArchDefinePpcgr)
1019 .Case("750", ArchDefineName | ArchDefinePpcgr)
1020 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1021 | ArchDefinePpcsq)
1022 .Case("a2", ArchDefineA2)
1023 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1024 .Case("pwr3", ArchDefinePpcgr)
1025 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1026 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1027 | ArchDefinePpcsq)
1028 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1029 | ArchDefinePpcgr | ArchDefinePpcsq)
1030 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1031 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1032 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1033 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1034 | ArchDefinePpcsq)
1035 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1036 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1037 | ArchDefinePpcgr | ArchDefinePpcsq)
1038 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1039 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1040 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1041 .Case("power3", ArchDefinePpcgr)
1042 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1043 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1044 | ArchDefinePpcsq)
1045 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1046 | ArchDefinePpcgr | ArchDefinePpcsq)
1047 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1048 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1049 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1050 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1051 | ArchDefinePpcsq)
1052 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1053 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1054 | ArchDefinePpcgr | ArchDefinePpcsq)
1055 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1056 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1057 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1058 .Default(ArchDefineNone);
1059
1060 if (defs & ArchDefineName)
1061 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1062 if (defs & ArchDefinePpcgr)
1063 Builder.defineMacro("_ARCH_PPCGR");
1064 if (defs & ArchDefinePpcsq)
1065 Builder.defineMacro("_ARCH_PPCSQ");
1066 if (defs & ArchDefine440)
1067 Builder.defineMacro("_ARCH_440");
1068 if (defs & ArchDefine603)
1069 Builder.defineMacro("_ARCH_603");
1070 if (defs & ArchDefine604)
1071 Builder.defineMacro("_ARCH_604");
1072 if (defs & ArchDefinePwr4)
1073 Builder.defineMacro("_ARCH_PWR4");
1074 if (defs & ArchDefinePwr5)
1075 Builder.defineMacro("_ARCH_PWR5");
1076 if (defs & ArchDefinePwr5x)
1077 Builder.defineMacro("_ARCH_PWR5X");
1078 if (defs & ArchDefinePwr6)
1079 Builder.defineMacro("_ARCH_PWR6");
1080 if (defs & ArchDefinePwr6x)
1081 Builder.defineMacro("_ARCH_PWR6X");
1082 if (defs & ArchDefinePwr7)
1083 Builder.defineMacro("_ARCH_PWR7");
1084 if (defs & ArchDefinePwr8)
1085 Builder.defineMacro("_ARCH_PWR8");
1086 if (defs & ArchDefineA2)
1087 Builder.defineMacro("_ARCH_A2");
1088 if (defs & ArchDefineA2q) {
1089 Builder.defineMacro("_ARCH_A2Q");
1090 Builder.defineMacro("_ARCH_QP");
1091 }
1092
1093 if (getTriple().getVendor() == llvm::Triple::BGQ) {
1094 Builder.defineMacro("__bg__");
1095 Builder.defineMacro("__THW_BLUEGENE__");
1096 Builder.defineMacro("__bgq__");
1097 Builder.defineMacro("__TOS_BGQ__");
1098 }
1099
1100 if (HasVSX)
1101 Builder.defineMacro("__VSX__");
1102 if (HasP8Vector)
1103 Builder.defineMacro("__POWER8_VECTOR__");
1104
1105 // FIXME: The following are not yet generated here by Clang, but are
1106 // generated by GCC:
1107 //
1108 // _SOFT_FLOAT_
1109 // __RECIP_PRECISION__
1110 // __APPLE_ALTIVEC__
1111 // __RECIP__
1112 // __RECIPF__
1113 // __RSQRTE__
1114 // __RSQRTEF__
1115 // _SOFT_DOUBLE_
1116 // __NO_LWSYNC__
1117 // __HAVE_BSWAP__
1118 // __LONGDOUBLE128
1119 // __CMODEL_MEDIUM__
1120 // __CMODEL_LARGE__
1121 // _CALL_SYSV
1122 // _CALL_DARWIN
1123 // __NO_FPRS__
1124}
1125
1126void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1127 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1128 .Case("7400", true)
1129 .Case("g4", true)
1130 .Case("7450", true)
1131 .Case("g4+", true)
1132 .Case("970", true)
1133 .Case("g5", true)
1134 .Case("pwr6", true)
1135 .Case("pwr7", true)
1136 .Case("pwr8", true)
1137 .Case("ppc64", true)
1138 .Case("ppc64le", true)
1139 .Default(false);
1140
1141 Features["qpx"] = (CPU == "a2q");
1142
1143 if (!ABI.empty())
1144 Features[ABI] = true;
1145}
1146
1147bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1148 return llvm::StringSwitch<bool>(Feature)
1149 .Case("powerpc", true)
1150 .Case("vsx", HasVSX)
1151 .Case("power8-vector", HasP8Vector)
1152 .Default(false);
1153}
1154
1155const char * const PPCTargetInfo::GCCRegNames[] = {
1156 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1157 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1158 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1159 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1160 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1161 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1162 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1163 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1164 "mq", "lr", "ctr", "ap",
1165 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1166 "xer",
1167 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1168 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1169 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1170 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1171 "vrsave", "vscr",
1172 "spe_acc", "spefscr",
1173 "sfp"
1174};
1175
1176void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1177 unsigned &NumNames) const {
1178 Names = GCCRegNames;
1179 NumNames = llvm::array_lengthof(GCCRegNames);
1180}
1181
1182const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1183 // While some of these aliases do map to different registers
1184 // they still share the same register name.
1185 { { "0" }, "r0" },
1186 { { "1"}, "r1" },
1187 { { "2" }, "r2" },
1188 { { "3" }, "r3" },
1189 { { "4" }, "r4" },
1190 { { "5" }, "r5" },
1191 { { "6" }, "r6" },
1192 { { "7" }, "r7" },
1193 { { "8" }, "r8" },
1194 { { "9" }, "r9" },
1195 { { "10" }, "r10" },
1196 { { "11" }, "r11" },
1197 { { "12" }, "r12" },
1198 { { "13" }, "r13" },
1199 { { "14" }, "r14" },
1200 { { "15" }, "r15" },
1201 { { "16" }, "r16" },
1202 { { "17" }, "r17" },
1203 { { "18" }, "r18" },
1204 { { "19" }, "r19" },
1205 { { "20" }, "r20" },
1206 { { "21" }, "r21" },
1207 { { "22" }, "r22" },
1208 { { "23" }, "r23" },
1209 { { "24" }, "r24" },
1210 { { "25" }, "r25" },
1211 { { "26" }, "r26" },
1212 { { "27" }, "r27" },
1213 { { "28" }, "r28" },
1214 { { "29" }, "r29" },
1215 { { "30" }, "r30" },
1216 { { "31" }, "r31" },
1217 { { "fr0" }, "f0" },
1218 { { "fr1" }, "f1" },
1219 { { "fr2" }, "f2" },
1220 { { "fr3" }, "f3" },
1221 { { "fr4" }, "f4" },
1222 { { "fr5" }, "f5" },
1223 { { "fr6" }, "f6" },
1224 { { "fr7" }, "f7" },
1225 { { "fr8" }, "f8" },
1226 { { "fr9" }, "f9" },
1227 { { "fr10" }, "f10" },
1228 { { "fr11" }, "f11" },
1229 { { "fr12" }, "f12" },
1230 { { "fr13" }, "f13" },
1231 { { "fr14" }, "f14" },
1232 { { "fr15" }, "f15" },
1233 { { "fr16" }, "f16" },
1234 { { "fr17" }, "f17" },
1235 { { "fr18" }, "f18" },
1236 { { "fr19" }, "f19" },
1237 { { "fr20" }, "f20" },
1238 { { "fr21" }, "f21" },
1239 { { "fr22" }, "f22" },
1240 { { "fr23" }, "f23" },
1241 { { "fr24" }, "f24" },
1242 { { "fr25" }, "f25" },
1243 { { "fr26" }, "f26" },
1244 { { "fr27" }, "f27" },
1245 { { "fr28" }, "f28" },
1246 { { "fr29" }, "f29" },
1247 { { "fr30" }, "f30" },
1248 { { "fr31" }, "f31" },
1249 { { "cc" }, "cr0" },
1250};
1251
1252void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1253 unsigned &NumAliases) const {
1254 Aliases = GCCRegAliases;
1255 NumAliases = llvm::array_lengthof(GCCRegAliases);
1256}
1257} // end anonymous namespace.
1258
1259namespace {
1260class PPC32TargetInfo : public PPCTargetInfo {
1261public:
1262 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1263 DescriptionString = "E-m:e-p:32:32-i64:64-n32";
1264
1265 switch (getTriple().getOS()) {
1266 case llvm::Triple::Linux:
1267 case llvm::Triple::FreeBSD:
1268 case llvm::Triple::NetBSD:
1269 SizeType = UnsignedInt;
1270 PtrDiffType = SignedInt;
1271 IntPtrType = SignedInt;
1272 break;
1273 default:
1274 break;
1275 }
1276
1277 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1278 LongDoubleWidth = LongDoubleAlign = 64;
1279 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1280 }
1281
1282 // PPC32 supports atomics up to 4 bytes.
1283 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1284 }
1285
1286 BuiltinVaListKind getBuiltinVaListKind() const override {
1287 // This is the ELF definition, and is overridden by the Darwin sub-target
1288 return TargetInfo::PowerABIBuiltinVaList;
1289 }
1290};
1291} // end anonymous namespace.
1292
1293// Note: ABI differences may eventually require us to have a separate
1294// TargetInfo for little endian.
1295namespace {
1296class PPC64TargetInfo : public PPCTargetInfo {
1297public:
1298 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1299 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1300 IntMaxType = SignedLong;
1301 Int64Type = SignedLong;
1302
1303 if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1304 DescriptionString = "e-m:e-i64:64-n32:64";
1305 ABI = "elfv2";
1306 } else {
1307 DescriptionString = "E-m:e-i64:64-n32:64";
1308 ABI = "elfv1";
1309 }
1310
1311 switch (getTriple().getOS()) {
1312 case llvm::Triple::FreeBSD:
1313 LongDoubleWidth = LongDoubleAlign = 64;
1314 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1315 break;
1316 case llvm::Triple::NetBSD:
1317 IntMaxType = SignedLongLong;
1318 Int64Type = SignedLongLong;
1319 break;
1320 default:
1321 break;
1322 }
1323
1324 // PPC64 supports atomics up to 8 bytes.
1325 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1326 }
1327 BuiltinVaListKind getBuiltinVaListKind() const override {
1328 return TargetInfo::CharPtrBuiltinVaList;
1329 }
1330 // PPC64 Linux-specifc ABI options.
1331 bool setABI(const std::string &Name) override {
1332 if (Name == "elfv1" || Name == "elfv2") {
1333 ABI = Name;
1334 return true;
1335 }
1336 return false;
1337 }
1338};
1339} // end anonymous namespace.
1340
1341
1342namespace {
1343class DarwinPPC32TargetInfo :
1344 public DarwinTargetInfo<PPC32TargetInfo> {
1345public:
1346 DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1347 : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1348 HasAlignMac68kSupport = true;
1349 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1350 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1351 LongLongAlign = 32;
1352 SuitableAlign = 128;
1353 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32";
1354 }
1355 BuiltinVaListKind getBuiltinVaListKind() const override {
1356 return TargetInfo::CharPtrBuiltinVaList;
1357 }
1358};
1359
1360class DarwinPPC64TargetInfo :
1361 public DarwinTargetInfo<PPC64TargetInfo> {
1362public:
1363 DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1364 : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1365 HasAlignMac68kSupport = true;
1366 SuitableAlign = 128;
1367 DescriptionString = "E-m:o-i64:64-n32:64";
1368 }
1369};
1370} // end anonymous namespace.
1371
1372namespace {
1373 static const unsigned NVPTXAddrSpaceMap[] = {
1374 1, // opencl_global
1375 3, // opencl_local
1376 4, // opencl_constant
1377 // FIXME: generic has to be added to the target
1378 0, // opencl_generic
1379 1, // cuda_device
1380 4, // cuda_constant
1381 3, // cuda_shared
1382 };
1383 class NVPTXTargetInfo : public TargetInfo {
1384 static const char * const GCCRegNames[];
1385 static const Builtin::Info BuiltinInfo[];
1386
1387 // The GPU profiles supported by the NVPTX backend
1388 enum GPUKind {
1389 GK_NONE,
1390 GK_SM20,
1391 GK_SM21,
1392 GK_SM30,
1393 GK_SM35,
1394 } GPU;
1395
1396 public:
1397 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1398 BigEndian = false;
1399 TLSSupported = false;
1400 LongWidth = LongAlign = 64;
1401 AddrSpaceMap = &NVPTXAddrSpaceMap;
1402 UseAddrSpaceMapMangling = true;
1403 // Define available target features
1404 // These must be defined in sorted order!
1405 NoAsmVariants = true;
1406 // Set the default GPU to sm20
1407 GPU = GK_SM20;
1408 }
1409 void getTargetDefines(const LangOptions &Opts,
1410 MacroBuilder &Builder) const override {
1411 Builder.defineMacro("__PTX__");
1412 Builder.defineMacro("__NVPTX__");
1413 if (Opts.CUDAIsDevice) {
1414 // Set __CUDA_ARCH__ for the GPU specified.
1415 std::string CUDAArchCode;
1416 switch (GPU) {
1417 case GK_SM20:
1418 CUDAArchCode = "200";
1419 break;
1420 case GK_SM21:
1421 CUDAArchCode = "210";
1422 break;
1423 case GK_SM30:
1424 CUDAArchCode = "300";
1425 break;
1426 case GK_SM35:
1427 CUDAArchCode = "350";
1428 break;
1429 default:
1430 llvm_unreachable("Unhandled target CPU");
1431 }
1432 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1433 }
1434 }
1435 void getTargetBuiltins(const Builtin::Info *&Records,
1436 unsigned &NumRecords) const override {
1437 Records = BuiltinInfo;
1438 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1439 }
1440 bool hasFeature(StringRef Feature) const override {
1441 return Feature == "ptx" || Feature == "nvptx";
1442 }
1443
1444 void getGCCRegNames(const char * const *&Names,
1445 unsigned &NumNames) const override;
1446 void getGCCRegAliases(const GCCRegAlias *&Aliases,
1447 unsigned &NumAliases) const override {
1448 // No aliases.
1449 Aliases = nullptr;
1450 NumAliases = 0;
1451 }
1452 bool
1453 validateAsmConstraint(const char *&Name,
1454 TargetInfo::ConstraintInfo &Info) const override {
1455 switch (*Name) {
1456 default: return false;
1457 case 'c':
1458 case 'h':
1459 case 'r':
1460 case 'l':
1461 case 'f':
1462 case 'd':
1463 Info.setAllowsRegister();
1464 return true;
1465 }
1466 }
1467 const char *getClobbers() const override {
1468 // FIXME: Is this really right?
1469 return "";
1470 }
1471 BuiltinVaListKind getBuiltinVaListKind() const override {
1472 // FIXME: implement
1473 return TargetInfo::CharPtrBuiltinVaList;
1474 }
1475 bool setCPU(const std::string &Name) override {
1476 GPU = llvm::StringSwitch<GPUKind>(Name)
1477 .Case("sm_20", GK_SM20)
1478 .Case("sm_21", GK_SM21)
1479 .Case("sm_30", GK_SM30)
1480 .Case("sm_35", GK_SM35)
1481 .Default(GK_NONE);
1482
1483 return GPU != GK_NONE;
1484 }
1485 };
1486
1487 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1488#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1489#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1490 ALL_LANGUAGES },
1491#include "clang/Basic/BuiltinsNVPTX.def"
1492 };
1493
1494 const char * const NVPTXTargetInfo::GCCRegNames[] = {
1495 "r0"
1496 };
1497
1498 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1499 unsigned &NumNames) const {
1500 Names = GCCRegNames;
1501 NumNames = llvm::array_lengthof(GCCRegNames);
1502 }
1503
1504 class NVPTX32TargetInfo : public NVPTXTargetInfo {
1505 public:
1506 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1507 PointerWidth = PointerAlign = 32;
1508 SizeType = PtrDiffType = TargetInfo::UnsignedInt;
1509 IntPtrType = TargetInfo::SignedInt;
1510 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1511 }
1512 };
1513
1514 class NVPTX64TargetInfo : public NVPTXTargetInfo {
1515 public:
1516 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1517 PointerWidth = PointerAlign = 64;
1518 SizeType = PtrDiffType = TargetInfo::UnsignedLongLong;
1519 IntPtrType = TargetInfo::SignedLongLong;
1520 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64";
1521 }
1522 };
1523}
1524
1525namespace {
1526
1527static const unsigned R600AddrSpaceMap[] = {
1528 1, // opencl_global
1529 3, // opencl_local
1530 2, // opencl_constant
1531 4, // opencl_generic
1532 1, // cuda_device
1533 2, // cuda_constant
1534 3 // cuda_shared
1535};
1536
1537// If you edit the description strings, make sure you update
1538// getPointerWidthV().
1539
1540static const char *DescriptionStringR600 =
1541 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1542 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1543
1544static const char *DescriptionStringR600DoubleOps =
1545 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1546 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1547
1548static const char *DescriptionStringSI =
1549 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1550 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1551 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1552
1553class R600TargetInfo : public TargetInfo {
1554 static const Builtin::Info BuiltinInfo[];
1555
1556 /// \brief The GPU profiles supported by the R600 target.
1557 enum GPUKind {
1558 GK_NONE,
1559 GK_R600,
1560 GK_R600_DOUBLE_OPS,
1561 GK_R700,
1562 GK_R700_DOUBLE_OPS,
1563 GK_EVERGREEN,
1564 GK_EVERGREEN_DOUBLE_OPS,
1565 GK_NORTHERN_ISLANDS,
1566 GK_CAYMAN,
1567 GK_SOUTHERN_ISLANDS,
1568 GK_SEA_ISLANDS
1569 } GPU;
1570
1571public:
1572 R600TargetInfo(const llvm::Triple &Triple)
1573 : TargetInfo(Triple), GPU(GK_R600) {
1574 DescriptionString = DescriptionStringR600;
1575 AddrSpaceMap = &R600AddrSpaceMap;
1576 UseAddrSpaceMapMangling = true;
1577 }
1578
1579 uint64_t getPointerWidthV(unsigned AddrSpace) const override {
1580 if (GPU <= GK_CAYMAN)
1581 return 32;
1582
1583 switch(AddrSpace) {
1584 default:
1585 return 64;
1586 case 0:
1587 case 3:
1588 case 5:
1589 return 32;
1590 }
1591 }
1592
1593 const char * getClobbers() const override {
1594 return "";
1595 }
1596
1597 void getGCCRegNames(const char * const *&Names,
1598 unsigned &numNames) const override {
1599 Names = nullptr;
1600 numNames = 0;
1601 }
1602
1603 void getGCCRegAliases(const GCCRegAlias *&Aliases,
1604 unsigned &NumAliases) const override {
1605 Aliases = nullptr;
1606 NumAliases = 0;
1607 }
1608
1609 bool validateAsmConstraint(const char *&Name,
1610 TargetInfo::ConstraintInfo &info) const override {
1611 return true;
1612 }
1613
1614 void getTargetBuiltins(const Builtin::Info *&Records,
1615 unsigned &NumRecords) const override {
1616 Records = BuiltinInfo;
1617 NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin;
1618 }
1619
1620 void getTargetDefines(const LangOptions &Opts,
1621 MacroBuilder &Builder) const override {
1622 Builder.defineMacro("__R600__");
1623 }
1624
1625 BuiltinVaListKind getBuiltinVaListKind() const override {
1626 return TargetInfo::CharPtrBuiltinVaList;
1627 }
1628
1629 bool setCPU(const std::string &Name) override {
1630 GPU = llvm::StringSwitch<GPUKind>(Name)
1631 .Case("r600" , GK_R600)
1632 .Case("rv610", GK_R600)
1633 .Case("rv620", GK_R600)
1634 .Case("rv630", GK_R600)
1635 .Case("rv635", GK_R600)
1636 .Case("rs780", GK_R600)
1637 .Case("rs880", GK_R600)
1638 .Case("rv670", GK_R600_DOUBLE_OPS)
1639 .Case("rv710", GK_R700)
1640 .Case("rv730", GK_R700)
1641 .Case("rv740", GK_R700_DOUBLE_OPS)
1642 .Case("rv770", GK_R700_DOUBLE_OPS)
1643 .Case("palm", GK_EVERGREEN)
1644 .Case("cedar", GK_EVERGREEN)
1645 .Case("sumo", GK_EVERGREEN)
1646 .Case("sumo2", GK_EVERGREEN)
1647 .Case("redwood", GK_EVERGREEN)
1648 .Case("juniper", GK_EVERGREEN)
1649 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
1650 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
1651 .Case("barts", GK_NORTHERN_ISLANDS)
1652 .Case("turks", GK_NORTHERN_ISLANDS)
1653 .Case("caicos", GK_NORTHERN_ISLANDS)
1654 .Case("cayman", GK_CAYMAN)
1655 .Case("aruba", GK_CAYMAN)
1656 .Case("tahiti", GK_SOUTHERN_ISLANDS)
1657 .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1658 .Case("verde", GK_SOUTHERN_ISLANDS)
1659 .Case("oland", GK_SOUTHERN_ISLANDS)
1660 .Case("hainan", GK_SOUTHERN_ISLANDS)
1661 .Case("bonaire", GK_SEA_ISLANDS)
1662 .Case("kabini", GK_SEA_ISLANDS)
1663 .Case("kaveri", GK_SEA_ISLANDS)
1664 .Case("hawaii", GK_SEA_ISLANDS)
1665 .Case("mullins", GK_SEA_ISLANDS)
1666 .Default(GK_NONE);
1667
1668 if (GPU == GK_NONE) {
1669 return false;
1670 }
1671
1672 // Set the correct data layout
1673 switch (GPU) {
1674 case GK_NONE:
1675 case GK_R600:
1676 case GK_R700:
1677 case GK_EVERGREEN:
1678 case GK_NORTHERN_ISLANDS:
1679 DescriptionString = DescriptionStringR600;
1680 break;
1681 case GK_R600_DOUBLE_OPS:
1682 case GK_R700_DOUBLE_OPS:
1683 case GK_EVERGREEN_DOUBLE_OPS:
1684 case GK_CAYMAN:
1685 DescriptionString = DescriptionStringR600DoubleOps;
1686 break;
1687 case GK_SOUTHERN_ISLANDS:
1688 case GK_SEA_ISLANDS:
1689 DescriptionString = DescriptionStringSI;
1690 break;
1691 }
1692
1693 return true;
1694 }
1695};
1696
1697const Builtin::Info R600TargetInfo::BuiltinInfo[] = {
1698#define BUILTIN(ID, TYPE, ATTRS) \
1699 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1700#include "clang/Basic/BuiltinsR600.def"
1701};
1702
1703} // end anonymous namespace
1704
1705namespace {
1706// Namespace for x86 abstract base class
1707const Builtin::Info BuiltinInfo[] = {
1708#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1709#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1710 ALL_LANGUAGES },
1711#include "clang/Basic/BuiltinsX86.def"
1712};
1713
1714static const char* const GCCRegNames[] = {
1715 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1716 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1717 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1718 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1719 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1720 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1721 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1722 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1723 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1724};
1725
1726const TargetInfo::AddlRegName AddlRegNames[] = {
1727 { { "al", "ah", "eax", "rax" }, 0 },
1728 { { "bl", "bh", "ebx", "rbx" }, 3 },
1729 { { "cl", "ch", "ecx", "rcx" }, 2 },
1730 { { "dl", "dh", "edx", "rdx" }, 1 },
1731 { { "esi", "rsi" }, 4 },
1732 { { "edi", "rdi" }, 5 },
1733 { { "esp", "rsp" }, 7 },
1734 { { "ebp", "rbp" }, 6 },
1735};
1736
1737// X86 target abstract base class; x86-32 and x86-64 are very close, so
1738// most of the implementation can be shared.
1739class X86TargetInfo : public TargetInfo {
1740 enum X86SSEEnum {
1741 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
1742 } SSELevel;
1743 enum MMX3DNowEnum {
1744 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1745 } MMX3DNowLevel;
1746 enum XOPEnum {
1747 NoXOP,
1748 SSE4A,
1749 FMA4,
1750 XOP
1751 } XOPLevel;
1752
1753 bool HasAES;
1754 bool HasPCLMUL;
1755 bool HasLZCNT;
1756 bool HasRDRND;
1757 bool HasFSGSBASE;
1758 bool HasBMI;
1759 bool HasBMI2;
1760 bool HasPOPCNT;
1761 bool HasRTM;
1762 bool HasPRFCHW;
1763 bool HasRDSEED;
1764 bool HasADX;
1765 bool HasTBM;
1766 bool HasFMA;
1767 bool HasF16C;
1768 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW,
1769 HasAVX512VL;
1770 bool HasSHA;
1771 bool HasCX16;
1772
1773 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1774 ///
1775 /// Each enumeration represents a particular CPU supported by Clang. These
1776 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1777 enum CPUKind {
1778 CK_Generic,
1779
1780 /// \name i386
1781 /// i386-generation processors.
1782 //@{
1783 CK_i386,
1784 //@}
1785
1786 /// \name i486
1787 /// i486-generation processors.
1788 //@{
1789 CK_i486,
1790 CK_WinChipC6,
1791 CK_WinChip2,
1792 CK_C3,
1793 //@}
1794
1795 /// \name i586
1796 /// i586-generation processors, P5 microarchitecture based.
1797 //@{
1798 CK_i586,
1799 CK_Pentium,
1800 CK_PentiumMMX,
1801 //@}
1802
1803 /// \name i686
1804 /// i686-generation processors, P6 / Pentium M microarchitecture based.
1805 //@{
1806 CK_i686,
1807 CK_PentiumPro,
1808 CK_Pentium2,
1809 CK_Pentium3,
1810 CK_Pentium3M,
1811 CK_PentiumM,
1812 CK_C3_2,
1813
1814 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1815 /// Clang however has some logic to suport this.
1816 // FIXME: Warn, deprecate, and potentially remove this.
1817 CK_Yonah,
1818 //@}
1819
1820 /// \name Netburst
1821 /// Netburst microarchitecture based processors.
1822 //@{
1823 CK_Pentium4,
1824 CK_Pentium4M,
1825 CK_Prescott,
1826 CK_Nocona,
1827 //@}
1828
1829 /// \name Core
1830 /// Core microarchitecture based processors.
1831 //@{
1832 CK_Core2,
1833
1834 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1835 /// codename which GCC no longer accepts as an option to -march, but Clang
1836 /// has some logic for recognizing it.
1837 // FIXME: Warn, deprecate, and potentially remove this.
1838 CK_Penryn,
1839 //@}
1840
1841 /// \name Atom
1842 /// Atom processors
1843 //@{
1844 CK_Bonnell,
1845 CK_Silvermont,
1846 //@}
1847
1848 /// \name Nehalem
1849 /// Nehalem microarchitecture based processors.
1850 CK_Nehalem,
1851
1852 /// \name Westmere
1853 /// Westmere microarchitecture based processors.
1854 CK_Westmere,
1855
1856 /// \name Sandy Bridge
1857 /// Sandy Bridge microarchitecture based processors.
1858 CK_SandyBridge,
1859
1860 /// \name Ivy Bridge
1861 /// Ivy Bridge microarchitecture based processors.
1862 CK_IvyBridge,
1863
1864 /// \name Haswell
1865 /// Haswell microarchitecture based processors.
1866 CK_Haswell,
1867
1868 /// \name Broadwell
1869 /// Broadwell microarchitecture based processors.
1870 CK_Broadwell,
1871
1872 /// \name Skylake
1873 /// Skylake microarchitecture based processors.
1874 CK_Skylake,
1875
1876 /// \name Knights Landing
1877 /// Knights Landing processor.
1878 CK_KNL,
1879
1880 /// \name K6
1881 /// K6 architecture processors.
1882 //@{
1883 CK_K6,
1884 CK_K6_2,
1885 CK_K6_3,
1886 //@}
1887
1888 /// \name K7
1889 /// K7 architecture processors.
1890 //@{
1891 CK_Athlon,
1892 CK_AthlonThunderbird,
1893 CK_Athlon4,
1894 CK_AthlonXP,
1895 CK_AthlonMP,
1896 //@}
1897
1898 /// \name K8
1899 /// K8 architecture processors.
1900 //@{
1901 CK_Athlon64,
1902 CK_Athlon64SSE3,
1903 CK_AthlonFX,
1904 CK_K8,
1905 CK_K8SSE3,
1906 CK_Opteron,
1907 CK_OpteronSSE3,
1908 CK_AMDFAM10,
1909 //@}
1910
1911 /// \name Bobcat
1912 /// Bobcat architecture processors.
1913 //@{
1914 CK_BTVER1,
1915 CK_BTVER2,
1916 //@}
1917
1918 /// \name Bulldozer
1919 /// Bulldozer architecture processors.
1920 //@{
1921 CK_BDVER1,
1922 CK_BDVER2,
1923 CK_BDVER3,
1924 CK_BDVER4,
1925 //@}
1926
1927 /// This specification is deprecated and will be removed in the future.
1928 /// Users should prefer \see CK_K8.
1929 // FIXME: Warn on this when the CPU is set to it.
1930 //@{
1931 CK_x86_64,
1932 //@}
1933
1934 /// \name Geode
1935 /// Geode processors.
1936 //@{
1937 CK_Geode
1938 //@}
1939 } CPU;
1940
1941 enum FPMathKind {
1942 FP_Default,
1943 FP_SSE,
1944 FP_387
1945 } FPMath;
1946
1947public:
1948 X86TargetInfo(const llvm::Triple &Triple)
1949 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1950 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
1951 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false),
1952 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false),
1953 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false),
1954 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false),
1955 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false),
1956 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) {
1957 BigEndian = false;
1958 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1959 }
1960 unsigned getFloatEvalMethod() const override {
1961 // X87 evaluates with 80 bits "long double" precision.
1962 return SSELevel == NoSSE ? 2 : 0;
1963 }
1964 void getTargetBuiltins(const Builtin::Info *&Records,
1965 unsigned &NumRecords) const override {
1966 Records = BuiltinInfo;
1967 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1968 }
1969 void getGCCRegNames(const char * const *&Names,
1970 unsigned &NumNames) const override {
1971 Names = GCCRegNames;
1972 NumNames = llvm::array_lengthof(GCCRegNames);
1973 }
1974 void getGCCRegAliases(const GCCRegAlias *&Aliases,
1975 unsigned &NumAliases) const override {
1976 Aliases = nullptr;
1977 NumAliases = 0;
1978 }
1979 void getGCCAddlRegNames(const AddlRegName *&Names,
1980 unsigned &NumNames) const override {
1981 Names = AddlRegNames;
1982 NumNames = llvm::array_lengthof(AddlRegNames);
1983 }
1984 bool validateAsmConstraint(const char *&Name,
1985 TargetInfo::ConstraintInfo &info) const override;
1986
1987 bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
1988
1989 bool validateInputSize(StringRef Constraint, unsigned Size) const override;
1990
1991 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
1992
1993 std::string convertConstraint(const char *&Constraint) const override;
1994 const char *getClobbers() const override {
1995 return "~{dirflag},~{fpsr},~{flags}";
1996 }
1997 void getTargetDefines(const LangOptions &Opts,
1998 MacroBuilder &Builder) const override;
1999 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2000 bool Enabled);
2001 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2002 bool Enabled);
2003 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2004 bool Enabled);
2005 void setFeatureEnabled(llvm::StringMap<bool> &Features,
2006 StringRef Name, bool Enabled) const override {
2007 setFeatureEnabledImpl(Features, Name, Enabled);
2008 }
2009 // This exists purely to cut down on the number of virtual calls in
2010 // getDefaultFeatures which calls this repeatedly.
2011 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2012 StringRef Name, bool Enabled);
2013 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
2014 bool hasFeature(StringRef Feature) const override;
2015 bool handleTargetFeatures(std::vector<std::string> &Features,
2016 DiagnosticsEngine &Diags) override;
2017 StringRef getABI() const override {
2018 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2019 return "avx";
2020 else if (getTriple().getArch() == llvm::Triple::x86 &&
2021 MMX3DNowLevel == NoMMX3DNow)
2022 return "no-mmx";
2023 return "";
2024 }
2025 bool setCPU(const std::string &Name) override {
2026 CPU = llvm::StringSwitch<CPUKind>(Name)
2027 .Case("i386", CK_i386)
2028 .Case("i486", CK_i486)
2029 .Case("winchip-c6", CK_WinChipC6)
2030 .Case("winchip2", CK_WinChip2)
2031 .Case("c3", CK_C3)
2032 .Case("i586", CK_i586)
2033 .Case("pentium", CK_Pentium)
2034 .Case("pentium-mmx", CK_PentiumMMX)
2035 .Case("i686", CK_i686)
2036 .Case("pentiumpro", CK_PentiumPro)
2037 .Case("pentium2", CK_Pentium2)
2038 .Case("pentium3", CK_Pentium3)
2039 .Case("pentium3m", CK_Pentium3M)
2040 .Case("pentium-m", CK_PentiumM)
2041 .Case("c3-2", CK_C3_2)
2042 .Case("yonah", CK_Yonah)
2043 .Case("pentium4", CK_Pentium4)
2044 .Case("pentium4m", CK_Pentium4M)
2045 .Case("prescott", CK_Prescott)
2046 .Case("nocona", CK_Nocona)
2047 .Case("core2", CK_Core2)
2048 .Case("penryn", CK_Penryn)
2049 .Case("bonnell", CK_Bonnell)
2050 .Case("atom", CK_Bonnell) // Legacy name.
2051 .Case("silvermont", CK_Silvermont)
2052 .Case("slm", CK_Silvermont) // Legacy name.
2053 .Case("nehalem", CK_Nehalem)
2054 .Case("corei7", CK_Nehalem) // Legacy name.
2055 .Case("westmere", CK_Westmere)
2056 .Case("sandybridge", CK_SandyBridge)
2057 .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2058 .Case("ivybridge", CK_IvyBridge)
2059 .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2060 .Case("haswell", CK_Haswell)
2061 .Case("core-avx2", CK_Haswell) // Legacy name.
2062 .Case("broadwell", CK_Broadwell)
2063 .Case("skylake", CK_Skylake)
2064 .Case("skx", CK_Skylake) // Legacy name.
2065 .Case("knl", CK_KNL)
2066 .Case("k6", CK_K6)
2067 .Case("k6-2", CK_K6_2)
2068 .Case("k6-3", CK_K6_3)
2069 .Case("athlon", CK_Athlon)
2070 .Case("athlon-tbird", CK_AthlonThunderbird)
2071 .Case("athlon-4", CK_Athlon4)
2072 .Case("athlon-xp", CK_AthlonXP)
2073 .Case("athlon-mp", CK_AthlonMP)
2074 .Case("athlon64", CK_Athlon64)
2075 .Case("athlon64-sse3", CK_Athlon64SSE3)
2076 .Case("athlon-fx", CK_AthlonFX)
2077 .Case("k8", CK_K8)
2078 .Case("k8-sse3", CK_K8SSE3)
2079 .Case("opteron", CK_Opteron)
2080 .Case("opteron-sse3", CK_OpteronSSE3)
2081 .Case("barcelona", CK_AMDFAM10)
2082 .Case("amdfam10", CK_AMDFAM10)
2083 .Case("btver1", CK_BTVER1)
2084 .Case("btver2", CK_BTVER2)
2085 .Case("bdver1", CK_BDVER1)
2086 .Case("bdver2", CK_BDVER2)
2087 .Case("bdver3", CK_BDVER3)
2088 .Case("bdver4", CK_BDVER4)
2089 .Case("x86-64", CK_x86_64)
2090 .Case("geode", CK_Geode)
2091 .Default(CK_Generic);
2092
2093 // Perform any per-CPU checks necessary to determine if this CPU is
2094 // acceptable.
2095 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2096 // invalid without explaining *why*.
2097 switch (CPU) {
2098 case CK_Generic:
2099 // No processor selected!
2100 return false;
2101
2102 case CK_i386:
2103 case CK_i486:
2104 case CK_WinChipC6:
2105 case CK_WinChip2:
2106 case CK_C3:
2107 case CK_i586:
2108 case CK_Pentium:
2109 case CK_PentiumMMX:
2110 case CK_i686:
2111 case CK_PentiumPro:
2112 case CK_Pentium2:
2113 case CK_Pentium3:
2114 case CK_Pentium3M:
2115 case CK_PentiumM:
2116 case CK_Yonah:
2117 case CK_C3_2:
2118 case CK_Pentium4:
2119 case CK_Pentium4M:
2120 case CK_Prescott:
2121 case CK_K6:
2122 case CK_K6_2:
2123 case CK_K6_3:
2124 case CK_Athlon:
2125 case CK_AthlonThunderbird:
2126 case CK_Athlon4:
2127 case CK_AthlonXP:
2128 case CK_AthlonMP:
2129 case CK_Geode:
2130 // Only accept certain architectures when compiling in 32-bit mode.
2131 if (getTriple().getArch() != llvm::Triple::x86)
2132 return false;
2133
2134 // Fallthrough
2135 case CK_Nocona:
2136 case CK_Core2:
2137 case CK_Penryn:
2138 case CK_Bonnell:
2139 case CK_Silvermont:
2140 case CK_Nehalem:
2141 case CK_Westmere:
2142 case CK_SandyBridge:
2143 case CK_IvyBridge:
2144 case CK_Haswell:
2145 case CK_Broadwell:
2146 case CK_Skylake:
2147 case CK_KNL:
2148 case CK_Athlon64:
2149 case CK_Athlon64SSE3:
2150 case CK_AthlonFX:
2151 case CK_K8:
2152 case CK_K8SSE3:
2153 case CK_Opteron:
2154 case CK_OpteronSSE3:
2155 case CK_AMDFAM10:
2156 case CK_BTVER1:
2157 case CK_BTVER2:
2158 case CK_BDVER1:
2159 case CK_BDVER2:
2160 case CK_BDVER3:
2161 case CK_BDVER4:
2162 case CK_x86_64:
2163 return true;
2164 }
2165 llvm_unreachable("Unhandled CPU kind");
2166 }
2167
2168 bool setFPMath(StringRef Name) override;
2169
2170 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2171 // We accept all non-ARM calling conventions
2172 return (CC == CC_X86ThisCall ||
2173 CC == CC_X86FastCall ||
2174 CC == CC_X86StdCall ||
2175 CC == CC_X86VectorCall ||
2176 CC == CC_C ||
2177 CC == CC_X86Pascal ||
2178 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2179 }
2180
2181 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2182 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2183 }
| 927};
928
929const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
930#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
931#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
932 ALL_LANGUAGES },
933#include "clang/Basic/BuiltinsPPC.def"
934};
935
936/// handleTargetFeatures - Perform initialization based on the user
937/// configured set of features.
938bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
939 DiagnosticsEngine &Diags) {
940 for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
941 // Ignore disabled features.
942 if (Features[i][0] == '-')
943 continue;
944
945 StringRef Feature = StringRef(Features[i]).substr(1);
946
947 if (Feature == "vsx") {
948 HasVSX = true;
949 continue;
950 }
951
952 if (Feature == "power8-vector") {
953 HasP8Vector = true;
954 continue;
955 }
956
957 // TODO: Finish this list and add an assert that we've handled them
958 // all.
959 }
960
961 return true;
962}
963
964/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
965/// #defines that are not tied to a specific subtarget.
966void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
967 MacroBuilder &Builder) const {
968 // Target identification.
969 Builder.defineMacro("__ppc__");
970 Builder.defineMacro("__PPC__");
971 Builder.defineMacro("_ARCH_PPC");
972 Builder.defineMacro("__powerpc__");
973 Builder.defineMacro("__POWERPC__");
974 if (PointerWidth == 64) {
975 Builder.defineMacro("_ARCH_PPC64");
976 Builder.defineMacro("__powerpc64__");
977 Builder.defineMacro("__ppc64__");
978 Builder.defineMacro("__PPC64__");
979 }
980
981 // Target properties.
982 if (getTriple().getArch() == llvm::Triple::ppc64le) {
983 Builder.defineMacro("_LITTLE_ENDIAN");
984 } else {
985 if (getTriple().getOS() != llvm::Triple::NetBSD &&
986 getTriple().getOS() != llvm::Triple::OpenBSD)
987 Builder.defineMacro("_BIG_ENDIAN");
988 }
989
990 // ABI options.
991 if (ABI == "elfv1")
992 Builder.defineMacro("_CALL_ELF", "1");
993 if (ABI == "elfv2")
994 Builder.defineMacro("_CALL_ELF", "2");
995
996 // Subtarget options.
997 Builder.defineMacro("__NATURAL_ALIGNMENT__");
998 Builder.defineMacro("__REGISTER_PREFIX__", "");
999
1000 // FIXME: Should be controlled by command line option.
1001 if (LongDoubleWidth == 128)
1002 Builder.defineMacro("__LONG_DOUBLE_128__");
1003
1004 if (Opts.AltiVec) {
1005 Builder.defineMacro("__VEC__", "10206");
1006 Builder.defineMacro("__ALTIVEC__");
1007 }
1008
1009 // CPU identification.
1010 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1011 .Case("440", ArchDefineName)
1012 .Case("450", ArchDefineName | ArchDefine440)
1013 .Case("601", ArchDefineName)
1014 .Case("602", ArchDefineName | ArchDefinePpcgr)
1015 .Case("603", ArchDefineName | ArchDefinePpcgr)
1016 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1017 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1018 .Case("604", ArchDefineName | ArchDefinePpcgr)
1019 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1020 .Case("620", ArchDefineName | ArchDefinePpcgr)
1021 .Case("630", ArchDefineName | ArchDefinePpcgr)
1022 .Case("7400", ArchDefineName | ArchDefinePpcgr)
1023 .Case("7450", ArchDefineName | ArchDefinePpcgr)
1024 .Case("750", ArchDefineName | ArchDefinePpcgr)
1025 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1026 | ArchDefinePpcsq)
1027 .Case("a2", ArchDefineA2)
1028 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1029 .Case("pwr3", ArchDefinePpcgr)
1030 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1031 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1032 | ArchDefinePpcsq)
1033 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1034 | ArchDefinePpcgr | ArchDefinePpcsq)
1035 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1036 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1037 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1038 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1039 | ArchDefinePpcsq)
1040 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1041 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1042 | ArchDefinePpcgr | ArchDefinePpcsq)
1043 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1044 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1045 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1046 .Case("power3", ArchDefinePpcgr)
1047 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1048 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1049 | ArchDefinePpcsq)
1050 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1051 | ArchDefinePpcgr | ArchDefinePpcsq)
1052 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1053 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1054 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1055 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1056 | ArchDefinePpcsq)
1057 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1058 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1059 | ArchDefinePpcgr | ArchDefinePpcsq)
1060 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1061 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1062 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1063 .Default(ArchDefineNone);
1064
1065 if (defs & ArchDefineName)
1066 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1067 if (defs & ArchDefinePpcgr)
1068 Builder.defineMacro("_ARCH_PPCGR");
1069 if (defs & ArchDefinePpcsq)
1070 Builder.defineMacro("_ARCH_PPCSQ");
1071 if (defs & ArchDefine440)
1072 Builder.defineMacro("_ARCH_440");
1073 if (defs & ArchDefine603)
1074 Builder.defineMacro("_ARCH_603");
1075 if (defs & ArchDefine604)
1076 Builder.defineMacro("_ARCH_604");
1077 if (defs & ArchDefinePwr4)
1078 Builder.defineMacro("_ARCH_PWR4");
1079 if (defs & ArchDefinePwr5)
1080 Builder.defineMacro("_ARCH_PWR5");
1081 if (defs & ArchDefinePwr5x)
1082 Builder.defineMacro("_ARCH_PWR5X");
1083 if (defs & ArchDefinePwr6)
1084 Builder.defineMacro("_ARCH_PWR6");
1085 if (defs & ArchDefinePwr6x)
1086 Builder.defineMacro("_ARCH_PWR6X");
1087 if (defs & ArchDefinePwr7)
1088 Builder.defineMacro("_ARCH_PWR7");
1089 if (defs & ArchDefinePwr8)
1090 Builder.defineMacro("_ARCH_PWR8");
1091 if (defs & ArchDefineA2)
1092 Builder.defineMacro("_ARCH_A2");
1093 if (defs & ArchDefineA2q) {
1094 Builder.defineMacro("_ARCH_A2Q");
1095 Builder.defineMacro("_ARCH_QP");
1096 }
1097
1098 if (getTriple().getVendor() == llvm::Triple::BGQ) {
1099 Builder.defineMacro("__bg__");
1100 Builder.defineMacro("__THW_BLUEGENE__");
1101 Builder.defineMacro("__bgq__");
1102 Builder.defineMacro("__TOS_BGQ__");
1103 }
1104
1105 if (HasVSX)
1106 Builder.defineMacro("__VSX__");
1107 if (HasP8Vector)
1108 Builder.defineMacro("__POWER8_VECTOR__");
1109
1110 // FIXME: The following are not yet generated here by Clang, but are
1111 // generated by GCC:
1112 //
1113 // _SOFT_FLOAT_
1114 // __RECIP_PRECISION__
1115 // __APPLE_ALTIVEC__
1116 // __RECIP__
1117 // __RECIPF__
1118 // __RSQRTE__
1119 // __RSQRTEF__
1120 // _SOFT_DOUBLE_
1121 // __NO_LWSYNC__
1122 // __HAVE_BSWAP__
1123 // __LONGDOUBLE128
1124 // __CMODEL_MEDIUM__
1125 // __CMODEL_LARGE__
1126 // _CALL_SYSV
1127 // _CALL_DARWIN
1128 // __NO_FPRS__
1129}
1130
1131void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1132 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1133 .Case("7400", true)
1134 .Case("g4", true)
1135 .Case("7450", true)
1136 .Case("g4+", true)
1137 .Case("970", true)
1138 .Case("g5", true)
1139 .Case("pwr6", true)
1140 .Case("pwr7", true)
1141 .Case("pwr8", true)
1142 .Case("ppc64", true)
1143 .Case("ppc64le", true)
1144 .Default(false);
1145
1146 Features["qpx"] = (CPU == "a2q");
1147
1148 if (!ABI.empty())
1149 Features[ABI] = true;
1150}
1151
1152bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1153 return llvm::StringSwitch<bool>(Feature)
1154 .Case("powerpc", true)
1155 .Case("vsx", HasVSX)
1156 .Case("power8-vector", HasP8Vector)
1157 .Default(false);
1158}
1159
1160const char * const PPCTargetInfo::GCCRegNames[] = {
1161 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1162 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1163 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1164 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1165 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1166 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1167 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1168 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1169 "mq", "lr", "ctr", "ap",
1170 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1171 "xer",
1172 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1173 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1174 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1175 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1176 "vrsave", "vscr",
1177 "spe_acc", "spefscr",
1178 "sfp"
1179};
1180
1181void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1182 unsigned &NumNames) const {
1183 Names = GCCRegNames;
1184 NumNames = llvm::array_lengthof(GCCRegNames);
1185}
1186
1187const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1188 // While some of these aliases do map to different registers
1189 // they still share the same register name.
1190 { { "0" }, "r0" },
1191 { { "1"}, "r1" },
1192 { { "2" }, "r2" },
1193 { { "3" }, "r3" },
1194 { { "4" }, "r4" },
1195 { { "5" }, "r5" },
1196 { { "6" }, "r6" },
1197 { { "7" }, "r7" },
1198 { { "8" }, "r8" },
1199 { { "9" }, "r9" },
1200 { { "10" }, "r10" },
1201 { { "11" }, "r11" },
1202 { { "12" }, "r12" },
1203 { { "13" }, "r13" },
1204 { { "14" }, "r14" },
1205 { { "15" }, "r15" },
1206 { { "16" }, "r16" },
1207 { { "17" }, "r17" },
1208 { { "18" }, "r18" },
1209 { { "19" }, "r19" },
1210 { { "20" }, "r20" },
1211 { { "21" }, "r21" },
1212 { { "22" }, "r22" },
1213 { { "23" }, "r23" },
1214 { { "24" }, "r24" },
1215 { { "25" }, "r25" },
1216 { { "26" }, "r26" },
1217 { { "27" }, "r27" },
1218 { { "28" }, "r28" },
1219 { { "29" }, "r29" },
1220 { { "30" }, "r30" },
1221 { { "31" }, "r31" },
1222 { { "fr0" }, "f0" },
1223 { { "fr1" }, "f1" },
1224 { { "fr2" }, "f2" },
1225 { { "fr3" }, "f3" },
1226 { { "fr4" }, "f4" },
1227 { { "fr5" }, "f5" },
1228 { { "fr6" }, "f6" },
1229 { { "fr7" }, "f7" },
1230 { { "fr8" }, "f8" },
1231 { { "fr9" }, "f9" },
1232 { { "fr10" }, "f10" },
1233 { { "fr11" }, "f11" },
1234 { { "fr12" }, "f12" },
1235 { { "fr13" }, "f13" },
1236 { { "fr14" }, "f14" },
1237 { { "fr15" }, "f15" },
1238 { { "fr16" }, "f16" },
1239 { { "fr17" }, "f17" },
1240 { { "fr18" }, "f18" },
1241 { { "fr19" }, "f19" },
1242 { { "fr20" }, "f20" },
1243 { { "fr21" }, "f21" },
1244 { { "fr22" }, "f22" },
1245 { { "fr23" }, "f23" },
1246 { { "fr24" }, "f24" },
1247 { { "fr25" }, "f25" },
1248 { { "fr26" }, "f26" },
1249 { { "fr27" }, "f27" },
1250 { { "fr28" }, "f28" },
1251 { { "fr29" }, "f29" },
1252 { { "fr30" }, "f30" },
1253 { { "fr31" }, "f31" },
1254 { { "cc" }, "cr0" },
1255};
1256
1257void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1258 unsigned &NumAliases) const {
1259 Aliases = GCCRegAliases;
1260 NumAliases = llvm::array_lengthof(GCCRegAliases);
1261}
1262} // end anonymous namespace.
1263
1264namespace {
1265class PPC32TargetInfo : public PPCTargetInfo {
1266public:
1267 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1268 DescriptionString = "E-m:e-p:32:32-i64:64-n32";
1269
1270 switch (getTriple().getOS()) {
1271 case llvm::Triple::Linux:
1272 case llvm::Triple::FreeBSD:
1273 case llvm::Triple::NetBSD:
1274 SizeType = UnsignedInt;
1275 PtrDiffType = SignedInt;
1276 IntPtrType = SignedInt;
1277 break;
1278 default:
1279 break;
1280 }
1281
1282 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1283 LongDoubleWidth = LongDoubleAlign = 64;
1284 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1285 }
1286
1287 // PPC32 supports atomics up to 4 bytes.
1288 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1289 }
1290
1291 BuiltinVaListKind getBuiltinVaListKind() const override {
1292 // This is the ELF definition, and is overridden by the Darwin sub-target
1293 return TargetInfo::PowerABIBuiltinVaList;
1294 }
1295};
1296} // end anonymous namespace.
1297
1298// Note: ABI differences may eventually require us to have a separate
1299// TargetInfo for little endian.
1300namespace {
1301class PPC64TargetInfo : public PPCTargetInfo {
1302public:
1303 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1304 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1305 IntMaxType = SignedLong;
1306 Int64Type = SignedLong;
1307
1308 if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1309 DescriptionString = "e-m:e-i64:64-n32:64";
1310 ABI = "elfv2";
1311 } else {
1312 DescriptionString = "E-m:e-i64:64-n32:64";
1313 ABI = "elfv1";
1314 }
1315
1316 switch (getTriple().getOS()) {
1317 case llvm::Triple::FreeBSD:
1318 LongDoubleWidth = LongDoubleAlign = 64;
1319 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1320 break;
1321 case llvm::Triple::NetBSD:
1322 IntMaxType = SignedLongLong;
1323 Int64Type = SignedLongLong;
1324 break;
1325 default:
1326 break;
1327 }
1328
1329 // PPC64 supports atomics up to 8 bytes.
1330 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1331 }
1332 BuiltinVaListKind getBuiltinVaListKind() const override {
1333 return TargetInfo::CharPtrBuiltinVaList;
1334 }
1335 // PPC64 Linux-specifc ABI options.
1336 bool setABI(const std::string &Name) override {
1337 if (Name == "elfv1" || Name == "elfv2") {
1338 ABI = Name;
1339 return true;
1340 }
1341 return false;
1342 }
1343};
1344} // end anonymous namespace.
1345
1346
1347namespace {
1348class DarwinPPC32TargetInfo :
1349 public DarwinTargetInfo<PPC32TargetInfo> {
1350public:
1351 DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1352 : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1353 HasAlignMac68kSupport = true;
1354 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1355 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1356 LongLongAlign = 32;
1357 SuitableAlign = 128;
1358 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32";
1359 }
1360 BuiltinVaListKind getBuiltinVaListKind() const override {
1361 return TargetInfo::CharPtrBuiltinVaList;
1362 }
1363};
1364
1365class DarwinPPC64TargetInfo :
1366 public DarwinTargetInfo<PPC64TargetInfo> {
1367public:
1368 DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1369 : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1370 HasAlignMac68kSupport = true;
1371 SuitableAlign = 128;
1372 DescriptionString = "E-m:o-i64:64-n32:64";
1373 }
1374};
1375} // end anonymous namespace.
1376
1377namespace {
1378 static const unsigned NVPTXAddrSpaceMap[] = {
1379 1, // opencl_global
1380 3, // opencl_local
1381 4, // opencl_constant
1382 // FIXME: generic has to be added to the target
1383 0, // opencl_generic
1384 1, // cuda_device
1385 4, // cuda_constant
1386 3, // cuda_shared
1387 };
1388 class NVPTXTargetInfo : public TargetInfo {
1389 static const char * const GCCRegNames[];
1390 static const Builtin::Info BuiltinInfo[];
1391
1392 // The GPU profiles supported by the NVPTX backend
1393 enum GPUKind {
1394 GK_NONE,
1395 GK_SM20,
1396 GK_SM21,
1397 GK_SM30,
1398 GK_SM35,
1399 } GPU;
1400
1401 public:
1402 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1403 BigEndian = false;
1404 TLSSupported = false;
1405 LongWidth = LongAlign = 64;
1406 AddrSpaceMap = &NVPTXAddrSpaceMap;
1407 UseAddrSpaceMapMangling = true;
1408 // Define available target features
1409 // These must be defined in sorted order!
1410 NoAsmVariants = true;
1411 // Set the default GPU to sm20
1412 GPU = GK_SM20;
1413 }
1414 void getTargetDefines(const LangOptions &Opts,
1415 MacroBuilder &Builder) const override {
1416 Builder.defineMacro("__PTX__");
1417 Builder.defineMacro("__NVPTX__");
1418 if (Opts.CUDAIsDevice) {
1419 // Set __CUDA_ARCH__ for the GPU specified.
1420 std::string CUDAArchCode;
1421 switch (GPU) {
1422 case GK_SM20:
1423 CUDAArchCode = "200";
1424 break;
1425 case GK_SM21:
1426 CUDAArchCode = "210";
1427 break;
1428 case GK_SM30:
1429 CUDAArchCode = "300";
1430 break;
1431 case GK_SM35:
1432 CUDAArchCode = "350";
1433 break;
1434 default:
1435 llvm_unreachable("Unhandled target CPU");
1436 }
1437 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1438 }
1439 }
1440 void getTargetBuiltins(const Builtin::Info *&Records,
1441 unsigned &NumRecords) const override {
1442 Records = BuiltinInfo;
1443 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1444 }
1445 bool hasFeature(StringRef Feature) const override {
1446 return Feature == "ptx" || Feature == "nvptx";
1447 }
1448
1449 void getGCCRegNames(const char * const *&Names,
1450 unsigned &NumNames) const override;
1451 void getGCCRegAliases(const GCCRegAlias *&Aliases,
1452 unsigned &NumAliases) const override {
1453 // No aliases.
1454 Aliases = nullptr;
1455 NumAliases = 0;
1456 }
1457 bool
1458 validateAsmConstraint(const char *&Name,
1459 TargetInfo::ConstraintInfo &Info) const override {
1460 switch (*Name) {
1461 default: return false;
1462 case 'c':
1463 case 'h':
1464 case 'r':
1465 case 'l':
1466 case 'f':
1467 case 'd':
1468 Info.setAllowsRegister();
1469 return true;
1470 }
1471 }
1472 const char *getClobbers() const override {
1473 // FIXME: Is this really right?
1474 return "";
1475 }
1476 BuiltinVaListKind getBuiltinVaListKind() const override {
1477 // FIXME: implement
1478 return TargetInfo::CharPtrBuiltinVaList;
1479 }
1480 bool setCPU(const std::string &Name) override {
1481 GPU = llvm::StringSwitch<GPUKind>(Name)
1482 .Case("sm_20", GK_SM20)
1483 .Case("sm_21", GK_SM21)
1484 .Case("sm_30", GK_SM30)
1485 .Case("sm_35", GK_SM35)
1486 .Default(GK_NONE);
1487
1488 return GPU != GK_NONE;
1489 }
1490 };
1491
1492 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1493#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1494#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1495 ALL_LANGUAGES },
1496#include "clang/Basic/BuiltinsNVPTX.def"
1497 };
1498
1499 const char * const NVPTXTargetInfo::GCCRegNames[] = {
1500 "r0"
1501 };
1502
1503 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1504 unsigned &NumNames) const {
1505 Names = GCCRegNames;
1506 NumNames = llvm::array_lengthof(GCCRegNames);
1507 }
1508
1509 class NVPTX32TargetInfo : public NVPTXTargetInfo {
1510 public:
1511 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1512 PointerWidth = PointerAlign = 32;
1513 SizeType = PtrDiffType = TargetInfo::UnsignedInt;
1514 IntPtrType = TargetInfo::SignedInt;
1515 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1516 }
1517 };
1518
1519 class NVPTX64TargetInfo : public NVPTXTargetInfo {
1520 public:
1521 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1522 PointerWidth = PointerAlign = 64;
1523 SizeType = PtrDiffType = TargetInfo::UnsignedLongLong;
1524 IntPtrType = TargetInfo::SignedLongLong;
1525 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64";
1526 }
1527 };
1528}
1529
1530namespace {
1531
1532static const unsigned R600AddrSpaceMap[] = {
1533 1, // opencl_global
1534 3, // opencl_local
1535 2, // opencl_constant
1536 4, // opencl_generic
1537 1, // cuda_device
1538 2, // cuda_constant
1539 3 // cuda_shared
1540};
1541
1542// If you edit the description strings, make sure you update
1543// getPointerWidthV().
1544
1545static const char *DescriptionStringR600 =
1546 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1547 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1548
1549static const char *DescriptionStringR600DoubleOps =
1550 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1551 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1552
1553static const char *DescriptionStringSI =
1554 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1555 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1556 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1557
1558class R600TargetInfo : public TargetInfo {
1559 static const Builtin::Info BuiltinInfo[];
1560
1561 /// \brief The GPU profiles supported by the R600 target.
1562 enum GPUKind {
1563 GK_NONE,
1564 GK_R600,
1565 GK_R600_DOUBLE_OPS,
1566 GK_R700,
1567 GK_R700_DOUBLE_OPS,
1568 GK_EVERGREEN,
1569 GK_EVERGREEN_DOUBLE_OPS,
1570 GK_NORTHERN_ISLANDS,
1571 GK_CAYMAN,
1572 GK_SOUTHERN_ISLANDS,
1573 GK_SEA_ISLANDS
1574 } GPU;
1575
1576public:
1577 R600TargetInfo(const llvm::Triple &Triple)
1578 : TargetInfo(Triple), GPU(GK_R600) {
1579 DescriptionString = DescriptionStringR600;
1580 AddrSpaceMap = &R600AddrSpaceMap;
1581 UseAddrSpaceMapMangling = true;
1582 }
1583
1584 uint64_t getPointerWidthV(unsigned AddrSpace) const override {
1585 if (GPU <= GK_CAYMAN)
1586 return 32;
1587
1588 switch(AddrSpace) {
1589 default:
1590 return 64;
1591 case 0:
1592 case 3:
1593 case 5:
1594 return 32;
1595 }
1596 }
1597
1598 const char * getClobbers() const override {
1599 return "";
1600 }
1601
1602 void getGCCRegNames(const char * const *&Names,
1603 unsigned &numNames) const override {
1604 Names = nullptr;
1605 numNames = 0;
1606 }
1607
1608 void getGCCRegAliases(const GCCRegAlias *&Aliases,
1609 unsigned &NumAliases) const override {
1610 Aliases = nullptr;
1611 NumAliases = 0;
1612 }
1613
1614 bool validateAsmConstraint(const char *&Name,
1615 TargetInfo::ConstraintInfo &info) const override {
1616 return true;
1617 }
1618
1619 void getTargetBuiltins(const Builtin::Info *&Records,
1620 unsigned &NumRecords) const override {
1621 Records = BuiltinInfo;
1622 NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin;
1623 }
1624
1625 void getTargetDefines(const LangOptions &Opts,
1626 MacroBuilder &Builder) const override {
1627 Builder.defineMacro("__R600__");
1628 }
1629
1630 BuiltinVaListKind getBuiltinVaListKind() const override {
1631 return TargetInfo::CharPtrBuiltinVaList;
1632 }
1633
1634 bool setCPU(const std::string &Name) override {
1635 GPU = llvm::StringSwitch<GPUKind>(Name)
1636 .Case("r600" , GK_R600)
1637 .Case("rv610", GK_R600)
1638 .Case("rv620", GK_R600)
1639 .Case("rv630", GK_R600)
1640 .Case("rv635", GK_R600)
1641 .Case("rs780", GK_R600)
1642 .Case("rs880", GK_R600)
1643 .Case("rv670", GK_R600_DOUBLE_OPS)
1644 .Case("rv710", GK_R700)
1645 .Case("rv730", GK_R700)
1646 .Case("rv740", GK_R700_DOUBLE_OPS)
1647 .Case("rv770", GK_R700_DOUBLE_OPS)
1648 .Case("palm", GK_EVERGREEN)
1649 .Case("cedar", GK_EVERGREEN)
1650 .Case("sumo", GK_EVERGREEN)
1651 .Case("sumo2", GK_EVERGREEN)
1652 .Case("redwood", GK_EVERGREEN)
1653 .Case("juniper", GK_EVERGREEN)
1654 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
1655 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
1656 .Case("barts", GK_NORTHERN_ISLANDS)
1657 .Case("turks", GK_NORTHERN_ISLANDS)
1658 .Case("caicos", GK_NORTHERN_ISLANDS)
1659 .Case("cayman", GK_CAYMAN)
1660 .Case("aruba", GK_CAYMAN)
1661 .Case("tahiti", GK_SOUTHERN_ISLANDS)
1662 .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1663 .Case("verde", GK_SOUTHERN_ISLANDS)
1664 .Case("oland", GK_SOUTHERN_ISLANDS)
1665 .Case("hainan", GK_SOUTHERN_ISLANDS)
1666 .Case("bonaire", GK_SEA_ISLANDS)
1667 .Case("kabini", GK_SEA_ISLANDS)
1668 .Case("kaveri", GK_SEA_ISLANDS)
1669 .Case("hawaii", GK_SEA_ISLANDS)
1670 .Case("mullins", GK_SEA_ISLANDS)
1671 .Default(GK_NONE);
1672
1673 if (GPU == GK_NONE) {
1674 return false;
1675 }
1676
1677 // Set the correct data layout
1678 switch (GPU) {
1679 case GK_NONE:
1680 case GK_R600:
1681 case GK_R700:
1682 case GK_EVERGREEN:
1683 case GK_NORTHERN_ISLANDS:
1684 DescriptionString = DescriptionStringR600;
1685 break;
1686 case GK_R600_DOUBLE_OPS:
1687 case GK_R700_DOUBLE_OPS:
1688 case GK_EVERGREEN_DOUBLE_OPS:
1689 case GK_CAYMAN:
1690 DescriptionString = DescriptionStringR600DoubleOps;
1691 break;
1692 case GK_SOUTHERN_ISLANDS:
1693 case GK_SEA_ISLANDS:
1694 DescriptionString = DescriptionStringSI;
1695 break;
1696 }
1697
1698 return true;
1699 }
1700};
1701
1702const Builtin::Info R600TargetInfo::BuiltinInfo[] = {
1703#define BUILTIN(ID, TYPE, ATTRS) \
1704 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1705#include "clang/Basic/BuiltinsR600.def"
1706};
1707
1708} // end anonymous namespace
1709
1710namespace {
1711// Namespace for x86 abstract base class
1712const Builtin::Info BuiltinInfo[] = {
1713#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1714#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1715 ALL_LANGUAGES },
1716#include "clang/Basic/BuiltinsX86.def"
1717};
1718
1719static const char* const GCCRegNames[] = {
1720 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1721 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1722 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1723 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1724 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1725 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1726 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1727 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1728 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1729};
1730
1731const TargetInfo::AddlRegName AddlRegNames[] = {
1732 { { "al", "ah", "eax", "rax" }, 0 },
1733 { { "bl", "bh", "ebx", "rbx" }, 3 },
1734 { { "cl", "ch", "ecx", "rcx" }, 2 },
1735 { { "dl", "dh", "edx", "rdx" }, 1 },
1736 { { "esi", "rsi" }, 4 },
1737 { { "edi", "rdi" }, 5 },
1738 { { "esp", "rsp" }, 7 },
1739 { { "ebp", "rbp" }, 6 },
1740};
1741
1742// X86 target abstract base class; x86-32 and x86-64 are very close, so
1743// most of the implementation can be shared.
1744class X86TargetInfo : public TargetInfo {
1745 enum X86SSEEnum {
1746 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
1747 } SSELevel;
1748 enum MMX3DNowEnum {
1749 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1750 } MMX3DNowLevel;
1751 enum XOPEnum {
1752 NoXOP,
1753 SSE4A,
1754 FMA4,
1755 XOP
1756 } XOPLevel;
1757
1758 bool HasAES;
1759 bool HasPCLMUL;
1760 bool HasLZCNT;
1761 bool HasRDRND;
1762 bool HasFSGSBASE;
1763 bool HasBMI;
1764 bool HasBMI2;
1765 bool HasPOPCNT;
1766 bool HasRTM;
1767 bool HasPRFCHW;
1768 bool HasRDSEED;
1769 bool HasADX;
1770 bool HasTBM;
1771 bool HasFMA;
1772 bool HasF16C;
1773 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW,
1774 HasAVX512VL;
1775 bool HasSHA;
1776 bool HasCX16;
1777
1778 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1779 ///
1780 /// Each enumeration represents a particular CPU supported by Clang. These
1781 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1782 enum CPUKind {
1783 CK_Generic,
1784
1785 /// \name i386
1786 /// i386-generation processors.
1787 //@{
1788 CK_i386,
1789 //@}
1790
1791 /// \name i486
1792 /// i486-generation processors.
1793 //@{
1794 CK_i486,
1795 CK_WinChipC6,
1796 CK_WinChip2,
1797 CK_C3,
1798 //@}
1799
1800 /// \name i586
1801 /// i586-generation processors, P5 microarchitecture based.
1802 //@{
1803 CK_i586,
1804 CK_Pentium,
1805 CK_PentiumMMX,
1806 //@}
1807
1808 /// \name i686
1809 /// i686-generation processors, P6 / Pentium M microarchitecture based.
1810 //@{
1811 CK_i686,
1812 CK_PentiumPro,
1813 CK_Pentium2,
1814 CK_Pentium3,
1815 CK_Pentium3M,
1816 CK_PentiumM,
1817 CK_C3_2,
1818
1819 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1820 /// Clang however has some logic to suport this.
1821 // FIXME: Warn, deprecate, and potentially remove this.
1822 CK_Yonah,
1823 //@}
1824
1825 /// \name Netburst
1826 /// Netburst microarchitecture based processors.
1827 //@{
1828 CK_Pentium4,
1829 CK_Pentium4M,
1830 CK_Prescott,
1831 CK_Nocona,
1832 //@}
1833
1834 /// \name Core
1835 /// Core microarchitecture based processors.
1836 //@{
1837 CK_Core2,
1838
1839 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1840 /// codename which GCC no longer accepts as an option to -march, but Clang
1841 /// has some logic for recognizing it.
1842 // FIXME: Warn, deprecate, and potentially remove this.
1843 CK_Penryn,
1844 //@}
1845
1846 /// \name Atom
1847 /// Atom processors
1848 //@{
1849 CK_Bonnell,
1850 CK_Silvermont,
1851 //@}
1852
1853 /// \name Nehalem
1854 /// Nehalem microarchitecture based processors.
1855 CK_Nehalem,
1856
1857 /// \name Westmere
1858 /// Westmere microarchitecture based processors.
1859 CK_Westmere,
1860
1861 /// \name Sandy Bridge
1862 /// Sandy Bridge microarchitecture based processors.
1863 CK_SandyBridge,
1864
1865 /// \name Ivy Bridge
1866 /// Ivy Bridge microarchitecture based processors.
1867 CK_IvyBridge,
1868
1869 /// \name Haswell
1870 /// Haswell microarchitecture based processors.
1871 CK_Haswell,
1872
1873 /// \name Broadwell
1874 /// Broadwell microarchitecture based processors.
1875 CK_Broadwell,
1876
1877 /// \name Skylake
1878 /// Skylake microarchitecture based processors.
1879 CK_Skylake,
1880
1881 /// \name Knights Landing
1882 /// Knights Landing processor.
1883 CK_KNL,
1884
1885 /// \name K6
1886 /// K6 architecture processors.
1887 //@{
1888 CK_K6,
1889 CK_K6_2,
1890 CK_K6_3,
1891 //@}
1892
1893 /// \name K7
1894 /// K7 architecture processors.
1895 //@{
1896 CK_Athlon,
1897 CK_AthlonThunderbird,
1898 CK_Athlon4,
1899 CK_AthlonXP,
1900 CK_AthlonMP,
1901 //@}
1902
1903 /// \name K8
1904 /// K8 architecture processors.
1905 //@{
1906 CK_Athlon64,
1907 CK_Athlon64SSE3,
1908 CK_AthlonFX,
1909 CK_K8,
1910 CK_K8SSE3,
1911 CK_Opteron,
1912 CK_OpteronSSE3,
1913 CK_AMDFAM10,
1914 //@}
1915
1916 /// \name Bobcat
1917 /// Bobcat architecture processors.
1918 //@{
1919 CK_BTVER1,
1920 CK_BTVER2,
1921 //@}
1922
1923 /// \name Bulldozer
1924 /// Bulldozer architecture processors.
1925 //@{
1926 CK_BDVER1,
1927 CK_BDVER2,
1928 CK_BDVER3,
1929 CK_BDVER4,
1930 //@}
1931
1932 /// This specification is deprecated and will be removed in the future.
1933 /// Users should prefer \see CK_K8.
1934 // FIXME: Warn on this when the CPU is set to it.
1935 //@{
1936 CK_x86_64,
1937 //@}
1938
1939 /// \name Geode
1940 /// Geode processors.
1941 //@{
1942 CK_Geode
1943 //@}
1944 } CPU;
1945
1946 enum FPMathKind {
1947 FP_Default,
1948 FP_SSE,
1949 FP_387
1950 } FPMath;
1951
1952public:
1953 X86TargetInfo(const llvm::Triple &Triple)
1954 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1955 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
1956 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false),
1957 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false),
1958 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false),
1959 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false),
1960 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false),
1961 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) {
1962 BigEndian = false;
1963 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1964 }
1965 unsigned getFloatEvalMethod() const override {
1966 // X87 evaluates with 80 bits "long double" precision.
1967 return SSELevel == NoSSE ? 2 : 0;
1968 }
1969 void getTargetBuiltins(const Builtin::Info *&Records,
1970 unsigned &NumRecords) const override {
1971 Records = BuiltinInfo;
1972 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1973 }
1974 void getGCCRegNames(const char * const *&Names,
1975 unsigned &NumNames) const override {
1976 Names = GCCRegNames;
1977 NumNames = llvm::array_lengthof(GCCRegNames);
1978 }
1979 void getGCCRegAliases(const GCCRegAlias *&Aliases,
1980 unsigned &NumAliases) const override {
1981 Aliases = nullptr;
1982 NumAliases = 0;
1983 }
1984 void getGCCAddlRegNames(const AddlRegName *&Names,
1985 unsigned &NumNames) const override {
1986 Names = AddlRegNames;
1987 NumNames = llvm::array_lengthof(AddlRegNames);
1988 }
1989 bool validateAsmConstraint(const char *&Name,
1990 TargetInfo::ConstraintInfo &info) const override;
1991
1992 bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
1993
1994 bool validateInputSize(StringRef Constraint, unsigned Size) const override;
1995
1996 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
1997
1998 std::string convertConstraint(const char *&Constraint) const override;
1999 const char *getClobbers() const override {
2000 return "~{dirflag},~{fpsr},~{flags}";
2001 }
2002 void getTargetDefines(const LangOptions &Opts,
2003 MacroBuilder &Builder) const override;
2004 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2005 bool Enabled);
2006 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2007 bool Enabled);
2008 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2009 bool Enabled);
2010 void setFeatureEnabled(llvm::StringMap<bool> &Features,
2011 StringRef Name, bool Enabled) const override {
2012 setFeatureEnabledImpl(Features, Name, Enabled);
2013 }
2014 // This exists purely to cut down on the number of virtual calls in
2015 // getDefaultFeatures which calls this repeatedly.
2016 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2017 StringRef Name, bool Enabled);
2018 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
2019 bool hasFeature(StringRef Feature) const override;
2020 bool handleTargetFeatures(std::vector<std::string> &Features,
2021 DiagnosticsEngine &Diags) override;
2022 StringRef getABI() const override {
2023 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2024 return "avx";
2025 else if (getTriple().getArch() == llvm::Triple::x86 &&
2026 MMX3DNowLevel == NoMMX3DNow)
2027 return "no-mmx";
2028 return "";
2029 }
2030 bool setCPU(const std::string &Name) override {
2031 CPU = llvm::StringSwitch<CPUKind>(Name)
2032 .Case("i386", CK_i386)
2033 .Case("i486", CK_i486)
2034 .Case("winchip-c6", CK_WinChipC6)
2035 .Case("winchip2", CK_WinChip2)
2036 .Case("c3", CK_C3)
2037 .Case("i586", CK_i586)
2038 .Case("pentium", CK_Pentium)
2039 .Case("pentium-mmx", CK_PentiumMMX)
2040 .Case("i686", CK_i686)
2041 .Case("pentiumpro", CK_PentiumPro)
2042 .Case("pentium2", CK_Pentium2)
2043 .Case("pentium3", CK_Pentium3)
2044 .Case("pentium3m", CK_Pentium3M)
2045 .Case("pentium-m", CK_PentiumM)
2046 .Case("c3-2", CK_C3_2)
2047 .Case("yonah", CK_Yonah)
2048 .Case("pentium4", CK_Pentium4)
2049 .Case("pentium4m", CK_Pentium4M)
2050 .Case("prescott", CK_Prescott)
2051 .Case("nocona", CK_Nocona)
2052 .Case("core2", CK_Core2)
2053 .Case("penryn", CK_Penryn)
2054 .Case("bonnell", CK_Bonnell)
2055 .Case("atom", CK_Bonnell) // Legacy name.
2056 .Case("silvermont", CK_Silvermont)
2057 .Case("slm", CK_Silvermont) // Legacy name.
2058 .Case("nehalem", CK_Nehalem)
2059 .Case("corei7", CK_Nehalem) // Legacy name.
2060 .Case("westmere", CK_Westmere)
2061 .Case("sandybridge", CK_SandyBridge)
2062 .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2063 .Case("ivybridge", CK_IvyBridge)
2064 .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2065 .Case("haswell", CK_Haswell)
2066 .Case("core-avx2", CK_Haswell) // Legacy name.
2067 .Case("broadwell", CK_Broadwell)
2068 .Case("skylake", CK_Skylake)
2069 .Case("skx", CK_Skylake) // Legacy name.
2070 .Case("knl", CK_KNL)
2071 .Case("k6", CK_K6)
2072 .Case("k6-2", CK_K6_2)
2073 .Case("k6-3", CK_K6_3)
2074 .Case("athlon", CK_Athlon)
2075 .Case("athlon-tbird", CK_AthlonThunderbird)
2076 .Case("athlon-4", CK_Athlon4)
2077 .Case("athlon-xp", CK_AthlonXP)
2078 .Case("athlon-mp", CK_AthlonMP)
2079 .Case("athlon64", CK_Athlon64)
2080 .Case("athlon64-sse3", CK_Athlon64SSE3)
2081 .Case("athlon-fx", CK_AthlonFX)
2082 .Case("k8", CK_K8)
2083 .Case("k8-sse3", CK_K8SSE3)
2084 .Case("opteron", CK_Opteron)
2085 .Case("opteron-sse3", CK_OpteronSSE3)
2086 .Case("barcelona", CK_AMDFAM10)
2087 .Case("amdfam10", CK_AMDFAM10)
2088 .Case("btver1", CK_BTVER1)
2089 .Case("btver2", CK_BTVER2)
2090 .Case("bdver1", CK_BDVER1)
2091 .Case("bdver2", CK_BDVER2)
2092 .Case("bdver3", CK_BDVER3)
2093 .Case("bdver4", CK_BDVER4)
2094 .Case("x86-64", CK_x86_64)
2095 .Case("geode", CK_Geode)
2096 .Default(CK_Generic);
2097
2098 // Perform any per-CPU checks necessary to determine if this CPU is
2099 // acceptable.
2100 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2101 // invalid without explaining *why*.
2102 switch (CPU) {
2103 case CK_Generic:
2104 // No processor selected!
2105 return false;
2106
2107 case CK_i386:
2108 case CK_i486:
2109 case CK_WinChipC6:
2110 case CK_WinChip2:
2111 case CK_C3:
2112 case CK_i586:
2113 case CK_Pentium:
2114 case CK_PentiumMMX:
2115 case CK_i686:
2116 case CK_PentiumPro:
2117 case CK_Pentium2:
2118 case CK_Pentium3:
2119 case CK_Pentium3M:
2120 case CK_PentiumM:
2121 case CK_Yonah:
2122 case CK_C3_2:
2123 case CK_Pentium4:
2124 case CK_Pentium4M:
2125 case CK_Prescott:
2126 case CK_K6:
2127 case CK_K6_2:
2128 case CK_K6_3:
2129 case CK_Athlon:
2130 case CK_AthlonThunderbird:
2131 case CK_Athlon4:
2132 case CK_AthlonXP:
2133 case CK_AthlonMP:
2134 case CK_Geode:
2135 // Only accept certain architectures when compiling in 32-bit mode.
2136 if (getTriple().getArch() != llvm::Triple::x86)
2137 return false;
2138
2139 // Fallthrough
2140 case CK_Nocona:
2141 case CK_Core2:
2142 case CK_Penryn:
2143 case CK_Bonnell:
2144 case CK_Silvermont:
2145 case CK_Nehalem:
2146 case CK_Westmere:
2147 case CK_SandyBridge:
2148 case CK_IvyBridge:
2149 case CK_Haswell:
2150 case CK_Broadwell:
2151 case CK_Skylake:
2152 case CK_KNL:
2153 case CK_Athlon64:
2154 case CK_Athlon64SSE3:
2155 case CK_AthlonFX:
2156 case CK_K8:
2157 case CK_K8SSE3:
2158 case CK_Opteron:
2159 case CK_OpteronSSE3:
2160 case CK_AMDFAM10:
2161 case CK_BTVER1:
2162 case CK_BTVER2:
2163 case CK_BDVER1:
2164 case CK_BDVER2:
2165 case CK_BDVER3:
2166 case CK_BDVER4:
2167 case CK_x86_64:
2168 return true;
2169 }
2170 llvm_unreachable("Unhandled CPU kind");
2171 }
2172
2173 bool setFPMath(StringRef Name) override;
2174
2175 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2176 // We accept all non-ARM calling conventions
2177 return (CC == CC_X86ThisCall ||
2178 CC == CC_X86FastCall ||
2179 CC == CC_X86StdCall ||
2180 CC == CC_X86VectorCall ||
2181 CC == CC_C ||
2182 CC == CC_X86Pascal ||
2183 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2184 }
2185
2186 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2187 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2188 }
|
| 2189
2190 bool hasSjLjLowering() const override {
2191 return true;
2192 }
|
2184};
2185
2186bool X86TargetInfo::setFPMath(StringRef Name) {
2187 if (Name == "387") {
2188 FPMath = FP_387;
2189 return true;
2190 }
2191 if (Name == "sse") {
2192 FPMath = FP_SSE;
2193 return true;
2194 }
2195 return false;
2196}
2197
2198void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2199 // FIXME: This *really* should not be here.
2200
2201 // X86_64 always has SSE2.
2202 if (getTriple().getArch() == llvm::Triple::x86_64)
2203 setFeatureEnabledImpl(Features, "sse2", true);
2204
2205 switch (CPU) {
2206 case CK_Generic:
2207 case CK_i386:
2208 case CK_i486:
2209 case CK_i586:
2210 case CK_Pentium:
2211 case CK_i686:
2212 case CK_PentiumPro:
2213 break;
2214 case CK_PentiumMMX:
2215 case CK_Pentium2:
2216 case CK_K6:
2217 case CK_WinChipC6:
2218 setFeatureEnabledImpl(Features, "mmx", true);
2219 break;
2220 case CK_Pentium3:
2221 case CK_Pentium3M:
2222 case CK_C3_2:
2223 setFeatureEnabledImpl(Features, "sse", true);
2224 break;
2225 case CK_PentiumM:
2226 case CK_Pentium4:
2227 case CK_Pentium4M:
2228 case CK_x86_64:
2229 setFeatureEnabledImpl(Features, "sse2", true);
2230 break;
2231 case CK_Yonah:
2232 case CK_Prescott:
2233 case CK_Nocona:
2234 setFeatureEnabledImpl(Features, "sse3", true);
2235 setFeatureEnabledImpl(Features, "cx16", true);
2236 break;
2237 case CK_Core2:
2238 case CK_Bonnell:
2239 setFeatureEnabledImpl(Features, "ssse3", true);
2240 setFeatureEnabledImpl(Features, "cx16", true);
2241 break;
2242 case CK_Penryn:
2243 setFeatureEnabledImpl(Features, "sse4.1", true);
2244 setFeatureEnabledImpl(Features, "cx16", true);
2245 break;
2246 case CK_Skylake:
2247 setFeatureEnabledImpl(Features, "avx512f", true);
2248 setFeatureEnabledImpl(Features, "avx512cd", true);
2249 setFeatureEnabledImpl(Features, "avx512dq", true);
2250 setFeatureEnabledImpl(Features, "avx512bw", true);
2251 setFeatureEnabledImpl(Features, "avx512vl", true);
2252 // FALLTHROUGH
2253 case CK_Broadwell:
2254 setFeatureEnabledImpl(Features, "rdseed", true);
2255 setFeatureEnabledImpl(Features, "adx", true);
2256 // FALLTHROUGH
2257 case CK_Haswell:
2258 setFeatureEnabledImpl(Features, "avx2", true);
2259 setFeatureEnabledImpl(Features, "lzcnt", true);
2260 setFeatureEnabledImpl(Features, "bmi", true);
2261 setFeatureEnabledImpl(Features, "bmi2", true);
2262 setFeatureEnabledImpl(Features, "rtm", true);
2263 setFeatureEnabledImpl(Features, "fma", true);
2264 // FALLTHROUGH
2265 case CK_IvyBridge:
2266 setFeatureEnabledImpl(Features, "rdrnd", true);
2267 setFeatureEnabledImpl(Features, "f16c", true);
2268 setFeatureEnabledImpl(Features, "fsgsbase", true);
2269 // FALLTHROUGH
2270 case CK_SandyBridge:
2271 setFeatureEnabledImpl(Features, "avx", true);
2272 // FALLTHROUGH
2273 case CK_Westmere:
2274 case CK_Silvermont:
2275 setFeatureEnabledImpl(Features, "aes", true);
2276 setFeatureEnabledImpl(Features, "pclmul", true);
2277 // FALLTHROUGH
2278 case CK_Nehalem:
2279 setFeatureEnabledImpl(Features, "sse4.2", true);
2280 setFeatureEnabledImpl(Features, "cx16", true);
2281 break;
2282 case CK_KNL:
2283 setFeatureEnabledImpl(Features, "avx512f", true);
2284 setFeatureEnabledImpl(Features, "avx512cd", true);
2285 setFeatureEnabledImpl(Features, "avx512er", true);
2286 setFeatureEnabledImpl(Features, "avx512pf", true);
2287 setFeatureEnabledImpl(Features, "rdseed", true);
2288 setFeatureEnabledImpl(Features, "adx", true);
2289 setFeatureEnabledImpl(Features, "lzcnt", true);
2290 setFeatureEnabledImpl(Features, "bmi", true);
2291 setFeatureEnabledImpl(Features, "bmi2", true);
2292 setFeatureEnabledImpl(Features, "rtm", true);
2293 setFeatureEnabledImpl(Features, "fma", true);
2294 setFeatureEnabledImpl(Features, "rdrnd", true);
2295 setFeatureEnabledImpl(Features, "f16c", true);
2296 setFeatureEnabledImpl(Features, "fsgsbase", true);
2297 setFeatureEnabledImpl(Features, "aes", true);
2298 setFeatureEnabledImpl(Features, "pclmul", true);
2299 setFeatureEnabledImpl(Features, "cx16", true);
2300 break;
2301 case CK_K6_2:
2302 case CK_K6_3:
2303 case CK_WinChip2:
2304 case CK_C3:
2305 setFeatureEnabledImpl(Features, "3dnow", true);
2306 break;
2307 case CK_Athlon:
2308 case CK_AthlonThunderbird:
2309 case CK_Geode:
2310 setFeatureEnabledImpl(Features, "3dnowa", true);
2311 break;
2312 case CK_Athlon4:
2313 case CK_AthlonXP:
2314 case CK_AthlonMP:
2315 setFeatureEnabledImpl(Features, "sse", true);
2316 setFeatureEnabledImpl(Features, "3dnowa", true);
2317 break;
2318 case CK_K8:
2319 case CK_Opteron:
2320 case CK_Athlon64:
2321 case CK_AthlonFX:
2322 setFeatureEnabledImpl(Features, "sse2", true);
2323 setFeatureEnabledImpl(Features, "3dnowa", true);
2324 break;
2325 case CK_AMDFAM10:
2326 setFeatureEnabledImpl(Features, "sse4a", true);
2327 setFeatureEnabledImpl(Features, "lzcnt", true);
2328 setFeatureEnabledImpl(Features, "popcnt", true);
2329 // FALLTHROUGH
2330 case CK_K8SSE3:
2331 case CK_OpteronSSE3:
2332 case CK_Athlon64SSE3:
2333 setFeatureEnabledImpl(Features, "sse3", true);
2334 setFeatureEnabledImpl(Features, "3dnowa", true);
2335 break;
2336 case CK_BTVER2:
2337 setFeatureEnabledImpl(Features, "avx", true);
2338 setFeatureEnabledImpl(Features, "aes", true);
2339 setFeatureEnabledImpl(Features, "pclmul", true);
2340 setFeatureEnabledImpl(Features, "bmi", true);
2341 setFeatureEnabledImpl(Features, "f16c", true);
2342 // FALLTHROUGH
2343 case CK_BTVER1:
2344 setFeatureEnabledImpl(Features, "ssse3", true);
2345 setFeatureEnabledImpl(Features, "sse4a", true);
2346 setFeatureEnabledImpl(Features, "lzcnt", true);
2347 setFeatureEnabledImpl(Features, "popcnt", true);
2348 setFeatureEnabledImpl(Features, "prfchw", true);
2349 setFeatureEnabledImpl(Features, "cx16", true);
2350 break;
2351 case CK_BDVER4:
2352 setFeatureEnabledImpl(Features, "avx2", true);
2353 setFeatureEnabledImpl(Features, "bmi2", true);
2354 // FALLTHROUGH
2355 case CK_BDVER3:
2356 setFeatureEnabledImpl(Features, "fsgsbase", true);
2357 // FALLTHROUGH
2358 case CK_BDVER2:
2359 setFeatureEnabledImpl(Features, "bmi", true);
2360 setFeatureEnabledImpl(Features, "fma", true);
2361 setFeatureEnabledImpl(Features, "f16c", true);
2362 setFeatureEnabledImpl(Features, "tbm", true);
2363 // FALLTHROUGH
2364 case CK_BDVER1:
2365 // xop implies avx, sse4a and fma4.
2366 setFeatureEnabledImpl(Features, "xop", true);
2367 setFeatureEnabledImpl(Features, "lzcnt", true);
2368 setFeatureEnabledImpl(Features, "aes", true);
2369 setFeatureEnabledImpl(Features, "pclmul", true);
2370 setFeatureEnabledImpl(Features, "prfchw", true);
2371 setFeatureEnabledImpl(Features, "cx16", true);
2372 break;
2373 }
2374}
2375
2376void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2377 X86SSEEnum Level, bool Enabled) {
2378 if (Enabled) {
2379 switch (Level) {
2380 case AVX512F:
2381 Features["avx512f"] = true;
2382 case AVX2:
2383 Features["avx2"] = true;
2384 case AVX:
2385 Features["avx"] = true;
2386 case SSE42:
2387 Features["sse4.2"] = true;
2388 case SSE41:
2389 Features["sse4.1"] = true;
2390 case SSSE3:
2391 Features["ssse3"] = true;
2392 case SSE3:
2393 Features["sse3"] = true;
2394 case SSE2:
2395 Features["sse2"] = true;
2396 case SSE1:
2397 Features["sse"] = true;
2398 case NoSSE:
2399 break;
2400 }
2401 return;
2402 }
2403
2404 switch (Level) {
2405 case NoSSE:
2406 case SSE1:
2407 Features["sse"] = false;
2408 case SSE2:
2409 Features["sse2"] = Features["pclmul"] = Features["aes"] =
2410 Features["sha"] = false;
2411 case SSE3:
2412 Features["sse3"] = false;
2413 setXOPLevel(Features, NoXOP, false);
2414 case SSSE3:
2415 Features["ssse3"] = false;
2416 case SSE41:
2417 Features["sse4.1"] = false;
2418 case SSE42:
2419 Features["sse4.2"] = false;
2420 case AVX:
2421 Features["fma"] = Features["avx"] = Features["f16c"] = false;
2422 setXOPLevel(Features, FMA4, false);
2423 case AVX2:
2424 Features["avx2"] = false;
2425 case AVX512F:
2426 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2427 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
2428 Features["avx512vl"] = false;
2429 }
2430}
2431
2432void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2433 MMX3DNowEnum Level, bool Enabled) {
2434 if (Enabled) {
2435 switch (Level) {
2436 case AMD3DNowAthlon:
2437 Features["3dnowa"] = true;
2438 case AMD3DNow:
2439 Features["3dnow"] = true;
2440 case MMX:
2441 Features["mmx"] = true;
2442 case NoMMX3DNow:
2443 break;
2444 }
2445 return;
2446 }
2447
2448 switch (Level) {
2449 case NoMMX3DNow:
2450 case MMX:
2451 Features["mmx"] = false;
2452 case AMD3DNow:
2453 Features["3dnow"] = false;
2454 case AMD3DNowAthlon:
2455 Features["3dnowa"] = false;
2456 }
2457}
2458
2459void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2460 bool Enabled) {
2461 if (Enabled) {
2462 switch (Level) {
2463 case XOP:
2464 Features["xop"] = true;
2465 case FMA4:
2466 Features["fma4"] = true;
2467 setSSELevel(Features, AVX, true);
2468 case SSE4A:
2469 Features["sse4a"] = true;
2470 setSSELevel(Features, SSE3, true);
2471 case NoXOP:
2472 break;
2473 }
2474 return;
2475 }
2476
2477 switch (Level) {
2478 case NoXOP:
2479 case SSE4A:
2480 Features["sse4a"] = false;
2481 case FMA4:
2482 Features["fma4"] = false;
2483 case XOP:
2484 Features["xop"] = false;
2485 }
2486}
2487
2488void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2489 StringRef Name, bool Enabled) {
2490 // FIXME: This *really* should not be here. We need some way of translating
2491 // options into llvm subtarget features.
2492 if (Name == "sse4")
2493 Name = "sse4.2";
2494
2495 Features[Name] = Enabled;
2496
2497 if (Name == "mmx") {
2498 setMMXLevel(Features, MMX, Enabled);
2499 } else if (Name == "sse") {
2500 setSSELevel(Features, SSE1, Enabled);
2501 } else if (Name == "sse2") {
2502 setSSELevel(Features, SSE2, Enabled);
2503 } else if (Name == "sse3") {
2504 setSSELevel(Features, SSE3, Enabled);
2505 } else if (Name == "ssse3") {
2506 setSSELevel(Features, SSSE3, Enabled);
2507 } else if (Name == "sse4.2") {
2508 setSSELevel(Features, SSE42, Enabled);
2509 } else if (Name == "sse4.1") {
2510 setSSELevel(Features, SSE41, Enabled);
2511 } else if (Name == "3dnow") {
2512 setMMXLevel(Features, AMD3DNow, Enabled);
2513 } else if (Name == "3dnowa") {
2514 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2515 } else if (Name == "aes") {
2516 if (Enabled)
2517 setSSELevel(Features, SSE2, Enabled);
2518 } else if (Name == "pclmul") {
2519 if (Enabled)
2520 setSSELevel(Features, SSE2, Enabled);
2521 } else if (Name == "avx") {
2522 setSSELevel(Features, AVX, Enabled);
2523 } else if (Name == "avx2") {
2524 setSSELevel(Features, AVX2, Enabled);
2525 } else if (Name == "avx512f") {
2526 setSSELevel(Features, AVX512F, Enabled);
2527 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
2528 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
2529 if (Enabled)
2530 setSSELevel(Features, AVX512F, Enabled);
2531 } else if (Name == "fma") {
2532 if (Enabled)
2533 setSSELevel(Features, AVX, Enabled);
2534 } else if (Name == "fma4") {
2535 setXOPLevel(Features, FMA4, Enabled);
2536 } else if (Name == "xop") {
2537 setXOPLevel(Features, XOP, Enabled);
2538 } else if (Name == "sse4a") {
2539 setXOPLevel(Features, SSE4A, Enabled);
2540 } else if (Name == "f16c") {
2541 if (Enabled)
2542 setSSELevel(Features, AVX, Enabled);
2543 } else if (Name == "sha") {
2544 if (Enabled)
2545 setSSELevel(Features, SSE2, Enabled);
2546 }
2547}
2548
2549/// handleTargetFeatures - Perform initialization based on the user
2550/// configured set of features.
2551bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2552 DiagnosticsEngine &Diags) {
2553 // Remember the maximum enabled sselevel.
2554 for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2555 // Ignore disabled features.
2556 if (Features[i][0] == '-')
2557 continue;
2558
2559 StringRef Feature = StringRef(Features[i]).substr(1);
2560
2561 if (Feature == "aes") {
2562 HasAES = true;
2563 continue;
2564 }
2565
2566 if (Feature == "pclmul") {
2567 HasPCLMUL = true;
2568 continue;
2569 }
2570
2571 if (Feature == "lzcnt") {
2572 HasLZCNT = true;
2573 continue;
2574 }
2575
2576 if (Feature == "rdrnd") {
2577 HasRDRND = true;
2578 continue;
2579 }
2580
2581 if (Feature == "fsgsbase") {
2582 HasFSGSBASE = true;
2583 continue;
2584 }
2585
2586 if (Feature == "bmi") {
2587 HasBMI = true;
2588 continue;
2589 }
2590
2591 if (Feature == "bmi2") {
2592 HasBMI2 = true;
2593 continue;
2594 }
2595
2596 if (Feature == "popcnt") {
2597 HasPOPCNT = true;
2598 continue;
2599 }
2600
2601 if (Feature == "rtm") {
2602 HasRTM = true;
2603 continue;
2604 }
2605
2606 if (Feature == "prfchw") {
2607 HasPRFCHW = true;
2608 continue;
2609 }
2610
2611 if (Feature == "rdseed") {
2612 HasRDSEED = true;
2613 continue;
2614 }
2615
2616 if (Feature == "adx") {
2617 HasADX = true;
2618 continue;
2619 }
2620
2621 if (Feature == "tbm") {
2622 HasTBM = true;
2623 continue;
2624 }
2625
2626 if (Feature == "fma") {
2627 HasFMA = true;
2628 continue;
2629 }
2630
2631 if (Feature == "f16c") {
2632 HasF16C = true;
2633 continue;
2634 }
2635
2636 if (Feature == "avx512cd") {
2637 HasAVX512CD = true;
2638 continue;
2639 }
2640
2641 if (Feature == "avx512er") {
2642 HasAVX512ER = true;
2643 continue;
2644 }
2645
2646 if (Feature == "avx512pf") {
2647 HasAVX512PF = true;
2648 continue;
2649 }
2650
2651 if (Feature == "avx512dq") {
2652 HasAVX512DQ = true;
2653 continue;
2654 }
2655
2656 if (Feature == "avx512bw") {
2657 HasAVX512BW = true;
2658 continue;
2659 }
2660
2661 if (Feature == "avx512vl") {
2662 HasAVX512VL = true;
2663 continue;
2664 }
2665
2666 if (Feature == "sha") {
2667 HasSHA = true;
2668 continue;
2669 }
2670
2671 if (Feature == "cx16") {
2672 HasCX16 = true;
2673 continue;
2674 }
2675
2676 assert(Features[i][0] == '+' && "Invalid target feature!");
2677 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2678 .Case("avx512f", AVX512F)
2679 .Case("avx2", AVX2)
2680 .Case("avx", AVX)
2681 .Case("sse4.2", SSE42)
2682 .Case("sse4.1", SSE41)
2683 .Case("ssse3", SSSE3)
2684 .Case("sse3", SSE3)
2685 .Case("sse2", SSE2)
2686 .Case("sse", SSE1)
2687 .Default(NoSSE);
2688 SSELevel = std::max(SSELevel, Level);
2689
2690 MMX3DNowEnum ThreeDNowLevel =
2691 llvm::StringSwitch<MMX3DNowEnum>(Feature)
2692 .Case("3dnowa", AMD3DNowAthlon)
2693 .Case("3dnow", AMD3DNow)
2694 .Case("mmx", MMX)
2695 .Default(NoMMX3DNow);
2696 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2697
2698 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
2699 .Case("xop", XOP)
2700 .Case("fma4", FMA4)
2701 .Case("sse4a", SSE4A)
2702 .Default(NoXOP);
2703 XOPLevel = std::max(XOPLevel, XLevel);
2704 }
2705
2706 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2707 // Can't do this earlier because we need to be able to explicitly enable
2708 // popcnt and still disable sse4.2.
2709 if (!HasPOPCNT && SSELevel >= SSE42 &&
2710 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){
2711 HasPOPCNT = true;
2712 Features.push_back("+popcnt");
2713 }
2714
2715 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2716 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow &&
2717 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){
2718 HasPRFCHW = true;
2719 Features.push_back("+prfchw");
2720 }
2721
2722 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
2723 // matches the selected sse level.
2724 if (FPMath == FP_SSE && SSELevel < SSE1) {
2725 Diags.Report(diag::err_target_unsupported_fpmath) << "sse";
2726 return false;
2727 } else if (FPMath == FP_387 && SSELevel >= SSE1) {
2728 Diags.Report(diag::err_target_unsupported_fpmath) << "387";
2729 return false;
2730 }
2731
2732 // Don't tell the backend if we're turning off mmx; it will end up disabling
2733 // SSE, which we don't want.
2734 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2735 // then enable MMX.
2736 std::vector<std::string>::iterator it;
2737 it = std::find(Features.begin(), Features.end(), "-mmx");
2738 if (it != Features.end())
2739 Features.erase(it);
2740 else if (SSELevel > NoSSE)
2741 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
2742 return true;
2743}
2744
2745/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2746/// definitions for this particular subtarget.
2747void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2748 MacroBuilder &Builder) const {
2749 // Target identification.
2750 if (getTriple().getArch() == llvm::Triple::x86_64) {
2751 Builder.defineMacro("__amd64__");
2752 Builder.defineMacro("__amd64");
2753 Builder.defineMacro("__x86_64");
2754 Builder.defineMacro("__x86_64__");
2755 if (getTriple().getArchName() == "x86_64h") {
2756 Builder.defineMacro("__x86_64h");
2757 Builder.defineMacro("__x86_64h__");
2758 }
2759 } else {
2760 DefineStd(Builder, "i386", Opts);
2761 }
2762
2763 // Subtarget options.
2764 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2765 // truly should be based on -mtune options.
2766 switch (CPU) {
2767 case CK_Generic:
2768 break;
2769 case CK_i386:
2770 // The rest are coming from the i386 define above.
2771 Builder.defineMacro("__tune_i386__");
2772 break;
2773 case CK_i486:
2774 case CK_WinChipC6:
2775 case CK_WinChip2:
2776 case CK_C3:
2777 defineCPUMacros(Builder, "i486");
2778 break;
2779 case CK_PentiumMMX:
2780 Builder.defineMacro("__pentium_mmx__");
2781 Builder.defineMacro("__tune_pentium_mmx__");
2782 // Fallthrough
2783 case CK_i586:
2784 case CK_Pentium:
2785 defineCPUMacros(Builder, "i586");
2786 defineCPUMacros(Builder, "pentium");
2787 break;
2788 case CK_Pentium3:
2789 case CK_Pentium3M:
2790 case CK_PentiumM:
2791 Builder.defineMacro("__tune_pentium3__");
2792 // Fallthrough
2793 case CK_Pentium2:
2794 case CK_C3_2:
2795 Builder.defineMacro("__tune_pentium2__");
2796 // Fallthrough
2797 case CK_PentiumPro:
2798 Builder.defineMacro("__tune_i686__");
2799 Builder.defineMacro("__tune_pentiumpro__");
2800 // Fallthrough
2801 case CK_i686:
2802 Builder.defineMacro("__i686");
2803 Builder.defineMacro("__i686__");
2804 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2805 Builder.defineMacro("__pentiumpro");
2806 Builder.defineMacro("__pentiumpro__");
2807 break;
2808 case CK_Pentium4:
2809 case CK_Pentium4M:
2810 defineCPUMacros(Builder, "pentium4");
2811 break;
2812 case CK_Yonah:
2813 case CK_Prescott:
2814 case CK_Nocona:
2815 defineCPUMacros(Builder, "nocona");
2816 break;
2817 case CK_Core2:
2818 case CK_Penryn:
2819 defineCPUMacros(Builder, "core2");
2820 break;
2821 case CK_Bonnell:
2822 defineCPUMacros(Builder, "atom");
2823 break;
2824 case CK_Silvermont:
2825 defineCPUMacros(Builder, "slm");
2826 break;
2827 case CK_Nehalem:
2828 case CK_Westmere:
2829 case CK_SandyBridge:
2830 case CK_IvyBridge:
2831 case CK_Haswell:
2832 case CK_Broadwell:
2833 // FIXME: Historically, we defined this legacy name, it would be nice to
2834 // remove it at some point. We've never exposed fine-grained names for
2835 // recent primary x86 CPUs, and we should keep it that way.
2836 defineCPUMacros(Builder, "corei7");
2837 break;
2838 case CK_Skylake:
2839 // FIXME: Historically, we defined this legacy name, it would be nice to
2840 // remove it at some point. This is the only fine-grained CPU macro in the
2841 // main intel CPU line, and it would be better to not have these and force
2842 // people to use ISA macros.
2843 defineCPUMacros(Builder, "skx");
2844 break;
2845 case CK_KNL:
2846 defineCPUMacros(Builder, "knl");
2847 break;
2848 case CK_K6_2:
2849 Builder.defineMacro("__k6_2__");
2850 Builder.defineMacro("__tune_k6_2__");
2851 // Fallthrough
2852 case CK_K6_3:
2853 if (CPU != CK_K6_2) { // In case of fallthrough
2854 // FIXME: GCC may be enabling these in cases where some other k6
2855 // architecture is specified but -m3dnow is explicitly provided. The
2856 // exact semantics need to be determined and emulated here.
2857 Builder.defineMacro("__k6_3__");
2858 Builder.defineMacro("__tune_k6_3__");
2859 }
2860 // Fallthrough
2861 case CK_K6:
2862 defineCPUMacros(Builder, "k6");
2863 break;
2864 case CK_Athlon:
2865 case CK_AthlonThunderbird:
2866 case CK_Athlon4:
2867 case CK_AthlonXP:
2868 case CK_AthlonMP:
2869 defineCPUMacros(Builder, "athlon");
2870 if (SSELevel != NoSSE) {
2871 Builder.defineMacro("__athlon_sse__");
2872 Builder.defineMacro("__tune_athlon_sse__");
2873 }
2874 break;
2875 case CK_K8:
2876 case CK_K8SSE3:
2877 case CK_x86_64:
2878 case CK_Opteron:
2879 case CK_OpteronSSE3:
2880 case CK_Athlon64:
2881 case CK_Athlon64SSE3:
2882 case CK_AthlonFX:
2883 defineCPUMacros(Builder, "k8");
2884 break;
2885 case CK_AMDFAM10:
2886 defineCPUMacros(Builder, "amdfam10");
2887 break;
2888 case CK_BTVER1:
2889 defineCPUMacros(Builder, "btver1");
2890 break;
2891 case CK_BTVER2:
2892 defineCPUMacros(Builder, "btver2");
2893 break;
2894 case CK_BDVER1:
2895 defineCPUMacros(Builder, "bdver1");
2896 break;
2897 case CK_BDVER2:
2898 defineCPUMacros(Builder, "bdver2");
2899 break;
2900 case CK_BDVER3:
2901 defineCPUMacros(Builder, "bdver3");
2902 break;
2903 case CK_BDVER4:
2904 defineCPUMacros(Builder, "bdver4");
2905 break;
2906 case CK_Geode:
2907 defineCPUMacros(Builder, "geode");
2908 break;
2909 }
2910
2911 // Target properties.
2912 Builder.defineMacro("__REGISTER_PREFIX__", "");
2913
2914 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2915 // functions in glibc header files that use FP Stack inline asm which the
2916 // backend can't deal with (PR879).
2917 Builder.defineMacro("__NO_MATH_INLINES");
2918
2919 if (HasAES)
2920 Builder.defineMacro("__AES__");
2921
2922 if (HasPCLMUL)
2923 Builder.defineMacro("__PCLMUL__");
2924
2925 if (HasLZCNT)
2926 Builder.defineMacro("__LZCNT__");
2927
2928 if (HasRDRND)
2929 Builder.defineMacro("__RDRND__");
2930
2931 if (HasFSGSBASE)
2932 Builder.defineMacro("__FSGSBASE__");
2933
2934 if (HasBMI)
2935 Builder.defineMacro("__BMI__");
2936
2937 if (HasBMI2)
2938 Builder.defineMacro("__BMI2__");
2939
2940 if (HasPOPCNT)
2941 Builder.defineMacro("__POPCNT__");
2942
2943 if (HasRTM)
2944 Builder.defineMacro("__RTM__");
2945
2946 if (HasPRFCHW)
2947 Builder.defineMacro("__PRFCHW__");
2948
2949 if (HasRDSEED)
2950 Builder.defineMacro("__RDSEED__");
2951
2952 if (HasADX)
2953 Builder.defineMacro("__ADX__");
2954
2955 if (HasTBM)
2956 Builder.defineMacro("__TBM__");
2957
2958 switch (XOPLevel) {
2959 case XOP:
2960 Builder.defineMacro("__XOP__");
2961 case FMA4:
2962 Builder.defineMacro("__FMA4__");
2963 case SSE4A:
2964 Builder.defineMacro("__SSE4A__");
2965 case NoXOP:
2966 break;
2967 }
2968
2969 if (HasFMA)
2970 Builder.defineMacro("__FMA__");
2971
2972 if (HasF16C)
2973 Builder.defineMacro("__F16C__");
2974
2975 if (HasAVX512CD)
2976 Builder.defineMacro("__AVX512CD__");
2977 if (HasAVX512ER)
2978 Builder.defineMacro("__AVX512ER__");
2979 if (HasAVX512PF)
2980 Builder.defineMacro("__AVX512PF__");
2981 if (HasAVX512DQ)
2982 Builder.defineMacro("__AVX512DQ__");
2983 if (HasAVX512BW)
2984 Builder.defineMacro("__AVX512BW__");
2985 if (HasAVX512VL)
2986 Builder.defineMacro("__AVX512VL__");
2987
2988 if (HasSHA)
2989 Builder.defineMacro("__SHA__");
2990
2991 if (HasCX16)
2992 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
2993
2994 // Each case falls through to the previous one here.
2995 switch (SSELevel) {
2996 case AVX512F:
2997 Builder.defineMacro("__AVX512F__");
2998 case AVX2:
2999 Builder.defineMacro("__AVX2__");
3000 case AVX:
3001 Builder.defineMacro("__AVX__");
3002 case SSE42:
3003 Builder.defineMacro("__SSE4_2__");
3004 case SSE41:
3005 Builder.defineMacro("__SSE4_1__");
3006 case SSSE3:
3007 Builder.defineMacro("__SSSE3__");
3008 case SSE3:
3009 Builder.defineMacro("__SSE3__");
3010 case SSE2:
3011 Builder.defineMacro("__SSE2__");
3012 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
3013 case SSE1:
3014 Builder.defineMacro("__SSE__");
3015 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
3016 case NoSSE:
3017 break;
3018 }
3019
3020 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
3021 switch (SSELevel) {
3022 case AVX512F:
3023 case AVX2:
3024 case AVX:
3025 case SSE42:
3026 case SSE41:
3027 case SSSE3:
3028 case SSE3:
3029 case SSE2:
3030 Builder.defineMacro("_M_IX86_FP", Twine(2));
3031 break;
3032 case SSE1:
3033 Builder.defineMacro("_M_IX86_FP", Twine(1));
3034 break;
3035 default:
3036 Builder.defineMacro("_M_IX86_FP", Twine(0));
3037 }
3038 }
3039
3040 // Each case falls through to the previous one here.
3041 switch (MMX3DNowLevel) {
3042 case AMD3DNowAthlon:
3043 Builder.defineMacro("__3dNOW_A__");
3044 case AMD3DNow:
3045 Builder.defineMacro("__3dNOW__");
3046 case MMX:
3047 Builder.defineMacro("__MMX__");
3048 case NoMMX3DNow:
3049 break;
3050 }
3051
3052 if (CPU >= CK_i486) {
3053 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3054 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3055 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3056 }
3057 if (CPU >= CK_i586)
3058 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3059}
3060
3061bool X86TargetInfo::hasFeature(StringRef Feature) const {
3062 return llvm::StringSwitch<bool>(Feature)
3063 .Case("aes", HasAES)
3064 .Case("avx", SSELevel >= AVX)
3065 .Case("avx2", SSELevel >= AVX2)
3066 .Case("avx512f", SSELevel >= AVX512F)
3067 .Case("avx512cd", HasAVX512CD)
3068 .Case("avx512er", HasAVX512ER)
3069 .Case("avx512pf", HasAVX512PF)
3070 .Case("avx512dq", HasAVX512DQ)
3071 .Case("avx512bw", HasAVX512BW)
3072 .Case("avx512vl", HasAVX512VL)
3073 .Case("bmi", HasBMI)
3074 .Case("bmi2", HasBMI2)
3075 .Case("cx16", HasCX16)
3076 .Case("f16c", HasF16C)
3077 .Case("fma", HasFMA)
3078 .Case("fma4", XOPLevel >= FMA4)
3079 .Case("fsgsbase", HasFSGSBASE)
3080 .Case("lzcnt", HasLZCNT)
3081 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3082 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3083 .Case("mmx", MMX3DNowLevel >= MMX)
3084 .Case("pclmul", HasPCLMUL)
3085 .Case("popcnt", HasPOPCNT)
3086 .Case("prfchw", HasPRFCHW)
3087 .Case("rdrnd", HasRDRND)
3088 .Case("rdseed", HasRDSEED)
3089 .Case("rtm", HasRTM)
3090 .Case("sha", HasSHA)
3091 .Case("sse", SSELevel >= SSE1)
3092 .Case("sse2", SSELevel >= SSE2)
3093 .Case("sse3", SSELevel >= SSE3)
3094 .Case("ssse3", SSELevel >= SSSE3)
3095 .Case("sse4.1", SSELevel >= SSE41)
3096 .Case("sse4.2", SSELevel >= SSE42)
3097 .Case("sse4a", XOPLevel >= SSE4A)
3098 .Case("tbm", HasTBM)
3099 .Case("x86", true)
3100 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3101 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3102 .Case("xop", XOPLevel >= XOP)
3103 .Default(false);
3104}
3105
3106bool
3107X86TargetInfo::validateAsmConstraint(const char *&Name,
3108 TargetInfo::ConstraintInfo &Info) const {
3109 switch (*Name) {
3110 default: return false;
3111 case 'I':
3112 Info.setRequiresImmediate(0, 31);
3113 return true;
3114 case 'J':
3115 Info.setRequiresImmediate(0, 63);
3116 return true;
3117 case 'K':
3118 Info.setRequiresImmediate(-128, 127);
3119 return true;
3120 case 'L':
3121 // FIXME: properly analyze this constraint:
3122 // must be one of 0xff, 0xffff, or 0xffffffff
3123 return true;
3124 case 'M':
3125 Info.setRequiresImmediate(0, 3);
3126 return true;
3127 case 'N':
3128 Info.setRequiresImmediate(0, 255);
3129 return true;
3130 case 'O':
3131 Info.setRequiresImmediate(0, 127);
3132 return true;
3133 case 'Y': // first letter of a pair:
3134 switch (*(Name+1)) {
3135 default: return false;
3136 case '0': // First SSE register.
3137 case 't': // Any SSE register, when SSE2 is enabled.
3138 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
3139 case 'm': // any MMX register, when inter-unit moves enabled.
3140 break; // falls through to setAllowsRegister.
3141 }
3142 case 'f': // any x87 floating point stack register.
3143 // Constraint 'f' cannot be used for output operands.
3144 if (Info.ConstraintStr[0] == '=')
3145 return false;
3146
3147 Info.setAllowsRegister();
3148 return true;
3149 case 'a': // eax.
3150 case 'b': // ebx.
3151 case 'c': // ecx.
3152 case 'd': // edx.
3153 case 'S': // esi.
3154 case 'D': // edi.
3155 case 'A': // edx:eax.
3156 case 't': // top of floating point stack.
3157 case 'u': // second from top of floating point stack.
3158 case 'q': // Any register accessible as [r]l: a, b, c, and d.
3159 case 'y': // Any MMX register.
3160 case 'x': // Any SSE register.
3161 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
3162 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
3163 case 'l': // "Index" registers: any general register that can be used as an
3164 // index in a base+index memory access.
3165 Info.setAllowsRegister();
3166 return true;
3167 case 'C': // SSE floating point constant.
3168 case 'G': // x87 floating point constant.
3169 case 'e': // 32-bit signed integer constant for use with zero-extending
3170 // x86_64 instructions.
3171 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
3172 // x86_64 instructions.
3173 return true;
3174 }
3175}
3176
3177bool X86TargetInfo::validateOutputSize(StringRef Constraint,
3178 unsigned Size) const {
3179 // Strip off constraint modifiers.
3180 while (Constraint[0] == '=' ||
3181 Constraint[0] == '+' ||
3182 Constraint[0] == '&')
3183 Constraint = Constraint.substr(1);
3184
3185 return validateOperandSize(Constraint, Size);
3186}
3187
3188bool X86TargetInfo::validateInputSize(StringRef Constraint,
3189 unsigned Size) const {
3190 return validateOperandSize(Constraint, Size);
3191}
3192
3193bool X86TargetInfo::validateOperandSize(StringRef Constraint,
3194 unsigned Size) const {
3195 switch (Constraint[0]) {
3196 default: break;
3197 case 'y':
3198 return Size <= 64;
3199 case 'f':
3200 case 't':
3201 case 'u':
3202 return Size <= 128;
3203 case 'x':
3204 // 256-bit ymm registers can be used if target supports AVX.
3205 return Size <= (SSELevel >= AVX ? 256U : 128U);
3206 }
3207
3208 return true;
3209}
3210
3211std::string
3212X86TargetInfo::convertConstraint(const char *&Constraint) const {
3213 switch (*Constraint) {
3214 case 'a': return std::string("{ax}");
3215 case 'b': return std::string("{bx}");
3216 case 'c': return std::string("{cx}");
3217 case 'd': return std::string("{dx}");
3218 case 'S': return std::string("{si}");
3219 case 'D': return std::string("{di}");
3220 case 'p': // address
3221 return std::string("im");
3222 case 't': // top of floating point stack.
3223 return std::string("{st}");
3224 case 'u': // second from top of floating point stack.
3225 return std::string("{st(1)}"); // second from top of floating point stack.
3226 default:
3227 return std::string(1, *Constraint);
3228 }
3229}
3230} // end anonymous namespace
3231
3232namespace {
3233// X86-32 generic target
3234class X86_32TargetInfo : public X86TargetInfo {
3235public:
3236 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3237 DoubleAlign = LongLongAlign = 32;
3238 LongDoubleWidth = 96;
3239 LongDoubleAlign = 32;
3240 SuitableAlign = 128;
3241 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
3242 SizeType = UnsignedInt;
3243 PtrDiffType = SignedInt;
3244 IntPtrType = SignedInt;
3245 RegParmMax = 3;
3246
3247 // Use fpret for all types.
3248 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3249 (1 << TargetInfo::Double) |
3250 (1 << TargetInfo::LongDouble));
3251
3252 // x86-32 has atomics up to 8 bytes
3253 // FIXME: Check that we actually have cmpxchg8b before setting
3254 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3255 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3256 }
3257 BuiltinVaListKind getBuiltinVaListKind() const override {
3258 return TargetInfo::CharPtrBuiltinVaList;
3259 }
3260
3261 int getEHDataRegisterNumber(unsigned RegNo) const override {
3262 if (RegNo == 0) return 0;
3263 if (RegNo == 1) return 2;
3264 return -1;
3265 }
3266 bool validateOperandSize(StringRef Constraint,
3267 unsigned Size) const override {
3268 switch (Constraint[0]) {
3269 default: break;
3270 case 'R':
3271 case 'q':
3272 case 'Q':
3273 case 'a':
3274 case 'b':
3275 case 'c':
3276 case 'd':
3277 case 'S':
3278 case 'D':
3279 return Size <= 32;
3280 case 'A':
3281 return Size <= 64;
3282 }
3283
3284 return X86TargetInfo::validateOperandSize(Constraint, Size);
3285 }
3286};
3287} // end anonymous namespace
3288
3289namespace {
3290class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3291public:
3292 NetBSDI386TargetInfo(const llvm::Triple &Triple)
3293 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3294
3295 unsigned getFloatEvalMethod() const override {
3296 unsigned Major, Minor, Micro;
3297 getTriple().getOSVersion(Major, Minor, Micro);
3298 // New NetBSD uses the default rounding mode.
3299 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3300 return X86_32TargetInfo::getFloatEvalMethod();
3301 // NetBSD before 6.99.26 defaults to "double" rounding.
3302 return 1;
3303 }
3304};
3305} // end anonymous namespace
3306
3307namespace {
3308class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3309public:
3310 OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3311 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3312 SizeType = UnsignedLong;
3313 IntPtrType = SignedLong;
3314 PtrDiffType = SignedLong;
3315 }
3316};
3317} // end anonymous namespace
3318
3319namespace {
3320class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3321public:
3322 BitrigI386TargetInfo(const llvm::Triple &Triple)
3323 : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3324 SizeType = UnsignedLong;
3325 IntPtrType = SignedLong;
3326 PtrDiffType = SignedLong;
3327 }
3328};
3329} // end anonymous namespace
3330
3331namespace {
3332class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3333public:
3334 DarwinI386TargetInfo(const llvm::Triple &Triple)
3335 : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3336 LongDoubleWidth = 128;
3337 LongDoubleAlign = 128;
3338 SuitableAlign = 128;
3339 MaxVectorAlign = 256;
3340 SizeType = UnsignedLong;
3341 IntPtrType = SignedLong;
3342 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3343 HasAlignMac68kSupport = true;
3344 }
3345
3346};
3347} // end anonymous namespace
3348
3349namespace {
3350// x86-32 Windows target
3351class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3352public:
3353 WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3354 : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3355 WCharType = UnsignedShort;
3356 DoubleAlign = LongLongAlign = 64;
| 2193};
2194
2195bool X86TargetInfo::setFPMath(StringRef Name) {
2196 if (Name == "387") {
2197 FPMath = FP_387;
2198 return true;
2199 }
2200 if (Name == "sse") {
2201 FPMath = FP_SSE;
2202 return true;
2203 }
2204 return false;
2205}
2206
2207void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2208 // FIXME: This *really* should not be here.
2209
2210 // X86_64 always has SSE2.
2211 if (getTriple().getArch() == llvm::Triple::x86_64)
2212 setFeatureEnabledImpl(Features, "sse2", true);
2213
2214 switch (CPU) {
2215 case CK_Generic:
2216 case CK_i386:
2217 case CK_i486:
2218 case CK_i586:
2219 case CK_Pentium:
2220 case CK_i686:
2221 case CK_PentiumPro:
2222 break;
2223 case CK_PentiumMMX:
2224 case CK_Pentium2:
2225 case CK_K6:
2226 case CK_WinChipC6:
2227 setFeatureEnabledImpl(Features, "mmx", true);
2228 break;
2229 case CK_Pentium3:
2230 case CK_Pentium3M:
2231 case CK_C3_2:
2232 setFeatureEnabledImpl(Features, "sse", true);
2233 break;
2234 case CK_PentiumM:
2235 case CK_Pentium4:
2236 case CK_Pentium4M:
2237 case CK_x86_64:
2238 setFeatureEnabledImpl(Features, "sse2", true);
2239 break;
2240 case CK_Yonah:
2241 case CK_Prescott:
2242 case CK_Nocona:
2243 setFeatureEnabledImpl(Features, "sse3", true);
2244 setFeatureEnabledImpl(Features, "cx16", true);
2245 break;
2246 case CK_Core2:
2247 case CK_Bonnell:
2248 setFeatureEnabledImpl(Features, "ssse3", true);
2249 setFeatureEnabledImpl(Features, "cx16", true);
2250 break;
2251 case CK_Penryn:
2252 setFeatureEnabledImpl(Features, "sse4.1", true);
2253 setFeatureEnabledImpl(Features, "cx16", true);
2254 break;
2255 case CK_Skylake:
2256 setFeatureEnabledImpl(Features, "avx512f", true);
2257 setFeatureEnabledImpl(Features, "avx512cd", true);
2258 setFeatureEnabledImpl(Features, "avx512dq", true);
2259 setFeatureEnabledImpl(Features, "avx512bw", true);
2260 setFeatureEnabledImpl(Features, "avx512vl", true);
2261 // FALLTHROUGH
2262 case CK_Broadwell:
2263 setFeatureEnabledImpl(Features, "rdseed", true);
2264 setFeatureEnabledImpl(Features, "adx", true);
2265 // FALLTHROUGH
2266 case CK_Haswell:
2267 setFeatureEnabledImpl(Features, "avx2", true);
2268 setFeatureEnabledImpl(Features, "lzcnt", true);
2269 setFeatureEnabledImpl(Features, "bmi", true);
2270 setFeatureEnabledImpl(Features, "bmi2", true);
2271 setFeatureEnabledImpl(Features, "rtm", true);
2272 setFeatureEnabledImpl(Features, "fma", true);
2273 // FALLTHROUGH
2274 case CK_IvyBridge:
2275 setFeatureEnabledImpl(Features, "rdrnd", true);
2276 setFeatureEnabledImpl(Features, "f16c", true);
2277 setFeatureEnabledImpl(Features, "fsgsbase", true);
2278 // FALLTHROUGH
2279 case CK_SandyBridge:
2280 setFeatureEnabledImpl(Features, "avx", true);
2281 // FALLTHROUGH
2282 case CK_Westmere:
2283 case CK_Silvermont:
2284 setFeatureEnabledImpl(Features, "aes", true);
2285 setFeatureEnabledImpl(Features, "pclmul", true);
2286 // FALLTHROUGH
2287 case CK_Nehalem:
2288 setFeatureEnabledImpl(Features, "sse4.2", true);
2289 setFeatureEnabledImpl(Features, "cx16", true);
2290 break;
2291 case CK_KNL:
2292 setFeatureEnabledImpl(Features, "avx512f", true);
2293 setFeatureEnabledImpl(Features, "avx512cd", true);
2294 setFeatureEnabledImpl(Features, "avx512er", true);
2295 setFeatureEnabledImpl(Features, "avx512pf", true);
2296 setFeatureEnabledImpl(Features, "rdseed", true);
2297 setFeatureEnabledImpl(Features, "adx", true);
2298 setFeatureEnabledImpl(Features, "lzcnt", true);
2299 setFeatureEnabledImpl(Features, "bmi", true);
2300 setFeatureEnabledImpl(Features, "bmi2", true);
2301 setFeatureEnabledImpl(Features, "rtm", true);
2302 setFeatureEnabledImpl(Features, "fma", true);
2303 setFeatureEnabledImpl(Features, "rdrnd", true);
2304 setFeatureEnabledImpl(Features, "f16c", true);
2305 setFeatureEnabledImpl(Features, "fsgsbase", true);
2306 setFeatureEnabledImpl(Features, "aes", true);
2307 setFeatureEnabledImpl(Features, "pclmul", true);
2308 setFeatureEnabledImpl(Features, "cx16", true);
2309 break;
2310 case CK_K6_2:
2311 case CK_K6_3:
2312 case CK_WinChip2:
2313 case CK_C3:
2314 setFeatureEnabledImpl(Features, "3dnow", true);
2315 break;
2316 case CK_Athlon:
2317 case CK_AthlonThunderbird:
2318 case CK_Geode:
2319 setFeatureEnabledImpl(Features, "3dnowa", true);
2320 break;
2321 case CK_Athlon4:
2322 case CK_AthlonXP:
2323 case CK_AthlonMP:
2324 setFeatureEnabledImpl(Features, "sse", true);
2325 setFeatureEnabledImpl(Features, "3dnowa", true);
2326 break;
2327 case CK_K8:
2328 case CK_Opteron:
2329 case CK_Athlon64:
2330 case CK_AthlonFX:
2331 setFeatureEnabledImpl(Features, "sse2", true);
2332 setFeatureEnabledImpl(Features, "3dnowa", true);
2333 break;
2334 case CK_AMDFAM10:
2335 setFeatureEnabledImpl(Features, "sse4a", true);
2336 setFeatureEnabledImpl(Features, "lzcnt", true);
2337 setFeatureEnabledImpl(Features, "popcnt", true);
2338 // FALLTHROUGH
2339 case CK_K8SSE3:
2340 case CK_OpteronSSE3:
2341 case CK_Athlon64SSE3:
2342 setFeatureEnabledImpl(Features, "sse3", true);
2343 setFeatureEnabledImpl(Features, "3dnowa", true);
2344 break;
2345 case CK_BTVER2:
2346 setFeatureEnabledImpl(Features, "avx", true);
2347 setFeatureEnabledImpl(Features, "aes", true);
2348 setFeatureEnabledImpl(Features, "pclmul", true);
2349 setFeatureEnabledImpl(Features, "bmi", true);
2350 setFeatureEnabledImpl(Features, "f16c", true);
2351 // FALLTHROUGH
2352 case CK_BTVER1:
2353 setFeatureEnabledImpl(Features, "ssse3", true);
2354 setFeatureEnabledImpl(Features, "sse4a", true);
2355 setFeatureEnabledImpl(Features, "lzcnt", true);
2356 setFeatureEnabledImpl(Features, "popcnt", true);
2357 setFeatureEnabledImpl(Features, "prfchw", true);
2358 setFeatureEnabledImpl(Features, "cx16", true);
2359 break;
2360 case CK_BDVER4:
2361 setFeatureEnabledImpl(Features, "avx2", true);
2362 setFeatureEnabledImpl(Features, "bmi2", true);
2363 // FALLTHROUGH
2364 case CK_BDVER3:
2365 setFeatureEnabledImpl(Features, "fsgsbase", true);
2366 // FALLTHROUGH
2367 case CK_BDVER2:
2368 setFeatureEnabledImpl(Features, "bmi", true);
2369 setFeatureEnabledImpl(Features, "fma", true);
2370 setFeatureEnabledImpl(Features, "f16c", true);
2371 setFeatureEnabledImpl(Features, "tbm", true);
2372 // FALLTHROUGH
2373 case CK_BDVER1:
2374 // xop implies avx, sse4a and fma4.
2375 setFeatureEnabledImpl(Features, "xop", true);
2376 setFeatureEnabledImpl(Features, "lzcnt", true);
2377 setFeatureEnabledImpl(Features, "aes", true);
2378 setFeatureEnabledImpl(Features, "pclmul", true);
2379 setFeatureEnabledImpl(Features, "prfchw", true);
2380 setFeatureEnabledImpl(Features, "cx16", true);
2381 break;
2382 }
2383}
2384
2385void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2386 X86SSEEnum Level, bool Enabled) {
2387 if (Enabled) {
2388 switch (Level) {
2389 case AVX512F:
2390 Features["avx512f"] = true;
2391 case AVX2:
2392 Features["avx2"] = true;
2393 case AVX:
2394 Features["avx"] = true;
2395 case SSE42:
2396 Features["sse4.2"] = true;
2397 case SSE41:
2398 Features["sse4.1"] = true;
2399 case SSSE3:
2400 Features["ssse3"] = true;
2401 case SSE3:
2402 Features["sse3"] = true;
2403 case SSE2:
2404 Features["sse2"] = true;
2405 case SSE1:
2406 Features["sse"] = true;
2407 case NoSSE:
2408 break;
2409 }
2410 return;
2411 }
2412
2413 switch (Level) {
2414 case NoSSE:
2415 case SSE1:
2416 Features["sse"] = false;
2417 case SSE2:
2418 Features["sse2"] = Features["pclmul"] = Features["aes"] =
2419 Features["sha"] = false;
2420 case SSE3:
2421 Features["sse3"] = false;
2422 setXOPLevel(Features, NoXOP, false);
2423 case SSSE3:
2424 Features["ssse3"] = false;
2425 case SSE41:
2426 Features["sse4.1"] = false;
2427 case SSE42:
2428 Features["sse4.2"] = false;
2429 case AVX:
2430 Features["fma"] = Features["avx"] = Features["f16c"] = false;
2431 setXOPLevel(Features, FMA4, false);
2432 case AVX2:
2433 Features["avx2"] = false;
2434 case AVX512F:
2435 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2436 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
2437 Features["avx512vl"] = false;
2438 }
2439}
2440
2441void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2442 MMX3DNowEnum Level, bool Enabled) {
2443 if (Enabled) {
2444 switch (Level) {
2445 case AMD3DNowAthlon:
2446 Features["3dnowa"] = true;
2447 case AMD3DNow:
2448 Features["3dnow"] = true;
2449 case MMX:
2450 Features["mmx"] = true;
2451 case NoMMX3DNow:
2452 break;
2453 }
2454 return;
2455 }
2456
2457 switch (Level) {
2458 case NoMMX3DNow:
2459 case MMX:
2460 Features["mmx"] = false;
2461 case AMD3DNow:
2462 Features["3dnow"] = false;
2463 case AMD3DNowAthlon:
2464 Features["3dnowa"] = false;
2465 }
2466}
2467
2468void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2469 bool Enabled) {
2470 if (Enabled) {
2471 switch (Level) {
2472 case XOP:
2473 Features["xop"] = true;
2474 case FMA4:
2475 Features["fma4"] = true;
2476 setSSELevel(Features, AVX, true);
2477 case SSE4A:
2478 Features["sse4a"] = true;
2479 setSSELevel(Features, SSE3, true);
2480 case NoXOP:
2481 break;
2482 }
2483 return;
2484 }
2485
2486 switch (Level) {
2487 case NoXOP:
2488 case SSE4A:
2489 Features["sse4a"] = false;
2490 case FMA4:
2491 Features["fma4"] = false;
2492 case XOP:
2493 Features["xop"] = false;
2494 }
2495}
2496
2497void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2498 StringRef Name, bool Enabled) {
2499 // FIXME: This *really* should not be here. We need some way of translating
2500 // options into llvm subtarget features.
2501 if (Name == "sse4")
2502 Name = "sse4.2";
2503
2504 Features[Name] = Enabled;
2505
2506 if (Name == "mmx") {
2507 setMMXLevel(Features, MMX, Enabled);
2508 } else if (Name == "sse") {
2509 setSSELevel(Features, SSE1, Enabled);
2510 } else if (Name == "sse2") {
2511 setSSELevel(Features, SSE2, Enabled);
2512 } else if (Name == "sse3") {
2513 setSSELevel(Features, SSE3, Enabled);
2514 } else if (Name == "ssse3") {
2515 setSSELevel(Features, SSSE3, Enabled);
2516 } else if (Name == "sse4.2") {
2517 setSSELevel(Features, SSE42, Enabled);
2518 } else if (Name == "sse4.1") {
2519 setSSELevel(Features, SSE41, Enabled);
2520 } else if (Name == "3dnow") {
2521 setMMXLevel(Features, AMD3DNow, Enabled);
2522 } else if (Name == "3dnowa") {
2523 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2524 } else if (Name == "aes") {
2525 if (Enabled)
2526 setSSELevel(Features, SSE2, Enabled);
2527 } else if (Name == "pclmul") {
2528 if (Enabled)
2529 setSSELevel(Features, SSE2, Enabled);
2530 } else if (Name == "avx") {
2531 setSSELevel(Features, AVX, Enabled);
2532 } else if (Name == "avx2") {
2533 setSSELevel(Features, AVX2, Enabled);
2534 } else if (Name == "avx512f") {
2535 setSSELevel(Features, AVX512F, Enabled);
2536 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
2537 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
2538 if (Enabled)
2539 setSSELevel(Features, AVX512F, Enabled);
2540 } else if (Name == "fma") {
2541 if (Enabled)
2542 setSSELevel(Features, AVX, Enabled);
2543 } else if (Name == "fma4") {
2544 setXOPLevel(Features, FMA4, Enabled);
2545 } else if (Name == "xop") {
2546 setXOPLevel(Features, XOP, Enabled);
2547 } else if (Name == "sse4a") {
2548 setXOPLevel(Features, SSE4A, Enabled);
2549 } else if (Name == "f16c") {
2550 if (Enabled)
2551 setSSELevel(Features, AVX, Enabled);
2552 } else if (Name == "sha") {
2553 if (Enabled)
2554 setSSELevel(Features, SSE2, Enabled);
2555 }
2556}
2557
2558/// handleTargetFeatures - Perform initialization based on the user
2559/// configured set of features.
2560bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2561 DiagnosticsEngine &Diags) {
2562 // Remember the maximum enabled sselevel.
2563 for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2564 // Ignore disabled features.
2565 if (Features[i][0] == '-')
2566 continue;
2567
2568 StringRef Feature = StringRef(Features[i]).substr(1);
2569
2570 if (Feature == "aes") {
2571 HasAES = true;
2572 continue;
2573 }
2574
2575 if (Feature == "pclmul") {
2576 HasPCLMUL = true;
2577 continue;
2578 }
2579
2580 if (Feature == "lzcnt") {
2581 HasLZCNT = true;
2582 continue;
2583 }
2584
2585 if (Feature == "rdrnd") {
2586 HasRDRND = true;
2587 continue;
2588 }
2589
2590 if (Feature == "fsgsbase") {
2591 HasFSGSBASE = true;
2592 continue;
2593 }
2594
2595 if (Feature == "bmi") {
2596 HasBMI = true;
2597 continue;
2598 }
2599
2600 if (Feature == "bmi2") {
2601 HasBMI2 = true;
2602 continue;
2603 }
2604
2605 if (Feature == "popcnt") {
2606 HasPOPCNT = true;
2607 continue;
2608 }
2609
2610 if (Feature == "rtm") {
2611 HasRTM = true;
2612 continue;
2613 }
2614
2615 if (Feature == "prfchw") {
2616 HasPRFCHW = true;
2617 continue;
2618 }
2619
2620 if (Feature == "rdseed") {
2621 HasRDSEED = true;
2622 continue;
2623 }
2624
2625 if (Feature == "adx") {
2626 HasADX = true;
2627 continue;
2628 }
2629
2630 if (Feature == "tbm") {
2631 HasTBM = true;
2632 continue;
2633 }
2634
2635 if (Feature == "fma") {
2636 HasFMA = true;
2637 continue;
2638 }
2639
2640 if (Feature == "f16c") {
2641 HasF16C = true;
2642 continue;
2643 }
2644
2645 if (Feature == "avx512cd") {
2646 HasAVX512CD = true;
2647 continue;
2648 }
2649
2650 if (Feature == "avx512er") {
2651 HasAVX512ER = true;
2652 continue;
2653 }
2654
2655 if (Feature == "avx512pf") {
2656 HasAVX512PF = true;
2657 continue;
2658 }
2659
2660 if (Feature == "avx512dq") {
2661 HasAVX512DQ = true;
2662 continue;
2663 }
2664
2665 if (Feature == "avx512bw") {
2666 HasAVX512BW = true;
2667 continue;
2668 }
2669
2670 if (Feature == "avx512vl") {
2671 HasAVX512VL = true;
2672 continue;
2673 }
2674
2675 if (Feature == "sha") {
2676 HasSHA = true;
2677 continue;
2678 }
2679
2680 if (Feature == "cx16") {
2681 HasCX16 = true;
2682 continue;
2683 }
2684
2685 assert(Features[i][0] == '+' && "Invalid target feature!");
2686 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2687 .Case("avx512f", AVX512F)
2688 .Case("avx2", AVX2)
2689 .Case("avx", AVX)
2690 .Case("sse4.2", SSE42)
2691 .Case("sse4.1", SSE41)
2692 .Case("ssse3", SSSE3)
2693 .Case("sse3", SSE3)
2694 .Case("sse2", SSE2)
2695 .Case("sse", SSE1)
2696 .Default(NoSSE);
2697 SSELevel = std::max(SSELevel, Level);
2698
2699 MMX3DNowEnum ThreeDNowLevel =
2700 llvm::StringSwitch<MMX3DNowEnum>(Feature)
2701 .Case("3dnowa", AMD3DNowAthlon)
2702 .Case("3dnow", AMD3DNow)
2703 .Case("mmx", MMX)
2704 .Default(NoMMX3DNow);
2705 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2706
2707 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
2708 .Case("xop", XOP)
2709 .Case("fma4", FMA4)
2710 .Case("sse4a", SSE4A)
2711 .Default(NoXOP);
2712 XOPLevel = std::max(XOPLevel, XLevel);
2713 }
2714
2715 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2716 // Can't do this earlier because we need to be able to explicitly enable
2717 // popcnt and still disable sse4.2.
2718 if (!HasPOPCNT && SSELevel >= SSE42 &&
2719 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){
2720 HasPOPCNT = true;
2721 Features.push_back("+popcnt");
2722 }
2723
2724 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2725 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow &&
2726 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){
2727 HasPRFCHW = true;
2728 Features.push_back("+prfchw");
2729 }
2730
2731 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
2732 // matches the selected sse level.
2733 if (FPMath == FP_SSE && SSELevel < SSE1) {
2734 Diags.Report(diag::err_target_unsupported_fpmath) << "sse";
2735 return false;
2736 } else if (FPMath == FP_387 && SSELevel >= SSE1) {
2737 Diags.Report(diag::err_target_unsupported_fpmath) << "387";
2738 return false;
2739 }
2740
2741 // Don't tell the backend if we're turning off mmx; it will end up disabling
2742 // SSE, which we don't want.
2743 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2744 // then enable MMX.
2745 std::vector<std::string>::iterator it;
2746 it = std::find(Features.begin(), Features.end(), "-mmx");
2747 if (it != Features.end())
2748 Features.erase(it);
2749 else if (SSELevel > NoSSE)
2750 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
2751 return true;
2752}
2753
2754/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2755/// definitions for this particular subtarget.
2756void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2757 MacroBuilder &Builder) const {
2758 // Target identification.
2759 if (getTriple().getArch() == llvm::Triple::x86_64) {
2760 Builder.defineMacro("__amd64__");
2761 Builder.defineMacro("__amd64");
2762 Builder.defineMacro("__x86_64");
2763 Builder.defineMacro("__x86_64__");
2764 if (getTriple().getArchName() == "x86_64h") {
2765 Builder.defineMacro("__x86_64h");
2766 Builder.defineMacro("__x86_64h__");
2767 }
2768 } else {
2769 DefineStd(Builder, "i386", Opts);
2770 }
2771
2772 // Subtarget options.
2773 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2774 // truly should be based on -mtune options.
2775 switch (CPU) {
2776 case CK_Generic:
2777 break;
2778 case CK_i386:
2779 // The rest are coming from the i386 define above.
2780 Builder.defineMacro("__tune_i386__");
2781 break;
2782 case CK_i486:
2783 case CK_WinChipC6:
2784 case CK_WinChip2:
2785 case CK_C3:
2786 defineCPUMacros(Builder, "i486");
2787 break;
2788 case CK_PentiumMMX:
2789 Builder.defineMacro("__pentium_mmx__");
2790 Builder.defineMacro("__tune_pentium_mmx__");
2791 // Fallthrough
2792 case CK_i586:
2793 case CK_Pentium:
2794 defineCPUMacros(Builder, "i586");
2795 defineCPUMacros(Builder, "pentium");
2796 break;
2797 case CK_Pentium3:
2798 case CK_Pentium3M:
2799 case CK_PentiumM:
2800 Builder.defineMacro("__tune_pentium3__");
2801 // Fallthrough
2802 case CK_Pentium2:
2803 case CK_C3_2:
2804 Builder.defineMacro("__tune_pentium2__");
2805 // Fallthrough
2806 case CK_PentiumPro:
2807 Builder.defineMacro("__tune_i686__");
2808 Builder.defineMacro("__tune_pentiumpro__");
2809 // Fallthrough
2810 case CK_i686:
2811 Builder.defineMacro("__i686");
2812 Builder.defineMacro("__i686__");
2813 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2814 Builder.defineMacro("__pentiumpro");
2815 Builder.defineMacro("__pentiumpro__");
2816 break;
2817 case CK_Pentium4:
2818 case CK_Pentium4M:
2819 defineCPUMacros(Builder, "pentium4");
2820 break;
2821 case CK_Yonah:
2822 case CK_Prescott:
2823 case CK_Nocona:
2824 defineCPUMacros(Builder, "nocona");
2825 break;
2826 case CK_Core2:
2827 case CK_Penryn:
2828 defineCPUMacros(Builder, "core2");
2829 break;
2830 case CK_Bonnell:
2831 defineCPUMacros(Builder, "atom");
2832 break;
2833 case CK_Silvermont:
2834 defineCPUMacros(Builder, "slm");
2835 break;
2836 case CK_Nehalem:
2837 case CK_Westmere:
2838 case CK_SandyBridge:
2839 case CK_IvyBridge:
2840 case CK_Haswell:
2841 case CK_Broadwell:
2842 // FIXME: Historically, we defined this legacy name, it would be nice to
2843 // remove it at some point. We've never exposed fine-grained names for
2844 // recent primary x86 CPUs, and we should keep it that way.
2845 defineCPUMacros(Builder, "corei7");
2846 break;
2847 case CK_Skylake:
2848 // FIXME: Historically, we defined this legacy name, it would be nice to
2849 // remove it at some point. This is the only fine-grained CPU macro in the
2850 // main intel CPU line, and it would be better to not have these and force
2851 // people to use ISA macros.
2852 defineCPUMacros(Builder, "skx");
2853 break;
2854 case CK_KNL:
2855 defineCPUMacros(Builder, "knl");
2856 break;
2857 case CK_K6_2:
2858 Builder.defineMacro("__k6_2__");
2859 Builder.defineMacro("__tune_k6_2__");
2860 // Fallthrough
2861 case CK_K6_3:
2862 if (CPU != CK_K6_2) { // In case of fallthrough
2863 // FIXME: GCC may be enabling these in cases where some other k6
2864 // architecture is specified but -m3dnow is explicitly provided. The
2865 // exact semantics need to be determined and emulated here.
2866 Builder.defineMacro("__k6_3__");
2867 Builder.defineMacro("__tune_k6_3__");
2868 }
2869 // Fallthrough
2870 case CK_K6:
2871 defineCPUMacros(Builder, "k6");
2872 break;
2873 case CK_Athlon:
2874 case CK_AthlonThunderbird:
2875 case CK_Athlon4:
2876 case CK_AthlonXP:
2877 case CK_AthlonMP:
2878 defineCPUMacros(Builder, "athlon");
2879 if (SSELevel != NoSSE) {
2880 Builder.defineMacro("__athlon_sse__");
2881 Builder.defineMacro("__tune_athlon_sse__");
2882 }
2883 break;
2884 case CK_K8:
2885 case CK_K8SSE3:
2886 case CK_x86_64:
2887 case CK_Opteron:
2888 case CK_OpteronSSE3:
2889 case CK_Athlon64:
2890 case CK_Athlon64SSE3:
2891 case CK_AthlonFX:
2892 defineCPUMacros(Builder, "k8");
2893 break;
2894 case CK_AMDFAM10:
2895 defineCPUMacros(Builder, "amdfam10");
2896 break;
2897 case CK_BTVER1:
2898 defineCPUMacros(Builder, "btver1");
2899 break;
2900 case CK_BTVER2:
2901 defineCPUMacros(Builder, "btver2");
2902 break;
2903 case CK_BDVER1:
2904 defineCPUMacros(Builder, "bdver1");
2905 break;
2906 case CK_BDVER2:
2907 defineCPUMacros(Builder, "bdver2");
2908 break;
2909 case CK_BDVER3:
2910 defineCPUMacros(Builder, "bdver3");
2911 break;
2912 case CK_BDVER4:
2913 defineCPUMacros(Builder, "bdver4");
2914 break;
2915 case CK_Geode:
2916 defineCPUMacros(Builder, "geode");
2917 break;
2918 }
2919
2920 // Target properties.
2921 Builder.defineMacro("__REGISTER_PREFIX__", "");
2922
2923 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2924 // functions in glibc header files that use FP Stack inline asm which the
2925 // backend can't deal with (PR879).
2926 Builder.defineMacro("__NO_MATH_INLINES");
2927
2928 if (HasAES)
2929 Builder.defineMacro("__AES__");
2930
2931 if (HasPCLMUL)
2932 Builder.defineMacro("__PCLMUL__");
2933
2934 if (HasLZCNT)
2935 Builder.defineMacro("__LZCNT__");
2936
2937 if (HasRDRND)
2938 Builder.defineMacro("__RDRND__");
2939
2940 if (HasFSGSBASE)
2941 Builder.defineMacro("__FSGSBASE__");
2942
2943 if (HasBMI)
2944 Builder.defineMacro("__BMI__");
2945
2946 if (HasBMI2)
2947 Builder.defineMacro("__BMI2__");
2948
2949 if (HasPOPCNT)
2950 Builder.defineMacro("__POPCNT__");
2951
2952 if (HasRTM)
2953 Builder.defineMacro("__RTM__");
2954
2955 if (HasPRFCHW)
2956 Builder.defineMacro("__PRFCHW__");
2957
2958 if (HasRDSEED)
2959 Builder.defineMacro("__RDSEED__");
2960
2961 if (HasADX)
2962 Builder.defineMacro("__ADX__");
2963
2964 if (HasTBM)
2965 Builder.defineMacro("__TBM__");
2966
2967 switch (XOPLevel) {
2968 case XOP:
2969 Builder.defineMacro("__XOP__");
2970 case FMA4:
2971 Builder.defineMacro("__FMA4__");
2972 case SSE4A:
2973 Builder.defineMacro("__SSE4A__");
2974 case NoXOP:
2975 break;
2976 }
2977
2978 if (HasFMA)
2979 Builder.defineMacro("__FMA__");
2980
2981 if (HasF16C)
2982 Builder.defineMacro("__F16C__");
2983
2984 if (HasAVX512CD)
2985 Builder.defineMacro("__AVX512CD__");
2986 if (HasAVX512ER)
2987 Builder.defineMacro("__AVX512ER__");
2988 if (HasAVX512PF)
2989 Builder.defineMacro("__AVX512PF__");
2990 if (HasAVX512DQ)
2991 Builder.defineMacro("__AVX512DQ__");
2992 if (HasAVX512BW)
2993 Builder.defineMacro("__AVX512BW__");
2994 if (HasAVX512VL)
2995 Builder.defineMacro("__AVX512VL__");
2996
2997 if (HasSHA)
2998 Builder.defineMacro("__SHA__");
2999
3000 if (HasCX16)
3001 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
3002
3003 // Each case falls through to the previous one here.
3004 switch (SSELevel) {
3005 case AVX512F:
3006 Builder.defineMacro("__AVX512F__");
3007 case AVX2:
3008 Builder.defineMacro("__AVX2__");
3009 case AVX:
3010 Builder.defineMacro("__AVX__");
3011 case SSE42:
3012 Builder.defineMacro("__SSE4_2__");
3013 case SSE41:
3014 Builder.defineMacro("__SSE4_1__");
3015 case SSSE3:
3016 Builder.defineMacro("__SSSE3__");
3017 case SSE3:
3018 Builder.defineMacro("__SSE3__");
3019 case SSE2:
3020 Builder.defineMacro("__SSE2__");
3021 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
3022 case SSE1:
3023 Builder.defineMacro("__SSE__");
3024 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
3025 case NoSSE:
3026 break;
3027 }
3028
3029 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
3030 switch (SSELevel) {
3031 case AVX512F:
3032 case AVX2:
3033 case AVX:
3034 case SSE42:
3035 case SSE41:
3036 case SSSE3:
3037 case SSE3:
3038 case SSE2:
3039 Builder.defineMacro("_M_IX86_FP", Twine(2));
3040 break;
3041 case SSE1:
3042 Builder.defineMacro("_M_IX86_FP", Twine(1));
3043 break;
3044 default:
3045 Builder.defineMacro("_M_IX86_FP", Twine(0));
3046 }
3047 }
3048
3049 // Each case falls through to the previous one here.
3050 switch (MMX3DNowLevel) {
3051 case AMD3DNowAthlon:
3052 Builder.defineMacro("__3dNOW_A__");
3053 case AMD3DNow:
3054 Builder.defineMacro("__3dNOW__");
3055 case MMX:
3056 Builder.defineMacro("__MMX__");
3057 case NoMMX3DNow:
3058 break;
3059 }
3060
3061 if (CPU >= CK_i486) {
3062 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3063 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3064 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3065 }
3066 if (CPU >= CK_i586)
3067 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3068}
3069
3070bool X86TargetInfo::hasFeature(StringRef Feature) const {
3071 return llvm::StringSwitch<bool>(Feature)
3072 .Case("aes", HasAES)
3073 .Case("avx", SSELevel >= AVX)
3074 .Case("avx2", SSELevel >= AVX2)
3075 .Case("avx512f", SSELevel >= AVX512F)
3076 .Case("avx512cd", HasAVX512CD)
3077 .Case("avx512er", HasAVX512ER)
3078 .Case("avx512pf", HasAVX512PF)
3079 .Case("avx512dq", HasAVX512DQ)
3080 .Case("avx512bw", HasAVX512BW)
3081 .Case("avx512vl", HasAVX512VL)
3082 .Case("bmi", HasBMI)
3083 .Case("bmi2", HasBMI2)
3084 .Case("cx16", HasCX16)
3085 .Case("f16c", HasF16C)
3086 .Case("fma", HasFMA)
3087 .Case("fma4", XOPLevel >= FMA4)
3088 .Case("fsgsbase", HasFSGSBASE)
3089 .Case("lzcnt", HasLZCNT)
3090 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3091 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3092 .Case("mmx", MMX3DNowLevel >= MMX)
3093 .Case("pclmul", HasPCLMUL)
3094 .Case("popcnt", HasPOPCNT)
3095 .Case("prfchw", HasPRFCHW)
3096 .Case("rdrnd", HasRDRND)
3097 .Case("rdseed", HasRDSEED)
3098 .Case("rtm", HasRTM)
3099 .Case("sha", HasSHA)
3100 .Case("sse", SSELevel >= SSE1)
3101 .Case("sse2", SSELevel >= SSE2)
3102 .Case("sse3", SSELevel >= SSE3)
3103 .Case("ssse3", SSELevel >= SSSE3)
3104 .Case("sse4.1", SSELevel >= SSE41)
3105 .Case("sse4.2", SSELevel >= SSE42)
3106 .Case("sse4a", XOPLevel >= SSE4A)
3107 .Case("tbm", HasTBM)
3108 .Case("x86", true)
3109 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3110 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3111 .Case("xop", XOPLevel >= XOP)
3112 .Default(false);
3113}
3114
3115bool
3116X86TargetInfo::validateAsmConstraint(const char *&Name,
3117 TargetInfo::ConstraintInfo &Info) const {
3118 switch (*Name) {
3119 default: return false;
3120 case 'I':
3121 Info.setRequiresImmediate(0, 31);
3122 return true;
3123 case 'J':
3124 Info.setRequiresImmediate(0, 63);
3125 return true;
3126 case 'K':
3127 Info.setRequiresImmediate(-128, 127);
3128 return true;
3129 case 'L':
3130 // FIXME: properly analyze this constraint:
3131 // must be one of 0xff, 0xffff, or 0xffffffff
3132 return true;
3133 case 'M':
3134 Info.setRequiresImmediate(0, 3);
3135 return true;
3136 case 'N':
3137 Info.setRequiresImmediate(0, 255);
3138 return true;
3139 case 'O':
3140 Info.setRequiresImmediate(0, 127);
3141 return true;
3142 case 'Y': // first letter of a pair:
3143 switch (*(Name+1)) {
3144 default: return false;
3145 case '0': // First SSE register.
3146 case 't': // Any SSE register, when SSE2 is enabled.
3147 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
3148 case 'm': // any MMX register, when inter-unit moves enabled.
3149 break; // falls through to setAllowsRegister.
3150 }
3151 case 'f': // any x87 floating point stack register.
3152 // Constraint 'f' cannot be used for output operands.
3153 if (Info.ConstraintStr[0] == '=')
3154 return false;
3155
3156 Info.setAllowsRegister();
3157 return true;
3158 case 'a': // eax.
3159 case 'b': // ebx.
3160 case 'c': // ecx.
3161 case 'd': // edx.
3162 case 'S': // esi.
3163 case 'D': // edi.
3164 case 'A': // edx:eax.
3165 case 't': // top of floating point stack.
3166 case 'u': // second from top of floating point stack.
3167 case 'q': // Any register accessible as [r]l: a, b, c, and d.
3168 case 'y': // Any MMX register.
3169 case 'x': // Any SSE register.
3170 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
3171 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
3172 case 'l': // "Index" registers: any general register that can be used as an
3173 // index in a base+index memory access.
3174 Info.setAllowsRegister();
3175 return true;
3176 case 'C': // SSE floating point constant.
3177 case 'G': // x87 floating point constant.
3178 case 'e': // 32-bit signed integer constant for use with zero-extending
3179 // x86_64 instructions.
3180 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
3181 // x86_64 instructions.
3182 return true;
3183 }
3184}
3185
3186bool X86TargetInfo::validateOutputSize(StringRef Constraint,
3187 unsigned Size) const {
3188 // Strip off constraint modifiers.
3189 while (Constraint[0] == '=' ||
3190 Constraint[0] == '+' ||
3191 Constraint[0] == '&')
3192 Constraint = Constraint.substr(1);
3193
3194 return validateOperandSize(Constraint, Size);
3195}
3196
3197bool X86TargetInfo::validateInputSize(StringRef Constraint,
3198 unsigned Size) const {
3199 return validateOperandSize(Constraint, Size);
3200}
3201
3202bool X86TargetInfo::validateOperandSize(StringRef Constraint,
3203 unsigned Size) const {
3204 switch (Constraint[0]) {
3205 default: break;
3206 case 'y':
3207 return Size <= 64;
3208 case 'f':
3209 case 't':
3210 case 'u':
3211 return Size <= 128;
3212 case 'x':
3213 // 256-bit ymm registers can be used if target supports AVX.
3214 return Size <= (SSELevel >= AVX ? 256U : 128U);
3215 }
3216
3217 return true;
3218}
3219
3220std::string
3221X86TargetInfo::convertConstraint(const char *&Constraint) const {
3222 switch (*Constraint) {
3223 case 'a': return std::string("{ax}");
3224 case 'b': return std::string("{bx}");
3225 case 'c': return std::string("{cx}");
3226 case 'd': return std::string("{dx}");
3227 case 'S': return std::string("{si}");
3228 case 'D': return std::string("{di}");
3229 case 'p': // address
3230 return std::string("im");
3231 case 't': // top of floating point stack.
3232 return std::string("{st}");
3233 case 'u': // second from top of floating point stack.
3234 return std::string("{st(1)}"); // second from top of floating point stack.
3235 default:
3236 return std::string(1, *Constraint);
3237 }
3238}
3239} // end anonymous namespace
3240
3241namespace {
3242// X86-32 generic target
3243class X86_32TargetInfo : public X86TargetInfo {
3244public:
3245 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3246 DoubleAlign = LongLongAlign = 32;
3247 LongDoubleWidth = 96;
3248 LongDoubleAlign = 32;
3249 SuitableAlign = 128;
3250 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
3251 SizeType = UnsignedInt;
3252 PtrDiffType = SignedInt;
3253 IntPtrType = SignedInt;
3254 RegParmMax = 3;
3255
3256 // Use fpret for all types.
3257 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3258 (1 << TargetInfo::Double) |
3259 (1 << TargetInfo::LongDouble));
3260
3261 // x86-32 has atomics up to 8 bytes
3262 // FIXME: Check that we actually have cmpxchg8b before setting
3263 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3264 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3265 }
3266 BuiltinVaListKind getBuiltinVaListKind() const override {
3267 return TargetInfo::CharPtrBuiltinVaList;
3268 }
3269
3270 int getEHDataRegisterNumber(unsigned RegNo) const override {
3271 if (RegNo == 0) return 0;
3272 if (RegNo == 1) return 2;
3273 return -1;
3274 }
3275 bool validateOperandSize(StringRef Constraint,
3276 unsigned Size) const override {
3277 switch (Constraint[0]) {
3278 default: break;
3279 case 'R':
3280 case 'q':
3281 case 'Q':
3282 case 'a':
3283 case 'b':
3284 case 'c':
3285 case 'd':
3286 case 'S':
3287 case 'D':
3288 return Size <= 32;
3289 case 'A':
3290 return Size <= 64;
3291 }
3292
3293 return X86TargetInfo::validateOperandSize(Constraint, Size);
3294 }
3295};
3296} // end anonymous namespace
3297
3298namespace {
3299class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3300public:
3301 NetBSDI386TargetInfo(const llvm::Triple &Triple)
3302 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3303
3304 unsigned getFloatEvalMethod() const override {
3305 unsigned Major, Minor, Micro;
3306 getTriple().getOSVersion(Major, Minor, Micro);
3307 // New NetBSD uses the default rounding mode.
3308 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3309 return X86_32TargetInfo::getFloatEvalMethod();
3310 // NetBSD before 6.99.26 defaults to "double" rounding.
3311 return 1;
3312 }
3313};
3314} // end anonymous namespace
3315
3316namespace {
3317class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3318public:
3319 OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3320 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3321 SizeType = UnsignedLong;
3322 IntPtrType = SignedLong;
3323 PtrDiffType = SignedLong;
3324 }
3325};
3326} // end anonymous namespace
3327
3328namespace {
3329class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3330public:
3331 BitrigI386TargetInfo(const llvm::Triple &Triple)
3332 : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3333 SizeType = UnsignedLong;
3334 IntPtrType = SignedLong;
3335 PtrDiffType = SignedLong;
3336 }
3337};
3338} // end anonymous namespace
3339
3340namespace {
3341class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3342public:
3343 DarwinI386TargetInfo(const llvm::Triple &Triple)
3344 : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3345 LongDoubleWidth = 128;
3346 LongDoubleAlign = 128;
3347 SuitableAlign = 128;
3348 MaxVectorAlign = 256;
3349 SizeType = UnsignedLong;
3350 IntPtrType = SignedLong;
3351 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3352 HasAlignMac68kSupport = true;
3353 }
3354
3355};
3356} // end anonymous namespace
3357
3358namespace {
3359// x86-32 Windows target
3360class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3361public:
3362 WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3363 : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3364 WCharType = UnsignedShort;
3365 DoubleAlign = LongLongAlign = 64;
|
3357 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
| 3366 bool IsWinCOFF =
3367 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3368 DescriptionString = IsWinCOFF ? "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"
3369 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-S32";
|
3358 }
3359 void getTargetDefines(const LangOptions &Opts,
3360 MacroBuilder &Builder) const override {
3361 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3362 }
3363};
3364
3365// x86-32 Windows Visual Studio target
3366class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3367public:
3368 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3369 : WindowsX86_32TargetInfo(Triple) {
3370 LongDoubleWidth = LongDoubleAlign = 64;
3371 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3372 }
3373 void getTargetDefines(const LangOptions &Opts,
3374 MacroBuilder &Builder) const override {
3375 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3376 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3377 // The value of the following reflects processor type.
3378 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3379 // We lost the original triple, so we use the default.
3380 Builder.defineMacro("_M_IX86", "600");
3381 }
3382};
3383} // end anonymous namespace
3384
3385static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3386 Builder.defineMacro("__MSVCRT__");
3387 Builder.defineMacro("__MINGW32__");
3388
3389 // Mingw defines __declspec(a) to __attribute__((a)). Clang supports
3390 // __declspec natively under -fms-extensions, but we define a no-op __declspec
3391 // macro anyway for pre-processor compatibility.
3392 if (Opts.MicrosoftExt)
3393 Builder.defineMacro("__declspec", "__declspec");
3394 else
3395 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3396
3397 if (!Opts.MicrosoftExt) {
3398 // Provide macros for all the calling convention keywords. Provide both
3399 // single and double underscore prefixed variants. These are available on
3400 // x64 as well as x86, even though they have no effect.
3401 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3402 for (const char *CC : CCs) {
3403 std::string GCCSpelling = "__attribute__((__";
3404 GCCSpelling += CC;
3405 GCCSpelling += "__))";
3406 Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3407 Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3408 }
3409 }
3410}
3411
3412namespace {
3413// x86-32 MinGW target
3414class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3415public:
3416 MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3417 : WindowsX86_32TargetInfo(Triple) {}
3418 void getTargetDefines(const LangOptions &Opts,
3419 MacroBuilder &Builder) const override {
3420 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3421 DefineStd(Builder, "WIN32", Opts);
3422 DefineStd(Builder, "WINNT", Opts);
3423 Builder.defineMacro("_X86_");
3424 addMinGWDefines(Opts, Builder);
3425 }
3426};
3427} // end anonymous namespace
3428
3429namespace {
3430// x86-32 Cygwin target
3431class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3432public:
3433 CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3434 : X86_32TargetInfo(Triple) {
3435 TLSSupported = false;
3436 WCharType = UnsignedShort;
3437 DoubleAlign = LongLongAlign = 64;
3438 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
3439 }
3440 void getTargetDefines(const LangOptions &Opts,
3441 MacroBuilder &Builder) const override {
3442 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3443 Builder.defineMacro("_X86_");
3444 Builder.defineMacro("__CYGWIN__");
3445 Builder.defineMacro("__CYGWIN32__");
3446 DefineStd(Builder, "unix", Opts);
3447 if (Opts.CPlusPlus)
3448 Builder.defineMacro("_GNU_SOURCE");
3449 }
3450};
3451} // end anonymous namespace
3452
3453namespace {
3454// x86-32 Haiku target
3455class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3456public:
3457 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3458 SizeType = UnsignedLong;
3459 IntPtrType = SignedLong;
3460 PtrDiffType = SignedLong;
3461 ProcessIDType = SignedLong;
3462 this->UserLabelPrefix = "";
3463 this->TLSSupported = false;
3464 }
3465 void getTargetDefines(const LangOptions &Opts,
3466 MacroBuilder &Builder) const override {
3467 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3468 Builder.defineMacro("__INTEL__");
3469 Builder.defineMacro("__HAIKU__");
3470 }
3471};
3472} // end anonymous namespace
3473
3474// RTEMS Target
3475template<typename Target>
3476class RTEMSTargetInfo : public OSTargetInfo<Target> {
3477protected:
3478 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3479 MacroBuilder &Builder) const override {
3480 // RTEMS defines; list based off of gcc output
3481
3482 Builder.defineMacro("__rtems__");
3483 Builder.defineMacro("__ELF__");
3484 }
3485
3486public:
3487 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3488 this->UserLabelPrefix = "";
3489
3490 switch (Triple.getArch()) {
3491 default:
3492 case llvm::Triple::x86:
3493 // this->MCountName = ".mcount";
3494 break;
3495 case llvm::Triple::mips:
3496 case llvm::Triple::mipsel:
3497 case llvm::Triple::ppc:
3498 case llvm::Triple::ppc64:
3499 case llvm::Triple::ppc64le:
3500 // this->MCountName = "_mcount";
3501 break;
3502 case llvm::Triple::arm:
3503 // this->MCountName = "__mcount";
3504 break;
3505 }
3506 }
3507};
3508
3509namespace {
3510// x86-32 RTEMS target
3511class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3512public:
3513 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3514 SizeType = UnsignedLong;
3515 IntPtrType = SignedLong;
3516 PtrDiffType = SignedLong;
3517 this->UserLabelPrefix = "";
3518 }
3519 void getTargetDefines(const LangOptions &Opts,
3520 MacroBuilder &Builder) const override {
3521 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3522 Builder.defineMacro("__INTEL__");
3523 Builder.defineMacro("__rtems__");
3524 }
3525};
3526} // end anonymous namespace
3527
3528namespace {
3529// x86-64 generic target
3530class X86_64TargetInfo : public X86TargetInfo {
3531public:
3532 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3533 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3534 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3535 LongDoubleWidth = 128;
3536 LongDoubleAlign = 128;
3537 LargeArrayMinWidth = 128;
3538 LargeArrayAlign = 128;
3539 SuitableAlign = 128;
3540 SizeType = IsX32 ? UnsignedInt : UnsignedLong;
3541 PtrDiffType = IsX32 ? SignedInt : SignedLong;
3542 IntPtrType = IsX32 ? SignedInt : SignedLong;
3543 IntMaxType = IsX32 ? SignedLongLong : SignedLong;
3544 Int64Type = IsX32 ? SignedLongLong : SignedLong;
3545 RegParmMax = 6;
3546
3547 // Pointers are 32-bit in x32.
3548 DescriptionString = (IsX32)
3549 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
3550 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
3551
3552 // Use fpret only for long double.
3553 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3554
3555 // Use fp2ret for _Complex long double.
3556 ComplexLongDoubleUsesFP2Ret = true;
3557
3558 // x86-64 has atomics up to 16 bytes.
3559 MaxAtomicPromoteWidth = 128;
3560 MaxAtomicInlineWidth = 128;
3561 }
3562 BuiltinVaListKind getBuiltinVaListKind() const override {
3563 return TargetInfo::X86_64ABIBuiltinVaList;
3564 }
3565
3566 int getEHDataRegisterNumber(unsigned RegNo) const override {
3567 if (RegNo == 0) return 0;
3568 if (RegNo == 1) return 1;
3569 return -1;
3570 }
3571
3572 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3573 return (CC == CC_C ||
3574 CC == CC_X86VectorCall ||
3575 CC == CC_IntelOclBicc ||
3576 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3577 }
3578
3579 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3580 return CC_C;
3581 }
3582
3583 // for x32 we need it here explicitly
3584 bool hasInt128Type() const override { return true; }
3585};
3586} // end anonymous namespace
3587
3588namespace {
3589// x86-64 Windows target
3590class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3591public:
3592 WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3593 : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3594 WCharType = UnsignedShort;
3595 LongWidth = LongAlign = 32;
3596 DoubleAlign = LongLongAlign = 64;
3597 IntMaxType = SignedLongLong;
3598 Int64Type = SignedLongLong;
3599 SizeType = UnsignedLongLong;
3600 PtrDiffType = SignedLongLong;
3601 IntPtrType = SignedLongLong;
3602 this->UserLabelPrefix = "";
3603 }
3604 void getTargetDefines(const LangOptions &Opts,
3605 MacroBuilder &Builder) const override {
3606 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3607 Builder.defineMacro("_WIN64");
3608 }
3609 BuiltinVaListKind getBuiltinVaListKind() const override {
3610 return TargetInfo::CharPtrBuiltinVaList;
3611 }
3612 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3613 return (CC == CC_C ||
3614 CC == CC_X86VectorCall ||
3615 CC == CC_IntelOclBicc ||
3616 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning;
3617 }
3618};
3619} // end anonymous namespace
3620
3621namespace {
3622// x86-64 Windows Visual Studio target
3623class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
3624public:
3625 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
3626 : WindowsX86_64TargetInfo(Triple) {
3627 LongDoubleWidth = LongDoubleAlign = 64;
3628 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3629 }
3630 void getTargetDefines(const LangOptions &Opts,
3631 MacroBuilder &Builder) const override {
3632 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3633 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3634 Builder.defineMacro("_M_X64");
3635 Builder.defineMacro("_M_AMD64");
3636 }
3637};
3638} // end anonymous namespace
3639
3640namespace {
3641// x86-64 MinGW target
3642class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3643public:
3644 MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3645 : WindowsX86_64TargetInfo(Triple) {}
3646 void getTargetDefines(const LangOptions &Opts,
3647 MacroBuilder &Builder) const override {
3648 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3649 DefineStd(Builder, "WIN64", Opts);
3650 Builder.defineMacro("__MINGW64__");
3651 addMinGWDefines(Opts, Builder);
3652
3653 // GCC defines this macro when it is using __gxx_personality_seh0.
3654 if (!Opts.SjLjExceptions)
3655 Builder.defineMacro("__SEH__");
3656 }
3657};
3658} // end anonymous namespace
3659
3660namespace {
3661class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3662public:
3663 DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3664 : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3665 Int64Type = SignedLongLong;
3666 MaxVectorAlign = 256;
3667 // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
3668 llvm::Triple T = llvm::Triple(Triple);
3669 if (T.isiOS())
3670 UseSignedCharForObjCBool = false;
3671 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
3672 }
3673};
3674} // end anonymous namespace
3675
3676namespace {
3677class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3678public:
3679 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3680 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3681 IntMaxType = SignedLongLong;
3682 Int64Type = SignedLongLong;
3683 }
3684};
3685} // end anonymous namespace
3686
3687namespace {
3688class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3689public:
3690 BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3691 : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3692 IntMaxType = SignedLongLong;
3693 Int64Type = SignedLongLong;
3694 }
3695};
3696}
3697
3698
3699namespace {
3700class ARMTargetInfo : public TargetInfo {
3701 // Possible FPU choices.
3702 enum FPUMode {
3703 VFP2FPU = (1 << 0),
3704 VFP3FPU = (1 << 1),
3705 VFP4FPU = (1 << 2),
3706 NeonFPU = (1 << 3),
3707 FPARMV8 = (1 << 4)
3708 };
3709
3710 // Possible HWDiv features.
3711 enum HWDivMode {
3712 HWDivThumb = (1 << 0),
3713 HWDivARM = (1 << 1)
3714 };
3715
3716 static bool FPUModeIsVFP(FPUMode Mode) {
3717 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
3718 }
3719
3720 static const TargetInfo::GCCRegAlias GCCRegAliases[];
3721 static const char * const GCCRegNames[];
3722
3723 std::string ABI, CPU;
3724
3725 enum {
3726 FP_Default,
3727 FP_VFP,
3728 FP_Neon
3729 } FPMath;
3730
3731 unsigned FPU : 5;
3732
3733 unsigned IsAAPCS : 1;
3734 unsigned IsThumb : 1;
3735 unsigned HWDiv : 2;
3736
3737 // Initialized via features.
3738 unsigned SoftFloat : 1;
3739 unsigned SoftFloatABI : 1;
3740
3741 unsigned CRC : 1;
3742 unsigned Crypto : 1;
3743
3744 // ACLE 6.5.1 Hardware floating point
3745 enum {
3746 HW_FP_HP = (1 << 1), /// half (16-bit)
3747 HW_FP_SP = (1 << 2), /// single (32-bit)
3748 HW_FP_DP = (1 << 3), /// double (64-bit)
3749 };
3750 uint32_t HW_FP;
3751
3752 static const Builtin::Info BuiltinInfo[];
3753
3754 static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3755 StringRef ArchName = T.getArchName();
3756 if (T.getArch() == llvm::Triple::arm ||
3757 T.getArch() == llvm::Triple::armeb) {
3758 StringRef VersionStr;
3759 if (ArchName.startswith("armv"))
3760 VersionStr = ArchName.substr(4, 1);
3761 else if (ArchName.startswith("armebv"))
3762 VersionStr = ArchName.substr(6, 1);
3763 else
3764 return false;
3765 unsigned Version;
3766 if (VersionStr.getAsInteger(10, Version))
3767 return false;
3768 return Version >= 6;
3769 }
3770 assert(T.getArch() == llvm::Triple::thumb ||
3771 T.getArch() == llvm::Triple::thumbeb);
3772 StringRef VersionStr;
3773 if (ArchName.startswith("thumbv"))
3774 VersionStr = ArchName.substr(6, 1);
3775 else if (ArchName.startswith("thumbebv"))
3776 VersionStr = ArchName.substr(8, 1);
3777 else
3778 return false;
3779 unsigned Version;
3780 if (VersionStr.getAsInteger(10, Version))
3781 return false;
3782 return Version >= 7;
3783 }
3784
3785 void setABIAAPCS() {
3786 IsAAPCS = true;
3787
3788 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
3789 const llvm::Triple &T = getTriple();
3790
3791 // size_t is unsigned long on MachO-derived environments and NetBSD.
3792 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD)
3793 SizeType = UnsignedLong;
3794 else
3795 SizeType = UnsignedInt;
3796
3797 switch (T.getOS()) {
3798 case llvm::Triple::NetBSD:
3799 WCharType = SignedInt;
3800 break;
3801 case llvm::Triple::Win32:
3802 WCharType = UnsignedShort;
3803 break;
3804 case llvm::Triple::Linux:
3805 default:
3806 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3807 WCharType = UnsignedInt;
3808 break;
3809 }
3810
3811 UseBitFieldTypeAlignment = true;
3812
3813 ZeroLengthBitfieldBoundary = 0;
3814
3815 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3816 // so set preferred for small types to 32.
3817 if (T.isOSBinFormatMachO()) {
3818 DescriptionString =
3819 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
3820 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
3821 } else if (T.isOSWindows()) {
3822 // FIXME: this is invalid for WindowsCE
3823 assert(!BigEndian && "Windows on ARM does not support big endian");
3824 DescriptionString = "e"
3825 "-m:e"
3826 "-p:32:32"
3827 "-i64:64"
3828 "-v128:64:128"
3829 "-a:0:32"
3830 "-n32"
3831 "-S64";
3832 } else {
3833 DescriptionString =
3834 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
3835 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
3836 }
3837
3838 // FIXME: Enumerated types are variable width in straight AAPCS.
3839 }
3840
3841 void setABIAPCS() {
3842 const llvm::Triple &T = getTriple();
3843
3844 IsAAPCS = false;
3845
3846 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3847
3848 // size_t is unsigned int on FreeBSD.
3849 if (T.getOS() == llvm::Triple::FreeBSD)
3850 SizeType = UnsignedInt;
3851 else
3852 SizeType = UnsignedLong;
3853
3854 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3855 WCharType = SignedInt;
3856
3857 // Do not respect the alignment of bit-field types when laying out
3858 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3859 UseBitFieldTypeAlignment = false;
3860
3861 /// gcc forces the alignment to 4 bytes, regardless of the type of the
3862 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
3863 /// gcc.
3864 ZeroLengthBitfieldBoundary = 32;
3865
3866 if (T.isOSBinFormatMachO())
3867 DescriptionString =
3868 BigEndian
3869 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
3870 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3871 else
3872 DescriptionString =
3873 BigEndian
3874 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
3875 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3876
3877 // FIXME: Override "preferred align" for double and long long.
3878 }
3879
3880public:
3881 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
3882 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
3883 IsAAPCS(true), HW_FP(0) {
3884 BigEndian = IsBigEndian;
3885
3886 switch (getTriple().getOS()) {
3887 case llvm::Triple::NetBSD:
3888 PtrDiffType = SignedLong;
3889 break;
3890 default:
3891 PtrDiffType = SignedInt;
3892 break;
3893 }
3894
3895 // {} in inline assembly are neon specifiers, not assembly variant
3896 // specifiers.
3897 NoAsmVariants = true;
3898
3899 // FIXME: Should we just treat this as a feature?
3900 IsThumb = getTriple().getArchName().startswith("thumb");
3901
3902 // FIXME: This duplicates code from the driver that sets the -target-abi
3903 // option - this code is used if -target-abi isn't passed and should
3904 // be unified in some way.
3905 if (Triple.isOSBinFormatMachO()) {
3906 // The backend is hardwired to assume AAPCS for M-class processors, ensure
3907 // the frontend matches that.
3908 if (Triple.getEnvironment() == llvm::Triple::EABI ||
3909 Triple.getOS() == llvm::Triple::UnknownOS ||
3910 StringRef(CPU).startswith("cortex-m")) {
3911 setABI("aapcs");
3912 } else {
3913 setABI("apcs-gnu");
3914 }
3915 } else if (Triple.isOSWindows()) {
3916 // FIXME: this is invalid for WindowsCE
3917 setABI("aapcs");
3918 } else {
3919 // Select the default based on the platform.
3920 switch (Triple.getEnvironment()) {
3921 case llvm::Triple::Android:
3922 case llvm::Triple::GNUEABI:
3923 case llvm::Triple::GNUEABIHF:
3924 setABI("aapcs-linux");
3925 break;
3926 case llvm::Triple::EABIHF:
3927 case llvm::Triple::EABI:
3928 setABI("aapcs");
3929 break;
3930 case llvm::Triple::GNU:
3931 setABI("apcs-gnu");
3932 break;
3933 default:
3934 if (Triple.getOS() == llvm::Triple::NetBSD)
3935 setABI("apcs-gnu");
3936 else
3937 setABI("aapcs");
3938 break;
3939 }
3940 }
3941
3942 // ARM targets default to using the ARM C++ ABI.
3943 TheCXXABI.set(TargetCXXABI::GenericARM);
3944
3945 // ARM has atomics up to 8 bytes
3946 MaxAtomicPromoteWidth = 64;
3947 if (shouldUseInlineAtomic(getTriple()))
3948 MaxAtomicInlineWidth = 64;
3949
3950 // Do force alignment of members that follow zero length bitfields. If
3951 // the alignment of the zero-length bitfield is greater than the member
3952 // that follows it, `bar', `bar' will be aligned as the type of the
3953 // zero length bitfield.
3954 UseZeroLengthBitfieldAlignment = true;
3955 }
3956 StringRef getABI() const override { return ABI; }
3957 bool setABI(const std::string &Name) override {
3958 ABI = Name;
3959
3960 // The defaults (above) are for AAPCS, check if we need to change them.
3961 //
3962 // FIXME: We need support for -meabi... we could just mangle it into the
3963 // name.
3964 if (Name == "apcs-gnu") {
3965 setABIAPCS();
3966 return true;
3967 }
3968 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
3969 setABIAAPCS();
3970 return true;
3971 }
3972 return false;
3973 }
3974
3975 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
3976 StringRef ArchName = getTriple().getArchName();
3977 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3978 Features["vfp2"] = true;
3979 else if (CPU == "cortex-a8" || CPU == "cortex-a9") {
3980 Features["vfp3"] = true;
3981 Features["neon"] = true;
3982 }
3983 else if (CPU == "cortex-a5") {
3984 Features["vfp4"] = true;
3985 Features["neon"] = true;
3986 } else if (CPU == "swift" || CPU == "cortex-a7" ||
3987 CPU == "cortex-a12" || CPU == "cortex-a15" ||
3988 CPU == "cortex-a17" || CPU == "krait") {
3989 Features["vfp4"] = true;
3990 Features["neon"] = true;
3991 Features["hwdiv"] = true;
3992 Features["hwdiv-arm"] = true;
3993 } else if (CPU == "cyclone") {
3994 Features["v8fp"] = true;
3995 Features["neon"] = true;
3996 Features["hwdiv"] = true;
3997 Features["hwdiv-arm"] = true;
3998 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") {
3999 Features["fp-armv8"] = true;
4000 Features["neon"] = true;
4001 Features["hwdiv"] = true;
4002 Features["hwdiv-arm"] = true;
4003 Features["crc"] = true;
4004 Features["crypto"] = true;
4005 } else if (CPU == "cortex-r5" ||
4006 // Enable the hwdiv extension for all v8a AArch32 cores by
4007 // default.
4008 ArchName == "armv8a" || ArchName == "armv8" ||
4009 ArchName == "armebv8a" || ArchName == "armebv8" ||
4010 ArchName == "thumbv8a" || ArchName == "thumbv8" ||
4011 ArchName == "thumbebv8a" || ArchName == "thumbebv8") {
4012 Features["hwdiv"] = true;
4013 Features["hwdiv-arm"] = true;
4014 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7") {
4015 Features["hwdiv"] = true;
4016 }
4017 }
4018
4019 bool handleTargetFeatures(std::vector<std::string> &Features,
4020 DiagnosticsEngine &Diags) override {
4021 FPU = 0;
4022 CRC = 0;
4023 Crypto = 0;
4024 SoftFloat = SoftFloatABI = false;
4025 HWDiv = 0;
4026
4027 for (const auto &Feature : Features) {
4028 if (Feature == "+soft-float") {
4029 SoftFloat = true;
4030 } else if (Feature == "+soft-float-abi") {
4031 SoftFloatABI = true;
4032 } else if (Feature == "+vfp2") {
4033 FPU |= VFP2FPU;
4034 HW_FP = HW_FP_SP | HW_FP_DP;
4035 } else if (Feature == "+vfp3") {
4036 FPU |= VFP3FPU;
4037 HW_FP = HW_FP_SP | HW_FP_DP;
4038 } else if (Feature == "+vfp4") {
4039 FPU |= VFP4FPU;
4040 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4041 } else if (Feature == "+fp-armv8") {
4042 FPU |= FPARMV8;
4043 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4044 } else if (Feature == "+neon") {
4045 FPU |= NeonFPU;
4046 HW_FP = HW_FP_SP | HW_FP_DP;
4047 } else if (Feature == "+hwdiv") {
4048 HWDiv |= HWDivThumb;
4049 } else if (Feature == "+hwdiv-arm") {
4050 HWDiv |= HWDivARM;
4051 } else if (Feature == "+crc") {
4052 CRC = 1;
4053 } else if (Feature == "+crypto") {
4054 Crypto = 1;
4055 } else if (Feature == "+fp-only-sp") {
4056 HW_FP &= ~HW_FP_DP;
4057 }
4058 }
4059
4060 if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
4061 Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
4062 return false;
4063 }
4064
4065 if (FPMath == FP_Neon)
4066 Features.push_back("+neonfp");
4067 else if (FPMath == FP_VFP)
4068 Features.push_back("-neonfp");
4069
4070 // Remove front-end specific options which the backend handles differently.
4071 const StringRef FrontEndFeatures[] = { "+soft-float", "+soft-float-abi" };
4072 for (const auto &FEFeature : FrontEndFeatures) {
4073 auto Feature = std::find(Features.begin(), Features.end(), FEFeature);
4074 if (Feature != Features.end())
4075 Features.erase(Feature);
4076 }
4077
4078 return true;
4079 }
4080
4081 bool hasFeature(StringRef Feature) const override {
4082 return llvm::StringSwitch<bool>(Feature)
4083 .Case("arm", true)
4084 .Case("softfloat", SoftFloat)
4085 .Case("thumb", IsThumb)
4086 .Case("neon", (FPU & NeonFPU) && !SoftFloat)
4087 .Case("hwdiv", HWDiv & HWDivThumb)
4088 .Case("hwdiv-arm", HWDiv & HWDivARM)
4089 .Default(false);
4090 }
4091 // FIXME: Should we actually have some table instead of these switches?
4092 static const char *getCPUDefineSuffix(StringRef Name) {
4093 return llvm::StringSwitch<const char *>(Name)
4094 .Cases("arm8", "arm810", "4")
4095 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110",
4096 "4")
4097 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
4098 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
4099 .Case("ep9312", "4T")
4100 .Cases("arm10tdmi", "arm1020t", "5T")
4101 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
4102 .Case("arm926ej-s", "5TEJ")
4103 .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
4104 .Cases("xscale", "iwmmxt", "5TE")
4105 .Case("arm1136j-s", "6J")
4106 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
4107 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
4108 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
4109 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
4110 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
4111 "7A")
4112 .Cases("cortex-r4", "cortex-r5", "7R")
4113 .Case("swift", "7S")
4114 .Case("cyclone", "8A")
4115 .Case("cortex-m3", "7M")
4116 .Cases("cortex-m4", "cortex-m7", "7EM")
4117 .Case("cortex-m0", "6M")
4118 .Cases("cortex-a53", "cortex-a57", "8A")
4119 .Default(nullptr);
4120 }
4121 static const char *getCPUProfile(StringRef Name) {
4122 return llvm::StringSwitch<const char *>(Name)
4123 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A")
4124 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
4125 "A")
4126 .Cases("cortex-a53", "cortex-a57", "A")
4127 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m7", "M")
4128 .Cases("cortex-r4", "cortex-r5", "R")
4129 .Default("");
4130 }
4131 bool setCPU(const std::string &Name) override {
4132 if (!getCPUDefineSuffix(Name))
4133 return false;
4134
4135 // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4136 StringRef Profile = getCPUProfile(Name);
4137 if (Profile == "M" && MaxAtomicInlineWidth) {
4138 MaxAtomicPromoteWidth = 32;
4139 MaxAtomicInlineWidth = 32;
4140 }
4141
4142 CPU = Name;
4143 return true;
4144 }
4145 bool setFPMath(StringRef Name) override;
4146 bool supportsThumb(StringRef ArchName, StringRef CPUArch,
4147 unsigned CPUArchVer) const {
4148 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) ||
4149 (CPUArch.find('M') != StringRef::npos);
4150 }
4151 bool supportsThumb2(StringRef ArchName, StringRef CPUArch,
4152 unsigned CPUArchVer) const {
4153 // We check both CPUArchVer and ArchName because when only triple is
4154 // specified, the default CPU is arm1136j-s.
4155 return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
4156 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
4157 }
4158 void getTargetDefines(const LangOptions &Opts,
4159 MacroBuilder &Builder) const override {
4160 // Target identification.
4161 Builder.defineMacro("__arm");
4162 Builder.defineMacro("__arm__");
4163
4164 // Target properties.
4165 Builder.defineMacro("__REGISTER_PREFIX__", "");
4166
4167 StringRef CPUArch = getCPUDefineSuffix(CPU);
4168 unsigned int CPUArchVer;
4169 if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer))
4170 llvm_unreachable("Invalid char for architecture version number");
4171 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
4172
4173 // ACLE 6.4.1 ARM/Thumb instruction set architecture
4174 StringRef CPUProfile = getCPUProfile(CPU);
4175 StringRef ArchName = getTriple().getArchName();
4176
4177 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
4178 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
4179 if (CPUArch[0] >= '8') {
4180 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4181 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4182 }
4183
4184 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
4185 // is not defined for the M-profile.
4186 // NOTE that the deffault profile is assumed to be 'A'
4187 if (CPUProfile.empty() || CPUProfile != "M")
4188 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
4189
4190 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
4191 // Thumb ISA (including v6-M). It is set to 2 if the core supports the
4192 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
4193 if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4194 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
4195 else if (supportsThumb(ArchName, CPUArch, CPUArchVer))
4196 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
4197
4198 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
4199 // instruction set such as ARM or Thumb.
4200 Builder.defineMacro("__ARM_32BIT_STATE", "1");
4201
4202 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
4203
4204 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
4205 if (!CPUProfile.empty())
4206 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
4207
4208 // ACLE 6.5.1 Hardware Floating Point
4209 if (HW_FP)
4210 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
4211
4212 // ACLE predefines.
4213 Builder.defineMacro("__ARM_ACLE", "200");
4214
4215 // Subtarget options.
4216
4217 // FIXME: It's more complicated than this and we don't really support
4218 // interworking.
4219 // Windows on ARM does not "support" interworking
4220 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows())
4221 Builder.defineMacro("__THUMB_INTERWORK__");
4222
4223 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
4224 // Embedded targets on Darwin follow AAPCS, but not EABI.
4225 // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
4226 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
4227 Builder.defineMacro("__ARM_EABI__");
4228 Builder.defineMacro("__ARM_PCS", "1");
4229
4230 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
4231 Builder.defineMacro("__ARM_PCS_VFP", "1");
4232 }
4233
4234 if (SoftFloat)
4235 Builder.defineMacro("__SOFTFP__");
4236
4237 if (CPU == "xscale")
4238 Builder.defineMacro("__XSCALE__");
4239
4240 if (IsThumb) {
4241 Builder.defineMacro("__THUMBEL__");
4242 Builder.defineMacro("__thumb__");
4243 if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4244 Builder.defineMacro("__thumb2__");
4245 }
4246 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
4247 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
4248
4249 // Note, this is always on in gcc, even though it doesn't make sense.
4250 Builder.defineMacro("__APCS_32__");
4251
4252 if (FPUModeIsVFP((FPUMode) FPU)) {
4253 Builder.defineMacro("__VFP_FP__");
4254 if (FPU & VFP2FPU)
4255 Builder.defineMacro("__ARM_VFPV2__");
4256 if (FPU & VFP3FPU)
4257 Builder.defineMacro("__ARM_VFPV3__");
4258 if (FPU & VFP4FPU)
4259 Builder.defineMacro("__ARM_VFPV4__");
4260 }
4261
4262 // This only gets set when Neon instructions are actually available, unlike
4263 // the VFP define, hence the soft float and arch check. This is subtly
4264 // different from gcc, we follow the intent which was that it should be set
4265 // when Neon instructions are actually available.
4266 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) {
4267 Builder.defineMacro("__ARM_NEON");
4268 Builder.defineMacro("__ARM_NEON__");
4269 }
4270
4271 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
4272 Opts.ShortWChar ? "2" : "4");
4273
4274 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4275 Opts.ShortEnums ? "1" : "4");
4276
4277 if (CRC)
4278 Builder.defineMacro("__ARM_FEATURE_CRC32");
4279
4280 if (Crypto)
4281 Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4282
4283 if (CPUArchVer >= 6 && CPUArch != "6M") {
4284 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4285 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4286 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4287 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4288 }
4289
4290 bool is5EOrAbove = (CPUArchVer >= 6 ||
4291 (CPUArchVer == 5 &&
4292 CPUArch.find('E') != StringRef::npos));
4293 bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer));
4294 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch == "7EM"))
4295 Builder.defineMacro("__ARM_FEATURE_DSP");
4296 }
4297 void getTargetBuiltins(const Builtin::Info *&Records,
4298 unsigned &NumRecords) const override {
4299 Records = BuiltinInfo;
4300 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
4301 }
4302 bool isCLZForZeroUndef() const override { return false; }
4303 BuiltinVaListKind getBuiltinVaListKind() const override {
4304 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
4305 }
4306 void getGCCRegNames(const char * const *&Names,
4307 unsigned &NumNames) const override;
4308 void getGCCRegAliases(const GCCRegAlias *&Aliases,
4309 unsigned &NumAliases) const override;
4310 bool validateAsmConstraint(const char *&Name,
4311 TargetInfo::ConstraintInfo &Info) const override {
4312 switch (*Name) {
4313 default: break;
4314 case 'l': // r0-r7
4315 case 'h': // r8-r15
4316 case 'w': // VFP Floating point register single precision
4317 case 'P': // VFP Floating point register double precision
4318 Info.setAllowsRegister();
4319 return true;
4320 case 'I':
4321 case 'J':
4322 case 'K':
4323 case 'L':
4324 case 'M':
4325 // FIXME
4326 return true;
4327 case 'Q': // A memory address that is a single base register.
4328 Info.setAllowsMemory();
4329 return true;
4330 case 'U': // a memory reference...
4331 switch (Name[1]) {
4332 case 'q': // ...ARMV4 ldrsb
4333 case 'v': // ...VFP load/store (reg+constant offset)
4334 case 'y': // ...iWMMXt load/store
4335 case 't': // address valid for load/store opaque types wider
4336 // than 128-bits
4337 case 'n': // valid address for Neon doubleword vector load/store
4338 case 'm': // valid address for Neon element and structure load/store
4339 case 's': // valid address for non-offset loads/stores of quad-word
4340 // values in four ARM registers
4341 Info.setAllowsMemory();
4342 Name++;
4343 return true;
4344 }
4345 }
4346 return false;
4347 }
4348 std::string convertConstraint(const char *&Constraint) const override {
4349 std::string R;
4350 switch (*Constraint) {
4351 case 'U': // Two-character constraint; add "^" hint for later parsing.
4352 R = std::string("^") + std::string(Constraint, 2);
4353 Constraint++;
4354 break;
4355 case 'p': // 'p' should be translated to 'r' by default.
4356 R = std::string("r");
4357 break;
4358 default:
4359 return std::string(1, *Constraint);
4360 }
4361 return R;
4362 }
4363 bool
4364 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4365 std::string &SuggestedModifier) const override {
4366 bool isOutput = (Constraint[0] == '=');
4367 bool isInOut = (Constraint[0] == '+');
4368
4369 // Strip off constraint modifiers.
4370 while (Constraint[0] == '=' ||
4371 Constraint[0] == '+' ||
4372 Constraint[0] == '&')
4373 Constraint = Constraint.substr(1);
4374
4375 switch (Constraint[0]) {
4376 default: break;
4377 case 'r': {
4378 switch (Modifier) {
4379 default:
4380 return (isInOut || isOutput || Size <= 64);
4381 case 'q':
4382 // A register of size 32 cannot fit a vector type.
4383 return false;
4384 }
4385 }
4386 }
4387
4388 return true;
4389 }
4390 const char *getClobbers() const override {
4391 // FIXME: Is this really right?
4392 return "";
4393 }
4394
4395 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4396 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4397 }
4398
4399 int getEHDataRegisterNumber(unsigned RegNo) const override {
4400 if (RegNo == 0) return 0;
4401 if (RegNo == 1) return 1;
4402 return -1;
4403 }
4404};
4405
4406bool ARMTargetInfo::setFPMath(StringRef Name) {
4407 if (Name == "neon") {
4408 FPMath = FP_Neon;
4409 return true;
4410 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
4411 Name == "vfp4") {
4412 FPMath = FP_VFP;
4413 return true;
4414 }
4415 return false;
4416}
4417
4418const char * const ARMTargetInfo::GCCRegNames[] = {
4419 // Integer registers
4420 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4421 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
4422
4423 // Float registers
4424 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
4425 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
4426 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
4427 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4428
4429 // Double registers
4430 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
4431 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
4432 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
4433 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4434
4435 // Quad registers
4436 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
4437 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
4438};
4439
4440void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
4441 unsigned &NumNames) const {
4442 Names = GCCRegNames;
4443 NumNames = llvm::array_lengthof(GCCRegNames);
4444}
4445
4446const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
4447 { { "a1" }, "r0" },
4448 { { "a2" }, "r1" },
4449 { { "a3" }, "r2" },
4450 { { "a4" }, "r3" },
4451 { { "v1" }, "r4" },
4452 { { "v2" }, "r5" },
4453 { { "v3" }, "r6" },
4454 { { "v4" }, "r7" },
4455 { { "v5" }, "r8" },
4456 { { "v6", "rfp" }, "r9" },
4457 { { "sl" }, "r10" },
4458 { { "fp" }, "r11" },
4459 { { "ip" }, "r12" },
4460 { { "r13" }, "sp" },
4461 { { "r14" }, "lr" },
4462 { { "r15" }, "pc" },
4463 // The S, D and Q registers overlap, but aren't really aliases; we
4464 // don't want to substitute one of these for a different-sized one.
4465};
4466
4467void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4468 unsigned &NumAliases) const {
4469 Aliases = GCCRegAliases;
4470 NumAliases = llvm::array_lengthof(GCCRegAliases);
4471}
4472
4473const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
4474#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4475#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4476 ALL_LANGUAGES },
4477#include "clang/Basic/BuiltinsNEON.def"
4478
4479#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4480#define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG },
4481#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4482 ALL_LANGUAGES },
4483#include "clang/Basic/BuiltinsARM.def"
4484};
4485
4486class ARMleTargetInfo : public ARMTargetInfo {
4487public:
4488 ARMleTargetInfo(const llvm::Triple &Triple)
4489 : ARMTargetInfo(Triple, false) { }
4490 virtual void getTargetDefines(const LangOptions &Opts,
4491 MacroBuilder &Builder) const {
4492 Builder.defineMacro("__ARMEL__");
4493 ARMTargetInfo::getTargetDefines(Opts, Builder);
4494 }
4495};
4496
4497class ARMbeTargetInfo : public ARMTargetInfo {
4498public:
4499 ARMbeTargetInfo(const llvm::Triple &Triple)
4500 : ARMTargetInfo(Triple, true) { }
4501 virtual void getTargetDefines(const LangOptions &Opts,
4502 MacroBuilder &Builder) const {
4503 Builder.defineMacro("__ARMEB__");
4504 Builder.defineMacro("__ARM_BIG_ENDIAN");
4505 ARMTargetInfo::getTargetDefines(Opts, Builder);
4506 }
4507};
4508} // end anonymous namespace.
4509
4510namespace {
4511class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
4512 const llvm::Triple Triple;
4513public:
4514 WindowsARMTargetInfo(const llvm::Triple &Triple)
4515 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
4516 TLSSupported = false;
4517 WCharType = UnsignedShort;
4518 SizeType = UnsignedInt;
4519 UserLabelPrefix = "";
4520 }
4521 void getVisualStudioDefines(const LangOptions &Opts,
4522 MacroBuilder &Builder) const {
4523 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
4524
4525 // FIXME: this is invalid for WindowsCE
4526 Builder.defineMacro("_M_ARM_NT", "1");
4527 Builder.defineMacro("_M_ARMT", "_M_ARM");
4528 Builder.defineMacro("_M_THUMB", "_M_ARM");
4529
4530 assert((Triple.getArch() == llvm::Triple::arm ||
4531 Triple.getArch() == llvm::Triple::thumb) &&
4532 "invalid architecture for Windows ARM target info");
4533 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
4534 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
4535
4536 // TODO map the complete set of values
4537 // 31: VFPv3 40: VFPv4
4538 Builder.defineMacro("_M_ARM_FP", "31");
4539 }
4540 BuiltinVaListKind getBuiltinVaListKind() const override {
4541 return TargetInfo::CharPtrBuiltinVaList;
4542 }
4543};
4544
4545// Windows ARM + Itanium C++ ABI Target
4546class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
4547public:
4548 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
4549 : WindowsARMTargetInfo(Triple) {
4550 TheCXXABI.set(TargetCXXABI::GenericARM);
4551 }
4552
4553 void getTargetDefines(const LangOptions &Opts,
4554 MacroBuilder &Builder) const override {
4555 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4556
4557 if (Opts.MSVCCompat)
4558 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4559 }
4560};
4561
4562// Windows ARM, MS (C++) ABI
4563class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
4564public:
4565 MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
4566 : WindowsARMTargetInfo(Triple) {
4567 TheCXXABI.set(TargetCXXABI::Microsoft);
4568 }
4569
4570 void getTargetDefines(const LangOptions &Opts,
4571 MacroBuilder &Builder) const override {
4572 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4573 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4574 }
4575};
4576}
4577
4578
4579namespace {
4580class DarwinARMTargetInfo :
4581 public DarwinTargetInfo<ARMleTargetInfo> {
4582protected:
4583 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4584 MacroBuilder &Builder) const override {
4585 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4586 }
4587
4588public:
4589 DarwinARMTargetInfo(const llvm::Triple &Triple)
4590 : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
4591 HasAlignMac68kSupport = true;
4592 // iOS always has 64-bit atomic instructions.
4593 // FIXME: This should be based off of the target features in
4594 // ARMleTargetInfo.
4595 MaxAtomicInlineWidth = 64;
4596
4597 // Darwin on iOS uses a variant of the ARM C++ ABI.
4598 TheCXXABI.set(TargetCXXABI::iOS);
4599 }
4600};
4601} // end anonymous namespace.
4602
4603
4604namespace {
4605class AArch64TargetInfo : public TargetInfo {
4606 virtual void setDescriptionString() = 0;
4607 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4608 static const char *const GCCRegNames[];
4609
4610 enum FPUModeEnum {
4611 FPUMode,
4612 NeonMode
4613 };
4614
4615 unsigned FPU;
4616 unsigned CRC;
4617 unsigned Crypto;
4618
4619 static const Builtin::Info BuiltinInfo[];
4620
4621 std::string ABI;
4622
4623public:
4624 AArch64TargetInfo(const llvm::Triple &Triple)
4625 : TargetInfo(Triple), ABI("aapcs") {
4626
4627 if (getTriple().getOS() == llvm::Triple::NetBSD) {
4628 WCharType = SignedInt;
4629
4630 // NetBSD apparently prefers consistency across ARM targets to consistency
4631 // across 64-bit targets.
4632 Int64Type = SignedLongLong;
4633 IntMaxType = SignedLongLong;
4634 } else {
4635 WCharType = UnsignedInt;
4636 Int64Type = SignedLong;
4637 IntMaxType = SignedLong;
4638 }
4639
4640 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4641 MaxVectorAlign = 128;
4642 RegParmMax = 8;
4643 MaxAtomicInlineWidth = 128;
4644 MaxAtomicPromoteWidth = 128;
4645
4646 LongDoubleWidth = LongDoubleAlign = 128;
4647 LongDoubleFormat = &llvm::APFloat::IEEEquad;
4648
4649 // {} in inline assembly are neon specifiers, not assembly variant
4650 // specifiers.
4651 NoAsmVariants = true;
4652
4653 // AArch64 targets default to using the ARM C++ ABI.
4654 TheCXXABI.set(TargetCXXABI::GenericAArch64);
4655 }
4656
4657 StringRef getABI() const override { return ABI; }
4658 bool setABI(const std::string &Name) override {
4659 if (Name != "aapcs" && Name != "darwinpcs")
4660 return false;
4661
4662 ABI = Name;
4663 return true;
4664 }
4665
4666 bool setCPU(const std::string &Name) override {
4667 bool CPUKnown = llvm::StringSwitch<bool>(Name)
4668 .Case("generic", true)
4669 .Cases("cortex-a53", "cortex-a57", true)
4670 .Case("cyclone", true)
4671 .Default(false);
4672 return CPUKnown;
4673 }
4674
4675 virtual void getTargetDefines(const LangOptions &Opts,
4676 MacroBuilder &Builder) const override {
4677 // Target identification.
4678 Builder.defineMacro("__aarch64__");
4679
4680 // Target properties.
4681 Builder.defineMacro("_LP64");
4682 Builder.defineMacro("__LP64__");
4683
4684 // ACLE predefines. Many can only have one possible value on v8 AArch64.
4685 Builder.defineMacro("__ARM_ACLE", "200");
4686 Builder.defineMacro("__ARM_ARCH", "8");
4687 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
4688
4689 Builder.defineMacro("__ARM_64BIT_STATE");
4690 Builder.defineMacro("__ARM_PCS_AAPCS64");
4691 Builder.defineMacro("__ARM_ARCH_ISA_A64");
4692
4693 Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
4694 Builder.defineMacro("__ARM_FEATURE_CLZ");
4695 Builder.defineMacro("__ARM_FEATURE_FMA");
4696 Builder.defineMacro("__ARM_FEATURE_DIV");
4697 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE
4698 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
4699 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4700 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4701
4702 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
4703
4704 // 0xe implies support for half, single and double precision operations.
4705 Builder.defineMacro("__ARM_FP", "0xe");
4706
4707 // PCS specifies this for SysV variants, which is all we support. Other ABIs
4708 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
4709 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
4710
4711 if (Opts.FastMath || Opts.FiniteMathOnly)
4712 Builder.defineMacro("__ARM_FP_FAST");
4713
4714 if (Opts.C99 && !Opts.Freestanding)
4715 Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
4716
4717 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
4718
4719 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4720 Opts.ShortEnums ? "1" : "4");
4721
4722 if (FPU == NeonMode) {
4723 Builder.defineMacro("__ARM_NEON");
4724 // 64-bit NEON supports half, single and double precision operations.
4725 Builder.defineMacro("__ARM_NEON_FP", "0xe");
4726 }
4727
4728 if (CRC)
4729 Builder.defineMacro("__ARM_FEATURE_CRC32");
4730
4731 if (Crypto)
4732 Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4733 }
4734
4735 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4736 unsigned &NumRecords) const override {
4737 Records = BuiltinInfo;
4738 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin;
4739 }
4740
4741 bool hasFeature(StringRef Feature) const override {
4742 return Feature == "aarch64" ||
4743 Feature == "arm64" ||
4744 (Feature == "neon" && FPU == NeonMode);
4745 }
4746
4747 bool handleTargetFeatures(std::vector<std::string> &Features,
4748 DiagnosticsEngine &Diags) override {
4749 FPU = FPUMode;
4750 CRC = 0;
4751 Crypto = 0;
4752 for (unsigned i = 0, e = Features.size(); i != e; ++i) {
4753 if (Features[i] == "+neon")
4754 FPU = NeonMode;
4755 if (Features[i] == "+crc")
4756 CRC = 1;
4757 if (Features[i] == "+crypto")
4758 Crypto = 1;
4759 }
4760
4761 setDescriptionString();
4762
4763 return true;
4764 }
4765
4766 bool isCLZForZeroUndef() const override { return false; }
4767
4768 BuiltinVaListKind getBuiltinVaListKind() const override {
4769 return TargetInfo::AArch64ABIBuiltinVaList;
4770 }
4771
4772 virtual void getGCCRegNames(const char *const *&Names,
4773 unsigned &NumNames) const override;
4774 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4775 unsigned &NumAliases) const override;
4776
4777 virtual bool
4778 validateAsmConstraint(const char *&Name,
4779 TargetInfo::ConstraintInfo &Info) const override {
4780 switch (*Name) {
4781 default:
4782 return false;
4783 case 'w': // Floating point and SIMD registers (V0-V31)
4784 Info.setAllowsRegister();
4785 return true;
4786 case 'I': // Constant that can be used with an ADD instruction
4787 case 'J': // Constant that can be used with a SUB instruction
4788 case 'K': // Constant that can be used with a 32-bit logical instruction
4789 case 'L': // Constant that can be used with a 64-bit logical instruction
4790 case 'M': // Constant that can be used as a 32-bit MOV immediate
4791 case 'N': // Constant that can be used as a 64-bit MOV immediate
4792 case 'Y': // Floating point constant zero
4793 case 'Z': // Integer constant zero
4794 return true;
4795 case 'Q': // A memory reference with base register and no offset
4796 Info.setAllowsMemory();
4797 return true;
4798 case 'S': // A symbolic address
4799 Info.setAllowsRegister();
4800 return true;
4801 case 'U':
4802 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
4803 // Utf: A memory address suitable for ldp/stp in TF mode.
4804 // Usa: An absolute symbolic address.
4805 // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
4806 llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
4807 case 'z': // Zero register, wzr or xzr
4808 Info.setAllowsRegister();
4809 return true;
4810 case 'x': // Floating point and SIMD registers (V0-V15)
4811 Info.setAllowsRegister();
4812 return true;
4813 }
4814 return false;
4815 }
4816
4817 bool
4818 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4819 std::string &SuggestedModifier) const override {
4820 // Strip off constraint modifiers.
4821 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
4822 Constraint = Constraint.substr(1);
4823
4824 switch (Constraint[0]) {
4825 default:
4826 return true;
4827 case 'z':
4828 case 'r': {
4829 switch (Modifier) {
4830 case 'x':
4831 case 'w':
4832 // For now assume that the person knows what they're
4833 // doing with the modifier.
4834 return true;
4835 default:
4836 // By default an 'r' constraint will be in the 'x'
4837 // registers.
4838 if (Size == 64)
4839 return true;
4840
4841 SuggestedModifier = "w";
4842 return false;
4843 }
4844 }
4845 }
4846 }
4847
4848 const char *getClobbers() const override { return ""; }
4849
4850 int getEHDataRegisterNumber(unsigned RegNo) const override {
4851 if (RegNo == 0)
4852 return 0;
4853 if (RegNo == 1)
4854 return 1;
4855 return -1;
4856 }
4857};
4858
4859const char *const AArch64TargetInfo::GCCRegNames[] = {
4860 // 32-bit Integer registers
4861 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
4862 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
4863 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
4864
4865 // 64-bit Integer registers
4866 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10",
4867 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
4868 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
4869
4870 // 32-bit floating point regsisters
4871 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10",
4872 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
4873 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4874
4875 // 64-bit floating point regsisters
4876 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10",
4877 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
4878 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4879
4880 // Vector registers
4881 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10",
4882 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
4883 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
4884};
4885
4886void AArch64TargetInfo::getGCCRegNames(const char *const *&Names,
4887 unsigned &NumNames) const {
4888 Names = GCCRegNames;
4889 NumNames = llvm::array_lengthof(GCCRegNames);
4890}
4891
4892const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
4893 { { "w31" }, "wsp" },
4894 { { "x29" }, "fp" },
4895 { { "x30" }, "lr" },
4896 { { "x31" }, "sp" },
4897 // The S/D/Q and W/X registers overlap, but aren't really aliases; we
4898 // don't want to substitute one of these for a different-sized one.
4899};
4900
4901void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4902 unsigned &NumAliases) const {
4903 Aliases = GCCRegAliases;
4904 NumAliases = llvm::array_lengthof(GCCRegAliases);
4905}
4906
4907const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
4908#define BUILTIN(ID, TYPE, ATTRS) \
4909 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4910#include "clang/Basic/BuiltinsNEON.def"
4911
4912#define BUILTIN(ID, TYPE, ATTRS) \
4913 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4914#include "clang/Basic/BuiltinsAArch64.def"
4915};
4916
4917class AArch64leTargetInfo : public AArch64TargetInfo {
4918 void setDescriptionString() override {
4919 if (getTriple().isOSBinFormatMachO())
4920 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128";
4921 else
4922 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128";
4923 }
4924
4925public:
4926 AArch64leTargetInfo(const llvm::Triple &Triple)
4927 : AArch64TargetInfo(Triple) {
4928 BigEndian = false;
4929 }
4930 void getTargetDefines(const LangOptions &Opts,
4931 MacroBuilder &Builder) const override {
4932 Builder.defineMacro("__AARCH64EL__");
4933 AArch64TargetInfo::getTargetDefines(Opts, Builder);
4934 }
4935};
4936
4937class AArch64beTargetInfo : public AArch64TargetInfo {
4938 void setDescriptionString() override {
4939 assert(!getTriple().isOSBinFormatMachO());
4940 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128";
4941 }
4942
4943public:
4944 AArch64beTargetInfo(const llvm::Triple &Triple)
4945 : AArch64TargetInfo(Triple) { }
4946 void getTargetDefines(const LangOptions &Opts,
4947 MacroBuilder &Builder) const override {
4948 Builder.defineMacro("__AARCH64EB__");
4949 Builder.defineMacro("__AARCH_BIG_ENDIAN");
4950 Builder.defineMacro("__ARM_BIG_ENDIAN");
4951 AArch64TargetInfo::getTargetDefines(Opts, Builder);
4952 }
4953};
4954} // end anonymous namespace.
4955
4956namespace {
4957class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
4958protected:
4959 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4960 MacroBuilder &Builder) const override {
4961 Builder.defineMacro("__AARCH64_SIMD__");
4962 Builder.defineMacro("__ARM64_ARCH_8__");
4963 Builder.defineMacro("__ARM_NEON__");
4964 Builder.defineMacro("__LITTLE_ENDIAN__");
4965 Builder.defineMacro("__REGISTER_PREFIX__", "");
4966 Builder.defineMacro("__arm64", "1");
4967 Builder.defineMacro("__arm64__", "1");
4968
4969 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4970 }
4971
4972public:
4973 DarwinAArch64TargetInfo(const llvm::Triple &Triple)
4974 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
4975 Int64Type = SignedLongLong;
4976 WCharType = SignedInt;
4977 UseSignedCharForObjCBool = false;
4978
4979 LongDoubleWidth = LongDoubleAlign = 64;
4980 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4981
4982 TheCXXABI.set(TargetCXXABI::iOS64);
4983 }
4984
4985 BuiltinVaListKind getBuiltinVaListKind() const override {
4986 return TargetInfo::CharPtrBuiltinVaList;
4987 }
4988};
4989} // end anonymous namespace
4990
4991namespace {
4992// Hexagon abstract base class
4993class HexagonTargetInfo : public TargetInfo {
4994 static const Builtin::Info BuiltinInfo[];
4995 static const char * const GCCRegNames[];
4996 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4997 std::string CPU;
4998public:
4999 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5000 BigEndian = false;
5001 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32";
5002
5003 // {} in inline assembly are packet specifiers, not assembly variant
5004 // specifiers.
5005 NoAsmVariants = true;
5006 }
5007
5008 void getTargetBuiltins(const Builtin::Info *&Records,
5009 unsigned &NumRecords) const override {
5010 Records = BuiltinInfo;
5011 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
5012 }
5013
5014 bool validateAsmConstraint(const char *&Name,
5015 TargetInfo::ConstraintInfo &Info) const override {
5016 return true;
5017 }
5018
5019 void getTargetDefines(const LangOptions &Opts,
5020 MacroBuilder &Builder) const override;
5021
5022 bool hasFeature(StringRef Feature) const override {
5023 return Feature == "hexagon";
5024 }
5025
5026 BuiltinVaListKind getBuiltinVaListKind() const override {
5027 return TargetInfo::CharPtrBuiltinVaList;
5028 }
5029 void getGCCRegNames(const char * const *&Names,
5030 unsigned &NumNames) const override;
5031 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5032 unsigned &NumAliases) const override;
5033 const char *getClobbers() const override {
5034 return "";
5035 }
5036
5037 static const char *getHexagonCPUSuffix(StringRef Name) {
5038 return llvm::StringSwitch<const char*>(Name)
5039 .Case("hexagonv4", "4")
5040 .Case("hexagonv5", "5")
5041 .Default(nullptr);
5042 }
5043
5044 bool setCPU(const std::string &Name) override {
5045 if (!getHexagonCPUSuffix(Name))
5046 return false;
5047
5048 CPU = Name;
5049 return true;
5050 }
5051};
5052
5053void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
5054 MacroBuilder &Builder) const {
5055 Builder.defineMacro("qdsp6");
5056 Builder.defineMacro("__qdsp6", "1");
5057 Builder.defineMacro("__qdsp6__", "1");
5058
5059 Builder.defineMacro("hexagon");
5060 Builder.defineMacro("__hexagon", "1");
5061 Builder.defineMacro("__hexagon__", "1");
5062
5063 if(CPU == "hexagonv1") {
5064 Builder.defineMacro("__HEXAGON_V1__");
5065 Builder.defineMacro("__HEXAGON_ARCH__", "1");
5066 if(Opts.HexagonQdsp6Compat) {
5067 Builder.defineMacro("__QDSP6_V1__");
5068 Builder.defineMacro("__QDSP6_ARCH__", "1");
5069 }
5070 }
5071 else if(CPU == "hexagonv2") {
5072 Builder.defineMacro("__HEXAGON_V2__");
5073 Builder.defineMacro("__HEXAGON_ARCH__", "2");
5074 if(Opts.HexagonQdsp6Compat) {
5075 Builder.defineMacro("__QDSP6_V2__");
5076 Builder.defineMacro("__QDSP6_ARCH__", "2");
5077 }
5078 }
5079 else if(CPU == "hexagonv3") {
5080 Builder.defineMacro("__HEXAGON_V3__");
5081 Builder.defineMacro("__HEXAGON_ARCH__", "3");
5082 if(Opts.HexagonQdsp6Compat) {
5083 Builder.defineMacro("__QDSP6_V3__");
5084 Builder.defineMacro("__QDSP6_ARCH__", "3");
5085 }
5086 }
5087 else if(CPU == "hexagonv4") {
5088 Builder.defineMacro("__HEXAGON_V4__");
5089 Builder.defineMacro("__HEXAGON_ARCH__", "4");
5090 if(Opts.HexagonQdsp6Compat) {
5091 Builder.defineMacro("__QDSP6_V4__");
5092 Builder.defineMacro("__QDSP6_ARCH__", "4");
5093 }
5094 }
5095 else if(CPU == "hexagonv5") {
5096 Builder.defineMacro("__HEXAGON_V5__");
5097 Builder.defineMacro("__HEXAGON_ARCH__", "5");
5098 if(Opts.HexagonQdsp6Compat) {
5099 Builder.defineMacro("__QDSP6_V5__");
5100 Builder.defineMacro("__QDSP6_ARCH__", "5");
5101 }
5102 }
5103}
5104
5105const char * const HexagonTargetInfo::GCCRegNames[] = {
5106 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5107 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5108 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5109 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
5110 "p0", "p1", "p2", "p3",
5111 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
5112};
5113
5114void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
5115 unsigned &NumNames) const {
5116 Names = GCCRegNames;
5117 NumNames = llvm::array_lengthof(GCCRegNames);
5118}
5119
5120
5121const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
5122 { { "sp" }, "r29" },
5123 { { "fp" }, "r30" },
5124 { { "lr" }, "r31" },
5125 };
5126
5127void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5128 unsigned &NumAliases) const {
5129 Aliases = GCCRegAliases;
5130 NumAliases = llvm::array_lengthof(GCCRegAliases);
5131}
5132
5133
5134const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
5135#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5136#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5137 ALL_LANGUAGES },
5138#include "clang/Basic/BuiltinsHexagon.def"
5139};
5140}
5141
5142
5143namespace {
5144// Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
5145class SparcTargetInfo : public TargetInfo {
5146 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5147 static const char * const GCCRegNames[];
5148 bool SoftFloat;
5149public:
5150 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {}
5151
5152 bool handleTargetFeatures(std::vector<std::string> &Features,
5153 DiagnosticsEngine &Diags) override {
5154 SoftFloat = false;
5155 for (unsigned i = 0, e = Features.size(); i != e; ++i)
5156 if (Features[i] == "+soft-float")
5157 SoftFloat = true;
5158 return true;
5159 }
5160 void getTargetDefines(const LangOptions &Opts,
5161 MacroBuilder &Builder) const override {
5162 DefineStd(Builder, "sparc", Opts);
5163 Builder.defineMacro("__REGISTER_PREFIX__", "");
5164
5165 if (SoftFloat)
5166 Builder.defineMacro("SOFT_FLOAT", "1");
5167 }
5168
5169 bool hasFeature(StringRef Feature) const override {
5170 return llvm::StringSwitch<bool>(Feature)
5171 .Case("softfloat", SoftFloat)
5172 .Case("sparc", true)
5173 .Default(false);
5174 }
5175
5176 void getTargetBuiltins(const Builtin::Info *&Records,
5177 unsigned &NumRecords) const override {
5178 // FIXME: Implement!
5179 }
5180 BuiltinVaListKind getBuiltinVaListKind() const override {
5181 return TargetInfo::VoidPtrBuiltinVaList;
5182 }
5183 void getGCCRegNames(const char * const *&Names,
5184 unsigned &NumNames) const override;
5185 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5186 unsigned &NumAliases) const override;
5187 bool validateAsmConstraint(const char *&Name,
5188 TargetInfo::ConstraintInfo &info) const override {
5189 // FIXME: Implement!
5190 switch (*Name) {
5191 case 'I': // Signed 13-bit constant
5192 case 'J': // Zero
5193 case 'K': // 32-bit constant with the low 12 bits clear
5194 case 'L': // A constant in the range supported by movcc (11-bit signed imm)
5195 case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
5196 case 'N': // Same as 'K' but zext (required for SIMode)
5197 case 'O': // The constant 4096
5198 return true;
5199 }
5200 return false;
5201 }
5202 const char *getClobbers() const override {
5203 // FIXME: Implement!
5204 return "";
5205 }
5206};
5207
5208const char * const SparcTargetInfo::GCCRegNames[] = {
5209 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5210 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5211 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5212 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5213};
5214
5215void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
5216 unsigned &NumNames) const {
5217 Names = GCCRegNames;
5218 NumNames = llvm::array_lengthof(GCCRegNames);
5219}
5220
5221const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
5222 { { "g0" }, "r0" },
5223 { { "g1" }, "r1" },
5224 { { "g2" }, "r2" },
5225 { { "g3" }, "r3" },
5226 { { "g4" }, "r4" },
5227 { { "g5" }, "r5" },
5228 { { "g6" }, "r6" },
5229 { { "g7" }, "r7" },
5230 { { "o0" }, "r8" },
5231 { { "o1" }, "r9" },
5232 { { "o2" }, "r10" },
5233 { { "o3" }, "r11" },
5234 { { "o4" }, "r12" },
5235 { { "o5" }, "r13" },
5236 { { "o6", "sp" }, "r14" },
5237 { { "o7" }, "r15" },
5238 { { "l0" }, "r16" },
5239 { { "l1" }, "r17" },
5240 { { "l2" }, "r18" },
5241 { { "l3" }, "r19" },
5242 { { "l4" }, "r20" },
5243 { { "l5" }, "r21" },
5244 { { "l6" }, "r22" },
5245 { { "l7" }, "r23" },
5246 { { "i0" }, "r24" },
5247 { { "i1" }, "r25" },
5248 { { "i2" }, "r26" },
5249 { { "i3" }, "r27" },
5250 { { "i4" }, "r28" },
5251 { { "i5" }, "r29" },
5252 { { "i6", "fp" }, "r30" },
5253 { { "i7" }, "r31" },
5254};
5255
5256void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5257 unsigned &NumAliases) const {
5258 Aliases = GCCRegAliases;
5259 NumAliases = llvm::array_lengthof(GCCRegAliases);
5260}
5261
5262// SPARC v8 is the 32-bit mode selected by Triple::sparc.
5263class SparcV8TargetInfo : public SparcTargetInfo {
5264public:
5265 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5266 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
5267 }
5268
5269 void getTargetDefines(const LangOptions &Opts,
5270 MacroBuilder &Builder) const override {
5271 SparcTargetInfo::getTargetDefines(Opts, Builder);
5272 Builder.defineMacro("__sparcv8");
5273 }
5274};
5275
5276// SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
5277class SparcV9TargetInfo : public SparcTargetInfo {
5278public:
5279 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5280 // FIXME: Support Sparc quad-precision long double?
5281 DescriptionString = "E-m:e-i64:64-n32:64-S128";
5282 // This is an LP64 platform.
5283 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5284
5285 // OpenBSD uses long long for int64_t and intmax_t.
5286 if (getTriple().getOS() == llvm::Triple::OpenBSD)
5287 IntMaxType = SignedLongLong;
5288 else
5289 IntMaxType = SignedLong;
5290 Int64Type = IntMaxType;
5291
5292 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
5293 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
5294 LongDoubleWidth = 128;
5295 LongDoubleAlign = 128;
5296 LongDoubleFormat = &llvm::APFloat::IEEEquad;
5297 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5298 }
5299
5300 void getTargetDefines(const LangOptions &Opts,
5301 MacroBuilder &Builder) const override {
5302 SparcTargetInfo::getTargetDefines(Opts, Builder);
5303 Builder.defineMacro("__sparcv9");
5304 Builder.defineMacro("__arch64__");
5305 // Solaris doesn't need these variants, but the BSDs do.
5306 if (getTriple().getOS() != llvm::Triple::Solaris) {
5307 Builder.defineMacro("__sparc64__");
5308 Builder.defineMacro("__sparc_v9__");
5309 Builder.defineMacro("__sparcv9__");
5310 }
5311 }
5312
5313 bool setCPU(const std::string &Name) override {
5314 bool CPUKnown = llvm::StringSwitch<bool>(Name)
5315 .Case("v9", true)
5316 .Case("ultrasparc", true)
5317 .Case("ultrasparc3", true)
5318 .Case("niagara", true)
5319 .Case("niagara2", true)
5320 .Case("niagara3", true)
5321 .Case("niagara4", true)
5322 .Default(false);
5323
5324 // No need to store the CPU yet. There aren't any CPU-specific
5325 // macros to define.
5326 return CPUKnown;
5327 }
5328};
5329
5330} // end anonymous namespace.
5331
5332namespace {
5333class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
5334public:
5335 SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
5336 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) {
5337 SizeType = UnsignedInt;
5338 PtrDiffType = SignedInt;
5339 }
5340};
5341} // end anonymous namespace.
5342
5343namespace {
5344class SystemZTargetInfo : public TargetInfo {
5345 static const char *const GCCRegNames[];
5346
5347public:
5348 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5349 TLSSupported = true;
5350 IntWidth = IntAlign = 32;
5351 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
5352 PointerWidth = PointerAlign = 64;
5353 LongDoubleWidth = 128;
5354 LongDoubleAlign = 64;
5355 LongDoubleFormat = &llvm::APFloat::IEEEquad;
5356 MinGlobalAlign = 16;
5357 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
5358 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5359 }
5360 void getTargetDefines(const LangOptions &Opts,
5361 MacroBuilder &Builder) const override {
5362 Builder.defineMacro("__s390__");
5363 Builder.defineMacro("__s390x__");
5364 Builder.defineMacro("__zarch__");
5365 Builder.defineMacro("__LONG_DOUBLE_128__");
5366 }
5367 void getTargetBuiltins(const Builtin::Info *&Records,
5368 unsigned &NumRecords) const override {
5369 // FIXME: Implement.
5370 Records = nullptr;
5371 NumRecords = 0;
5372 }
5373
5374 void getGCCRegNames(const char *const *&Names,
5375 unsigned &NumNames) const override;
5376 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5377 unsigned &NumAliases) const override {
5378 // No aliases.
5379 Aliases = nullptr;
5380 NumAliases = 0;
5381 }
5382 bool validateAsmConstraint(const char *&Name,
5383 TargetInfo::ConstraintInfo &info) const override;
5384 const char *getClobbers() const override {
5385 // FIXME: Is this really right?
5386 return "";
5387 }
5388 BuiltinVaListKind getBuiltinVaListKind() const override {
5389 return TargetInfo::SystemZBuiltinVaList;
5390 }
5391 bool setCPU(const std::string &Name) override {
5392 bool CPUKnown = llvm::StringSwitch<bool>(Name)
5393 .Case("z10", true)
5394 .Case("z196", true)
5395 .Case("zEC12", true)
5396 .Default(false);
5397
5398 // No need to store the CPU yet. There aren't any CPU-specific
5399 // macros to define.
5400 return CPUKnown;
5401 }
5402};
5403
5404const char *const SystemZTargetInfo::GCCRegNames[] = {
5405 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5406 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5407 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
5408 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
5409};
5410
5411void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
5412 unsigned &NumNames) const {
5413 Names = GCCRegNames;
5414 NumNames = llvm::array_lengthof(GCCRegNames);
5415}
5416
5417bool SystemZTargetInfo::
5418validateAsmConstraint(const char *&Name,
5419 TargetInfo::ConstraintInfo &Info) const {
5420 switch (*Name) {
5421 default:
5422 return false;
5423
5424 case 'a': // Address register
5425 case 'd': // Data register (equivalent to 'r')
5426 case 'f': // Floating-point register
5427 Info.setAllowsRegister();
5428 return true;
5429
5430 case 'I': // Unsigned 8-bit constant
5431 case 'J': // Unsigned 12-bit constant
5432 case 'K': // Signed 16-bit constant
5433 case 'L': // Signed 20-bit displacement (on all targets we support)
5434 case 'M': // 0x7fffffff
5435 return true;
5436
5437 case 'Q': // Memory with base and unsigned 12-bit displacement
5438 case 'R': // Likewise, plus an index
5439 case 'S': // Memory with base and signed 20-bit displacement
5440 case 'T': // Likewise, plus an index
5441 Info.setAllowsMemory();
5442 return true;
5443 }
5444}
5445}
5446
5447namespace {
5448 class MSP430TargetInfo : public TargetInfo {
5449 static const char * const GCCRegNames[];
5450 public:
5451 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5452 BigEndian = false;
5453 TLSSupported = false;
5454 IntWidth = 16; IntAlign = 16;
5455 LongWidth = 32; LongLongWidth = 64;
5456 LongAlign = LongLongAlign = 16;
5457 PointerWidth = 16; PointerAlign = 16;
5458 SuitableAlign = 16;
5459 SizeType = UnsignedInt;
5460 IntMaxType = SignedLongLong;
5461 IntPtrType = SignedInt;
5462 PtrDiffType = SignedInt;
5463 SigAtomicType = SignedLong;
5464 DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16";
5465 }
5466 void getTargetDefines(const LangOptions &Opts,
5467 MacroBuilder &Builder) const override {
5468 Builder.defineMacro("MSP430");
5469 Builder.defineMacro("__MSP430__");
5470 // FIXME: defines for different 'flavours' of MCU
5471 }
5472 void getTargetBuiltins(const Builtin::Info *&Records,
5473 unsigned &NumRecords) const override {
5474 // FIXME: Implement.
5475 Records = nullptr;
5476 NumRecords = 0;
5477 }
5478 bool hasFeature(StringRef Feature) const override {
5479 return Feature == "msp430";
5480 }
5481 void getGCCRegNames(const char * const *&Names,
5482 unsigned &NumNames) const override;
5483 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5484 unsigned &NumAliases) const override {
5485 // No aliases.
5486 Aliases = nullptr;
5487 NumAliases = 0;
5488 }
5489 bool
5490 validateAsmConstraint(const char *&Name,
5491 TargetInfo::ConstraintInfo &info) const override {
5492 // FIXME: implement
5493 switch (*Name) {
5494 case 'K': // the constant 1
5495 case 'L': // constant -1^20 .. 1^19
5496 case 'M': // constant 1-4:
5497 return true;
5498 }
5499 // No target constraints for now.
5500 return false;
5501 }
5502 const char *getClobbers() const override {
5503 // FIXME: Is this really right?
5504 return "";
5505 }
5506 BuiltinVaListKind getBuiltinVaListKind() const override {
5507 // FIXME: implement
5508 return TargetInfo::CharPtrBuiltinVaList;
5509 }
5510 };
5511
5512 const char * const MSP430TargetInfo::GCCRegNames[] = {
5513 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5514 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5515 };
5516
5517 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
5518 unsigned &NumNames) const {
5519 Names = GCCRegNames;
5520 NumNames = llvm::array_lengthof(GCCRegNames);
5521 }
5522}
5523
5524namespace {
5525
5526 // LLVM and Clang cannot be used directly to output native binaries for
5527 // target, but is used to compile C code to llvm bitcode with correct
5528 // type and alignment information.
5529 //
5530 // TCE uses the llvm bitcode as input and uses it for generating customized
5531 // target processor and program binary. TCE co-design environment is
5532 // publicly available in http://tce.cs.tut.fi
5533
5534 static const unsigned TCEOpenCLAddrSpaceMap[] = {
5535 3, // opencl_global
5536 4, // opencl_local
5537 5, // opencl_constant
5538 // FIXME: generic has to be added to the target
5539 0, // opencl_generic
5540 0, // cuda_device
5541 0, // cuda_constant
5542 0 // cuda_shared
5543 };
5544
5545 class TCETargetInfo : public TargetInfo{
5546 public:
5547 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5548 TLSSupported = false;
5549 IntWidth = 32;
5550 LongWidth = LongLongWidth = 32;
5551 PointerWidth = 32;
5552 IntAlign = 32;
5553 LongAlign = LongLongAlign = 32;
5554 PointerAlign = 32;
5555 SuitableAlign = 32;
5556 SizeType = UnsignedInt;
5557 IntMaxType = SignedLong;
5558 IntPtrType = SignedInt;
5559 PtrDiffType = SignedInt;
5560 FloatWidth = 32;
5561 FloatAlign = 32;
5562 DoubleWidth = 32;
5563 DoubleAlign = 32;
5564 LongDoubleWidth = 32;
5565 LongDoubleAlign = 32;
5566 FloatFormat = &llvm::APFloat::IEEEsingle;
5567 DoubleFormat = &llvm::APFloat::IEEEsingle;
5568 LongDoubleFormat = &llvm::APFloat::IEEEsingle;
5569 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
5570 "-f64:32-v64:32-v128:32-a:0:32-n32";
5571 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
5572 UseAddrSpaceMapMangling = true;
5573 }
5574
5575 void getTargetDefines(const LangOptions &Opts,
5576 MacroBuilder &Builder) const override {
5577 DefineStd(Builder, "tce", Opts);
5578 Builder.defineMacro("__TCE__");
5579 Builder.defineMacro("__TCE_V1__");
5580 }
5581 bool hasFeature(StringRef Feature) const override {
5582 return Feature == "tce";
5583 }
5584
5585 void getTargetBuiltins(const Builtin::Info *&Records,
5586 unsigned &NumRecords) const override {}
5587 const char *getClobbers() const override {
5588 return "";
5589 }
5590 BuiltinVaListKind getBuiltinVaListKind() const override {
5591 return TargetInfo::VoidPtrBuiltinVaList;
5592 }
5593 void getGCCRegNames(const char * const *&Names,
5594 unsigned &NumNames) const override {}
5595 bool validateAsmConstraint(const char *&Name,
5596 TargetInfo::ConstraintInfo &info) const override{
5597 return true;
5598 }
5599 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5600 unsigned &NumAliases) const override {}
5601 };
5602}
5603
5604namespace {
5605class MipsTargetInfoBase : public TargetInfo {
5606 virtual void setDescriptionString() = 0;
5607
5608 static const Builtin::Info BuiltinInfo[];
5609 std::string CPU;
5610 bool IsMips16;
5611 bool IsMicromips;
5612 bool IsNan2008;
5613 bool IsSingleFloat;
5614 enum MipsFloatABI {
5615 HardFloat, SoftFloat
5616 } FloatABI;
5617 enum DspRevEnum {
5618 NoDSP, DSP1, DSP2
5619 } DspRev;
5620 bool HasMSA;
5621
5622protected:
5623 bool HasFP64;
5624 std::string ABI;
5625
5626public:
5627 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
5628 const std::string &CPUStr)
5629 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
5630 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
| 3370 }
3371 void getTargetDefines(const LangOptions &Opts,
3372 MacroBuilder &Builder) const override {
3373 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3374 }
3375};
3376
3377// x86-32 Windows Visual Studio target
3378class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3379public:
3380 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3381 : WindowsX86_32TargetInfo(Triple) {
3382 LongDoubleWidth = LongDoubleAlign = 64;
3383 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3384 }
3385 void getTargetDefines(const LangOptions &Opts,
3386 MacroBuilder &Builder) const override {
3387 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3388 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3389 // The value of the following reflects processor type.
3390 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3391 // We lost the original triple, so we use the default.
3392 Builder.defineMacro("_M_IX86", "600");
3393 }
3394};
3395} // end anonymous namespace
3396
3397static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3398 Builder.defineMacro("__MSVCRT__");
3399 Builder.defineMacro("__MINGW32__");
3400
3401 // Mingw defines __declspec(a) to __attribute__((a)). Clang supports
3402 // __declspec natively under -fms-extensions, but we define a no-op __declspec
3403 // macro anyway for pre-processor compatibility.
3404 if (Opts.MicrosoftExt)
3405 Builder.defineMacro("__declspec", "__declspec");
3406 else
3407 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3408
3409 if (!Opts.MicrosoftExt) {
3410 // Provide macros for all the calling convention keywords. Provide both
3411 // single and double underscore prefixed variants. These are available on
3412 // x64 as well as x86, even though they have no effect.
3413 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3414 for (const char *CC : CCs) {
3415 std::string GCCSpelling = "__attribute__((__";
3416 GCCSpelling += CC;
3417 GCCSpelling += "__))";
3418 Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3419 Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3420 }
3421 }
3422}
3423
3424namespace {
3425// x86-32 MinGW target
3426class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3427public:
3428 MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3429 : WindowsX86_32TargetInfo(Triple) {}
3430 void getTargetDefines(const LangOptions &Opts,
3431 MacroBuilder &Builder) const override {
3432 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3433 DefineStd(Builder, "WIN32", Opts);
3434 DefineStd(Builder, "WINNT", Opts);
3435 Builder.defineMacro("_X86_");
3436 addMinGWDefines(Opts, Builder);
3437 }
3438};
3439} // end anonymous namespace
3440
3441namespace {
3442// x86-32 Cygwin target
3443class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3444public:
3445 CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3446 : X86_32TargetInfo(Triple) {
3447 TLSSupported = false;
3448 WCharType = UnsignedShort;
3449 DoubleAlign = LongLongAlign = 64;
3450 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
3451 }
3452 void getTargetDefines(const LangOptions &Opts,
3453 MacroBuilder &Builder) const override {
3454 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3455 Builder.defineMacro("_X86_");
3456 Builder.defineMacro("__CYGWIN__");
3457 Builder.defineMacro("__CYGWIN32__");
3458 DefineStd(Builder, "unix", Opts);
3459 if (Opts.CPlusPlus)
3460 Builder.defineMacro("_GNU_SOURCE");
3461 }
3462};
3463} // end anonymous namespace
3464
3465namespace {
3466// x86-32 Haiku target
3467class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3468public:
3469 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3470 SizeType = UnsignedLong;
3471 IntPtrType = SignedLong;
3472 PtrDiffType = SignedLong;
3473 ProcessIDType = SignedLong;
3474 this->UserLabelPrefix = "";
3475 this->TLSSupported = false;
3476 }
3477 void getTargetDefines(const LangOptions &Opts,
3478 MacroBuilder &Builder) const override {
3479 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3480 Builder.defineMacro("__INTEL__");
3481 Builder.defineMacro("__HAIKU__");
3482 }
3483};
3484} // end anonymous namespace
3485
3486// RTEMS Target
3487template<typename Target>
3488class RTEMSTargetInfo : public OSTargetInfo<Target> {
3489protected:
3490 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3491 MacroBuilder &Builder) const override {
3492 // RTEMS defines; list based off of gcc output
3493
3494 Builder.defineMacro("__rtems__");
3495 Builder.defineMacro("__ELF__");
3496 }
3497
3498public:
3499 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3500 this->UserLabelPrefix = "";
3501
3502 switch (Triple.getArch()) {
3503 default:
3504 case llvm::Triple::x86:
3505 // this->MCountName = ".mcount";
3506 break;
3507 case llvm::Triple::mips:
3508 case llvm::Triple::mipsel:
3509 case llvm::Triple::ppc:
3510 case llvm::Triple::ppc64:
3511 case llvm::Triple::ppc64le:
3512 // this->MCountName = "_mcount";
3513 break;
3514 case llvm::Triple::arm:
3515 // this->MCountName = "__mcount";
3516 break;
3517 }
3518 }
3519};
3520
3521namespace {
3522// x86-32 RTEMS target
3523class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3524public:
3525 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3526 SizeType = UnsignedLong;
3527 IntPtrType = SignedLong;
3528 PtrDiffType = SignedLong;
3529 this->UserLabelPrefix = "";
3530 }
3531 void getTargetDefines(const LangOptions &Opts,
3532 MacroBuilder &Builder) const override {
3533 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3534 Builder.defineMacro("__INTEL__");
3535 Builder.defineMacro("__rtems__");
3536 }
3537};
3538} // end anonymous namespace
3539
3540namespace {
3541// x86-64 generic target
3542class X86_64TargetInfo : public X86TargetInfo {
3543public:
3544 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3545 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3546 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3547 LongDoubleWidth = 128;
3548 LongDoubleAlign = 128;
3549 LargeArrayMinWidth = 128;
3550 LargeArrayAlign = 128;
3551 SuitableAlign = 128;
3552 SizeType = IsX32 ? UnsignedInt : UnsignedLong;
3553 PtrDiffType = IsX32 ? SignedInt : SignedLong;
3554 IntPtrType = IsX32 ? SignedInt : SignedLong;
3555 IntMaxType = IsX32 ? SignedLongLong : SignedLong;
3556 Int64Type = IsX32 ? SignedLongLong : SignedLong;
3557 RegParmMax = 6;
3558
3559 // Pointers are 32-bit in x32.
3560 DescriptionString = (IsX32)
3561 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
3562 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
3563
3564 // Use fpret only for long double.
3565 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3566
3567 // Use fp2ret for _Complex long double.
3568 ComplexLongDoubleUsesFP2Ret = true;
3569
3570 // x86-64 has atomics up to 16 bytes.
3571 MaxAtomicPromoteWidth = 128;
3572 MaxAtomicInlineWidth = 128;
3573 }
3574 BuiltinVaListKind getBuiltinVaListKind() const override {
3575 return TargetInfo::X86_64ABIBuiltinVaList;
3576 }
3577
3578 int getEHDataRegisterNumber(unsigned RegNo) const override {
3579 if (RegNo == 0) return 0;
3580 if (RegNo == 1) return 1;
3581 return -1;
3582 }
3583
3584 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3585 return (CC == CC_C ||
3586 CC == CC_X86VectorCall ||
3587 CC == CC_IntelOclBicc ||
3588 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3589 }
3590
3591 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3592 return CC_C;
3593 }
3594
3595 // for x32 we need it here explicitly
3596 bool hasInt128Type() const override { return true; }
3597};
3598} // end anonymous namespace
3599
3600namespace {
3601// x86-64 Windows target
3602class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3603public:
3604 WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3605 : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3606 WCharType = UnsignedShort;
3607 LongWidth = LongAlign = 32;
3608 DoubleAlign = LongLongAlign = 64;
3609 IntMaxType = SignedLongLong;
3610 Int64Type = SignedLongLong;
3611 SizeType = UnsignedLongLong;
3612 PtrDiffType = SignedLongLong;
3613 IntPtrType = SignedLongLong;
3614 this->UserLabelPrefix = "";
3615 }
3616 void getTargetDefines(const LangOptions &Opts,
3617 MacroBuilder &Builder) const override {
3618 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3619 Builder.defineMacro("_WIN64");
3620 }
3621 BuiltinVaListKind getBuiltinVaListKind() const override {
3622 return TargetInfo::CharPtrBuiltinVaList;
3623 }
3624 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3625 return (CC == CC_C ||
3626 CC == CC_X86VectorCall ||
3627 CC == CC_IntelOclBicc ||
3628 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning;
3629 }
3630};
3631} // end anonymous namespace
3632
3633namespace {
3634// x86-64 Windows Visual Studio target
3635class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
3636public:
3637 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
3638 : WindowsX86_64TargetInfo(Triple) {
3639 LongDoubleWidth = LongDoubleAlign = 64;
3640 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3641 }
3642 void getTargetDefines(const LangOptions &Opts,
3643 MacroBuilder &Builder) const override {
3644 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3645 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3646 Builder.defineMacro("_M_X64");
3647 Builder.defineMacro("_M_AMD64");
3648 }
3649};
3650} // end anonymous namespace
3651
3652namespace {
3653// x86-64 MinGW target
3654class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3655public:
3656 MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3657 : WindowsX86_64TargetInfo(Triple) {}
3658 void getTargetDefines(const LangOptions &Opts,
3659 MacroBuilder &Builder) const override {
3660 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3661 DefineStd(Builder, "WIN64", Opts);
3662 Builder.defineMacro("__MINGW64__");
3663 addMinGWDefines(Opts, Builder);
3664
3665 // GCC defines this macro when it is using __gxx_personality_seh0.
3666 if (!Opts.SjLjExceptions)
3667 Builder.defineMacro("__SEH__");
3668 }
3669};
3670} // end anonymous namespace
3671
3672namespace {
3673class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3674public:
3675 DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3676 : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3677 Int64Type = SignedLongLong;
3678 MaxVectorAlign = 256;
3679 // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
3680 llvm::Triple T = llvm::Triple(Triple);
3681 if (T.isiOS())
3682 UseSignedCharForObjCBool = false;
3683 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
3684 }
3685};
3686} // end anonymous namespace
3687
3688namespace {
3689class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3690public:
3691 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3692 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3693 IntMaxType = SignedLongLong;
3694 Int64Type = SignedLongLong;
3695 }
3696};
3697} // end anonymous namespace
3698
3699namespace {
3700class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3701public:
3702 BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3703 : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3704 IntMaxType = SignedLongLong;
3705 Int64Type = SignedLongLong;
3706 }
3707};
3708}
3709
3710
3711namespace {
3712class ARMTargetInfo : public TargetInfo {
3713 // Possible FPU choices.
3714 enum FPUMode {
3715 VFP2FPU = (1 << 0),
3716 VFP3FPU = (1 << 1),
3717 VFP4FPU = (1 << 2),
3718 NeonFPU = (1 << 3),
3719 FPARMV8 = (1 << 4)
3720 };
3721
3722 // Possible HWDiv features.
3723 enum HWDivMode {
3724 HWDivThumb = (1 << 0),
3725 HWDivARM = (1 << 1)
3726 };
3727
3728 static bool FPUModeIsVFP(FPUMode Mode) {
3729 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
3730 }
3731
3732 static const TargetInfo::GCCRegAlias GCCRegAliases[];
3733 static const char * const GCCRegNames[];
3734
3735 std::string ABI, CPU;
3736
3737 enum {
3738 FP_Default,
3739 FP_VFP,
3740 FP_Neon
3741 } FPMath;
3742
3743 unsigned FPU : 5;
3744
3745 unsigned IsAAPCS : 1;
3746 unsigned IsThumb : 1;
3747 unsigned HWDiv : 2;
3748
3749 // Initialized via features.
3750 unsigned SoftFloat : 1;
3751 unsigned SoftFloatABI : 1;
3752
3753 unsigned CRC : 1;
3754 unsigned Crypto : 1;
3755
3756 // ACLE 6.5.1 Hardware floating point
3757 enum {
3758 HW_FP_HP = (1 << 1), /// half (16-bit)
3759 HW_FP_SP = (1 << 2), /// single (32-bit)
3760 HW_FP_DP = (1 << 3), /// double (64-bit)
3761 };
3762 uint32_t HW_FP;
3763
3764 static const Builtin::Info BuiltinInfo[];
3765
3766 static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3767 StringRef ArchName = T.getArchName();
3768 if (T.getArch() == llvm::Triple::arm ||
3769 T.getArch() == llvm::Triple::armeb) {
3770 StringRef VersionStr;
3771 if (ArchName.startswith("armv"))
3772 VersionStr = ArchName.substr(4, 1);
3773 else if (ArchName.startswith("armebv"))
3774 VersionStr = ArchName.substr(6, 1);
3775 else
3776 return false;
3777 unsigned Version;
3778 if (VersionStr.getAsInteger(10, Version))
3779 return false;
3780 return Version >= 6;
3781 }
3782 assert(T.getArch() == llvm::Triple::thumb ||
3783 T.getArch() == llvm::Triple::thumbeb);
3784 StringRef VersionStr;
3785 if (ArchName.startswith("thumbv"))
3786 VersionStr = ArchName.substr(6, 1);
3787 else if (ArchName.startswith("thumbebv"))
3788 VersionStr = ArchName.substr(8, 1);
3789 else
3790 return false;
3791 unsigned Version;
3792 if (VersionStr.getAsInteger(10, Version))
3793 return false;
3794 return Version >= 7;
3795 }
3796
3797 void setABIAAPCS() {
3798 IsAAPCS = true;
3799
3800 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
3801 const llvm::Triple &T = getTriple();
3802
3803 // size_t is unsigned long on MachO-derived environments and NetBSD.
3804 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD)
3805 SizeType = UnsignedLong;
3806 else
3807 SizeType = UnsignedInt;
3808
3809 switch (T.getOS()) {
3810 case llvm::Triple::NetBSD:
3811 WCharType = SignedInt;
3812 break;
3813 case llvm::Triple::Win32:
3814 WCharType = UnsignedShort;
3815 break;
3816 case llvm::Triple::Linux:
3817 default:
3818 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3819 WCharType = UnsignedInt;
3820 break;
3821 }
3822
3823 UseBitFieldTypeAlignment = true;
3824
3825 ZeroLengthBitfieldBoundary = 0;
3826
3827 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3828 // so set preferred for small types to 32.
3829 if (T.isOSBinFormatMachO()) {
3830 DescriptionString =
3831 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
3832 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
3833 } else if (T.isOSWindows()) {
3834 // FIXME: this is invalid for WindowsCE
3835 assert(!BigEndian && "Windows on ARM does not support big endian");
3836 DescriptionString = "e"
3837 "-m:e"
3838 "-p:32:32"
3839 "-i64:64"
3840 "-v128:64:128"
3841 "-a:0:32"
3842 "-n32"
3843 "-S64";
3844 } else {
3845 DescriptionString =
3846 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
3847 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
3848 }
3849
3850 // FIXME: Enumerated types are variable width in straight AAPCS.
3851 }
3852
3853 void setABIAPCS() {
3854 const llvm::Triple &T = getTriple();
3855
3856 IsAAPCS = false;
3857
3858 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3859
3860 // size_t is unsigned int on FreeBSD.
3861 if (T.getOS() == llvm::Triple::FreeBSD)
3862 SizeType = UnsignedInt;
3863 else
3864 SizeType = UnsignedLong;
3865
3866 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3867 WCharType = SignedInt;
3868
3869 // Do not respect the alignment of bit-field types when laying out
3870 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3871 UseBitFieldTypeAlignment = false;
3872
3873 /// gcc forces the alignment to 4 bytes, regardless of the type of the
3874 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
3875 /// gcc.
3876 ZeroLengthBitfieldBoundary = 32;
3877
3878 if (T.isOSBinFormatMachO())
3879 DescriptionString =
3880 BigEndian
3881 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
3882 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3883 else
3884 DescriptionString =
3885 BigEndian
3886 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
3887 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3888
3889 // FIXME: Override "preferred align" for double and long long.
3890 }
3891
3892public:
3893 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
3894 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
3895 IsAAPCS(true), HW_FP(0) {
3896 BigEndian = IsBigEndian;
3897
3898 switch (getTriple().getOS()) {
3899 case llvm::Triple::NetBSD:
3900 PtrDiffType = SignedLong;
3901 break;
3902 default:
3903 PtrDiffType = SignedInt;
3904 break;
3905 }
3906
3907 // {} in inline assembly are neon specifiers, not assembly variant
3908 // specifiers.
3909 NoAsmVariants = true;
3910
3911 // FIXME: Should we just treat this as a feature?
3912 IsThumb = getTriple().getArchName().startswith("thumb");
3913
3914 // FIXME: This duplicates code from the driver that sets the -target-abi
3915 // option - this code is used if -target-abi isn't passed and should
3916 // be unified in some way.
3917 if (Triple.isOSBinFormatMachO()) {
3918 // The backend is hardwired to assume AAPCS for M-class processors, ensure
3919 // the frontend matches that.
3920 if (Triple.getEnvironment() == llvm::Triple::EABI ||
3921 Triple.getOS() == llvm::Triple::UnknownOS ||
3922 StringRef(CPU).startswith("cortex-m")) {
3923 setABI("aapcs");
3924 } else {
3925 setABI("apcs-gnu");
3926 }
3927 } else if (Triple.isOSWindows()) {
3928 // FIXME: this is invalid for WindowsCE
3929 setABI("aapcs");
3930 } else {
3931 // Select the default based on the platform.
3932 switch (Triple.getEnvironment()) {
3933 case llvm::Triple::Android:
3934 case llvm::Triple::GNUEABI:
3935 case llvm::Triple::GNUEABIHF:
3936 setABI("aapcs-linux");
3937 break;
3938 case llvm::Triple::EABIHF:
3939 case llvm::Triple::EABI:
3940 setABI("aapcs");
3941 break;
3942 case llvm::Triple::GNU:
3943 setABI("apcs-gnu");
3944 break;
3945 default:
3946 if (Triple.getOS() == llvm::Triple::NetBSD)
3947 setABI("apcs-gnu");
3948 else
3949 setABI("aapcs");
3950 break;
3951 }
3952 }
3953
3954 // ARM targets default to using the ARM C++ ABI.
3955 TheCXXABI.set(TargetCXXABI::GenericARM);
3956
3957 // ARM has atomics up to 8 bytes
3958 MaxAtomicPromoteWidth = 64;
3959 if (shouldUseInlineAtomic(getTriple()))
3960 MaxAtomicInlineWidth = 64;
3961
3962 // Do force alignment of members that follow zero length bitfields. If
3963 // the alignment of the zero-length bitfield is greater than the member
3964 // that follows it, `bar', `bar' will be aligned as the type of the
3965 // zero length bitfield.
3966 UseZeroLengthBitfieldAlignment = true;
3967 }
3968 StringRef getABI() const override { return ABI; }
3969 bool setABI(const std::string &Name) override {
3970 ABI = Name;
3971
3972 // The defaults (above) are for AAPCS, check if we need to change them.
3973 //
3974 // FIXME: We need support for -meabi... we could just mangle it into the
3975 // name.
3976 if (Name == "apcs-gnu") {
3977 setABIAPCS();
3978 return true;
3979 }
3980 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
3981 setABIAAPCS();
3982 return true;
3983 }
3984 return false;
3985 }
3986
3987 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
3988 StringRef ArchName = getTriple().getArchName();
3989 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3990 Features["vfp2"] = true;
3991 else if (CPU == "cortex-a8" || CPU == "cortex-a9") {
3992 Features["vfp3"] = true;
3993 Features["neon"] = true;
3994 }
3995 else if (CPU == "cortex-a5") {
3996 Features["vfp4"] = true;
3997 Features["neon"] = true;
3998 } else if (CPU == "swift" || CPU == "cortex-a7" ||
3999 CPU == "cortex-a12" || CPU == "cortex-a15" ||
4000 CPU == "cortex-a17" || CPU == "krait") {
4001 Features["vfp4"] = true;
4002 Features["neon"] = true;
4003 Features["hwdiv"] = true;
4004 Features["hwdiv-arm"] = true;
4005 } else if (CPU == "cyclone") {
4006 Features["v8fp"] = true;
4007 Features["neon"] = true;
4008 Features["hwdiv"] = true;
4009 Features["hwdiv-arm"] = true;
4010 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") {
4011 Features["fp-armv8"] = true;
4012 Features["neon"] = true;
4013 Features["hwdiv"] = true;
4014 Features["hwdiv-arm"] = true;
4015 Features["crc"] = true;
4016 Features["crypto"] = true;
4017 } else if (CPU == "cortex-r5" ||
4018 // Enable the hwdiv extension for all v8a AArch32 cores by
4019 // default.
4020 ArchName == "armv8a" || ArchName == "armv8" ||
4021 ArchName == "armebv8a" || ArchName == "armebv8" ||
4022 ArchName == "thumbv8a" || ArchName == "thumbv8" ||
4023 ArchName == "thumbebv8a" || ArchName == "thumbebv8") {
4024 Features["hwdiv"] = true;
4025 Features["hwdiv-arm"] = true;
4026 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7") {
4027 Features["hwdiv"] = true;
4028 }
4029 }
4030
4031 bool handleTargetFeatures(std::vector<std::string> &Features,
4032 DiagnosticsEngine &Diags) override {
4033 FPU = 0;
4034 CRC = 0;
4035 Crypto = 0;
4036 SoftFloat = SoftFloatABI = false;
4037 HWDiv = 0;
4038
4039 for (const auto &Feature : Features) {
4040 if (Feature == "+soft-float") {
4041 SoftFloat = true;
4042 } else if (Feature == "+soft-float-abi") {
4043 SoftFloatABI = true;
4044 } else if (Feature == "+vfp2") {
4045 FPU |= VFP2FPU;
4046 HW_FP = HW_FP_SP | HW_FP_DP;
4047 } else if (Feature == "+vfp3") {
4048 FPU |= VFP3FPU;
4049 HW_FP = HW_FP_SP | HW_FP_DP;
4050 } else if (Feature == "+vfp4") {
4051 FPU |= VFP4FPU;
4052 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4053 } else if (Feature == "+fp-armv8") {
4054 FPU |= FPARMV8;
4055 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4056 } else if (Feature == "+neon") {
4057 FPU |= NeonFPU;
4058 HW_FP = HW_FP_SP | HW_FP_DP;
4059 } else if (Feature == "+hwdiv") {
4060 HWDiv |= HWDivThumb;
4061 } else if (Feature == "+hwdiv-arm") {
4062 HWDiv |= HWDivARM;
4063 } else if (Feature == "+crc") {
4064 CRC = 1;
4065 } else if (Feature == "+crypto") {
4066 Crypto = 1;
4067 } else if (Feature == "+fp-only-sp") {
4068 HW_FP &= ~HW_FP_DP;
4069 }
4070 }
4071
4072 if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
4073 Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
4074 return false;
4075 }
4076
4077 if (FPMath == FP_Neon)
4078 Features.push_back("+neonfp");
4079 else if (FPMath == FP_VFP)
4080 Features.push_back("-neonfp");
4081
4082 // Remove front-end specific options which the backend handles differently.
4083 const StringRef FrontEndFeatures[] = { "+soft-float", "+soft-float-abi" };
4084 for (const auto &FEFeature : FrontEndFeatures) {
4085 auto Feature = std::find(Features.begin(), Features.end(), FEFeature);
4086 if (Feature != Features.end())
4087 Features.erase(Feature);
4088 }
4089
4090 return true;
4091 }
4092
4093 bool hasFeature(StringRef Feature) const override {
4094 return llvm::StringSwitch<bool>(Feature)
4095 .Case("arm", true)
4096 .Case("softfloat", SoftFloat)
4097 .Case("thumb", IsThumb)
4098 .Case("neon", (FPU & NeonFPU) && !SoftFloat)
4099 .Case("hwdiv", HWDiv & HWDivThumb)
4100 .Case("hwdiv-arm", HWDiv & HWDivARM)
4101 .Default(false);
4102 }
4103 // FIXME: Should we actually have some table instead of these switches?
4104 static const char *getCPUDefineSuffix(StringRef Name) {
4105 return llvm::StringSwitch<const char *>(Name)
4106 .Cases("arm8", "arm810", "4")
4107 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110",
4108 "4")
4109 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
4110 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
4111 .Case("ep9312", "4T")
4112 .Cases("arm10tdmi", "arm1020t", "5T")
4113 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
4114 .Case("arm926ej-s", "5TEJ")
4115 .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
4116 .Cases("xscale", "iwmmxt", "5TE")
4117 .Case("arm1136j-s", "6J")
4118 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
4119 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
4120 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
4121 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
4122 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
4123 "7A")
4124 .Cases("cortex-r4", "cortex-r5", "7R")
4125 .Case("swift", "7S")
4126 .Case("cyclone", "8A")
4127 .Case("cortex-m3", "7M")
4128 .Cases("cortex-m4", "cortex-m7", "7EM")
4129 .Case("cortex-m0", "6M")
4130 .Cases("cortex-a53", "cortex-a57", "8A")
4131 .Default(nullptr);
4132 }
4133 static const char *getCPUProfile(StringRef Name) {
4134 return llvm::StringSwitch<const char *>(Name)
4135 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A")
4136 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
4137 "A")
4138 .Cases("cortex-a53", "cortex-a57", "A")
4139 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m7", "M")
4140 .Cases("cortex-r4", "cortex-r5", "R")
4141 .Default("");
4142 }
4143 bool setCPU(const std::string &Name) override {
4144 if (!getCPUDefineSuffix(Name))
4145 return false;
4146
4147 // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4148 StringRef Profile = getCPUProfile(Name);
4149 if (Profile == "M" && MaxAtomicInlineWidth) {
4150 MaxAtomicPromoteWidth = 32;
4151 MaxAtomicInlineWidth = 32;
4152 }
4153
4154 CPU = Name;
4155 return true;
4156 }
4157 bool setFPMath(StringRef Name) override;
4158 bool supportsThumb(StringRef ArchName, StringRef CPUArch,
4159 unsigned CPUArchVer) const {
4160 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) ||
4161 (CPUArch.find('M') != StringRef::npos);
4162 }
4163 bool supportsThumb2(StringRef ArchName, StringRef CPUArch,
4164 unsigned CPUArchVer) const {
4165 // We check both CPUArchVer and ArchName because when only triple is
4166 // specified, the default CPU is arm1136j-s.
4167 return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
4168 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
4169 }
4170 void getTargetDefines(const LangOptions &Opts,
4171 MacroBuilder &Builder) const override {
4172 // Target identification.
4173 Builder.defineMacro("__arm");
4174 Builder.defineMacro("__arm__");
4175
4176 // Target properties.
4177 Builder.defineMacro("__REGISTER_PREFIX__", "");
4178
4179 StringRef CPUArch = getCPUDefineSuffix(CPU);
4180 unsigned int CPUArchVer;
4181 if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer))
4182 llvm_unreachable("Invalid char for architecture version number");
4183 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
4184
4185 // ACLE 6.4.1 ARM/Thumb instruction set architecture
4186 StringRef CPUProfile = getCPUProfile(CPU);
4187 StringRef ArchName = getTriple().getArchName();
4188
4189 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
4190 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
4191 if (CPUArch[0] >= '8') {
4192 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4193 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4194 }
4195
4196 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
4197 // is not defined for the M-profile.
4198 // NOTE that the deffault profile is assumed to be 'A'
4199 if (CPUProfile.empty() || CPUProfile != "M")
4200 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
4201
4202 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
4203 // Thumb ISA (including v6-M). It is set to 2 if the core supports the
4204 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
4205 if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4206 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
4207 else if (supportsThumb(ArchName, CPUArch, CPUArchVer))
4208 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
4209
4210 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
4211 // instruction set such as ARM or Thumb.
4212 Builder.defineMacro("__ARM_32BIT_STATE", "1");
4213
4214 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
4215
4216 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
4217 if (!CPUProfile.empty())
4218 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
4219
4220 // ACLE 6.5.1 Hardware Floating Point
4221 if (HW_FP)
4222 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
4223
4224 // ACLE predefines.
4225 Builder.defineMacro("__ARM_ACLE", "200");
4226
4227 // Subtarget options.
4228
4229 // FIXME: It's more complicated than this and we don't really support
4230 // interworking.
4231 // Windows on ARM does not "support" interworking
4232 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows())
4233 Builder.defineMacro("__THUMB_INTERWORK__");
4234
4235 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
4236 // Embedded targets on Darwin follow AAPCS, but not EABI.
4237 // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
4238 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
4239 Builder.defineMacro("__ARM_EABI__");
4240 Builder.defineMacro("__ARM_PCS", "1");
4241
4242 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
4243 Builder.defineMacro("__ARM_PCS_VFP", "1");
4244 }
4245
4246 if (SoftFloat)
4247 Builder.defineMacro("__SOFTFP__");
4248
4249 if (CPU == "xscale")
4250 Builder.defineMacro("__XSCALE__");
4251
4252 if (IsThumb) {
4253 Builder.defineMacro("__THUMBEL__");
4254 Builder.defineMacro("__thumb__");
4255 if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4256 Builder.defineMacro("__thumb2__");
4257 }
4258 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
4259 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
4260
4261 // Note, this is always on in gcc, even though it doesn't make sense.
4262 Builder.defineMacro("__APCS_32__");
4263
4264 if (FPUModeIsVFP((FPUMode) FPU)) {
4265 Builder.defineMacro("__VFP_FP__");
4266 if (FPU & VFP2FPU)
4267 Builder.defineMacro("__ARM_VFPV2__");
4268 if (FPU & VFP3FPU)
4269 Builder.defineMacro("__ARM_VFPV3__");
4270 if (FPU & VFP4FPU)
4271 Builder.defineMacro("__ARM_VFPV4__");
4272 }
4273
4274 // This only gets set when Neon instructions are actually available, unlike
4275 // the VFP define, hence the soft float and arch check. This is subtly
4276 // different from gcc, we follow the intent which was that it should be set
4277 // when Neon instructions are actually available.
4278 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) {
4279 Builder.defineMacro("__ARM_NEON");
4280 Builder.defineMacro("__ARM_NEON__");
4281 }
4282
4283 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
4284 Opts.ShortWChar ? "2" : "4");
4285
4286 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4287 Opts.ShortEnums ? "1" : "4");
4288
4289 if (CRC)
4290 Builder.defineMacro("__ARM_FEATURE_CRC32");
4291
4292 if (Crypto)
4293 Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4294
4295 if (CPUArchVer >= 6 && CPUArch != "6M") {
4296 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4297 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4298 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4299 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4300 }
4301
4302 bool is5EOrAbove = (CPUArchVer >= 6 ||
4303 (CPUArchVer == 5 &&
4304 CPUArch.find('E') != StringRef::npos));
4305 bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer));
4306 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch == "7EM"))
4307 Builder.defineMacro("__ARM_FEATURE_DSP");
4308 }
4309 void getTargetBuiltins(const Builtin::Info *&Records,
4310 unsigned &NumRecords) const override {
4311 Records = BuiltinInfo;
4312 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
4313 }
4314 bool isCLZForZeroUndef() const override { return false; }
4315 BuiltinVaListKind getBuiltinVaListKind() const override {
4316 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
4317 }
4318 void getGCCRegNames(const char * const *&Names,
4319 unsigned &NumNames) const override;
4320 void getGCCRegAliases(const GCCRegAlias *&Aliases,
4321 unsigned &NumAliases) const override;
4322 bool validateAsmConstraint(const char *&Name,
4323 TargetInfo::ConstraintInfo &Info) const override {
4324 switch (*Name) {
4325 default: break;
4326 case 'l': // r0-r7
4327 case 'h': // r8-r15
4328 case 'w': // VFP Floating point register single precision
4329 case 'P': // VFP Floating point register double precision
4330 Info.setAllowsRegister();
4331 return true;
4332 case 'I':
4333 case 'J':
4334 case 'K':
4335 case 'L':
4336 case 'M':
4337 // FIXME
4338 return true;
4339 case 'Q': // A memory address that is a single base register.
4340 Info.setAllowsMemory();
4341 return true;
4342 case 'U': // a memory reference...
4343 switch (Name[1]) {
4344 case 'q': // ...ARMV4 ldrsb
4345 case 'v': // ...VFP load/store (reg+constant offset)
4346 case 'y': // ...iWMMXt load/store
4347 case 't': // address valid for load/store opaque types wider
4348 // than 128-bits
4349 case 'n': // valid address for Neon doubleword vector load/store
4350 case 'm': // valid address for Neon element and structure load/store
4351 case 's': // valid address for non-offset loads/stores of quad-word
4352 // values in four ARM registers
4353 Info.setAllowsMemory();
4354 Name++;
4355 return true;
4356 }
4357 }
4358 return false;
4359 }
4360 std::string convertConstraint(const char *&Constraint) const override {
4361 std::string R;
4362 switch (*Constraint) {
4363 case 'U': // Two-character constraint; add "^" hint for later parsing.
4364 R = std::string("^") + std::string(Constraint, 2);
4365 Constraint++;
4366 break;
4367 case 'p': // 'p' should be translated to 'r' by default.
4368 R = std::string("r");
4369 break;
4370 default:
4371 return std::string(1, *Constraint);
4372 }
4373 return R;
4374 }
4375 bool
4376 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4377 std::string &SuggestedModifier) const override {
4378 bool isOutput = (Constraint[0] == '=');
4379 bool isInOut = (Constraint[0] == '+');
4380
4381 // Strip off constraint modifiers.
4382 while (Constraint[0] == '=' ||
4383 Constraint[0] == '+' ||
4384 Constraint[0] == '&')
4385 Constraint = Constraint.substr(1);
4386
4387 switch (Constraint[0]) {
4388 default: break;
4389 case 'r': {
4390 switch (Modifier) {
4391 default:
4392 return (isInOut || isOutput || Size <= 64);
4393 case 'q':
4394 // A register of size 32 cannot fit a vector type.
4395 return false;
4396 }
4397 }
4398 }
4399
4400 return true;
4401 }
4402 const char *getClobbers() const override {
4403 // FIXME: Is this really right?
4404 return "";
4405 }
4406
4407 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4408 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4409 }
4410
4411 int getEHDataRegisterNumber(unsigned RegNo) const override {
4412 if (RegNo == 0) return 0;
4413 if (RegNo == 1) return 1;
4414 return -1;
4415 }
4416};
4417
4418bool ARMTargetInfo::setFPMath(StringRef Name) {
4419 if (Name == "neon") {
4420 FPMath = FP_Neon;
4421 return true;
4422 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
4423 Name == "vfp4") {
4424 FPMath = FP_VFP;
4425 return true;
4426 }
4427 return false;
4428}
4429
4430const char * const ARMTargetInfo::GCCRegNames[] = {
4431 // Integer registers
4432 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4433 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
4434
4435 // Float registers
4436 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
4437 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
4438 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
4439 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4440
4441 // Double registers
4442 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
4443 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
4444 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
4445 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4446
4447 // Quad registers
4448 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
4449 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
4450};
4451
4452void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
4453 unsigned &NumNames) const {
4454 Names = GCCRegNames;
4455 NumNames = llvm::array_lengthof(GCCRegNames);
4456}
4457
4458const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
4459 { { "a1" }, "r0" },
4460 { { "a2" }, "r1" },
4461 { { "a3" }, "r2" },
4462 { { "a4" }, "r3" },
4463 { { "v1" }, "r4" },
4464 { { "v2" }, "r5" },
4465 { { "v3" }, "r6" },
4466 { { "v4" }, "r7" },
4467 { { "v5" }, "r8" },
4468 { { "v6", "rfp" }, "r9" },
4469 { { "sl" }, "r10" },
4470 { { "fp" }, "r11" },
4471 { { "ip" }, "r12" },
4472 { { "r13" }, "sp" },
4473 { { "r14" }, "lr" },
4474 { { "r15" }, "pc" },
4475 // The S, D and Q registers overlap, but aren't really aliases; we
4476 // don't want to substitute one of these for a different-sized one.
4477};
4478
4479void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4480 unsigned &NumAliases) const {
4481 Aliases = GCCRegAliases;
4482 NumAliases = llvm::array_lengthof(GCCRegAliases);
4483}
4484
4485const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
4486#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4487#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4488 ALL_LANGUAGES },
4489#include "clang/Basic/BuiltinsNEON.def"
4490
4491#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4492#define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG },
4493#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4494 ALL_LANGUAGES },
4495#include "clang/Basic/BuiltinsARM.def"
4496};
4497
4498class ARMleTargetInfo : public ARMTargetInfo {
4499public:
4500 ARMleTargetInfo(const llvm::Triple &Triple)
4501 : ARMTargetInfo(Triple, false) { }
4502 virtual void getTargetDefines(const LangOptions &Opts,
4503 MacroBuilder &Builder) const {
4504 Builder.defineMacro("__ARMEL__");
4505 ARMTargetInfo::getTargetDefines(Opts, Builder);
4506 }
4507};
4508
4509class ARMbeTargetInfo : public ARMTargetInfo {
4510public:
4511 ARMbeTargetInfo(const llvm::Triple &Triple)
4512 : ARMTargetInfo(Triple, true) { }
4513 virtual void getTargetDefines(const LangOptions &Opts,
4514 MacroBuilder &Builder) const {
4515 Builder.defineMacro("__ARMEB__");
4516 Builder.defineMacro("__ARM_BIG_ENDIAN");
4517 ARMTargetInfo::getTargetDefines(Opts, Builder);
4518 }
4519};
4520} // end anonymous namespace.
4521
4522namespace {
4523class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
4524 const llvm::Triple Triple;
4525public:
4526 WindowsARMTargetInfo(const llvm::Triple &Triple)
4527 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
4528 TLSSupported = false;
4529 WCharType = UnsignedShort;
4530 SizeType = UnsignedInt;
4531 UserLabelPrefix = "";
4532 }
4533 void getVisualStudioDefines(const LangOptions &Opts,
4534 MacroBuilder &Builder) const {
4535 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
4536
4537 // FIXME: this is invalid for WindowsCE
4538 Builder.defineMacro("_M_ARM_NT", "1");
4539 Builder.defineMacro("_M_ARMT", "_M_ARM");
4540 Builder.defineMacro("_M_THUMB", "_M_ARM");
4541
4542 assert((Triple.getArch() == llvm::Triple::arm ||
4543 Triple.getArch() == llvm::Triple::thumb) &&
4544 "invalid architecture for Windows ARM target info");
4545 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
4546 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
4547
4548 // TODO map the complete set of values
4549 // 31: VFPv3 40: VFPv4
4550 Builder.defineMacro("_M_ARM_FP", "31");
4551 }
4552 BuiltinVaListKind getBuiltinVaListKind() const override {
4553 return TargetInfo::CharPtrBuiltinVaList;
4554 }
4555};
4556
4557// Windows ARM + Itanium C++ ABI Target
4558class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
4559public:
4560 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
4561 : WindowsARMTargetInfo(Triple) {
4562 TheCXXABI.set(TargetCXXABI::GenericARM);
4563 }
4564
4565 void getTargetDefines(const LangOptions &Opts,
4566 MacroBuilder &Builder) const override {
4567 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4568
4569 if (Opts.MSVCCompat)
4570 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4571 }
4572};
4573
4574// Windows ARM, MS (C++) ABI
4575class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
4576public:
4577 MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
4578 : WindowsARMTargetInfo(Triple) {
4579 TheCXXABI.set(TargetCXXABI::Microsoft);
4580 }
4581
4582 void getTargetDefines(const LangOptions &Opts,
4583 MacroBuilder &Builder) const override {
4584 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4585 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4586 }
4587};
4588}
4589
4590
4591namespace {
4592class DarwinARMTargetInfo :
4593 public DarwinTargetInfo<ARMleTargetInfo> {
4594protected:
4595 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4596 MacroBuilder &Builder) const override {
4597 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4598 }
4599
4600public:
4601 DarwinARMTargetInfo(const llvm::Triple &Triple)
4602 : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
4603 HasAlignMac68kSupport = true;
4604 // iOS always has 64-bit atomic instructions.
4605 // FIXME: This should be based off of the target features in
4606 // ARMleTargetInfo.
4607 MaxAtomicInlineWidth = 64;
4608
4609 // Darwin on iOS uses a variant of the ARM C++ ABI.
4610 TheCXXABI.set(TargetCXXABI::iOS);
4611 }
4612};
4613} // end anonymous namespace.
4614
4615
4616namespace {
4617class AArch64TargetInfo : public TargetInfo {
4618 virtual void setDescriptionString() = 0;
4619 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4620 static const char *const GCCRegNames[];
4621
4622 enum FPUModeEnum {
4623 FPUMode,
4624 NeonMode
4625 };
4626
4627 unsigned FPU;
4628 unsigned CRC;
4629 unsigned Crypto;
4630
4631 static const Builtin::Info BuiltinInfo[];
4632
4633 std::string ABI;
4634
4635public:
4636 AArch64TargetInfo(const llvm::Triple &Triple)
4637 : TargetInfo(Triple), ABI("aapcs") {
4638
4639 if (getTriple().getOS() == llvm::Triple::NetBSD) {
4640 WCharType = SignedInt;
4641
4642 // NetBSD apparently prefers consistency across ARM targets to consistency
4643 // across 64-bit targets.
4644 Int64Type = SignedLongLong;
4645 IntMaxType = SignedLongLong;
4646 } else {
4647 WCharType = UnsignedInt;
4648 Int64Type = SignedLong;
4649 IntMaxType = SignedLong;
4650 }
4651
4652 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4653 MaxVectorAlign = 128;
4654 RegParmMax = 8;
4655 MaxAtomicInlineWidth = 128;
4656 MaxAtomicPromoteWidth = 128;
4657
4658 LongDoubleWidth = LongDoubleAlign = 128;
4659 LongDoubleFormat = &llvm::APFloat::IEEEquad;
4660
4661 // {} in inline assembly are neon specifiers, not assembly variant
4662 // specifiers.
4663 NoAsmVariants = true;
4664
4665 // AArch64 targets default to using the ARM C++ ABI.
4666 TheCXXABI.set(TargetCXXABI::GenericAArch64);
4667 }
4668
4669 StringRef getABI() const override { return ABI; }
4670 bool setABI(const std::string &Name) override {
4671 if (Name != "aapcs" && Name != "darwinpcs")
4672 return false;
4673
4674 ABI = Name;
4675 return true;
4676 }
4677
4678 bool setCPU(const std::string &Name) override {
4679 bool CPUKnown = llvm::StringSwitch<bool>(Name)
4680 .Case("generic", true)
4681 .Cases("cortex-a53", "cortex-a57", true)
4682 .Case("cyclone", true)
4683 .Default(false);
4684 return CPUKnown;
4685 }
4686
4687 virtual void getTargetDefines(const LangOptions &Opts,
4688 MacroBuilder &Builder) const override {
4689 // Target identification.
4690 Builder.defineMacro("__aarch64__");
4691
4692 // Target properties.
4693 Builder.defineMacro("_LP64");
4694 Builder.defineMacro("__LP64__");
4695
4696 // ACLE predefines. Many can only have one possible value on v8 AArch64.
4697 Builder.defineMacro("__ARM_ACLE", "200");
4698 Builder.defineMacro("__ARM_ARCH", "8");
4699 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
4700
4701 Builder.defineMacro("__ARM_64BIT_STATE");
4702 Builder.defineMacro("__ARM_PCS_AAPCS64");
4703 Builder.defineMacro("__ARM_ARCH_ISA_A64");
4704
4705 Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
4706 Builder.defineMacro("__ARM_FEATURE_CLZ");
4707 Builder.defineMacro("__ARM_FEATURE_FMA");
4708 Builder.defineMacro("__ARM_FEATURE_DIV");
4709 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE
4710 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
4711 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4712 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4713
4714 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
4715
4716 // 0xe implies support for half, single and double precision operations.
4717 Builder.defineMacro("__ARM_FP", "0xe");
4718
4719 // PCS specifies this for SysV variants, which is all we support. Other ABIs
4720 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
4721 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
4722
4723 if (Opts.FastMath || Opts.FiniteMathOnly)
4724 Builder.defineMacro("__ARM_FP_FAST");
4725
4726 if (Opts.C99 && !Opts.Freestanding)
4727 Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
4728
4729 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
4730
4731 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4732 Opts.ShortEnums ? "1" : "4");
4733
4734 if (FPU == NeonMode) {
4735 Builder.defineMacro("__ARM_NEON");
4736 // 64-bit NEON supports half, single and double precision operations.
4737 Builder.defineMacro("__ARM_NEON_FP", "0xe");
4738 }
4739
4740 if (CRC)
4741 Builder.defineMacro("__ARM_FEATURE_CRC32");
4742
4743 if (Crypto)
4744 Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4745 }
4746
4747 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4748 unsigned &NumRecords) const override {
4749 Records = BuiltinInfo;
4750 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin;
4751 }
4752
4753 bool hasFeature(StringRef Feature) const override {
4754 return Feature == "aarch64" ||
4755 Feature == "arm64" ||
4756 (Feature == "neon" && FPU == NeonMode);
4757 }
4758
4759 bool handleTargetFeatures(std::vector<std::string> &Features,
4760 DiagnosticsEngine &Diags) override {
4761 FPU = FPUMode;
4762 CRC = 0;
4763 Crypto = 0;
4764 for (unsigned i = 0, e = Features.size(); i != e; ++i) {
4765 if (Features[i] == "+neon")
4766 FPU = NeonMode;
4767 if (Features[i] == "+crc")
4768 CRC = 1;
4769 if (Features[i] == "+crypto")
4770 Crypto = 1;
4771 }
4772
4773 setDescriptionString();
4774
4775 return true;
4776 }
4777
4778 bool isCLZForZeroUndef() const override { return false; }
4779
4780 BuiltinVaListKind getBuiltinVaListKind() const override {
4781 return TargetInfo::AArch64ABIBuiltinVaList;
4782 }
4783
4784 virtual void getGCCRegNames(const char *const *&Names,
4785 unsigned &NumNames) const override;
4786 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4787 unsigned &NumAliases) const override;
4788
4789 virtual bool
4790 validateAsmConstraint(const char *&Name,
4791 TargetInfo::ConstraintInfo &Info) const override {
4792 switch (*Name) {
4793 default:
4794 return false;
4795 case 'w': // Floating point and SIMD registers (V0-V31)
4796 Info.setAllowsRegister();
4797 return true;
4798 case 'I': // Constant that can be used with an ADD instruction
4799 case 'J': // Constant that can be used with a SUB instruction
4800 case 'K': // Constant that can be used with a 32-bit logical instruction
4801 case 'L': // Constant that can be used with a 64-bit logical instruction
4802 case 'M': // Constant that can be used as a 32-bit MOV immediate
4803 case 'N': // Constant that can be used as a 64-bit MOV immediate
4804 case 'Y': // Floating point constant zero
4805 case 'Z': // Integer constant zero
4806 return true;
4807 case 'Q': // A memory reference with base register and no offset
4808 Info.setAllowsMemory();
4809 return true;
4810 case 'S': // A symbolic address
4811 Info.setAllowsRegister();
4812 return true;
4813 case 'U':
4814 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
4815 // Utf: A memory address suitable for ldp/stp in TF mode.
4816 // Usa: An absolute symbolic address.
4817 // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
4818 llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
4819 case 'z': // Zero register, wzr or xzr
4820 Info.setAllowsRegister();
4821 return true;
4822 case 'x': // Floating point and SIMD registers (V0-V15)
4823 Info.setAllowsRegister();
4824 return true;
4825 }
4826 return false;
4827 }
4828
4829 bool
4830 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4831 std::string &SuggestedModifier) const override {
4832 // Strip off constraint modifiers.
4833 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
4834 Constraint = Constraint.substr(1);
4835
4836 switch (Constraint[0]) {
4837 default:
4838 return true;
4839 case 'z':
4840 case 'r': {
4841 switch (Modifier) {
4842 case 'x':
4843 case 'w':
4844 // For now assume that the person knows what they're
4845 // doing with the modifier.
4846 return true;
4847 default:
4848 // By default an 'r' constraint will be in the 'x'
4849 // registers.
4850 if (Size == 64)
4851 return true;
4852
4853 SuggestedModifier = "w";
4854 return false;
4855 }
4856 }
4857 }
4858 }
4859
4860 const char *getClobbers() const override { return ""; }
4861
4862 int getEHDataRegisterNumber(unsigned RegNo) const override {
4863 if (RegNo == 0)
4864 return 0;
4865 if (RegNo == 1)
4866 return 1;
4867 return -1;
4868 }
4869};
4870
4871const char *const AArch64TargetInfo::GCCRegNames[] = {
4872 // 32-bit Integer registers
4873 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
4874 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
4875 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
4876
4877 // 64-bit Integer registers
4878 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10",
4879 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
4880 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
4881
4882 // 32-bit floating point regsisters
4883 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10",
4884 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
4885 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4886
4887 // 64-bit floating point regsisters
4888 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10",
4889 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
4890 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4891
4892 // Vector registers
4893 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10",
4894 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
4895 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
4896};
4897
4898void AArch64TargetInfo::getGCCRegNames(const char *const *&Names,
4899 unsigned &NumNames) const {
4900 Names = GCCRegNames;
4901 NumNames = llvm::array_lengthof(GCCRegNames);
4902}
4903
4904const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
4905 { { "w31" }, "wsp" },
4906 { { "x29" }, "fp" },
4907 { { "x30" }, "lr" },
4908 { { "x31" }, "sp" },
4909 // The S/D/Q and W/X registers overlap, but aren't really aliases; we
4910 // don't want to substitute one of these for a different-sized one.
4911};
4912
4913void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4914 unsigned &NumAliases) const {
4915 Aliases = GCCRegAliases;
4916 NumAliases = llvm::array_lengthof(GCCRegAliases);
4917}
4918
4919const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
4920#define BUILTIN(ID, TYPE, ATTRS) \
4921 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4922#include "clang/Basic/BuiltinsNEON.def"
4923
4924#define BUILTIN(ID, TYPE, ATTRS) \
4925 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4926#include "clang/Basic/BuiltinsAArch64.def"
4927};
4928
4929class AArch64leTargetInfo : public AArch64TargetInfo {
4930 void setDescriptionString() override {
4931 if (getTriple().isOSBinFormatMachO())
4932 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128";
4933 else
4934 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128";
4935 }
4936
4937public:
4938 AArch64leTargetInfo(const llvm::Triple &Triple)
4939 : AArch64TargetInfo(Triple) {
4940 BigEndian = false;
4941 }
4942 void getTargetDefines(const LangOptions &Opts,
4943 MacroBuilder &Builder) const override {
4944 Builder.defineMacro("__AARCH64EL__");
4945 AArch64TargetInfo::getTargetDefines(Opts, Builder);
4946 }
4947};
4948
4949class AArch64beTargetInfo : public AArch64TargetInfo {
4950 void setDescriptionString() override {
4951 assert(!getTriple().isOSBinFormatMachO());
4952 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128";
4953 }
4954
4955public:
4956 AArch64beTargetInfo(const llvm::Triple &Triple)
4957 : AArch64TargetInfo(Triple) { }
4958 void getTargetDefines(const LangOptions &Opts,
4959 MacroBuilder &Builder) const override {
4960 Builder.defineMacro("__AARCH64EB__");
4961 Builder.defineMacro("__AARCH_BIG_ENDIAN");
4962 Builder.defineMacro("__ARM_BIG_ENDIAN");
4963 AArch64TargetInfo::getTargetDefines(Opts, Builder);
4964 }
4965};
4966} // end anonymous namespace.
4967
4968namespace {
4969class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
4970protected:
4971 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4972 MacroBuilder &Builder) const override {
4973 Builder.defineMacro("__AARCH64_SIMD__");
4974 Builder.defineMacro("__ARM64_ARCH_8__");
4975 Builder.defineMacro("__ARM_NEON__");
4976 Builder.defineMacro("__LITTLE_ENDIAN__");
4977 Builder.defineMacro("__REGISTER_PREFIX__", "");
4978 Builder.defineMacro("__arm64", "1");
4979 Builder.defineMacro("__arm64__", "1");
4980
4981 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4982 }
4983
4984public:
4985 DarwinAArch64TargetInfo(const llvm::Triple &Triple)
4986 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
4987 Int64Type = SignedLongLong;
4988 WCharType = SignedInt;
4989 UseSignedCharForObjCBool = false;
4990
4991 LongDoubleWidth = LongDoubleAlign = 64;
4992 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4993
4994 TheCXXABI.set(TargetCXXABI::iOS64);
4995 }
4996
4997 BuiltinVaListKind getBuiltinVaListKind() const override {
4998 return TargetInfo::CharPtrBuiltinVaList;
4999 }
5000};
5001} // end anonymous namespace
5002
5003namespace {
5004// Hexagon abstract base class
5005class HexagonTargetInfo : public TargetInfo {
5006 static const Builtin::Info BuiltinInfo[];
5007 static const char * const GCCRegNames[];
5008 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5009 std::string CPU;
5010public:
5011 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5012 BigEndian = false;
5013 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32";
5014
5015 // {} in inline assembly are packet specifiers, not assembly variant
5016 // specifiers.
5017 NoAsmVariants = true;
5018 }
5019
5020 void getTargetBuiltins(const Builtin::Info *&Records,
5021 unsigned &NumRecords) const override {
5022 Records = BuiltinInfo;
5023 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
5024 }
5025
5026 bool validateAsmConstraint(const char *&Name,
5027 TargetInfo::ConstraintInfo &Info) const override {
5028 return true;
5029 }
5030
5031 void getTargetDefines(const LangOptions &Opts,
5032 MacroBuilder &Builder) const override;
5033
5034 bool hasFeature(StringRef Feature) const override {
5035 return Feature == "hexagon";
5036 }
5037
5038 BuiltinVaListKind getBuiltinVaListKind() const override {
5039 return TargetInfo::CharPtrBuiltinVaList;
5040 }
5041 void getGCCRegNames(const char * const *&Names,
5042 unsigned &NumNames) const override;
5043 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5044 unsigned &NumAliases) const override;
5045 const char *getClobbers() const override {
5046 return "";
5047 }
5048
5049 static const char *getHexagonCPUSuffix(StringRef Name) {
5050 return llvm::StringSwitch<const char*>(Name)
5051 .Case("hexagonv4", "4")
5052 .Case("hexagonv5", "5")
5053 .Default(nullptr);
5054 }
5055
5056 bool setCPU(const std::string &Name) override {
5057 if (!getHexagonCPUSuffix(Name))
5058 return false;
5059
5060 CPU = Name;
5061 return true;
5062 }
5063};
5064
5065void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
5066 MacroBuilder &Builder) const {
5067 Builder.defineMacro("qdsp6");
5068 Builder.defineMacro("__qdsp6", "1");
5069 Builder.defineMacro("__qdsp6__", "1");
5070
5071 Builder.defineMacro("hexagon");
5072 Builder.defineMacro("__hexagon", "1");
5073 Builder.defineMacro("__hexagon__", "1");
5074
5075 if(CPU == "hexagonv1") {
5076 Builder.defineMacro("__HEXAGON_V1__");
5077 Builder.defineMacro("__HEXAGON_ARCH__", "1");
5078 if(Opts.HexagonQdsp6Compat) {
5079 Builder.defineMacro("__QDSP6_V1__");
5080 Builder.defineMacro("__QDSP6_ARCH__", "1");
5081 }
5082 }
5083 else if(CPU == "hexagonv2") {
5084 Builder.defineMacro("__HEXAGON_V2__");
5085 Builder.defineMacro("__HEXAGON_ARCH__", "2");
5086 if(Opts.HexagonQdsp6Compat) {
5087 Builder.defineMacro("__QDSP6_V2__");
5088 Builder.defineMacro("__QDSP6_ARCH__", "2");
5089 }
5090 }
5091 else if(CPU == "hexagonv3") {
5092 Builder.defineMacro("__HEXAGON_V3__");
5093 Builder.defineMacro("__HEXAGON_ARCH__", "3");
5094 if(Opts.HexagonQdsp6Compat) {
5095 Builder.defineMacro("__QDSP6_V3__");
5096 Builder.defineMacro("__QDSP6_ARCH__", "3");
5097 }
5098 }
5099 else if(CPU == "hexagonv4") {
5100 Builder.defineMacro("__HEXAGON_V4__");
5101 Builder.defineMacro("__HEXAGON_ARCH__", "4");
5102 if(Opts.HexagonQdsp6Compat) {
5103 Builder.defineMacro("__QDSP6_V4__");
5104 Builder.defineMacro("__QDSP6_ARCH__", "4");
5105 }
5106 }
5107 else if(CPU == "hexagonv5") {
5108 Builder.defineMacro("__HEXAGON_V5__");
5109 Builder.defineMacro("__HEXAGON_ARCH__", "5");
5110 if(Opts.HexagonQdsp6Compat) {
5111 Builder.defineMacro("__QDSP6_V5__");
5112 Builder.defineMacro("__QDSP6_ARCH__", "5");
5113 }
5114 }
5115}
5116
5117const char * const HexagonTargetInfo::GCCRegNames[] = {
5118 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5119 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5120 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5121 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
5122 "p0", "p1", "p2", "p3",
5123 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
5124};
5125
5126void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
5127 unsigned &NumNames) const {
5128 Names = GCCRegNames;
5129 NumNames = llvm::array_lengthof(GCCRegNames);
5130}
5131
5132
5133const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
5134 { { "sp" }, "r29" },
5135 { { "fp" }, "r30" },
5136 { { "lr" }, "r31" },
5137 };
5138
5139void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5140 unsigned &NumAliases) const {
5141 Aliases = GCCRegAliases;
5142 NumAliases = llvm::array_lengthof(GCCRegAliases);
5143}
5144
5145
5146const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
5147#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5148#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5149 ALL_LANGUAGES },
5150#include "clang/Basic/BuiltinsHexagon.def"
5151};
5152}
5153
5154
5155namespace {
5156// Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
5157class SparcTargetInfo : public TargetInfo {
5158 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5159 static const char * const GCCRegNames[];
5160 bool SoftFloat;
5161public:
5162 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {}
5163
5164 bool handleTargetFeatures(std::vector<std::string> &Features,
5165 DiagnosticsEngine &Diags) override {
5166 SoftFloat = false;
5167 for (unsigned i = 0, e = Features.size(); i != e; ++i)
5168 if (Features[i] == "+soft-float")
5169 SoftFloat = true;
5170 return true;
5171 }
5172 void getTargetDefines(const LangOptions &Opts,
5173 MacroBuilder &Builder) const override {
5174 DefineStd(Builder, "sparc", Opts);
5175 Builder.defineMacro("__REGISTER_PREFIX__", "");
5176
5177 if (SoftFloat)
5178 Builder.defineMacro("SOFT_FLOAT", "1");
5179 }
5180
5181 bool hasFeature(StringRef Feature) const override {
5182 return llvm::StringSwitch<bool>(Feature)
5183 .Case("softfloat", SoftFloat)
5184 .Case("sparc", true)
5185 .Default(false);
5186 }
5187
5188 void getTargetBuiltins(const Builtin::Info *&Records,
5189 unsigned &NumRecords) const override {
5190 // FIXME: Implement!
5191 }
5192 BuiltinVaListKind getBuiltinVaListKind() const override {
5193 return TargetInfo::VoidPtrBuiltinVaList;
5194 }
5195 void getGCCRegNames(const char * const *&Names,
5196 unsigned &NumNames) const override;
5197 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5198 unsigned &NumAliases) const override;
5199 bool validateAsmConstraint(const char *&Name,
5200 TargetInfo::ConstraintInfo &info) const override {
5201 // FIXME: Implement!
5202 switch (*Name) {
5203 case 'I': // Signed 13-bit constant
5204 case 'J': // Zero
5205 case 'K': // 32-bit constant with the low 12 bits clear
5206 case 'L': // A constant in the range supported by movcc (11-bit signed imm)
5207 case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
5208 case 'N': // Same as 'K' but zext (required for SIMode)
5209 case 'O': // The constant 4096
5210 return true;
5211 }
5212 return false;
5213 }
5214 const char *getClobbers() const override {
5215 // FIXME: Implement!
5216 return "";
5217 }
5218};
5219
5220const char * const SparcTargetInfo::GCCRegNames[] = {
5221 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5222 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5223 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5224 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5225};
5226
5227void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
5228 unsigned &NumNames) const {
5229 Names = GCCRegNames;
5230 NumNames = llvm::array_lengthof(GCCRegNames);
5231}
5232
5233const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
5234 { { "g0" }, "r0" },
5235 { { "g1" }, "r1" },
5236 { { "g2" }, "r2" },
5237 { { "g3" }, "r3" },
5238 { { "g4" }, "r4" },
5239 { { "g5" }, "r5" },
5240 { { "g6" }, "r6" },
5241 { { "g7" }, "r7" },
5242 { { "o0" }, "r8" },
5243 { { "o1" }, "r9" },
5244 { { "o2" }, "r10" },
5245 { { "o3" }, "r11" },
5246 { { "o4" }, "r12" },
5247 { { "o5" }, "r13" },
5248 { { "o6", "sp" }, "r14" },
5249 { { "o7" }, "r15" },
5250 { { "l0" }, "r16" },
5251 { { "l1" }, "r17" },
5252 { { "l2" }, "r18" },
5253 { { "l3" }, "r19" },
5254 { { "l4" }, "r20" },
5255 { { "l5" }, "r21" },
5256 { { "l6" }, "r22" },
5257 { { "l7" }, "r23" },
5258 { { "i0" }, "r24" },
5259 { { "i1" }, "r25" },
5260 { { "i2" }, "r26" },
5261 { { "i3" }, "r27" },
5262 { { "i4" }, "r28" },
5263 { { "i5" }, "r29" },
5264 { { "i6", "fp" }, "r30" },
5265 { { "i7" }, "r31" },
5266};
5267
5268void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5269 unsigned &NumAliases) const {
5270 Aliases = GCCRegAliases;
5271 NumAliases = llvm::array_lengthof(GCCRegAliases);
5272}
5273
5274// SPARC v8 is the 32-bit mode selected by Triple::sparc.
5275class SparcV8TargetInfo : public SparcTargetInfo {
5276public:
5277 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5278 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
5279 }
5280
5281 void getTargetDefines(const LangOptions &Opts,
5282 MacroBuilder &Builder) const override {
5283 SparcTargetInfo::getTargetDefines(Opts, Builder);
5284 Builder.defineMacro("__sparcv8");
5285 }
5286};
5287
5288// SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
5289class SparcV9TargetInfo : public SparcTargetInfo {
5290public:
5291 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5292 // FIXME: Support Sparc quad-precision long double?
5293 DescriptionString = "E-m:e-i64:64-n32:64-S128";
5294 // This is an LP64 platform.
5295 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5296
5297 // OpenBSD uses long long for int64_t and intmax_t.
5298 if (getTriple().getOS() == llvm::Triple::OpenBSD)
5299 IntMaxType = SignedLongLong;
5300 else
5301 IntMaxType = SignedLong;
5302 Int64Type = IntMaxType;
5303
5304 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
5305 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
5306 LongDoubleWidth = 128;
5307 LongDoubleAlign = 128;
5308 LongDoubleFormat = &llvm::APFloat::IEEEquad;
5309 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5310 }
5311
5312 void getTargetDefines(const LangOptions &Opts,
5313 MacroBuilder &Builder) const override {
5314 SparcTargetInfo::getTargetDefines(Opts, Builder);
5315 Builder.defineMacro("__sparcv9");
5316 Builder.defineMacro("__arch64__");
5317 // Solaris doesn't need these variants, but the BSDs do.
5318 if (getTriple().getOS() != llvm::Triple::Solaris) {
5319 Builder.defineMacro("__sparc64__");
5320 Builder.defineMacro("__sparc_v9__");
5321 Builder.defineMacro("__sparcv9__");
5322 }
5323 }
5324
5325 bool setCPU(const std::string &Name) override {
5326 bool CPUKnown = llvm::StringSwitch<bool>(Name)
5327 .Case("v9", true)
5328 .Case("ultrasparc", true)
5329 .Case("ultrasparc3", true)
5330 .Case("niagara", true)
5331 .Case("niagara2", true)
5332 .Case("niagara3", true)
5333 .Case("niagara4", true)
5334 .Default(false);
5335
5336 // No need to store the CPU yet. There aren't any CPU-specific
5337 // macros to define.
5338 return CPUKnown;
5339 }
5340};
5341
5342} // end anonymous namespace.
5343
5344namespace {
5345class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
5346public:
5347 SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
5348 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) {
5349 SizeType = UnsignedInt;
5350 PtrDiffType = SignedInt;
5351 }
5352};
5353} // end anonymous namespace.
5354
5355namespace {
5356class SystemZTargetInfo : public TargetInfo {
5357 static const char *const GCCRegNames[];
5358
5359public:
5360 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5361 TLSSupported = true;
5362 IntWidth = IntAlign = 32;
5363 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
5364 PointerWidth = PointerAlign = 64;
5365 LongDoubleWidth = 128;
5366 LongDoubleAlign = 64;
5367 LongDoubleFormat = &llvm::APFloat::IEEEquad;
5368 MinGlobalAlign = 16;
5369 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
5370 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5371 }
5372 void getTargetDefines(const LangOptions &Opts,
5373 MacroBuilder &Builder) const override {
5374 Builder.defineMacro("__s390__");
5375 Builder.defineMacro("__s390x__");
5376 Builder.defineMacro("__zarch__");
5377 Builder.defineMacro("__LONG_DOUBLE_128__");
5378 }
5379 void getTargetBuiltins(const Builtin::Info *&Records,
5380 unsigned &NumRecords) const override {
5381 // FIXME: Implement.
5382 Records = nullptr;
5383 NumRecords = 0;
5384 }
5385
5386 void getGCCRegNames(const char *const *&Names,
5387 unsigned &NumNames) const override;
5388 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5389 unsigned &NumAliases) const override {
5390 // No aliases.
5391 Aliases = nullptr;
5392 NumAliases = 0;
5393 }
5394 bool validateAsmConstraint(const char *&Name,
5395 TargetInfo::ConstraintInfo &info) const override;
5396 const char *getClobbers() const override {
5397 // FIXME: Is this really right?
5398 return "";
5399 }
5400 BuiltinVaListKind getBuiltinVaListKind() const override {
5401 return TargetInfo::SystemZBuiltinVaList;
5402 }
5403 bool setCPU(const std::string &Name) override {
5404 bool CPUKnown = llvm::StringSwitch<bool>(Name)
5405 .Case("z10", true)
5406 .Case("z196", true)
5407 .Case("zEC12", true)
5408 .Default(false);
5409
5410 // No need to store the CPU yet. There aren't any CPU-specific
5411 // macros to define.
5412 return CPUKnown;
5413 }
5414};
5415
5416const char *const SystemZTargetInfo::GCCRegNames[] = {
5417 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5418 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5419 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
5420 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
5421};
5422
5423void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
5424 unsigned &NumNames) const {
5425 Names = GCCRegNames;
5426 NumNames = llvm::array_lengthof(GCCRegNames);
5427}
5428
5429bool SystemZTargetInfo::
5430validateAsmConstraint(const char *&Name,
5431 TargetInfo::ConstraintInfo &Info) const {
5432 switch (*Name) {
5433 default:
5434 return false;
5435
5436 case 'a': // Address register
5437 case 'd': // Data register (equivalent to 'r')
5438 case 'f': // Floating-point register
5439 Info.setAllowsRegister();
5440 return true;
5441
5442 case 'I': // Unsigned 8-bit constant
5443 case 'J': // Unsigned 12-bit constant
5444 case 'K': // Signed 16-bit constant
5445 case 'L': // Signed 20-bit displacement (on all targets we support)
5446 case 'M': // 0x7fffffff
5447 return true;
5448
5449 case 'Q': // Memory with base and unsigned 12-bit displacement
5450 case 'R': // Likewise, plus an index
5451 case 'S': // Memory with base and signed 20-bit displacement
5452 case 'T': // Likewise, plus an index
5453 Info.setAllowsMemory();
5454 return true;
5455 }
5456}
5457}
5458
5459namespace {
5460 class MSP430TargetInfo : public TargetInfo {
5461 static const char * const GCCRegNames[];
5462 public:
5463 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5464 BigEndian = false;
5465 TLSSupported = false;
5466 IntWidth = 16; IntAlign = 16;
5467 LongWidth = 32; LongLongWidth = 64;
5468 LongAlign = LongLongAlign = 16;
5469 PointerWidth = 16; PointerAlign = 16;
5470 SuitableAlign = 16;
5471 SizeType = UnsignedInt;
5472 IntMaxType = SignedLongLong;
5473 IntPtrType = SignedInt;
5474 PtrDiffType = SignedInt;
5475 SigAtomicType = SignedLong;
5476 DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16";
5477 }
5478 void getTargetDefines(const LangOptions &Opts,
5479 MacroBuilder &Builder) const override {
5480 Builder.defineMacro("MSP430");
5481 Builder.defineMacro("__MSP430__");
5482 // FIXME: defines for different 'flavours' of MCU
5483 }
5484 void getTargetBuiltins(const Builtin::Info *&Records,
5485 unsigned &NumRecords) const override {
5486 // FIXME: Implement.
5487 Records = nullptr;
5488 NumRecords = 0;
5489 }
5490 bool hasFeature(StringRef Feature) const override {
5491 return Feature == "msp430";
5492 }
5493 void getGCCRegNames(const char * const *&Names,
5494 unsigned &NumNames) const override;
5495 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5496 unsigned &NumAliases) const override {
5497 // No aliases.
5498 Aliases = nullptr;
5499 NumAliases = 0;
5500 }
5501 bool
5502 validateAsmConstraint(const char *&Name,
5503 TargetInfo::ConstraintInfo &info) const override {
5504 // FIXME: implement
5505 switch (*Name) {
5506 case 'K': // the constant 1
5507 case 'L': // constant -1^20 .. 1^19
5508 case 'M': // constant 1-4:
5509 return true;
5510 }
5511 // No target constraints for now.
5512 return false;
5513 }
5514 const char *getClobbers() const override {
5515 // FIXME: Is this really right?
5516 return "";
5517 }
5518 BuiltinVaListKind getBuiltinVaListKind() const override {
5519 // FIXME: implement
5520 return TargetInfo::CharPtrBuiltinVaList;
5521 }
5522 };
5523
5524 const char * const MSP430TargetInfo::GCCRegNames[] = {
5525 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5526 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5527 };
5528
5529 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
5530 unsigned &NumNames) const {
5531 Names = GCCRegNames;
5532 NumNames = llvm::array_lengthof(GCCRegNames);
5533 }
5534}
5535
5536namespace {
5537
5538 // LLVM and Clang cannot be used directly to output native binaries for
5539 // target, but is used to compile C code to llvm bitcode with correct
5540 // type and alignment information.
5541 //
5542 // TCE uses the llvm bitcode as input and uses it for generating customized
5543 // target processor and program binary. TCE co-design environment is
5544 // publicly available in http://tce.cs.tut.fi
5545
5546 static const unsigned TCEOpenCLAddrSpaceMap[] = {
5547 3, // opencl_global
5548 4, // opencl_local
5549 5, // opencl_constant
5550 // FIXME: generic has to be added to the target
5551 0, // opencl_generic
5552 0, // cuda_device
5553 0, // cuda_constant
5554 0 // cuda_shared
5555 };
5556
5557 class TCETargetInfo : public TargetInfo{
5558 public:
5559 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5560 TLSSupported = false;
5561 IntWidth = 32;
5562 LongWidth = LongLongWidth = 32;
5563 PointerWidth = 32;
5564 IntAlign = 32;
5565 LongAlign = LongLongAlign = 32;
5566 PointerAlign = 32;
5567 SuitableAlign = 32;
5568 SizeType = UnsignedInt;
5569 IntMaxType = SignedLong;
5570 IntPtrType = SignedInt;
5571 PtrDiffType = SignedInt;
5572 FloatWidth = 32;
5573 FloatAlign = 32;
5574 DoubleWidth = 32;
5575 DoubleAlign = 32;
5576 LongDoubleWidth = 32;
5577 LongDoubleAlign = 32;
5578 FloatFormat = &llvm::APFloat::IEEEsingle;
5579 DoubleFormat = &llvm::APFloat::IEEEsingle;
5580 LongDoubleFormat = &llvm::APFloat::IEEEsingle;
5581 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
5582 "-f64:32-v64:32-v128:32-a:0:32-n32";
5583 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
5584 UseAddrSpaceMapMangling = true;
5585 }
5586
5587 void getTargetDefines(const LangOptions &Opts,
5588 MacroBuilder &Builder) const override {
5589 DefineStd(Builder, "tce", Opts);
5590 Builder.defineMacro("__TCE__");
5591 Builder.defineMacro("__TCE_V1__");
5592 }
5593 bool hasFeature(StringRef Feature) const override {
5594 return Feature == "tce";
5595 }
5596
5597 void getTargetBuiltins(const Builtin::Info *&Records,
5598 unsigned &NumRecords) const override {}
5599 const char *getClobbers() const override {
5600 return "";
5601 }
5602 BuiltinVaListKind getBuiltinVaListKind() const override {
5603 return TargetInfo::VoidPtrBuiltinVaList;
5604 }
5605 void getGCCRegNames(const char * const *&Names,
5606 unsigned &NumNames) const override {}
5607 bool validateAsmConstraint(const char *&Name,
5608 TargetInfo::ConstraintInfo &info) const override{
5609 return true;
5610 }
5611 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5612 unsigned &NumAliases) const override {}
5613 };
5614}
5615
5616namespace {
5617class MipsTargetInfoBase : public TargetInfo {
5618 virtual void setDescriptionString() = 0;
5619
5620 static const Builtin::Info BuiltinInfo[];
5621 std::string CPU;
5622 bool IsMips16;
5623 bool IsMicromips;
5624 bool IsNan2008;
5625 bool IsSingleFloat;
5626 enum MipsFloatABI {
5627 HardFloat, SoftFloat
5628 } FloatABI;
5629 enum DspRevEnum {
5630 NoDSP, DSP1, DSP2
5631 } DspRev;
5632 bool HasMSA;
5633
5634protected:
5635 bool HasFP64;
5636 std::string ABI;
5637
5638public:
5639 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
5640 const std::string &CPUStr)
5641 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
5642 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
|
5631 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {}
| 5643 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {
5644 TheCXXABI.set(TargetCXXABI::GenericMIPS);
5645 }
|
5632
5633 bool isNaN2008Default() const {
5634 return CPU == "mips32r6" || CPU == "mips64r6";
5635 }
5636
5637 bool isFP64Default() const {
5638 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
5639 }
5640
5641 StringRef getABI() const override { return ABI; }
5642 bool setCPU(const std::string &Name) override {
5643 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
5644 getTriple().getArch() == llvm::Triple::mipsel;
5645 CPU = Name;
5646 return llvm::StringSwitch<bool>(Name)
5647 .Case("mips1", IsMips32)
5648 .Case("mips2", IsMips32)
5649 .Case("mips3", true)
5650 .Case("mips4", true)
5651 .Case("mips5", true)
5652 .Case("mips32", IsMips32)
5653 .Case("mips32r2", IsMips32)
5654 .Case("mips32r6", IsMips32)
5655 .Case("mips64", true)
5656 .Case("mips64r2", true)
5657 .Case("mips64r6", true)
5658 .Case("octeon", true)
5659 .Default(false);
5660 }
5661 const std::string& getCPU() const { return CPU; }
5662 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
5663 // The backend enables certain ABI's by default according to the
5664 // architecture.
5665 // Disable both possible defaults so that we don't end up with multiple
5666 // ABI's selected and trigger an assertion.
5667 Features["o32"] = false;
5668 Features["n64"] = false;
5669
5670 Features[ABI] = true;
5671 if (CPU == "octeon")
5672 Features["mips64r2"] = Features["cnmips"] = true;
5673 else
5674 Features[CPU] = true;
5675 }
5676
5677 void getTargetDefines(const LangOptions &Opts,
5678 MacroBuilder &Builder) const override {
5679 Builder.defineMacro("__mips__");
5680 Builder.defineMacro("_mips");
5681 if (Opts.GNUMode)
5682 Builder.defineMacro("mips");
5683
5684 Builder.defineMacro("__REGISTER_PREFIX__", "");
5685
5686 switch (FloatABI) {
5687 case HardFloat:
5688 Builder.defineMacro("__mips_hard_float", Twine(1));
5689 break;
5690 case SoftFloat:
5691 Builder.defineMacro("__mips_soft_float", Twine(1));
5692 break;
5693 }
5694
5695 if (IsSingleFloat)
5696 Builder.defineMacro("__mips_single_float", Twine(1));
5697
5698 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
5699 Builder.defineMacro("_MIPS_FPSET",
5700 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
5701
5702 if (IsMips16)
5703 Builder.defineMacro("__mips16", Twine(1));
5704
5705 if (IsMicromips)
5706 Builder.defineMacro("__mips_micromips", Twine(1));
5707
5708 if (IsNan2008)
5709 Builder.defineMacro("__mips_nan2008", Twine(1));
5710
5711 switch (DspRev) {
5712 default:
5713 break;
5714 case DSP1:
5715 Builder.defineMacro("__mips_dsp_rev", Twine(1));
5716 Builder.defineMacro("__mips_dsp", Twine(1));
5717 break;
5718 case DSP2:
5719 Builder.defineMacro("__mips_dsp_rev", Twine(2));
5720 Builder.defineMacro("__mips_dspr2", Twine(1));
5721 Builder.defineMacro("__mips_dsp", Twine(1));
5722 break;
5723 }
5724
5725 if (HasMSA)
5726 Builder.defineMacro("__mips_msa", Twine(1));
5727
5728 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
5729 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
5730 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
5731
5732 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
5733 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
5734 }
5735
5736 void getTargetBuiltins(const Builtin::Info *&Records,
5737 unsigned &NumRecords) const override {
5738 Records = BuiltinInfo;
5739 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
5740 }
5741 bool hasFeature(StringRef Feature) const override {
5742 return llvm::StringSwitch<bool>(Feature)
5743 .Case("mips", true)
5744 .Case("fp64", HasFP64)
5745 .Default(false);
5746 }
5747 BuiltinVaListKind getBuiltinVaListKind() const override {
5748 return TargetInfo::VoidPtrBuiltinVaList;
5749 }
5750 void getGCCRegNames(const char * const *&Names,
5751 unsigned &NumNames) const override {
5752 static const char *const GCCRegNames[] = {
5753 // CPU register names
5754 // Must match second column of GCCRegAliases
5755 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
5756 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
5757 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
5758 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
5759 // Floating point register names
5760 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
5761 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
5762 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
5763 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
5764 // Hi/lo and condition register names
5765 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
5766 "$fcc5","$fcc6","$fcc7",
5767 // MSA register names
5768 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
5769 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
5770 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
5771 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
5772 // MSA control register names
5773 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
5774 "$msarequest", "$msamap", "$msaunmap"
5775 };
5776 Names = GCCRegNames;
5777 NumNames = llvm::array_lengthof(GCCRegNames);
5778 }
5779 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5780 unsigned &NumAliases) const override = 0;
5781 bool validateAsmConstraint(const char *&Name,
5782 TargetInfo::ConstraintInfo &Info) const override {
5783 switch (*Name) {
5784 default:
5785 return false;
5786 case 'r': // CPU registers.
5787 case 'd': // Equivalent to "r" unless generating MIPS16 code.
5788 case 'y': // Equivalent to "r", backward compatibility only.
5789 case 'f': // floating-point registers.
5790 case 'c': // $25 for indirect jumps
5791 case 'l': // lo register
5792 case 'x': // hilo register pair
5793 Info.setAllowsRegister();
5794 return true;
5795 case 'I': // Signed 16-bit constant
5796 case 'J': // Integer 0
5797 case 'K': // Unsigned 16-bit constant
5798 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
5799 case 'M': // Constants not loadable via lui, addiu, or ori
5800 case 'N': // Constant -1 to -65535
5801 case 'O': // A signed 15-bit constant
5802 case 'P': // A constant between 1 go 65535
5803 return true;
5804 case 'R': // An address that can be used in a non-macro load or store
5805 Info.setAllowsMemory();
5806 return true;
5807 }
5808 }
5809
5810 const char *getClobbers() const override {
5811 // In GCC, $1 is not widely used in generated code (it's used only in a few
5812 // specific situations), so there is no real need for users to add it to
5813 // the clobbers list if they want to use it in their inline assembly code.
5814 //
5815 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
5816 // code generation, so using it in inline assembly without adding it to the
5817 // clobbers list can cause conflicts between the inline assembly code and
5818 // the surrounding generated code.
5819 //
5820 // Another problem is that LLVM is allowed to choose $1 for inline assembly
5821 // operands, which will conflict with the ".set at" assembler option (which
5822 // we use only for inline assembly, in order to maintain compatibility with
5823 // GCC) and will also conflict with the user's usage of $1.
5824 //
5825 // The easiest way to avoid these conflicts and keep $1 as an allocatable
5826 // register for generated code is to automatically clobber $1 for all inline
5827 // assembly code.
5828 //
5829 // FIXME: We should automatically clobber $1 only for inline assembly code
5830 // which actually uses it. This would allow LLVM to use $1 for inline
5831 // assembly operands if the user's assembly code doesn't use it.
5832 return "~{$1}";
5833 }
5834
5835 bool handleTargetFeatures(std::vector<std::string> &Features,
5836 DiagnosticsEngine &Diags) override {
5837 IsMips16 = false;
5838 IsMicromips = false;
5839 IsNan2008 = isNaN2008Default();
5840 IsSingleFloat = false;
5841 FloatABI = HardFloat;
5842 DspRev = NoDSP;
5843 HasFP64 = isFP64Default();
5844
5845 for (std::vector<std::string>::iterator it = Features.begin(),
5846 ie = Features.end(); it != ie; ++it) {
5847 if (*it == "+single-float")
5848 IsSingleFloat = true;
5849 else if (*it == "+soft-float")
5850 FloatABI = SoftFloat;
5851 else if (*it == "+mips16")
5852 IsMips16 = true;
5853 else if (*it == "+micromips")
5854 IsMicromips = true;
5855 else if (*it == "+dsp")
5856 DspRev = std::max(DspRev, DSP1);
5857 else if (*it == "+dspr2")
5858 DspRev = std::max(DspRev, DSP2);
5859 else if (*it == "+msa")
5860 HasMSA = true;
5861 else if (*it == "+fp64")
5862 HasFP64 = true;
5863 else if (*it == "-fp64")
5864 HasFP64 = false;
5865 else if (*it == "+nan2008")
5866 IsNan2008 = true;
5867 else if (*it == "-nan2008")
5868 IsNan2008 = false;
5869 }
5870
5871 // Remove front-end specific options.
5872 std::vector<std::string>::iterator it =
5873 std::find(Features.begin(), Features.end(), "+soft-float");
5874 if (it != Features.end())
5875 Features.erase(it);
5876
5877 setDescriptionString();
5878
5879 return true;
5880 }
5881
5882 int getEHDataRegisterNumber(unsigned RegNo) const override {
5883 if (RegNo == 0) return 4;
5884 if (RegNo == 1) return 5;
5885 return -1;
5886 }
5887
5888 bool isCLZForZeroUndef() const override { return false; }
5889};
5890
5891const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
5892#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5893#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5894 ALL_LANGUAGES },
5895#include "clang/Basic/BuiltinsMips.def"
5896};
5897
5898class Mips32TargetInfoBase : public MipsTargetInfoBase {
5899public:
5900 Mips32TargetInfoBase(const llvm::Triple &Triple)
5901 : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
5902 SizeType = UnsignedInt;
5903 PtrDiffType = SignedInt;
5904 Int64Type = SignedLongLong;
5905 IntMaxType = Int64Type;
5906 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
5907 }
5908 bool setABI(const std::string &Name) override {
5909 if (Name == "o32" || Name == "eabi") {
5910 ABI = Name;
5911 return true;
5912 }
5913 return false;
5914 }
5915 void getTargetDefines(const LangOptions &Opts,
5916 MacroBuilder &Builder) const override {
5917 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
5918
5919 Builder.defineMacro("__mips", "32");
5920 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
5921
5922 const std::string& CPUStr = getCPU();
5923 if (CPUStr == "mips32")
5924 Builder.defineMacro("__mips_isa_rev", "1");
5925 else if (CPUStr == "mips32r2")
5926 Builder.defineMacro("__mips_isa_rev", "2");
5927 else if (CPUStr == "mips32r6")
5928 Builder.defineMacro("__mips_isa_rev", "6");
5929
5930 if (ABI == "o32") {
5931 Builder.defineMacro("__mips_o32");
5932 Builder.defineMacro("_ABIO32", "1");
5933 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
5934 }
5935 else if (ABI == "eabi")
5936 Builder.defineMacro("__mips_eabi");
5937 else
5938 llvm_unreachable("Invalid ABI for Mips32.");
5939 }
5940 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5941 unsigned &NumAliases) const override {
5942 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
5943 { { "at" }, "$1" },
5944 { { "v0" }, "$2" },
5945 { { "v1" }, "$3" },
5946 { { "a0" }, "$4" },
5947 { { "a1" }, "$5" },
5948 { { "a2" }, "$6" },
5949 { { "a3" }, "$7" },
5950 { { "t0" }, "$8" },
5951 { { "t1" }, "$9" },
5952 { { "t2" }, "$10" },
5953 { { "t3" }, "$11" },
5954 { { "t4" }, "$12" },
5955 { { "t5" }, "$13" },
5956 { { "t6" }, "$14" },
5957 { { "t7" }, "$15" },
5958 { { "s0" }, "$16" },
5959 { { "s1" }, "$17" },
5960 { { "s2" }, "$18" },
5961 { { "s3" }, "$19" },
5962 { { "s4" }, "$20" },
5963 { { "s5" }, "$21" },
5964 { { "s6" }, "$22" },
5965 { { "s7" }, "$23" },
5966 { { "t8" }, "$24" },
5967 { { "t9" }, "$25" },
5968 { { "k0" }, "$26" },
5969 { { "k1" }, "$27" },
5970 { { "gp" }, "$28" },
5971 { { "sp","$sp" }, "$29" },
5972 { { "fp","$fp" }, "$30" },
5973 { { "ra" }, "$31" }
5974 };
5975 Aliases = GCCRegAliases;
5976 NumAliases = llvm::array_lengthof(GCCRegAliases);
5977 }
5978};
5979
5980class Mips32EBTargetInfo : public Mips32TargetInfoBase {
5981 void setDescriptionString() override {
5982 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
5983 }
5984
5985public:
5986 Mips32EBTargetInfo(const llvm::Triple &Triple)
5987 : Mips32TargetInfoBase(Triple) {
5988 }
5989 void getTargetDefines(const LangOptions &Opts,
5990 MacroBuilder &Builder) const override {
5991 DefineStd(Builder, "MIPSEB", Opts);
5992 Builder.defineMacro("_MIPSEB");
5993 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
5994 }
5995};
5996
5997class Mips32ELTargetInfo : public Mips32TargetInfoBase {
5998 void setDescriptionString() override {
5999 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6000 }
6001
6002public:
6003 Mips32ELTargetInfo(const llvm::Triple &Triple)
6004 : Mips32TargetInfoBase(Triple) {
6005 BigEndian = false;
6006 }
6007 void getTargetDefines(const LangOptions &Opts,
6008 MacroBuilder &Builder) const override {
6009 DefineStd(Builder, "MIPSEL", Opts);
6010 Builder.defineMacro("_MIPSEL");
6011 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6012 }
6013};
6014
6015class Mips64TargetInfoBase : public MipsTargetInfoBase {
6016public:
6017 Mips64TargetInfoBase(const llvm::Triple &Triple)
6018 : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
6019 LongDoubleWidth = LongDoubleAlign = 128;
6020 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6021 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
6022 LongDoubleWidth = LongDoubleAlign = 64;
6023 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6024 }
6025 setN64ABITypes();
6026 SuitableAlign = 128;
6027 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6028 }
6029
6030 void setN64ABITypes() {
6031 LongWidth = LongAlign = 64;
6032 PointerWidth = PointerAlign = 64;
6033 SizeType = UnsignedLong;
6034 PtrDiffType = SignedLong;
6035 Int64Type = SignedLong;
6036 IntMaxType = Int64Type;
6037 }
6038
6039 void setN32ABITypes() {
6040 LongWidth = LongAlign = 32;
6041 PointerWidth = PointerAlign = 32;
6042 SizeType = UnsignedInt;
6043 PtrDiffType = SignedInt;
6044 Int64Type = SignedLongLong;
6045 IntMaxType = Int64Type;
6046 }
6047
6048 bool setABI(const std::string &Name) override {
6049 if (Name == "n32") {
6050 setN32ABITypes();
6051 ABI = Name;
6052 return true;
6053 }
6054 if (Name == "n64") {
6055 setN64ABITypes();
6056 ABI = Name;
6057 return true;
6058 }
6059 return false;
6060 }
6061
6062 void getTargetDefines(const LangOptions &Opts,
6063 MacroBuilder &Builder) const override {
6064 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6065
6066 Builder.defineMacro("__mips", "64");
6067 Builder.defineMacro("__mips64");
6068 Builder.defineMacro("__mips64__");
6069 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
6070
6071 const std::string& CPUStr = getCPU();
6072 if (CPUStr == "mips64")
6073 Builder.defineMacro("__mips_isa_rev", "1");
6074 else if (CPUStr == "mips64r2")
6075 Builder.defineMacro("__mips_isa_rev", "2");
6076 else if (CPUStr == "mips64r6")
6077 Builder.defineMacro("__mips_isa_rev", "6");
6078
6079 if (ABI == "n32") {
6080 Builder.defineMacro("__mips_n32");
6081 Builder.defineMacro("_ABIN32", "2");
6082 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
6083 }
6084 else if (ABI == "n64") {
6085 Builder.defineMacro("__mips_n64");
6086 Builder.defineMacro("_ABI64", "3");
6087 Builder.defineMacro("_MIPS_SIM", "_ABI64");
6088 }
6089 else
6090 llvm_unreachable("Invalid ABI for Mips64.");
6091 }
6092 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6093 unsigned &NumAliases) const override {
6094 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6095 { { "at" }, "$1" },
6096 { { "v0" }, "$2" },
6097 { { "v1" }, "$3" },
6098 { { "a0" }, "$4" },
6099 { { "a1" }, "$5" },
6100 { { "a2" }, "$6" },
6101 { { "a3" }, "$7" },
6102 { { "a4" }, "$8" },
6103 { { "a5" }, "$9" },
6104 { { "a6" }, "$10" },
6105 { { "a7" }, "$11" },
6106 { { "t0" }, "$12" },
6107 { { "t1" }, "$13" },
6108 { { "t2" }, "$14" },
6109 { { "t3" }, "$15" },
6110 { { "s0" }, "$16" },
6111 { { "s1" }, "$17" },
6112 { { "s2" }, "$18" },
6113 { { "s3" }, "$19" },
6114 { { "s4" }, "$20" },
6115 { { "s5" }, "$21" },
6116 { { "s6" }, "$22" },
6117 { { "s7" }, "$23" },
6118 { { "t8" }, "$24" },
6119 { { "t9" }, "$25" },
6120 { { "k0" }, "$26" },
6121 { { "k1" }, "$27" },
6122 { { "gp" }, "$28" },
6123 { { "sp","$sp" }, "$29" },
6124 { { "fp","$fp" }, "$30" },
6125 { { "ra" }, "$31" }
6126 };
6127 Aliases = GCCRegAliases;
6128 NumAliases = llvm::array_lengthof(GCCRegAliases);
6129 }
6130
6131 bool hasInt128Type() const override { return true; }
6132};
6133
6134class Mips64EBTargetInfo : public Mips64TargetInfoBase {
6135 void setDescriptionString() override {
6136 if (ABI == "n32")
6137 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6138 else
6139 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6140
6141 }
6142
6143public:
6144 Mips64EBTargetInfo(const llvm::Triple &Triple)
6145 : Mips64TargetInfoBase(Triple) {}
6146 void getTargetDefines(const LangOptions &Opts,
6147 MacroBuilder &Builder) const override {
6148 DefineStd(Builder, "MIPSEB", Opts);
6149 Builder.defineMacro("_MIPSEB");
6150 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6151 }
6152};
6153
6154class Mips64ELTargetInfo : public Mips64TargetInfoBase {
6155 void setDescriptionString() override {
6156 if (ABI == "n32")
6157 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6158 else
6159 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6160 }
6161public:
6162 Mips64ELTargetInfo(const llvm::Triple &Triple)
6163 : Mips64TargetInfoBase(Triple) {
6164 // Default ABI is n64.
6165 BigEndian = false;
6166 }
6167 void getTargetDefines(const LangOptions &Opts,
6168 MacroBuilder &Builder) const override {
6169 DefineStd(Builder, "MIPSEL", Opts);
6170 Builder.defineMacro("_MIPSEL");
6171 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6172 }
6173};
6174} // end anonymous namespace.
6175
6176namespace {
6177class PNaClTargetInfo : public TargetInfo {
6178public:
6179 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6180 BigEndian = false;
6181 this->UserLabelPrefix = "";
6182 this->LongAlign = 32;
6183 this->LongWidth = 32;
6184 this->PointerAlign = 32;
6185 this->PointerWidth = 32;
6186 this->IntMaxType = TargetInfo::SignedLongLong;
6187 this->Int64Type = TargetInfo::SignedLongLong;
6188 this->DoubleAlign = 64;
6189 this->LongDoubleWidth = 64;
6190 this->LongDoubleAlign = 64;
6191 this->SizeType = TargetInfo::UnsignedInt;
6192 this->PtrDiffType = TargetInfo::SignedInt;
6193 this->IntPtrType = TargetInfo::SignedInt;
6194 this->RegParmMax = 0; // Disallow regparm
6195 }
6196
6197 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
6198 }
6199 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
6200 Builder.defineMacro("__le32__");
6201 Builder.defineMacro("__pnacl__");
6202 }
6203 void getTargetDefines(const LangOptions &Opts,
6204 MacroBuilder &Builder) const override {
6205 getArchDefines(Opts, Builder);
6206 }
6207 bool hasFeature(StringRef Feature) const override {
6208 return Feature == "pnacl";
6209 }
6210 void getTargetBuiltins(const Builtin::Info *&Records,
6211 unsigned &NumRecords) const override {
6212 }
6213 BuiltinVaListKind getBuiltinVaListKind() const override {
6214 return TargetInfo::PNaClABIBuiltinVaList;
6215 }
6216 void getGCCRegNames(const char * const *&Names,
6217 unsigned &NumNames) const override;
6218 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6219 unsigned &NumAliases) const override;
6220 bool validateAsmConstraint(const char *&Name,
6221 TargetInfo::ConstraintInfo &Info) const override {
6222 return false;
6223 }
6224
6225 const char *getClobbers() const override {
6226 return "";
6227 }
6228};
6229
6230void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
6231 unsigned &NumNames) const {
6232 Names = nullptr;
6233 NumNames = 0;
6234}
6235
6236void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
6237 unsigned &NumAliases) const {
6238 Aliases = nullptr;
6239 NumAliases = 0;
6240}
6241} // end anonymous namespace.
6242
6243namespace {
6244class Le64TargetInfo : public TargetInfo {
6245 static const Builtin::Info BuiltinInfo[];
6246
6247public:
6248 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6249 BigEndian = false;
6250 NoAsmVariants = true;
6251 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6252 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6253 DescriptionString =
6254 "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128";
6255 }
6256
6257 void getTargetDefines(const LangOptions &Opts,
6258 MacroBuilder &Builder) const override {
6259 DefineStd(Builder, "unix", Opts);
6260 defineCPUMacros(Builder, "le64", /*Tuning=*/false);
6261 Builder.defineMacro("__ELF__");
6262 }
6263 void getTargetBuiltins(const Builtin::Info *&Records,
6264 unsigned &NumRecords) const override {
6265 Records = BuiltinInfo;
6266 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin;
6267 }
6268 BuiltinVaListKind getBuiltinVaListKind() const override {
6269 return TargetInfo::PNaClABIBuiltinVaList;
6270 }
6271 const char *getClobbers() const override { return ""; }
6272 void getGCCRegNames(const char *const *&Names,
6273 unsigned &NumNames) const override {
6274 Names = nullptr;
6275 NumNames = 0;
6276 }
6277 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6278 unsigned &NumAliases) const override {
6279 Aliases = nullptr;
6280 NumAliases = 0;
6281 }
6282 bool validateAsmConstraint(const char *&Name,
6283 TargetInfo::ConstraintInfo &Info) const override {
6284 return false;
6285 }
6286
6287 bool hasProtectedVisibility() const override { return false; }
6288};
6289} // end anonymous namespace.
6290
6291const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
6292#define BUILTIN(ID, TYPE, ATTRS) \
6293 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6294#include "clang/Basic/BuiltinsLe64.def"
6295};
6296
6297namespace {
6298 static const unsigned SPIRAddrSpaceMap[] = {
6299 1, // opencl_global
6300 3, // opencl_local
6301 2, // opencl_constant
6302 4, // opencl_generic
6303 0, // cuda_device
6304 0, // cuda_constant
6305 0 // cuda_shared
6306 };
6307 class SPIRTargetInfo : public TargetInfo {
6308 public:
6309 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6310 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
6311 "SPIR target must use unknown OS");
6312 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
6313 "SPIR target must use unknown environment type");
6314 BigEndian = false;
6315 TLSSupported = false;
6316 LongWidth = LongAlign = 64;
6317 AddrSpaceMap = &SPIRAddrSpaceMap;
6318 UseAddrSpaceMapMangling = true;
6319 // Define available target features
6320 // These must be defined in sorted order!
6321 NoAsmVariants = true;
6322 }
6323 void getTargetDefines(const LangOptions &Opts,
6324 MacroBuilder &Builder) const override {
6325 DefineStd(Builder, "SPIR", Opts);
6326 }
6327 bool hasFeature(StringRef Feature) const override {
6328 return Feature == "spir";
6329 }
6330
6331 void getTargetBuiltins(const Builtin::Info *&Records,
6332 unsigned &NumRecords) const override {}
6333 const char *getClobbers() const override {
6334 return "";
6335 }
6336 void getGCCRegNames(const char * const *&Names,
6337 unsigned &NumNames) const override {}
6338 bool
6339 validateAsmConstraint(const char *&Name,
6340 TargetInfo::ConstraintInfo &info) const override {
6341 return true;
6342 }
6343 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6344 unsigned &NumAliases) const override {}
6345 BuiltinVaListKind getBuiltinVaListKind() const override {
6346 return TargetInfo::VoidPtrBuiltinVaList;
6347 }
6348 };
6349
6350
6351 class SPIR32TargetInfo : public SPIRTargetInfo {
6352 public:
6353 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6354 PointerWidth = PointerAlign = 32;
6355 SizeType = TargetInfo::UnsignedInt;
6356 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
6357 DescriptionString
6358 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
6359 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6360 }
6361 void getTargetDefines(const LangOptions &Opts,
6362 MacroBuilder &Builder) const override {
6363 DefineStd(Builder, "SPIR32", Opts);
6364 }
6365 };
6366
6367 class SPIR64TargetInfo : public SPIRTargetInfo {
6368 public:
6369 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6370 PointerWidth = PointerAlign = 64;
6371 SizeType = TargetInfo::UnsignedLong;
6372 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
6373 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
6374 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6375 }
6376 void getTargetDefines(const LangOptions &Opts,
6377 MacroBuilder &Builder) const override {
6378 DefineStd(Builder, "SPIR64", Opts);
6379 }
6380 };
6381}
6382
6383namespace {
6384class XCoreTargetInfo : public TargetInfo {
6385 static const Builtin::Info BuiltinInfo[];
6386public:
6387 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6388 BigEndian = false;
6389 NoAsmVariants = true;
6390 LongLongAlign = 32;
6391 SuitableAlign = 32;
6392 DoubleAlign = LongDoubleAlign = 32;
6393 SizeType = UnsignedInt;
6394 PtrDiffType = SignedInt;
6395 IntPtrType = SignedInt;
6396 WCharType = UnsignedChar;
6397 WIntType = UnsignedInt;
6398 UseZeroLengthBitfieldAlignment = true;
6399 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
6400 "-f64:32-a:0:32-n32";
6401 }
6402 void getTargetDefines(const LangOptions &Opts,
6403 MacroBuilder &Builder) const override {
6404 Builder.defineMacro("__XS1B__");
6405 }
6406 void getTargetBuiltins(const Builtin::Info *&Records,
6407 unsigned &NumRecords) const override {
6408 Records = BuiltinInfo;
6409 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin;
6410 }
6411 BuiltinVaListKind getBuiltinVaListKind() const override {
6412 return TargetInfo::VoidPtrBuiltinVaList;
6413 }
6414 const char *getClobbers() const override {
6415 return "";
6416 }
6417 void getGCCRegNames(const char * const *&Names,
6418 unsigned &NumNames) const override {
6419 static const char * const GCCRegNames[] = {
6420 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6421 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
6422 };
6423 Names = GCCRegNames;
6424 NumNames = llvm::array_lengthof(GCCRegNames);
6425 }
6426 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6427 unsigned &NumAliases) const override {
6428 Aliases = nullptr;
6429 NumAliases = 0;
6430 }
6431 bool validateAsmConstraint(const char *&Name,
6432 TargetInfo::ConstraintInfo &Info) const override {
6433 return false;
6434 }
6435 int getEHDataRegisterNumber(unsigned RegNo) const override {
6436 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
6437 return (RegNo < 2)? RegNo : -1;
6438 }
6439};
6440
6441const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
6442#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6443#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6444 ALL_LANGUAGES },
6445#include "clang/Basic/BuiltinsXCore.def"
6446};
6447} // end anonymous namespace.
6448
6449
6450//===----------------------------------------------------------------------===//
6451// Driver code
6452//===----------------------------------------------------------------------===//
6453
6454static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
6455 llvm::Triple::OSType os = Triple.getOS();
6456
6457 switch (Triple.getArch()) {
6458 default:
6459 return nullptr;
6460
6461 case llvm::Triple::xcore:
6462 return new XCoreTargetInfo(Triple);
6463
6464 case llvm::Triple::hexagon:
6465 return new HexagonTargetInfo(Triple);
6466
6467 case llvm::Triple::aarch64:
6468 if (Triple.isOSDarwin())
6469 return new DarwinAArch64TargetInfo(Triple);
6470
6471 switch (os) {
6472 case llvm::Triple::FreeBSD:
6473 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple);
6474 case llvm::Triple::Linux:
6475 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
6476 case llvm::Triple::NetBSD:
6477 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
6478 default:
6479 return new AArch64leTargetInfo(Triple);
6480 }
6481
6482 case llvm::Triple::aarch64_be:
6483 switch (os) {
6484 case llvm::Triple::FreeBSD:
6485 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple);
6486 case llvm::Triple::Linux:
6487 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
6488 case llvm::Triple::NetBSD:
6489 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
6490 default:
6491 return new AArch64beTargetInfo(Triple);
6492 }
6493
6494 case llvm::Triple::arm:
6495 case llvm::Triple::thumb:
6496 if (Triple.isOSBinFormatMachO())
6497 return new DarwinARMTargetInfo(Triple);
6498
6499 switch (os) {
6500 case llvm::Triple::Linux:
6501 return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
6502 case llvm::Triple::FreeBSD:
6503 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
6504 case llvm::Triple::NetBSD:
6505 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
6506 case llvm::Triple::OpenBSD:
6507 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
6508 case llvm::Triple::Bitrig:
6509 return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
6510 case llvm::Triple::RTEMS:
6511 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
6512 case llvm::Triple::NaCl:
6513 return new NaClTargetInfo<ARMleTargetInfo>(Triple);
6514 case llvm::Triple::Win32:
6515 switch (Triple.getEnvironment()) {
6516 default:
6517 return new ARMleTargetInfo(Triple);
6518 case llvm::Triple::Itanium:
6519 return new ItaniumWindowsARMleTargetInfo(Triple);
6520 case llvm::Triple::MSVC:
6521 return new MicrosoftARMleTargetInfo(Triple);
6522 }
6523 default:
6524 return new ARMleTargetInfo(Triple);
6525 }
6526
6527 case llvm::Triple::armeb:
6528 case llvm::Triple::thumbeb:
6529 if (Triple.isOSDarwin())
6530 return new DarwinARMTargetInfo(Triple);
6531
6532 switch (os) {
6533 case llvm::Triple::Linux:
6534 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
6535 case llvm::Triple::FreeBSD:
6536 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
6537 case llvm::Triple::NetBSD:
6538 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
6539 case llvm::Triple::OpenBSD:
6540 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
6541 case llvm::Triple::Bitrig:
6542 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
6543 case llvm::Triple::RTEMS:
6544 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
6545 case llvm::Triple::NaCl:
6546 return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
6547 default:
6548 return new ARMbeTargetInfo(Triple);
6549 }
6550
6551 case llvm::Triple::msp430:
6552 return new MSP430TargetInfo(Triple);
6553
6554 case llvm::Triple::mips:
6555 switch (os) {
6556 case llvm::Triple::Linux:
6557 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
6558 case llvm::Triple::RTEMS:
6559 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
6560 case llvm::Triple::FreeBSD:
6561 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6562 case llvm::Triple::NetBSD:
6563 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6564 default:
6565 return new Mips32EBTargetInfo(Triple);
6566 }
6567
6568 case llvm::Triple::mipsel:
6569 switch (os) {
6570 case llvm::Triple::Linux:
6571 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
6572 case llvm::Triple::RTEMS:
6573 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
6574 case llvm::Triple::FreeBSD:
6575 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6576 case llvm::Triple::NetBSD:
6577 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6578 case llvm::Triple::NaCl:
6579 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple);
6580 default:
6581 return new Mips32ELTargetInfo(Triple);
6582 }
6583
6584 case llvm::Triple::mips64:
6585 switch (os) {
6586 case llvm::Triple::Linux:
6587 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
6588 case llvm::Triple::RTEMS:
6589 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
6590 case llvm::Triple::FreeBSD:
6591 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6592 case llvm::Triple::NetBSD:
6593 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6594 case llvm::Triple::OpenBSD:
6595 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6596 default:
6597 return new Mips64EBTargetInfo(Triple);
6598 }
6599
6600 case llvm::Triple::mips64el:
6601 switch (os) {
6602 case llvm::Triple::Linux:
6603 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
6604 case llvm::Triple::RTEMS:
6605 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
6606 case llvm::Triple::FreeBSD:
6607 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6608 case llvm::Triple::NetBSD:
6609 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6610 case llvm::Triple::OpenBSD:
6611 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6612 default:
6613 return new Mips64ELTargetInfo(Triple);
6614 }
6615
6616 case llvm::Triple::le32:
6617 switch (os) {
6618 case llvm::Triple::NaCl:
6619 return new NaClTargetInfo<PNaClTargetInfo>(Triple);
6620 default:
6621 return nullptr;
6622 }
6623
6624 case llvm::Triple::le64:
6625 return new Le64TargetInfo(Triple);
6626
6627 case llvm::Triple::ppc:
6628 if (Triple.isOSDarwin())
6629 return new DarwinPPC32TargetInfo(Triple);
6630 switch (os) {
6631 case llvm::Triple::Linux:
6632 return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
6633 case llvm::Triple::FreeBSD:
6634 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
6635 case llvm::Triple::NetBSD:
6636 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
6637 case llvm::Triple::OpenBSD:
6638 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
6639 case llvm::Triple::RTEMS:
6640 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
6641 default:
6642 return new PPC32TargetInfo(Triple);
6643 }
6644
6645 case llvm::Triple::ppc64:
6646 if (Triple.isOSDarwin())
6647 return new DarwinPPC64TargetInfo(Triple);
6648 switch (os) {
6649 case llvm::Triple::Linux:
6650 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6651 case llvm::Triple::Lv2:
6652 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
6653 case llvm::Triple::FreeBSD:
6654 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
6655 case llvm::Triple::NetBSD:
6656 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
6657 default:
6658 return new PPC64TargetInfo(Triple);
6659 }
6660
6661 case llvm::Triple::ppc64le:
6662 switch (os) {
6663 case llvm::Triple::Linux:
6664 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
| 5646
5647 bool isNaN2008Default() const {
5648 return CPU == "mips32r6" || CPU == "mips64r6";
5649 }
5650
5651 bool isFP64Default() const {
5652 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
5653 }
5654
5655 StringRef getABI() const override { return ABI; }
5656 bool setCPU(const std::string &Name) override {
5657 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
5658 getTriple().getArch() == llvm::Triple::mipsel;
5659 CPU = Name;
5660 return llvm::StringSwitch<bool>(Name)
5661 .Case("mips1", IsMips32)
5662 .Case("mips2", IsMips32)
5663 .Case("mips3", true)
5664 .Case("mips4", true)
5665 .Case("mips5", true)
5666 .Case("mips32", IsMips32)
5667 .Case("mips32r2", IsMips32)
5668 .Case("mips32r6", IsMips32)
5669 .Case("mips64", true)
5670 .Case("mips64r2", true)
5671 .Case("mips64r6", true)
5672 .Case("octeon", true)
5673 .Default(false);
5674 }
5675 const std::string& getCPU() const { return CPU; }
5676 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
5677 // The backend enables certain ABI's by default according to the
5678 // architecture.
5679 // Disable both possible defaults so that we don't end up with multiple
5680 // ABI's selected and trigger an assertion.
5681 Features["o32"] = false;
5682 Features["n64"] = false;
5683
5684 Features[ABI] = true;
5685 if (CPU == "octeon")
5686 Features["mips64r2"] = Features["cnmips"] = true;
5687 else
5688 Features[CPU] = true;
5689 }
5690
5691 void getTargetDefines(const LangOptions &Opts,
5692 MacroBuilder &Builder) const override {
5693 Builder.defineMacro("__mips__");
5694 Builder.defineMacro("_mips");
5695 if (Opts.GNUMode)
5696 Builder.defineMacro("mips");
5697
5698 Builder.defineMacro("__REGISTER_PREFIX__", "");
5699
5700 switch (FloatABI) {
5701 case HardFloat:
5702 Builder.defineMacro("__mips_hard_float", Twine(1));
5703 break;
5704 case SoftFloat:
5705 Builder.defineMacro("__mips_soft_float", Twine(1));
5706 break;
5707 }
5708
5709 if (IsSingleFloat)
5710 Builder.defineMacro("__mips_single_float", Twine(1));
5711
5712 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
5713 Builder.defineMacro("_MIPS_FPSET",
5714 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
5715
5716 if (IsMips16)
5717 Builder.defineMacro("__mips16", Twine(1));
5718
5719 if (IsMicromips)
5720 Builder.defineMacro("__mips_micromips", Twine(1));
5721
5722 if (IsNan2008)
5723 Builder.defineMacro("__mips_nan2008", Twine(1));
5724
5725 switch (DspRev) {
5726 default:
5727 break;
5728 case DSP1:
5729 Builder.defineMacro("__mips_dsp_rev", Twine(1));
5730 Builder.defineMacro("__mips_dsp", Twine(1));
5731 break;
5732 case DSP2:
5733 Builder.defineMacro("__mips_dsp_rev", Twine(2));
5734 Builder.defineMacro("__mips_dspr2", Twine(1));
5735 Builder.defineMacro("__mips_dsp", Twine(1));
5736 break;
5737 }
5738
5739 if (HasMSA)
5740 Builder.defineMacro("__mips_msa", Twine(1));
5741
5742 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
5743 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
5744 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
5745
5746 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
5747 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
5748 }
5749
5750 void getTargetBuiltins(const Builtin::Info *&Records,
5751 unsigned &NumRecords) const override {
5752 Records = BuiltinInfo;
5753 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
5754 }
5755 bool hasFeature(StringRef Feature) const override {
5756 return llvm::StringSwitch<bool>(Feature)
5757 .Case("mips", true)
5758 .Case("fp64", HasFP64)
5759 .Default(false);
5760 }
5761 BuiltinVaListKind getBuiltinVaListKind() const override {
5762 return TargetInfo::VoidPtrBuiltinVaList;
5763 }
5764 void getGCCRegNames(const char * const *&Names,
5765 unsigned &NumNames) const override {
5766 static const char *const GCCRegNames[] = {
5767 // CPU register names
5768 // Must match second column of GCCRegAliases
5769 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
5770 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
5771 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
5772 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
5773 // Floating point register names
5774 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
5775 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
5776 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
5777 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
5778 // Hi/lo and condition register names
5779 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
5780 "$fcc5","$fcc6","$fcc7",
5781 // MSA register names
5782 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
5783 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
5784 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
5785 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
5786 // MSA control register names
5787 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
5788 "$msarequest", "$msamap", "$msaunmap"
5789 };
5790 Names = GCCRegNames;
5791 NumNames = llvm::array_lengthof(GCCRegNames);
5792 }
5793 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5794 unsigned &NumAliases) const override = 0;
5795 bool validateAsmConstraint(const char *&Name,
5796 TargetInfo::ConstraintInfo &Info) const override {
5797 switch (*Name) {
5798 default:
5799 return false;
5800 case 'r': // CPU registers.
5801 case 'd': // Equivalent to "r" unless generating MIPS16 code.
5802 case 'y': // Equivalent to "r", backward compatibility only.
5803 case 'f': // floating-point registers.
5804 case 'c': // $25 for indirect jumps
5805 case 'l': // lo register
5806 case 'x': // hilo register pair
5807 Info.setAllowsRegister();
5808 return true;
5809 case 'I': // Signed 16-bit constant
5810 case 'J': // Integer 0
5811 case 'K': // Unsigned 16-bit constant
5812 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
5813 case 'M': // Constants not loadable via lui, addiu, or ori
5814 case 'N': // Constant -1 to -65535
5815 case 'O': // A signed 15-bit constant
5816 case 'P': // A constant between 1 go 65535
5817 return true;
5818 case 'R': // An address that can be used in a non-macro load or store
5819 Info.setAllowsMemory();
5820 return true;
5821 }
5822 }
5823
5824 const char *getClobbers() const override {
5825 // In GCC, $1 is not widely used in generated code (it's used only in a few
5826 // specific situations), so there is no real need for users to add it to
5827 // the clobbers list if they want to use it in their inline assembly code.
5828 //
5829 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
5830 // code generation, so using it in inline assembly without adding it to the
5831 // clobbers list can cause conflicts between the inline assembly code and
5832 // the surrounding generated code.
5833 //
5834 // Another problem is that LLVM is allowed to choose $1 for inline assembly
5835 // operands, which will conflict with the ".set at" assembler option (which
5836 // we use only for inline assembly, in order to maintain compatibility with
5837 // GCC) and will also conflict with the user's usage of $1.
5838 //
5839 // The easiest way to avoid these conflicts and keep $1 as an allocatable
5840 // register for generated code is to automatically clobber $1 for all inline
5841 // assembly code.
5842 //
5843 // FIXME: We should automatically clobber $1 only for inline assembly code
5844 // which actually uses it. This would allow LLVM to use $1 for inline
5845 // assembly operands if the user's assembly code doesn't use it.
5846 return "~{$1}";
5847 }
5848
5849 bool handleTargetFeatures(std::vector<std::string> &Features,
5850 DiagnosticsEngine &Diags) override {
5851 IsMips16 = false;
5852 IsMicromips = false;
5853 IsNan2008 = isNaN2008Default();
5854 IsSingleFloat = false;
5855 FloatABI = HardFloat;
5856 DspRev = NoDSP;
5857 HasFP64 = isFP64Default();
5858
5859 for (std::vector<std::string>::iterator it = Features.begin(),
5860 ie = Features.end(); it != ie; ++it) {
5861 if (*it == "+single-float")
5862 IsSingleFloat = true;
5863 else if (*it == "+soft-float")
5864 FloatABI = SoftFloat;
5865 else if (*it == "+mips16")
5866 IsMips16 = true;
5867 else if (*it == "+micromips")
5868 IsMicromips = true;
5869 else if (*it == "+dsp")
5870 DspRev = std::max(DspRev, DSP1);
5871 else if (*it == "+dspr2")
5872 DspRev = std::max(DspRev, DSP2);
5873 else if (*it == "+msa")
5874 HasMSA = true;
5875 else if (*it == "+fp64")
5876 HasFP64 = true;
5877 else if (*it == "-fp64")
5878 HasFP64 = false;
5879 else if (*it == "+nan2008")
5880 IsNan2008 = true;
5881 else if (*it == "-nan2008")
5882 IsNan2008 = false;
5883 }
5884
5885 // Remove front-end specific options.
5886 std::vector<std::string>::iterator it =
5887 std::find(Features.begin(), Features.end(), "+soft-float");
5888 if (it != Features.end())
5889 Features.erase(it);
5890
5891 setDescriptionString();
5892
5893 return true;
5894 }
5895
5896 int getEHDataRegisterNumber(unsigned RegNo) const override {
5897 if (RegNo == 0) return 4;
5898 if (RegNo == 1) return 5;
5899 return -1;
5900 }
5901
5902 bool isCLZForZeroUndef() const override { return false; }
5903};
5904
5905const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
5906#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5907#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5908 ALL_LANGUAGES },
5909#include "clang/Basic/BuiltinsMips.def"
5910};
5911
5912class Mips32TargetInfoBase : public MipsTargetInfoBase {
5913public:
5914 Mips32TargetInfoBase(const llvm::Triple &Triple)
5915 : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
5916 SizeType = UnsignedInt;
5917 PtrDiffType = SignedInt;
5918 Int64Type = SignedLongLong;
5919 IntMaxType = Int64Type;
5920 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
5921 }
5922 bool setABI(const std::string &Name) override {
5923 if (Name == "o32" || Name == "eabi") {
5924 ABI = Name;
5925 return true;
5926 }
5927 return false;
5928 }
5929 void getTargetDefines(const LangOptions &Opts,
5930 MacroBuilder &Builder) const override {
5931 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
5932
5933 Builder.defineMacro("__mips", "32");
5934 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
5935
5936 const std::string& CPUStr = getCPU();
5937 if (CPUStr == "mips32")
5938 Builder.defineMacro("__mips_isa_rev", "1");
5939 else if (CPUStr == "mips32r2")
5940 Builder.defineMacro("__mips_isa_rev", "2");
5941 else if (CPUStr == "mips32r6")
5942 Builder.defineMacro("__mips_isa_rev", "6");
5943
5944 if (ABI == "o32") {
5945 Builder.defineMacro("__mips_o32");
5946 Builder.defineMacro("_ABIO32", "1");
5947 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
5948 }
5949 else if (ABI == "eabi")
5950 Builder.defineMacro("__mips_eabi");
5951 else
5952 llvm_unreachable("Invalid ABI for Mips32.");
5953 }
5954 void getGCCRegAliases(const GCCRegAlias *&Aliases,
5955 unsigned &NumAliases) const override {
5956 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
5957 { { "at" }, "$1" },
5958 { { "v0" }, "$2" },
5959 { { "v1" }, "$3" },
5960 { { "a0" }, "$4" },
5961 { { "a1" }, "$5" },
5962 { { "a2" }, "$6" },
5963 { { "a3" }, "$7" },
5964 { { "t0" }, "$8" },
5965 { { "t1" }, "$9" },
5966 { { "t2" }, "$10" },
5967 { { "t3" }, "$11" },
5968 { { "t4" }, "$12" },
5969 { { "t5" }, "$13" },
5970 { { "t6" }, "$14" },
5971 { { "t7" }, "$15" },
5972 { { "s0" }, "$16" },
5973 { { "s1" }, "$17" },
5974 { { "s2" }, "$18" },
5975 { { "s3" }, "$19" },
5976 { { "s4" }, "$20" },
5977 { { "s5" }, "$21" },
5978 { { "s6" }, "$22" },
5979 { { "s7" }, "$23" },
5980 { { "t8" }, "$24" },
5981 { { "t9" }, "$25" },
5982 { { "k0" }, "$26" },
5983 { { "k1" }, "$27" },
5984 { { "gp" }, "$28" },
5985 { { "sp","$sp" }, "$29" },
5986 { { "fp","$fp" }, "$30" },
5987 { { "ra" }, "$31" }
5988 };
5989 Aliases = GCCRegAliases;
5990 NumAliases = llvm::array_lengthof(GCCRegAliases);
5991 }
5992};
5993
5994class Mips32EBTargetInfo : public Mips32TargetInfoBase {
5995 void setDescriptionString() override {
5996 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
5997 }
5998
5999public:
6000 Mips32EBTargetInfo(const llvm::Triple &Triple)
6001 : Mips32TargetInfoBase(Triple) {
6002 }
6003 void getTargetDefines(const LangOptions &Opts,
6004 MacroBuilder &Builder) const override {
6005 DefineStd(Builder, "MIPSEB", Opts);
6006 Builder.defineMacro("_MIPSEB");
6007 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6008 }
6009};
6010
6011class Mips32ELTargetInfo : public Mips32TargetInfoBase {
6012 void setDescriptionString() override {
6013 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6014 }
6015
6016public:
6017 Mips32ELTargetInfo(const llvm::Triple &Triple)
6018 : Mips32TargetInfoBase(Triple) {
6019 BigEndian = false;
6020 }
6021 void getTargetDefines(const LangOptions &Opts,
6022 MacroBuilder &Builder) const override {
6023 DefineStd(Builder, "MIPSEL", Opts);
6024 Builder.defineMacro("_MIPSEL");
6025 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6026 }
6027};
6028
6029class Mips64TargetInfoBase : public MipsTargetInfoBase {
6030public:
6031 Mips64TargetInfoBase(const llvm::Triple &Triple)
6032 : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
6033 LongDoubleWidth = LongDoubleAlign = 128;
6034 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6035 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
6036 LongDoubleWidth = LongDoubleAlign = 64;
6037 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6038 }
6039 setN64ABITypes();
6040 SuitableAlign = 128;
6041 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6042 }
6043
6044 void setN64ABITypes() {
6045 LongWidth = LongAlign = 64;
6046 PointerWidth = PointerAlign = 64;
6047 SizeType = UnsignedLong;
6048 PtrDiffType = SignedLong;
6049 Int64Type = SignedLong;
6050 IntMaxType = Int64Type;
6051 }
6052
6053 void setN32ABITypes() {
6054 LongWidth = LongAlign = 32;
6055 PointerWidth = PointerAlign = 32;
6056 SizeType = UnsignedInt;
6057 PtrDiffType = SignedInt;
6058 Int64Type = SignedLongLong;
6059 IntMaxType = Int64Type;
6060 }
6061
6062 bool setABI(const std::string &Name) override {
6063 if (Name == "n32") {
6064 setN32ABITypes();
6065 ABI = Name;
6066 return true;
6067 }
6068 if (Name == "n64") {
6069 setN64ABITypes();
6070 ABI = Name;
6071 return true;
6072 }
6073 return false;
6074 }
6075
6076 void getTargetDefines(const LangOptions &Opts,
6077 MacroBuilder &Builder) const override {
6078 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6079
6080 Builder.defineMacro("__mips", "64");
6081 Builder.defineMacro("__mips64");
6082 Builder.defineMacro("__mips64__");
6083 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
6084
6085 const std::string& CPUStr = getCPU();
6086 if (CPUStr == "mips64")
6087 Builder.defineMacro("__mips_isa_rev", "1");
6088 else if (CPUStr == "mips64r2")
6089 Builder.defineMacro("__mips_isa_rev", "2");
6090 else if (CPUStr == "mips64r6")
6091 Builder.defineMacro("__mips_isa_rev", "6");
6092
6093 if (ABI == "n32") {
6094 Builder.defineMacro("__mips_n32");
6095 Builder.defineMacro("_ABIN32", "2");
6096 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
6097 }
6098 else if (ABI == "n64") {
6099 Builder.defineMacro("__mips_n64");
6100 Builder.defineMacro("_ABI64", "3");
6101 Builder.defineMacro("_MIPS_SIM", "_ABI64");
6102 }
6103 else
6104 llvm_unreachable("Invalid ABI for Mips64.");
6105 }
6106 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6107 unsigned &NumAliases) const override {
6108 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6109 { { "at" }, "$1" },
6110 { { "v0" }, "$2" },
6111 { { "v1" }, "$3" },
6112 { { "a0" }, "$4" },
6113 { { "a1" }, "$5" },
6114 { { "a2" }, "$6" },
6115 { { "a3" }, "$7" },
6116 { { "a4" }, "$8" },
6117 { { "a5" }, "$9" },
6118 { { "a6" }, "$10" },
6119 { { "a7" }, "$11" },
6120 { { "t0" }, "$12" },
6121 { { "t1" }, "$13" },
6122 { { "t2" }, "$14" },
6123 { { "t3" }, "$15" },
6124 { { "s0" }, "$16" },
6125 { { "s1" }, "$17" },
6126 { { "s2" }, "$18" },
6127 { { "s3" }, "$19" },
6128 { { "s4" }, "$20" },
6129 { { "s5" }, "$21" },
6130 { { "s6" }, "$22" },
6131 { { "s7" }, "$23" },
6132 { { "t8" }, "$24" },
6133 { { "t9" }, "$25" },
6134 { { "k0" }, "$26" },
6135 { { "k1" }, "$27" },
6136 { { "gp" }, "$28" },
6137 { { "sp","$sp" }, "$29" },
6138 { { "fp","$fp" }, "$30" },
6139 { { "ra" }, "$31" }
6140 };
6141 Aliases = GCCRegAliases;
6142 NumAliases = llvm::array_lengthof(GCCRegAliases);
6143 }
6144
6145 bool hasInt128Type() const override { return true; }
6146};
6147
6148class Mips64EBTargetInfo : public Mips64TargetInfoBase {
6149 void setDescriptionString() override {
6150 if (ABI == "n32")
6151 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6152 else
6153 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6154
6155 }
6156
6157public:
6158 Mips64EBTargetInfo(const llvm::Triple &Triple)
6159 : Mips64TargetInfoBase(Triple) {}
6160 void getTargetDefines(const LangOptions &Opts,
6161 MacroBuilder &Builder) const override {
6162 DefineStd(Builder, "MIPSEB", Opts);
6163 Builder.defineMacro("_MIPSEB");
6164 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6165 }
6166};
6167
6168class Mips64ELTargetInfo : public Mips64TargetInfoBase {
6169 void setDescriptionString() override {
6170 if (ABI == "n32")
6171 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6172 else
6173 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6174 }
6175public:
6176 Mips64ELTargetInfo(const llvm::Triple &Triple)
6177 : Mips64TargetInfoBase(Triple) {
6178 // Default ABI is n64.
6179 BigEndian = false;
6180 }
6181 void getTargetDefines(const LangOptions &Opts,
6182 MacroBuilder &Builder) const override {
6183 DefineStd(Builder, "MIPSEL", Opts);
6184 Builder.defineMacro("_MIPSEL");
6185 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6186 }
6187};
6188} // end anonymous namespace.
6189
6190namespace {
6191class PNaClTargetInfo : public TargetInfo {
6192public:
6193 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6194 BigEndian = false;
6195 this->UserLabelPrefix = "";
6196 this->LongAlign = 32;
6197 this->LongWidth = 32;
6198 this->PointerAlign = 32;
6199 this->PointerWidth = 32;
6200 this->IntMaxType = TargetInfo::SignedLongLong;
6201 this->Int64Type = TargetInfo::SignedLongLong;
6202 this->DoubleAlign = 64;
6203 this->LongDoubleWidth = 64;
6204 this->LongDoubleAlign = 64;
6205 this->SizeType = TargetInfo::UnsignedInt;
6206 this->PtrDiffType = TargetInfo::SignedInt;
6207 this->IntPtrType = TargetInfo::SignedInt;
6208 this->RegParmMax = 0; // Disallow regparm
6209 }
6210
6211 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
6212 }
6213 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
6214 Builder.defineMacro("__le32__");
6215 Builder.defineMacro("__pnacl__");
6216 }
6217 void getTargetDefines(const LangOptions &Opts,
6218 MacroBuilder &Builder) const override {
6219 getArchDefines(Opts, Builder);
6220 }
6221 bool hasFeature(StringRef Feature) const override {
6222 return Feature == "pnacl";
6223 }
6224 void getTargetBuiltins(const Builtin::Info *&Records,
6225 unsigned &NumRecords) const override {
6226 }
6227 BuiltinVaListKind getBuiltinVaListKind() const override {
6228 return TargetInfo::PNaClABIBuiltinVaList;
6229 }
6230 void getGCCRegNames(const char * const *&Names,
6231 unsigned &NumNames) const override;
6232 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6233 unsigned &NumAliases) const override;
6234 bool validateAsmConstraint(const char *&Name,
6235 TargetInfo::ConstraintInfo &Info) const override {
6236 return false;
6237 }
6238
6239 const char *getClobbers() const override {
6240 return "";
6241 }
6242};
6243
6244void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
6245 unsigned &NumNames) const {
6246 Names = nullptr;
6247 NumNames = 0;
6248}
6249
6250void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
6251 unsigned &NumAliases) const {
6252 Aliases = nullptr;
6253 NumAliases = 0;
6254}
6255} // end anonymous namespace.
6256
6257namespace {
6258class Le64TargetInfo : public TargetInfo {
6259 static const Builtin::Info BuiltinInfo[];
6260
6261public:
6262 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6263 BigEndian = false;
6264 NoAsmVariants = true;
6265 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6266 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6267 DescriptionString =
6268 "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128";
6269 }
6270
6271 void getTargetDefines(const LangOptions &Opts,
6272 MacroBuilder &Builder) const override {
6273 DefineStd(Builder, "unix", Opts);
6274 defineCPUMacros(Builder, "le64", /*Tuning=*/false);
6275 Builder.defineMacro("__ELF__");
6276 }
6277 void getTargetBuiltins(const Builtin::Info *&Records,
6278 unsigned &NumRecords) const override {
6279 Records = BuiltinInfo;
6280 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin;
6281 }
6282 BuiltinVaListKind getBuiltinVaListKind() const override {
6283 return TargetInfo::PNaClABIBuiltinVaList;
6284 }
6285 const char *getClobbers() const override { return ""; }
6286 void getGCCRegNames(const char *const *&Names,
6287 unsigned &NumNames) const override {
6288 Names = nullptr;
6289 NumNames = 0;
6290 }
6291 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6292 unsigned &NumAliases) const override {
6293 Aliases = nullptr;
6294 NumAliases = 0;
6295 }
6296 bool validateAsmConstraint(const char *&Name,
6297 TargetInfo::ConstraintInfo &Info) const override {
6298 return false;
6299 }
6300
6301 bool hasProtectedVisibility() const override { return false; }
6302};
6303} // end anonymous namespace.
6304
6305const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
6306#define BUILTIN(ID, TYPE, ATTRS) \
6307 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6308#include "clang/Basic/BuiltinsLe64.def"
6309};
6310
6311namespace {
6312 static const unsigned SPIRAddrSpaceMap[] = {
6313 1, // opencl_global
6314 3, // opencl_local
6315 2, // opencl_constant
6316 4, // opencl_generic
6317 0, // cuda_device
6318 0, // cuda_constant
6319 0 // cuda_shared
6320 };
6321 class SPIRTargetInfo : public TargetInfo {
6322 public:
6323 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6324 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
6325 "SPIR target must use unknown OS");
6326 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
6327 "SPIR target must use unknown environment type");
6328 BigEndian = false;
6329 TLSSupported = false;
6330 LongWidth = LongAlign = 64;
6331 AddrSpaceMap = &SPIRAddrSpaceMap;
6332 UseAddrSpaceMapMangling = true;
6333 // Define available target features
6334 // These must be defined in sorted order!
6335 NoAsmVariants = true;
6336 }
6337 void getTargetDefines(const LangOptions &Opts,
6338 MacroBuilder &Builder) const override {
6339 DefineStd(Builder, "SPIR", Opts);
6340 }
6341 bool hasFeature(StringRef Feature) const override {
6342 return Feature == "spir";
6343 }
6344
6345 void getTargetBuiltins(const Builtin::Info *&Records,
6346 unsigned &NumRecords) const override {}
6347 const char *getClobbers() const override {
6348 return "";
6349 }
6350 void getGCCRegNames(const char * const *&Names,
6351 unsigned &NumNames) const override {}
6352 bool
6353 validateAsmConstraint(const char *&Name,
6354 TargetInfo::ConstraintInfo &info) const override {
6355 return true;
6356 }
6357 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6358 unsigned &NumAliases) const override {}
6359 BuiltinVaListKind getBuiltinVaListKind() const override {
6360 return TargetInfo::VoidPtrBuiltinVaList;
6361 }
6362 };
6363
6364
6365 class SPIR32TargetInfo : public SPIRTargetInfo {
6366 public:
6367 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6368 PointerWidth = PointerAlign = 32;
6369 SizeType = TargetInfo::UnsignedInt;
6370 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
6371 DescriptionString
6372 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
6373 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6374 }
6375 void getTargetDefines(const LangOptions &Opts,
6376 MacroBuilder &Builder) const override {
6377 DefineStd(Builder, "SPIR32", Opts);
6378 }
6379 };
6380
6381 class SPIR64TargetInfo : public SPIRTargetInfo {
6382 public:
6383 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6384 PointerWidth = PointerAlign = 64;
6385 SizeType = TargetInfo::UnsignedLong;
6386 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
6387 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
6388 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6389 }
6390 void getTargetDefines(const LangOptions &Opts,
6391 MacroBuilder &Builder) const override {
6392 DefineStd(Builder, "SPIR64", Opts);
6393 }
6394 };
6395}
6396
6397namespace {
6398class XCoreTargetInfo : public TargetInfo {
6399 static const Builtin::Info BuiltinInfo[];
6400public:
6401 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6402 BigEndian = false;
6403 NoAsmVariants = true;
6404 LongLongAlign = 32;
6405 SuitableAlign = 32;
6406 DoubleAlign = LongDoubleAlign = 32;
6407 SizeType = UnsignedInt;
6408 PtrDiffType = SignedInt;
6409 IntPtrType = SignedInt;
6410 WCharType = UnsignedChar;
6411 WIntType = UnsignedInt;
6412 UseZeroLengthBitfieldAlignment = true;
6413 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
6414 "-f64:32-a:0:32-n32";
6415 }
6416 void getTargetDefines(const LangOptions &Opts,
6417 MacroBuilder &Builder) const override {
6418 Builder.defineMacro("__XS1B__");
6419 }
6420 void getTargetBuiltins(const Builtin::Info *&Records,
6421 unsigned &NumRecords) const override {
6422 Records = BuiltinInfo;
6423 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin;
6424 }
6425 BuiltinVaListKind getBuiltinVaListKind() const override {
6426 return TargetInfo::VoidPtrBuiltinVaList;
6427 }
6428 const char *getClobbers() const override {
6429 return "";
6430 }
6431 void getGCCRegNames(const char * const *&Names,
6432 unsigned &NumNames) const override {
6433 static const char * const GCCRegNames[] = {
6434 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6435 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
6436 };
6437 Names = GCCRegNames;
6438 NumNames = llvm::array_lengthof(GCCRegNames);
6439 }
6440 void getGCCRegAliases(const GCCRegAlias *&Aliases,
6441 unsigned &NumAliases) const override {
6442 Aliases = nullptr;
6443 NumAliases = 0;
6444 }
6445 bool validateAsmConstraint(const char *&Name,
6446 TargetInfo::ConstraintInfo &Info) const override {
6447 return false;
6448 }
6449 int getEHDataRegisterNumber(unsigned RegNo) const override {
6450 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
6451 return (RegNo < 2)? RegNo : -1;
6452 }
6453};
6454
6455const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
6456#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6457#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6458 ALL_LANGUAGES },
6459#include "clang/Basic/BuiltinsXCore.def"
6460};
6461} // end anonymous namespace.
6462
6463
6464//===----------------------------------------------------------------------===//
6465// Driver code
6466//===----------------------------------------------------------------------===//
6467
6468static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
6469 llvm::Triple::OSType os = Triple.getOS();
6470
6471 switch (Triple.getArch()) {
6472 default:
6473 return nullptr;
6474
6475 case llvm::Triple::xcore:
6476 return new XCoreTargetInfo(Triple);
6477
6478 case llvm::Triple::hexagon:
6479 return new HexagonTargetInfo(Triple);
6480
6481 case llvm::Triple::aarch64:
6482 if (Triple.isOSDarwin())
6483 return new DarwinAArch64TargetInfo(Triple);
6484
6485 switch (os) {
6486 case llvm::Triple::FreeBSD:
6487 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple);
6488 case llvm::Triple::Linux:
6489 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
6490 case llvm::Triple::NetBSD:
6491 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
6492 default:
6493 return new AArch64leTargetInfo(Triple);
6494 }
6495
6496 case llvm::Triple::aarch64_be:
6497 switch (os) {
6498 case llvm::Triple::FreeBSD:
6499 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple);
6500 case llvm::Triple::Linux:
6501 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
6502 case llvm::Triple::NetBSD:
6503 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
6504 default:
6505 return new AArch64beTargetInfo(Triple);
6506 }
6507
6508 case llvm::Triple::arm:
6509 case llvm::Triple::thumb:
6510 if (Triple.isOSBinFormatMachO())
6511 return new DarwinARMTargetInfo(Triple);
6512
6513 switch (os) {
6514 case llvm::Triple::Linux:
6515 return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
6516 case llvm::Triple::FreeBSD:
6517 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
6518 case llvm::Triple::NetBSD:
6519 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
6520 case llvm::Triple::OpenBSD:
6521 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
6522 case llvm::Triple::Bitrig:
6523 return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
6524 case llvm::Triple::RTEMS:
6525 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
6526 case llvm::Triple::NaCl:
6527 return new NaClTargetInfo<ARMleTargetInfo>(Triple);
6528 case llvm::Triple::Win32:
6529 switch (Triple.getEnvironment()) {
6530 default:
6531 return new ARMleTargetInfo(Triple);
6532 case llvm::Triple::Itanium:
6533 return new ItaniumWindowsARMleTargetInfo(Triple);
6534 case llvm::Triple::MSVC:
6535 return new MicrosoftARMleTargetInfo(Triple);
6536 }
6537 default:
6538 return new ARMleTargetInfo(Triple);
6539 }
6540
6541 case llvm::Triple::armeb:
6542 case llvm::Triple::thumbeb:
6543 if (Triple.isOSDarwin())
6544 return new DarwinARMTargetInfo(Triple);
6545
6546 switch (os) {
6547 case llvm::Triple::Linux:
6548 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
6549 case llvm::Triple::FreeBSD:
6550 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
6551 case llvm::Triple::NetBSD:
6552 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
6553 case llvm::Triple::OpenBSD:
6554 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
6555 case llvm::Triple::Bitrig:
6556 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
6557 case llvm::Triple::RTEMS:
6558 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
6559 case llvm::Triple::NaCl:
6560 return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
6561 default:
6562 return new ARMbeTargetInfo(Triple);
6563 }
6564
6565 case llvm::Triple::msp430:
6566 return new MSP430TargetInfo(Triple);
6567
6568 case llvm::Triple::mips:
6569 switch (os) {
6570 case llvm::Triple::Linux:
6571 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
6572 case llvm::Triple::RTEMS:
6573 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
6574 case llvm::Triple::FreeBSD:
6575 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6576 case llvm::Triple::NetBSD:
6577 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6578 default:
6579 return new Mips32EBTargetInfo(Triple);
6580 }
6581
6582 case llvm::Triple::mipsel:
6583 switch (os) {
6584 case llvm::Triple::Linux:
6585 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
6586 case llvm::Triple::RTEMS:
6587 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
6588 case llvm::Triple::FreeBSD:
6589 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6590 case llvm::Triple::NetBSD:
6591 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6592 case llvm::Triple::NaCl:
6593 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple);
6594 default:
6595 return new Mips32ELTargetInfo(Triple);
6596 }
6597
6598 case llvm::Triple::mips64:
6599 switch (os) {
6600 case llvm::Triple::Linux:
6601 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
6602 case llvm::Triple::RTEMS:
6603 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
6604 case llvm::Triple::FreeBSD:
6605 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6606 case llvm::Triple::NetBSD:
6607 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6608 case llvm::Triple::OpenBSD:
6609 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6610 default:
6611 return new Mips64EBTargetInfo(Triple);
6612 }
6613
6614 case llvm::Triple::mips64el:
6615 switch (os) {
6616 case llvm::Triple::Linux:
6617 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
6618 case llvm::Triple::RTEMS:
6619 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
6620 case llvm::Triple::FreeBSD:
6621 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6622 case llvm::Triple::NetBSD:
6623 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6624 case llvm::Triple::OpenBSD:
6625 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6626 default:
6627 return new Mips64ELTargetInfo(Triple);
6628 }
6629
6630 case llvm::Triple::le32:
6631 switch (os) {
6632 case llvm::Triple::NaCl:
6633 return new NaClTargetInfo<PNaClTargetInfo>(Triple);
6634 default:
6635 return nullptr;
6636 }
6637
6638 case llvm::Triple::le64:
6639 return new Le64TargetInfo(Triple);
6640
6641 case llvm::Triple::ppc:
6642 if (Triple.isOSDarwin())
6643 return new DarwinPPC32TargetInfo(Triple);
6644 switch (os) {
6645 case llvm::Triple::Linux:
6646 return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
6647 case llvm::Triple::FreeBSD:
6648 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
6649 case llvm::Triple::NetBSD:
6650 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
6651 case llvm::Triple::OpenBSD:
6652 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
6653 case llvm::Triple::RTEMS:
6654 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
6655 default:
6656 return new PPC32TargetInfo(Triple);
6657 }
6658
6659 case llvm::Triple::ppc64:
6660 if (Triple.isOSDarwin())
6661 return new DarwinPPC64TargetInfo(Triple);
6662 switch (os) {
6663 case llvm::Triple::Linux:
6664 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6665 case llvm::Triple::Lv2:
6666 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
6667 case llvm::Triple::FreeBSD:
6668 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
6669 case llvm::Triple::NetBSD:
6670 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
6671 default:
6672 return new PPC64TargetInfo(Triple);
6673 }
6674
6675 case llvm::Triple::ppc64le:
6676 switch (os) {
6677 case llvm::Triple::Linux:
6678 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
|
| 6679 case llvm::Triple::NetBSD:
6680 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
|
6665 default:
6666 return new PPC64TargetInfo(Triple);
6667 }
6668
6669 case llvm::Triple::nvptx:
6670 return new NVPTX32TargetInfo(Triple);
6671 case llvm::Triple::nvptx64:
6672 return new NVPTX64TargetInfo(Triple);
6673
6674 case llvm::Triple::amdgcn:
6675 case llvm::Triple::r600:
6676 return new R600TargetInfo(Triple);
6677
6678 case llvm::Triple::sparc:
6679 switch (os) {
6680 case llvm::Triple::Linux:
6681 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
6682 case llvm::Triple::Solaris:
6683 return new SolarisSparcV8TargetInfo(Triple);
6684 case llvm::Triple::NetBSD:
6685 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
6686 case llvm::Triple::OpenBSD:
6687 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
6688 case llvm::Triple::RTEMS:
6689 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
6690 default:
6691 return new SparcV8TargetInfo(Triple);
6692 }
6693
6694 case llvm::Triple::sparcv9:
6695 switch (os) {
6696 case llvm::Triple::Linux:
6697 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
6698 case llvm::Triple::Solaris:
6699 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
6700 case llvm::Triple::NetBSD:
6701 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
6702 case llvm::Triple::OpenBSD:
6703 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
6704 case llvm::Triple::FreeBSD:
6705 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
6706 default:
6707 return new SparcV9TargetInfo(Triple);
6708 }
6709
6710 case llvm::Triple::systemz:
6711 switch (os) {
6712 case llvm::Triple::Linux:
6713 return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
6714 default:
6715 return new SystemZTargetInfo(Triple);
6716 }
6717
6718 case llvm::Triple::tce:
6719 return new TCETargetInfo(Triple);
6720
6721 case llvm::Triple::x86:
6722 if (Triple.isOSDarwin())
6723 return new DarwinI386TargetInfo(Triple);
6724
6725 switch (os) {
6726 case llvm::Triple::Linux:
6727 return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
6728 case llvm::Triple::DragonFly:
6729 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
6730 case llvm::Triple::NetBSD:
6731 return new NetBSDI386TargetInfo(Triple);
6732 case llvm::Triple::OpenBSD:
6733 return new OpenBSDI386TargetInfo(Triple);
6734 case llvm::Triple::Bitrig:
6735 return new BitrigI386TargetInfo(Triple);
6736 case llvm::Triple::FreeBSD:
6737 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6738 case llvm::Triple::KFreeBSD:
6739 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6740 case llvm::Triple::Minix:
6741 return new MinixTargetInfo<X86_32TargetInfo>(Triple);
6742 case llvm::Triple::Solaris:
6743 return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
6744 case llvm::Triple::Win32: {
6745 switch (Triple.getEnvironment()) {
6746 default:
6747 return new X86_32TargetInfo(Triple);
6748 case llvm::Triple::Cygnus:
6749 return new CygwinX86_32TargetInfo(Triple);
6750 case llvm::Triple::GNU:
6751 return new MinGWX86_32TargetInfo(Triple);
6752 case llvm::Triple::Itanium:
6753 case llvm::Triple::MSVC:
6754 return new MicrosoftX86_32TargetInfo(Triple);
6755 }
6756 }
6757 case llvm::Triple::Haiku:
6758 return new HaikuX86_32TargetInfo(Triple);
6759 case llvm::Triple::RTEMS:
6760 return new RTEMSX86_32TargetInfo(Triple);
6761 case llvm::Triple::NaCl:
6762 return new NaClTargetInfo<X86_32TargetInfo>(Triple);
6763 default:
6764 return new X86_32TargetInfo(Triple);
6765 }
6766
6767 case llvm::Triple::x86_64:
6768 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
6769 return new DarwinX86_64TargetInfo(Triple);
6770
6771 switch (os) {
6772 case llvm::Triple::Linux:
6773 return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
6774 case llvm::Triple::DragonFly:
6775 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
6776 case llvm::Triple::NetBSD:
6777 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
6778 case llvm::Triple::OpenBSD:
6779 return new OpenBSDX86_64TargetInfo(Triple);
6780 case llvm::Triple::Bitrig:
6781 return new BitrigX86_64TargetInfo(Triple);
6782 case llvm::Triple::FreeBSD:
6783 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6784 case llvm::Triple::KFreeBSD:
6785 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6786 case llvm::Triple::Solaris:
6787 return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
6788 case llvm::Triple::Win32: {
6789 switch (Triple.getEnvironment()) {
6790 default:
6791 return new X86_64TargetInfo(Triple);
6792 case llvm::Triple::GNU:
6793 return new MinGWX86_64TargetInfo(Triple);
6794 case llvm::Triple::MSVC:
6795 return new MicrosoftX86_64TargetInfo(Triple);
6796 }
6797 }
6798 case llvm::Triple::NaCl:
6799 return new NaClTargetInfo<X86_64TargetInfo>(Triple);
6800 default:
6801 return new X86_64TargetInfo(Triple);
6802 }
6803
6804 case llvm::Triple::spir: {
6805 if (Triple.getOS() != llvm::Triple::UnknownOS ||
6806 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6807 return nullptr;
6808 return new SPIR32TargetInfo(Triple);
6809 }
6810 case llvm::Triple::spir64: {
6811 if (Triple.getOS() != llvm::Triple::UnknownOS ||
6812 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6813 return nullptr;
6814 return new SPIR64TargetInfo(Triple);
6815 }
6816 }
6817}
6818
6819/// CreateTargetInfo - Return the target info object for the specified target
6820/// triple.
6821TargetInfo *
6822TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
6823 const std::shared_ptr<TargetOptions> &Opts) {
6824 llvm::Triple Triple(Opts->Triple);
6825
6826 // Construct the target
6827 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
6828 if (!Target) {
6829 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
6830 return nullptr;
6831 }
6832 Target->TargetOpts = Opts;
6833
6834 // Set the target CPU if specified.
6835 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
6836 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
6837 return nullptr;
6838 }
6839
6840 // Set the target ABI if specified.
6841 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
6842 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
6843 return nullptr;
6844 }
6845
6846 // Set the fp math unit.
6847 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
6848 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
6849 return nullptr;
6850 }
6851
6852 // Compute the default target features, we need the target to handle this
6853 // because features may have dependencies on one another.
6854 llvm::StringMap<bool> Features;
6855 Target->getDefaultFeatures(Features);
6856
6857 // Apply the user specified deltas.
6858 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size();
6859 I < N; ++I) {
6860 const char *Name = Opts->FeaturesAsWritten[I].c_str();
6861 // Apply the feature via the target.
6862 bool Enabled = Name[0] == '+';
6863 Target->setFeatureEnabled(Features, Name + 1, Enabled);
6864 }
6865
6866 // Add the features to the compile options.
6867 //
6868 // FIXME: If we are completely confident that we have the right set, we only
6869 // need to pass the minuses.
6870 Opts->Features.clear();
6871 for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
6872 ie = Features.end(); it != ie; ++it)
6873 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
6874 if (!Target->handleTargetFeatures(Opts->Features, Diags))
6875 return nullptr;
6876
6877 return Target.release();
6878}
| 6681 default:
6682 return new PPC64TargetInfo(Triple);
6683 }
6684
6685 case llvm::Triple::nvptx:
6686 return new NVPTX32TargetInfo(Triple);
6687 case llvm::Triple::nvptx64:
6688 return new NVPTX64TargetInfo(Triple);
6689
6690 case llvm::Triple::amdgcn:
6691 case llvm::Triple::r600:
6692 return new R600TargetInfo(Triple);
6693
6694 case llvm::Triple::sparc:
6695 switch (os) {
6696 case llvm::Triple::Linux:
6697 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
6698 case llvm::Triple::Solaris:
6699 return new SolarisSparcV8TargetInfo(Triple);
6700 case llvm::Triple::NetBSD:
6701 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
6702 case llvm::Triple::OpenBSD:
6703 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
6704 case llvm::Triple::RTEMS:
6705 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
6706 default:
6707 return new SparcV8TargetInfo(Triple);
6708 }
6709
6710 case llvm::Triple::sparcv9:
6711 switch (os) {
6712 case llvm::Triple::Linux:
6713 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
6714 case llvm::Triple::Solaris:
6715 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
6716 case llvm::Triple::NetBSD:
6717 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
6718 case llvm::Triple::OpenBSD:
6719 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
6720 case llvm::Triple::FreeBSD:
6721 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
6722 default:
6723 return new SparcV9TargetInfo(Triple);
6724 }
6725
6726 case llvm::Triple::systemz:
6727 switch (os) {
6728 case llvm::Triple::Linux:
6729 return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
6730 default:
6731 return new SystemZTargetInfo(Triple);
6732 }
6733
6734 case llvm::Triple::tce:
6735 return new TCETargetInfo(Triple);
6736
6737 case llvm::Triple::x86:
6738 if (Triple.isOSDarwin())
6739 return new DarwinI386TargetInfo(Triple);
6740
6741 switch (os) {
6742 case llvm::Triple::Linux:
6743 return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
6744 case llvm::Triple::DragonFly:
6745 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
6746 case llvm::Triple::NetBSD:
6747 return new NetBSDI386TargetInfo(Triple);
6748 case llvm::Triple::OpenBSD:
6749 return new OpenBSDI386TargetInfo(Triple);
6750 case llvm::Triple::Bitrig:
6751 return new BitrigI386TargetInfo(Triple);
6752 case llvm::Triple::FreeBSD:
6753 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6754 case llvm::Triple::KFreeBSD:
6755 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6756 case llvm::Triple::Minix:
6757 return new MinixTargetInfo<X86_32TargetInfo>(Triple);
6758 case llvm::Triple::Solaris:
6759 return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
6760 case llvm::Triple::Win32: {
6761 switch (Triple.getEnvironment()) {
6762 default:
6763 return new X86_32TargetInfo(Triple);
6764 case llvm::Triple::Cygnus:
6765 return new CygwinX86_32TargetInfo(Triple);
6766 case llvm::Triple::GNU:
6767 return new MinGWX86_32TargetInfo(Triple);
6768 case llvm::Triple::Itanium:
6769 case llvm::Triple::MSVC:
6770 return new MicrosoftX86_32TargetInfo(Triple);
6771 }
6772 }
6773 case llvm::Triple::Haiku:
6774 return new HaikuX86_32TargetInfo(Triple);
6775 case llvm::Triple::RTEMS:
6776 return new RTEMSX86_32TargetInfo(Triple);
6777 case llvm::Triple::NaCl:
6778 return new NaClTargetInfo<X86_32TargetInfo>(Triple);
6779 default:
6780 return new X86_32TargetInfo(Triple);
6781 }
6782
6783 case llvm::Triple::x86_64:
6784 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
6785 return new DarwinX86_64TargetInfo(Triple);
6786
6787 switch (os) {
6788 case llvm::Triple::Linux:
6789 return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
6790 case llvm::Triple::DragonFly:
6791 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
6792 case llvm::Triple::NetBSD:
6793 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
6794 case llvm::Triple::OpenBSD:
6795 return new OpenBSDX86_64TargetInfo(Triple);
6796 case llvm::Triple::Bitrig:
6797 return new BitrigX86_64TargetInfo(Triple);
6798 case llvm::Triple::FreeBSD:
6799 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6800 case llvm::Triple::KFreeBSD:
6801 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6802 case llvm::Triple::Solaris:
6803 return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
6804 case llvm::Triple::Win32: {
6805 switch (Triple.getEnvironment()) {
6806 default:
6807 return new X86_64TargetInfo(Triple);
6808 case llvm::Triple::GNU:
6809 return new MinGWX86_64TargetInfo(Triple);
6810 case llvm::Triple::MSVC:
6811 return new MicrosoftX86_64TargetInfo(Triple);
6812 }
6813 }
6814 case llvm::Triple::NaCl:
6815 return new NaClTargetInfo<X86_64TargetInfo>(Triple);
6816 default:
6817 return new X86_64TargetInfo(Triple);
6818 }
6819
6820 case llvm::Triple::spir: {
6821 if (Triple.getOS() != llvm::Triple::UnknownOS ||
6822 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6823 return nullptr;
6824 return new SPIR32TargetInfo(Triple);
6825 }
6826 case llvm::Triple::spir64: {
6827 if (Triple.getOS() != llvm::Triple::UnknownOS ||
6828 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6829 return nullptr;
6830 return new SPIR64TargetInfo(Triple);
6831 }
6832 }
6833}
6834
6835/// CreateTargetInfo - Return the target info object for the specified target
6836/// triple.
6837TargetInfo *
6838TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
6839 const std::shared_ptr<TargetOptions> &Opts) {
6840 llvm::Triple Triple(Opts->Triple);
6841
6842 // Construct the target
6843 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
6844 if (!Target) {
6845 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
6846 return nullptr;
6847 }
6848 Target->TargetOpts = Opts;
6849
6850 // Set the target CPU if specified.
6851 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
6852 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
6853 return nullptr;
6854 }
6855
6856 // Set the target ABI if specified.
6857 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
6858 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
6859 return nullptr;
6860 }
6861
6862 // Set the fp math unit.
6863 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
6864 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
6865 return nullptr;
6866 }
6867
6868 // Compute the default target features, we need the target to handle this
6869 // because features may have dependencies on one another.
6870 llvm::StringMap<bool> Features;
6871 Target->getDefaultFeatures(Features);
6872
6873 // Apply the user specified deltas.
6874 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size();
6875 I < N; ++I) {
6876 const char *Name = Opts->FeaturesAsWritten[I].c_str();
6877 // Apply the feature via the target.
6878 bool Enabled = Name[0] == '+';
6879 Target->setFeatureEnabled(Features, Name + 1, Enabled);
6880 }
6881
6882 // Add the features to the compile options.
6883 //
6884 // FIXME: If we are completely confident that we have the right set, we only
6885 // need to pass the minuses.
6886 Opts->Features.clear();
6887 for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
6888 ie = Features.end(); it != ie; ++it)
6889 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
6890 if (!Target->handleTargetFeatures(Opts->Features, Diags))
6891 return nullptr;
6892
6893 return Target.release();
6894}
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