| XCoreRegisterInfo.td (223017) | XCoreRegisterInfo.td (224145) |
|---|---|
| 1//===- XCoreRegisterInfo.td - XCore Register defs ----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 30 unchanged lines hidden (view full) --- 39def DP : Ri<13, "dp">, DwarfRegNum<[13]>; 40def SP : Ri<14, "sp">, DwarfRegNum<[14]>; 41def LR : Ri<15, "lr">, DwarfRegNum<[15]>; 42 43// Register classes. 44// 45def GRRegs : RegisterClass<"XCore", [i32], 32, 46 // Return values and arguments | 1//===- XCoreRegisterInfo.td - XCore Register defs ----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 30 unchanged lines hidden (view full) --- 39def DP : Ri<13, "dp">, DwarfRegNum<[13]>; 40def SP : Ri<14, "sp">, DwarfRegNum<[14]>; 41def LR : Ri<15, "lr">, DwarfRegNum<[15]>; 42 43// Register classes. 44// 45def GRRegs : RegisterClass<"XCore", [i32], 32, 46 // Return values and arguments |
| 47 [R0, R1, R2, R3, | 47 (add R0, R1, R2, R3, |
| 48 // Not preserved across procedure calls 49 R11, 50 // Callee save | 48 // Not preserved across procedure calls 49 R11, 50 // Callee save |
| 51 R4, R5, R6, R7, R8, R9, R10]>; | 51 R4, R5, R6, R7, R8, R9, R10)>; |
| 52 53// Reserved | 52 53// Reserved |
| 54def RRegs : RegisterClass<"XCore", [i32], 32, [CP, DP, SP, LR]> { | 54def RRegs : RegisterClass<"XCore", [i32], 32, (add CP, DP, SP, LR)> { |
| 55 let isAllocatable = 0; 56} | 55 let isAllocatable = 0; 56} |