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XCoreInstrInfo.cpp (198090) XCoreInstrInfo.cpp (200581)
1//===- XCoreInstrInfo.cpp - XCore Instruction Information -------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the XCore implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "XCoreMachineFunctionInfo.h"
15#include "XCoreInstrInfo.h"
16#include "XCore.h"
17#include "llvm/ADT/STLExtras.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineLocation.h"
21#include "llvm/CodeGen/MachineModuleInfo.h"
22#include "XCoreGenInstrInfo.inc"
23#include "llvm/Support/Debug.h"
24#include "llvm/Support/ErrorHandling.h"
25
26namespace llvm {
27namespace XCore {
28
29 // XCore Condition Codes
30 enum CondCode {
31 COND_TRUE,
32 COND_FALSE,
33 COND_INVALID
34 };
35}
36}
37
38using namespace llvm;
39
40XCoreInstrInfo::XCoreInstrInfo()
41 : TargetInstrInfoImpl(XCoreInsts, array_lengthof(XCoreInsts)),
42 RI(*this) {
43}
44
45static bool isZeroImm(const MachineOperand &op) {
46 return op.isImm() && op.getImm() == 0;
47}
48
49/// Return true if the instruction is a register to register move and
50/// leave the source and dest operands in the passed parameters.
51///
52bool XCoreInstrInfo::isMoveInstr(const MachineInstr &MI,
53 unsigned &SrcReg, unsigned &DstReg,
54 unsigned &SrcSR, unsigned &DstSR) const {
55 SrcSR = DstSR = 0; // No sub-registers.
56
57 // We look for 4 kinds of patterns here:
58 // add dst, src, 0
59 // sub dst, src, 0
60 // or dst, src, src
61 // and dst, src, src
62 if ((MI.getOpcode() == XCore::ADD_2rus || MI.getOpcode() == XCore::SUB_2rus)
63 && isZeroImm(MI.getOperand(2))) {
64 DstReg = MI.getOperand(0).getReg();
65 SrcReg = MI.getOperand(1).getReg();
66 return true;
67 } else if ((MI.getOpcode() == XCore::OR_3r || MI.getOpcode() == XCore::AND_3r)
68 && MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
69 DstReg = MI.getOperand(0).getReg();
70 SrcReg = MI.getOperand(1).getReg();
71 return true;
72 }
73 return false;
74}
75
76/// isLoadFromStackSlot - If the specified machine instruction is a direct
77/// load from a stack slot, return the virtual or physical register number of
78/// the destination along with the FrameIndex of the loaded stack slot. If
79/// not, return 0. This predicate must return 0 if the instruction has
80/// any side effects other than loading from the stack slot.
81unsigned
82XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const{
83 int Opcode = MI->getOpcode();
84 if (Opcode == XCore::LDWFI)
85 {
86 if ((MI->getOperand(1).isFI()) && // is a stack slot
87 (MI->getOperand(2).isImm()) && // the imm is zero
88 (isZeroImm(MI->getOperand(2))))
89 {
90 FrameIndex = MI->getOperand(1).getIndex();
91 return MI->getOperand(0).getReg();
92 }
93 }
94 return 0;
95}
96
97 /// isStoreToStackSlot - If the specified machine instruction is a direct
98 /// store to a stack slot, return the virtual or physical register number of
99 /// the source reg along with the FrameIndex of the loaded stack slot. If
100 /// not, return 0. This predicate must return 0 if the instruction has
101 /// any side effects other than storing to the stack slot.
102unsigned
103XCoreInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
104 int &FrameIndex) const {
105 int Opcode = MI->getOpcode();
106 if (Opcode == XCore::STWFI)
107 {
108 if ((MI->getOperand(1).isFI()) && // is a stack slot
109 (MI->getOperand(2).isImm()) && // the imm is zero
110 (isZeroImm(MI->getOperand(2))))
111 {
112 FrameIndex = MI->getOperand(1).getIndex();
113 return MI->getOperand(0).getReg();
114 }
115 }
116 return 0;
117}
118
119//===----------------------------------------------------------------------===//
120// Branch Analysis
121//===----------------------------------------------------------------------===//
122
123static inline bool IsBRU(unsigned BrOpc) {
124 return BrOpc == XCore::BRFU_u6
125 || BrOpc == XCore::BRFU_lu6
126 || BrOpc == XCore::BRBU_u6
127 || BrOpc == XCore::BRBU_lu6;
128}
129
130static inline bool IsBRT(unsigned BrOpc) {
131 return BrOpc == XCore::BRFT_ru6
132 || BrOpc == XCore::BRFT_lru6
133 || BrOpc == XCore::BRBT_ru6
134 || BrOpc == XCore::BRBT_lru6;
135}
136
137static inline bool IsBRF(unsigned BrOpc) {
138 return BrOpc == XCore::BRFF_ru6
139 || BrOpc == XCore::BRFF_lru6
140 || BrOpc == XCore::BRBF_ru6
141 || BrOpc == XCore::BRBF_lru6;
142}
143
144static inline bool IsCondBranch(unsigned BrOpc) {
145 return IsBRF(BrOpc) || IsBRT(BrOpc);
146}
147
148/// GetCondFromBranchOpc - Return the XCore CC that matches
149/// the correspondent Branch instruction opcode.
150static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
151{
152 if (IsBRT(BrOpc)) {
153 return XCore::COND_TRUE;
154 } else if (IsBRF(BrOpc)) {
155 return XCore::COND_FALSE;
156 } else {
157 return XCore::COND_INVALID;
158 }
159}
160
161/// GetCondBranchFromCond - Return the Branch instruction
162/// opcode that matches the cc.
163static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
164{
165 switch (CC) {
166 default: llvm_unreachable("Illegal condition code!");
167 case XCore::COND_TRUE : return XCore::BRFT_lru6;
168 case XCore::COND_FALSE : return XCore::BRFF_lru6;
169 }
170}
171
172/// GetOppositeBranchCondition - Return the inverse of the specified
173/// condition, e.g. turning COND_E to COND_NE.
174static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
175{
176 switch (CC) {
177 default: llvm_unreachable("Illegal condition code!");
178 case XCore::COND_TRUE : return XCore::COND_FALSE;
179 case XCore::COND_FALSE : return XCore::COND_TRUE;
180 }
181}
182
183/// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
184/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
185/// implemented for a target). Upon success, this returns false and returns
186/// with the following information in various cases:
187///
188/// 1. If this block ends with no branches (it just falls through to its succ)
189/// just return false, leaving TBB/FBB null.
190/// 2. If this block ends with only an unconditional branch, it sets TBB to be
191/// the destination block.
192/// 3. If this block ends with an conditional branch and it falls through to
193/// an successor block, it sets TBB to be the branch destination block and a
194/// list of operands that evaluate the condition. These
195/// operands can be passed to other TargetInstrInfo methods to create new
196/// branches.
197/// 4. If this block ends with an conditional branch and an unconditional
198/// block, it returns the 'true' destination in TBB, the 'false' destination
199/// in FBB, and a list of operands that evaluate the condition. These
200/// operands can be passed to other TargetInstrInfo methods to create new
201/// branches.
202///
203/// Note that RemoveBranch and InsertBranch must be implemented to support
204/// cases where this method returns success.
205///
206bool
207XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
208 MachineBasicBlock *&FBB,
209 SmallVectorImpl<MachineOperand> &Cond,
210 bool AllowModify) const {
211 // If the block has no terminators, it just falls into the block after it.
212 MachineBasicBlock::iterator I = MBB.end();
213 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
214 return false;
215
216 // Get the last instruction in the block.
217 MachineInstr *LastInst = I;
218
219 // If there is only one terminator instruction, process it.
220 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
221 if (IsBRU(LastInst->getOpcode())) {
222 TBB = LastInst->getOperand(0).getMBB();
223 return false;
224 }
225
226 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
227 if (BranchCode == XCore::COND_INVALID)
228 return true; // Can't handle indirect branch.
229
230 // Conditional branch
231 // Block ends with fall-through condbranch.
232
233 TBB = LastInst->getOperand(1).getMBB();
234 Cond.push_back(MachineOperand::CreateImm(BranchCode));
235 Cond.push_back(LastInst->getOperand(0));
236 return false;
237 }
238
239 // Get the instruction before it if it's a terminator.
240 MachineInstr *SecondLastInst = I;
241
242 // If there are three terminators, we don't know what sort of block this is.
243 if (SecondLastInst && I != MBB.begin() &&
244 isUnpredicatedTerminator(--I))
245 return true;
246
247 unsigned SecondLastOpc = SecondLastInst->getOpcode();
248 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
249
250 // If the block ends with conditional branch followed by unconditional,
251 // handle it.
252 if (BranchCode != XCore::COND_INVALID
253 && IsBRU(LastInst->getOpcode())) {
254
255 TBB = SecondLastInst->getOperand(1).getMBB();
256 Cond.push_back(MachineOperand::CreateImm(BranchCode));
257 Cond.push_back(SecondLastInst->getOperand(0));
258
259 FBB = LastInst->getOperand(0).getMBB();
260 return false;
261 }
262
263 // If the block ends with two unconditional branches, handle it. The second
264 // one is not executed, so remove it.
265 if (IsBRU(SecondLastInst->getOpcode()) &&
266 IsBRU(LastInst->getOpcode())) {
267 TBB = SecondLastInst->getOperand(0).getMBB();
268 I = LastInst;
269 if (AllowModify)
270 I->eraseFromParent();
271 return false;
272 }
273
274 // Otherwise, can't handle this.
275 return true;
276}
277
278unsigned
279XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
280 MachineBasicBlock *FBB,
281 const SmallVectorImpl<MachineOperand> &Cond)const{
282 // FIXME there should probably be a DebugLoc argument here
283 DebugLoc dl = DebugLoc::getUnknownLoc();
284 // Shouldn't be a fall through.
285 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
286 assert((Cond.size() == 2 || Cond.size() == 0) &&
287 "Unexpected number of components!");
288
289 if (FBB == 0) { // One way branch.
290 if (Cond.empty()) {
291 // Unconditional branch
292 BuildMI(&MBB, dl, get(XCore::BRFU_lu6)).addMBB(TBB);
293 } else {
294 // Conditional branch.
295 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
296 BuildMI(&MBB, dl, get(Opc)).addReg(Cond[1].getReg())
297 .addMBB(TBB);
298 }
299 return 1;
300 }
301
302 // Two-way Conditional branch.
303 assert(Cond.size() == 2 && "Unexpected number of components!");
304 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
305 BuildMI(&MBB, dl, get(Opc)).addReg(Cond[1].getReg())
306 .addMBB(TBB);
307 BuildMI(&MBB, dl, get(XCore::BRFU_lu6)).addMBB(FBB);
308 return 2;
309}
310
311unsigned
312XCoreInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
313 MachineBasicBlock::iterator I = MBB.end();
314 if (I == MBB.begin()) return 0;
315 --I;
316 if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode()))
317 return 0;
318
319 // Remove the branch.
320 I->eraseFromParent();
321
322 I = MBB.end();
323
324 if (I == MBB.begin()) return 1;
325 --I;
326 if (!IsCondBranch(I->getOpcode()))
327 return 1;
328
329 // Remove the branch.
330 I->eraseFromParent();
331 return 2;
332}
333
334bool XCoreInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
335 MachineBasicBlock::iterator I,
336 unsigned DestReg, unsigned SrcReg,
337 const TargetRegisterClass *DestRC,
338 const TargetRegisterClass *SrcRC) const {
339 DebugLoc DL = DebugLoc::getUnknownLoc();
340 if (I != MBB.end()) DL = I->getDebugLoc();
341
342 if (DestRC == SrcRC) {
343 if (DestRC == XCore::GRRegsRegisterClass) {
344 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
345 .addReg(SrcReg)
346 .addImm(0);
347 return true;
348 } else {
349 return false;
350 }
351 }
352
353 if (SrcRC == XCore::RRegsRegisterClass && SrcReg == XCore::SP &&
354 DestRC == XCore::GRRegsRegisterClass) {
355 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg)
356 .addImm(0);
357 return true;
358 }
359 if (DestRC == XCore::RRegsRegisterClass && DestReg == XCore::SP &&
360 SrcRC == XCore::GRRegsRegisterClass) {
361 BuildMI(MBB, I, DL, get(XCore::SETSP_1r))
362 .addReg(SrcReg);
363 return true;
364 }
365 return false;
366}
367
368void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
369 MachineBasicBlock::iterator I,
370 unsigned SrcReg, bool isKill,
371 int FrameIndex,
372 const TargetRegisterClass *RC) const
373{
374 DebugLoc DL = DebugLoc::getUnknownLoc();
375 if (I != MBB.end()) DL = I->getDebugLoc();
376 BuildMI(MBB, I, DL, get(XCore::STWFI))
377 .addReg(SrcReg, getKillRegState(isKill))
378 .addFrameIndex(FrameIndex)
379 .addImm(0);
380}
381
382void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
383 MachineBasicBlock::iterator I,
384 unsigned DestReg, int FrameIndex,
385 const TargetRegisterClass *RC) const
386{
387 DebugLoc DL = DebugLoc::getUnknownLoc();
388 if (I != MBB.end()) DL = I->getDebugLoc();
389 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
390 .addFrameIndex(FrameIndex)
391 .addImm(0);
392}
393
394bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
395 MachineBasicBlock::iterator MI,
396 const std::vector<CalleeSavedInfo> &CSI) const
397{
398 if (CSI.empty()) {
399 return true;
400 }
401 MachineFunction *MF = MBB.getParent();
402 const MachineFrameInfo *MFI = MF->getFrameInfo();
403 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
404 XCoreFunctionInfo *XFI = MF->getInfo<XCoreFunctionInfo>();
405
406 bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF);
407
408 DebugLoc DL = DebugLoc::getUnknownLoc();
409 if (MI != MBB.end()) DL = MI->getDebugLoc();
410
411 for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
412 it != CSI.end(); ++it) {
413 // Add the callee-saved register as live-in. It's killed at the spill.
414 MBB.addLiveIn(it->getReg());
415
416 storeRegToStackSlot(MBB, MI, it->getReg(), true,
417 it->getFrameIdx(), it->getRegClass());
418 if (emitFrameMoves) {
419 unsigned SaveLabelId = MMI->NextLabelID();
420 BuildMI(MBB, MI, DL, get(XCore::DBG_LABEL)).addImm(SaveLabelId);
421 XFI->getSpillLabels().push_back(
422 std::pair<unsigned, CalleeSavedInfo>(SaveLabelId, *it));
423 }
424 }
425 return true;
426}
427
428bool XCoreInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
429 MachineBasicBlock::iterator MI,
430 const std::vector<CalleeSavedInfo> &CSI) const
431{
432 bool AtStart = MI == MBB.begin();
433 MachineBasicBlock::iterator BeforeI = MI;
434 if (!AtStart)
435 --BeforeI;
436 for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
437 it != CSI.end(); ++it) {
438
439 loadRegFromStackSlot(MBB, MI, it->getReg(),
440 it->getFrameIdx(),
441 it->getRegClass());
442 assert(MI != MBB.begin() &&
443 "loadRegFromStackSlot didn't insert any code!");
444 // Insert in reverse order. loadRegFromStackSlot can insert multiple
445 // instructions.
446 if (AtStart)
447 MI = MBB.begin();
448 else {
449 MI = BeforeI;
450 ++MI;
451 }
452 }
453 return true;
454}
455
1//===- XCoreInstrInfo.cpp - XCore Instruction Information -------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the XCore implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "XCoreMachineFunctionInfo.h"
15#include "XCoreInstrInfo.h"
16#include "XCore.h"
17#include "llvm/ADT/STLExtras.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineLocation.h"
21#include "llvm/CodeGen/MachineModuleInfo.h"
22#include "XCoreGenInstrInfo.inc"
23#include "llvm/Support/Debug.h"
24#include "llvm/Support/ErrorHandling.h"
25
26namespace llvm {
27namespace XCore {
28
29 // XCore Condition Codes
30 enum CondCode {
31 COND_TRUE,
32 COND_FALSE,
33 COND_INVALID
34 };
35}
36}
37
38using namespace llvm;
39
40XCoreInstrInfo::XCoreInstrInfo()
41 : TargetInstrInfoImpl(XCoreInsts, array_lengthof(XCoreInsts)),
42 RI(*this) {
43}
44
45static bool isZeroImm(const MachineOperand &op) {
46 return op.isImm() && op.getImm() == 0;
47}
48
49/// Return true if the instruction is a register to register move and
50/// leave the source and dest operands in the passed parameters.
51///
52bool XCoreInstrInfo::isMoveInstr(const MachineInstr &MI,
53 unsigned &SrcReg, unsigned &DstReg,
54 unsigned &SrcSR, unsigned &DstSR) const {
55 SrcSR = DstSR = 0; // No sub-registers.
56
57 // We look for 4 kinds of patterns here:
58 // add dst, src, 0
59 // sub dst, src, 0
60 // or dst, src, src
61 // and dst, src, src
62 if ((MI.getOpcode() == XCore::ADD_2rus || MI.getOpcode() == XCore::SUB_2rus)
63 && isZeroImm(MI.getOperand(2))) {
64 DstReg = MI.getOperand(0).getReg();
65 SrcReg = MI.getOperand(1).getReg();
66 return true;
67 } else if ((MI.getOpcode() == XCore::OR_3r || MI.getOpcode() == XCore::AND_3r)
68 && MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
69 DstReg = MI.getOperand(0).getReg();
70 SrcReg = MI.getOperand(1).getReg();
71 return true;
72 }
73 return false;
74}
75
76/// isLoadFromStackSlot - If the specified machine instruction is a direct
77/// load from a stack slot, return the virtual or physical register number of
78/// the destination along with the FrameIndex of the loaded stack slot. If
79/// not, return 0. This predicate must return 0 if the instruction has
80/// any side effects other than loading from the stack slot.
81unsigned
82XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const{
83 int Opcode = MI->getOpcode();
84 if (Opcode == XCore::LDWFI)
85 {
86 if ((MI->getOperand(1).isFI()) && // is a stack slot
87 (MI->getOperand(2).isImm()) && // the imm is zero
88 (isZeroImm(MI->getOperand(2))))
89 {
90 FrameIndex = MI->getOperand(1).getIndex();
91 return MI->getOperand(0).getReg();
92 }
93 }
94 return 0;
95}
96
97 /// isStoreToStackSlot - If the specified machine instruction is a direct
98 /// store to a stack slot, return the virtual or physical register number of
99 /// the source reg along with the FrameIndex of the loaded stack slot. If
100 /// not, return 0. This predicate must return 0 if the instruction has
101 /// any side effects other than storing to the stack slot.
102unsigned
103XCoreInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
104 int &FrameIndex) const {
105 int Opcode = MI->getOpcode();
106 if (Opcode == XCore::STWFI)
107 {
108 if ((MI->getOperand(1).isFI()) && // is a stack slot
109 (MI->getOperand(2).isImm()) && // the imm is zero
110 (isZeroImm(MI->getOperand(2))))
111 {
112 FrameIndex = MI->getOperand(1).getIndex();
113 return MI->getOperand(0).getReg();
114 }
115 }
116 return 0;
117}
118
119//===----------------------------------------------------------------------===//
120// Branch Analysis
121//===----------------------------------------------------------------------===//
122
123static inline bool IsBRU(unsigned BrOpc) {
124 return BrOpc == XCore::BRFU_u6
125 || BrOpc == XCore::BRFU_lu6
126 || BrOpc == XCore::BRBU_u6
127 || BrOpc == XCore::BRBU_lu6;
128}
129
130static inline bool IsBRT(unsigned BrOpc) {
131 return BrOpc == XCore::BRFT_ru6
132 || BrOpc == XCore::BRFT_lru6
133 || BrOpc == XCore::BRBT_ru6
134 || BrOpc == XCore::BRBT_lru6;
135}
136
137static inline bool IsBRF(unsigned BrOpc) {
138 return BrOpc == XCore::BRFF_ru6
139 || BrOpc == XCore::BRFF_lru6
140 || BrOpc == XCore::BRBF_ru6
141 || BrOpc == XCore::BRBF_lru6;
142}
143
144static inline bool IsCondBranch(unsigned BrOpc) {
145 return IsBRF(BrOpc) || IsBRT(BrOpc);
146}
147
148/// GetCondFromBranchOpc - Return the XCore CC that matches
149/// the correspondent Branch instruction opcode.
150static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
151{
152 if (IsBRT(BrOpc)) {
153 return XCore::COND_TRUE;
154 } else if (IsBRF(BrOpc)) {
155 return XCore::COND_FALSE;
156 } else {
157 return XCore::COND_INVALID;
158 }
159}
160
161/// GetCondBranchFromCond - Return the Branch instruction
162/// opcode that matches the cc.
163static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
164{
165 switch (CC) {
166 default: llvm_unreachable("Illegal condition code!");
167 case XCore::COND_TRUE : return XCore::BRFT_lru6;
168 case XCore::COND_FALSE : return XCore::BRFF_lru6;
169 }
170}
171
172/// GetOppositeBranchCondition - Return the inverse of the specified
173/// condition, e.g. turning COND_E to COND_NE.
174static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
175{
176 switch (CC) {
177 default: llvm_unreachable("Illegal condition code!");
178 case XCore::COND_TRUE : return XCore::COND_FALSE;
179 case XCore::COND_FALSE : return XCore::COND_TRUE;
180 }
181}
182
183/// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
184/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
185/// implemented for a target). Upon success, this returns false and returns
186/// with the following information in various cases:
187///
188/// 1. If this block ends with no branches (it just falls through to its succ)
189/// just return false, leaving TBB/FBB null.
190/// 2. If this block ends with only an unconditional branch, it sets TBB to be
191/// the destination block.
192/// 3. If this block ends with an conditional branch and it falls through to
193/// an successor block, it sets TBB to be the branch destination block and a
194/// list of operands that evaluate the condition. These
195/// operands can be passed to other TargetInstrInfo methods to create new
196/// branches.
197/// 4. If this block ends with an conditional branch and an unconditional
198/// block, it returns the 'true' destination in TBB, the 'false' destination
199/// in FBB, and a list of operands that evaluate the condition. These
200/// operands can be passed to other TargetInstrInfo methods to create new
201/// branches.
202///
203/// Note that RemoveBranch and InsertBranch must be implemented to support
204/// cases where this method returns success.
205///
206bool
207XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
208 MachineBasicBlock *&FBB,
209 SmallVectorImpl<MachineOperand> &Cond,
210 bool AllowModify) const {
211 // If the block has no terminators, it just falls into the block after it.
212 MachineBasicBlock::iterator I = MBB.end();
213 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
214 return false;
215
216 // Get the last instruction in the block.
217 MachineInstr *LastInst = I;
218
219 // If there is only one terminator instruction, process it.
220 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
221 if (IsBRU(LastInst->getOpcode())) {
222 TBB = LastInst->getOperand(0).getMBB();
223 return false;
224 }
225
226 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
227 if (BranchCode == XCore::COND_INVALID)
228 return true; // Can't handle indirect branch.
229
230 // Conditional branch
231 // Block ends with fall-through condbranch.
232
233 TBB = LastInst->getOperand(1).getMBB();
234 Cond.push_back(MachineOperand::CreateImm(BranchCode));
235 Cond.push_back(LastInst->getOperand(0));
236 return false;
237 }
238
239 // Get the instruction before it if it's a terminator.
240 MachineInstr *SecondLastInst = I;
241
242 // If there are three terminators, we don't know what sort of block this is.
243 if (SecondLastInst && I != MBB.begin() &&
244 isUnpredicatedTerminator(--I))
245 return true;
246
247 unsigned SecondLastOpc = SecondLastInst->getOpcode();
248 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
249
250 // If the block ends with conditional branch followed by unconditional,
251 // handle it.
252 if (BranchCode != XCore::COND_INVALID
253 && IsBRU(LastInst->getOpcode())) {
254
255 TBB = SecondLastInst->getOperand(1).getMBB();
256 Cond.push_back(MachineOperand::CreateImm(BranchCode));
257 Cond.push_back(SecondLastInst->getOperand(0));
258
259 FBB = LastInst->getOperand(0).getMBB();
260 return false;
261 }
262
263 // If the block ends with two unconditional branches, handle it. The second
264 // one is not executed, so remove it.
265 if (IsBRU(SecondLastInst->getOpcode()) &&
266 IsBRU(LastInst->getOpcode())) {
267 TBB = SecondLastInst->getOperand(0).getMBB();
268 I = LastInst;
269 if (AllowModify)
270 I->eraseFromParent();
271 return false;
272 }
273
274 // Otherwise, can't handle this.
275 return true;
276}
277
278unsigned
279XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
280 MachineBasicBlock *FBB,
281 const SmallVectorImpl<MachineOperand> &Cond)const{
282 // FIXME there should probably be a DebugLoc argument here
283 DebugLoc dl = DebugLoc::getUnknownLoc();
284 // Shouldn't be a fall through.
285 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
286 assert((Cond.size() == 2 || Cond.size() == 0) &&
287 "Unexpected number of components!");
288
289 if (FBB == 0) { // One way branch.
290 if (Cond.empty()) {
291 // Unconditional branch
292 BuildMI(&MBB, dl, get(XCore::BRFU_lu6)).addMBB(TBB);
293 } else {
294 // Conditional branch.
295 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
296 BuildMI(&MBB, dl, get(Opc)).addReg(Cond[1].getReg())
297 .addMBB(TBB);
298 }
299 return 1;
300 }
301
302 // Two-way Conditional branch.
303 assert(Cond.size() == 2 && "Unexpected number of components!");
304 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
305 BuildMI(&MBB, dl, get(Opc)).addReg(Cond[1].getReg())
306 .addMBB(TBB);
307 BuildMI(&MBB, dl, get(XCore::BRFU_lu6)).addMBB(FBB);
308 return 2;
309}
310
311unsigned
312XCoreInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
313 MachineBasicBlock::iterator I = MBB.end();
314 if (I == MBB.begin()) return 0;
315 --I;
316 if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode()))
317 return 0;
318
319 // Remove the branch.
320 I->eraseFromParent();
321
322 I = MBB.end();
323
324 if (I == MBB.begin()) return 1;
325 --I;
326 if (!IsCondBranch(I->getOpcode()))
327 return 1;
328
329 // Remove the branch.
330 I->eraseFromParent();
331 return 2;
332}
333
334bool XCoreInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
335 MachineBasicBlock::iterator I,
336 unsigned DestReg, unsigned SrcReg,
337 const TargetRegisterClass *DestRC,
338 const TargetRegisterClass *SrcRC) const {
339 DebugLoc DL = DebugLoc::getUnknownLoc();
340 if (I != MBB.end()) DL = I->getDebugLoc();
341
342 if (DestRC == SrcRC) {
343 if (DestRC == XCore::GRRegsRegisterClass) {
344 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
345 .addReg(SrcReg)
346 .addImm(0);
347 return true;
348 } else {
349 return false;
350 }
351 }
352
353 if (SrcRC == XCore::RRegsRegisterClass && SrcReg == XCore::SP &&
354 DestRC == XCore::GRRegsRegisterClass) {
355 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg)
356 .addImm(0);
357 return true;
358 }
359 if (DestRC == XCore::RRegsRegisterClass && DestReg == XCore::SP &&
360 SrcRC == XCore::GRRegsRegisterClass) {
361 BuildMI(MBB, I, DL, get(XCore::SETSP_1r))
362 .addReg(SrcReg);
363 return true;
364 }
365 return false;
366}
367
368void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
369 MachineBasicBlock::iterator I,
370 unsigned SrcReg, bool isKill,
371 int FrameIndex,
372 const TargetRegisterClass *RC) const
373{
374 DebugLoc DL = DebugLoc::getUnknownLoc();
375 if (I != MBB.end()) DL = I->getDebugLoc();
376 BuildMI(MBB, I, DL, get(XCore::STWFI))
377 .addReg(SrcReg, getKillRegState(isKill))
378 .addFrameIndex(FrameIndex)
379 .addImm(0);
380}
381
382void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
383 MachineBasicBlock::iterator I,
384 unsigned DestReg, int FrameIndex,
385 const TargetRegisterClass *RC) const
386{
387 DebugLoc DL = DebugLoc::getUnknownLoc();
388 if (I != MBB.end()) DL = I->getDebugLoc();
389 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
390 .addFrameIndex(FrameIndex)
391 .addImm(0);
392}
393
394bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
395 MachineBasicBlock::iterator MI,
396 const std::vector<CalleeSavedInfo> &CSI) const
397{
398 if (CSI.empty()) {
399 return true;
400 }
401 MachineFunction *MF = MBB.getParent();
402 const MachineFrameInfo *MFI = MF->getFrameInfo();
403 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
404 XCoreFunctionInfo *XFI = MF->getInfo<XCoreFunctionInfo>();
405
406 bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF);
407
408 DebugLoc DL = DebugLoc::getUnknownLoc();
409 if (MI != MBB.end()) DL = MI->getDebugLoc();
410
411 for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
412 it != CSI.end(); ++it) {
413 // Add the callee-saved register as live-in. It's killed at the spill.
414 MBB.addLiveIn(it->getReg());
415
416 storeRegToStackSlot(MBB, MI, it->getReg(), true,
417 it->getFrameIdx(), it->getRegClass());
418 if (emitFrameMoves) {
419 unsigned SaveLabelId = MMI->NextLabelID();
420 BuildMI(MBB, MI, DL, get(XCore::DBG_LABEL)).addImm(SaveLabelId);
421 XFI->getSpillLabels().push_back(
422 std::pair<unsigned, CalleeSavedInfo>(SaveLabelId, *it));
423 }
424 }
425 return true;
426}
427
428bool XCoreInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
429 MachineBasicBlock::iterator MI,
430 const std::vector<CalleeSavedInfo> &CSI) const
431{
432 bool AtStart = MI == MBB.begin();
433 MachineBasicBlock::iterator BeforeI = MI;
434 if (!AtStart)
435 --BeforeI;
436 for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
437 it != CSI.end(); ++it) {
438
439 loadRegFromStackSlot(MBB, MI, it->getReg(),
440 it->getFrameIdx(),
441 it->getRegClass());
442 assert(MI != MBB.begin() &&
443 "loadRegFromStackSlot didn't insert any code!");
444 // Insert in reverse order. loadRegFromStackSlot can insert multiple
445 // instructions.
446 if (AtStart)
447 MI = MBB.begin();
448 else {
449 MI = BeforeI;
450 ++MI;
451 }
452 }
453 return true;
454}
455
456/// BlockHasNoFallThrough - Analyse if MachineBasicBlock does not
457/// fall-through into its successor block.
458bool XCoreInstrInfo::
459BlockHasNoFallThrough(const MachineBasicBlock &MBB) const
460{
461 if (MBB.empty()) return false;
462
463 switch (MBB.back().getOpcode()) {
464 case XCore::RETSP_u6: // Return.
465 case XCore::RETSP_lu6:
466 case XCore::BAU_1r: // Indirect branch.
467 case XCore::BRFU_u6: // Uncond branch.
468 case XCore::BRFU_lu6:
469 case XCore::BRBU_u6:
470 case XCore::BRBU_lu6:
471 return true;
472 default: return false;
473 }
474}
475
476/// ReverseBranchCondition - Return the inverse opcode of the
477/// specified Branch instruction.
478bool XCoreInstrInfo::
479ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
480{
481 assert((Cond.size() == 2) &&
482 "Invalid XCore branch condition!");
483 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm()));
484 return false;
485}
456/// ReverseBranchCondition - Return the inverse opcode of the
457/// specified Branch instruction.
458bool XCoreInstrInfo::
459ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
460{
461 assert((Cond.size() == 2) &&
462 "Invalid XCore branch condition!");
463 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm()));
464 return false;
465}