1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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7686 int64_t Offset = 0;
7687 if (TLI.isGAPlusOffset(Base, GV, Offset))
7688 return (GV->getAlignment() >= N && (Offset % N) == 0);
7689 // DAG combine handles the stack object case.
7690 return false;
7691}
7692
7693static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
7694 MVT EVT, LoadSDNode *&LDBase,
7695 unsigned &LastLoadedElt,
7696 SelectionDAG &DAG, MachineFrameInfo *MFI,
7697 const TargetLowering &TLI) {
7698 LDBase = NULL;
7699 LastLoadedElt = -1;
7700 for (unsigned i = 0; i < NumElems; ++i) {
7701 if (N->getMaskElt(i) < 0) {
7702 if (!LDBase)
7703 return false;
7704 continue;
7705 }
7706
7707 SDValue Elt = DAG.getShuffleScalarElt(N, i);
7708 if (!Elt.getNode() ||
7709 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
7710 return false;
7711 if (!LDBase) {
7712 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
7713 return false;
7714 LDBase = cast<LoadSDNode>(Elt.getNode());
7715 LastLoadedElt = i;
7716 continue;
7717 }
7718 if (Elt.getOpcode() == ISD::UNDEF)
7719 continue;
7720
7721 LoadSDNode *LD = cast<LoadSDNode>(Elt);
7722 if (!TLI.isConsecutiveLoad(LD, LDBase, EVT.getSizeInBits()/8, i, MFI))
7723 return false;
7724 LastLoadedElt = i;
7725 }
7726 return true;
7727}
7728
7729/// PerformShuffleCombine - Combine a vector_shuffle that is equal to
7730/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
7731/// if the load addresses are consecutive, non-overlapping, and in the right
7732/// order. In the case of v2i64, it will see if it can rewrite the
7733/// shuffle to be an appropriate build vector so it can take advantage of
7734// performBuildVectorCombine.
7735static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
7736 const TargetLowering &TLI) {
7737 DebugLoc dl = N->getDebugLoc();
7738 MVT VT = N->getValueType(0);
7739 MVT EVT = VT.getVectorElementType();
7740 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
7741 unsigned NumElems = VT.getVectorNumElements();
7742
7743 if (VT.getSizeInBits() != 128)
7744 return SDValue();
7745
7746 // Try to combine a vector_shuffle into a 128-bit load.
7747 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7748 LoadSDNode *LD = NULL;
7749 unsigned LastLoadedElt;
7750 if (!EltsFromConsecutiveLoads(SVN, NumElems, EVT, LD, LastLoadedElt, DAG,
7751 MFI, TLI))
7752 return SDValue();
7753
7754 if (LastLoadedElt == NumElems - 1) {
7755 if (isBaseAlignmentOfN(16, LD->getBasePtr().getNode(), TLI))
7756 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
7757 LD->getSrcValue(), LD->getSrcValueOffset(),
7758 LD->isVolatile());
7759 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
7760 LD->getSrcValue(), LD->getSrcValueOffset(),
7761 LD->isVolatile(), LD->getAlignment());
7762 } else if (NumElems == 4 && LastLoadedElt == 1) {
7763 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
7764 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
7765 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
7766 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
7767 }
7768 return SDValue();
7769}
7770
7771/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
7772static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
7773 const X86Subtarget *Subtarget) {

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8359 TargetLowering &TLI = DAG.getTargetLoweringInfo();
8360 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
8361 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
8362 DCI.CommitTargetLoweringOpt(TLO);
8363 }
8364 return SDValue();
8365}
8366
8367static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
8368 SDValue Op = N->getOperand(0);
8369 if (Op.getOpcode() == ISD::BIT_CONVERT)
8370 Op = Op.getOperand(0);
8371 MVT VT = N->getValueType(0), OpVT = Op.getValueType();
8372 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
8373 VT.getVectorElementType().getSizeInBits() ==
8374 OpVT.getVectorElementType().getSizeInBits()) {
8375 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
8376 }
8377 return SDValue();
8378}
8379
8380SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
8381 DAGCombinerInfo &DCI) const {
8382 SelectionDAG &DAG = DCI.DAG;
8383 switch (N->getOpcode()) {
8384 default: break;
8385 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
8386 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
8387 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
8388 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
8389 case ISD::SHL:
8390 case ISD::SRA:
8391 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
8392 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
8393 case X86ISD::FXOR:
8394 case X86ISD::FOR: return PerformFORCombine(N, DAG);
8395 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
8396 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
8397 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
8398 }
8399
8400 return SDValue();
8401}
8402
8403//===----------------------------------------------------------------------===//
8404// X86 Inline Assembly Support
8405//===----------------------------------------------------------------------===//

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