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SparcInstrInfo.td (261991) SparcInstrInfo.td (262613)
1//===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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71 return isShiftedUInt<22, 10>(N->getZExtValue());
72}], HI22>;
73
74// Addressing modes.
75def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
76def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
77
78// Address operands
1//===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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71 return isShiftedUInt<22, 10>(N->getZExtValue());
72}], HI22>;
73
74// Addressing modes.
75def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
76def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
77
78// Address operands
79def SparcMEMrrAsmOperand : AsmOperandClass {
80 let Name = "MEMrr";
81 let ParserMethod = "parseMEMOperand";
82}
83
84def SparcMEMriAsmOperand : AsmOperandClass {
85 let Name = "MEMri";
86 let ParserMethod = "parseMEMOperand";
87}
88
79def MEMrr : Operand<iPTR> {
80 let PrintMethod = "printMemOperand";
81 let MIOperandInfo = (ops ptr_rc, ptr_rc);
89def MEMrr : Operand<iPTR> {
90 let PrintMethod = "printMemOperand";
91 let MIOperandInfo = (ops ptr_rc, ptr_rc);
92 let ParserMatchClass = SparcMEMrrAsmOperand;
82}
83def MEMri : Operand<iPTR> {
84 let PrintMethod = "printMemOperand";
85 let MIOperandInfo = (ops ptr_rc, i32imm);
93}
94def MEMri : Operand<iPTR> {
95 let PrintMethod = "printMemOperand";
96 let MIOperandInfo = (ops ptr_rc, i32imm);
97 let ParserMatchClass = SparcMEMriAsmOperand;
86}
87
88def TLSSym : Operand<iPTR>;
89
90// Branch targets have OtherVT type.
98}
99
100def TLSSym : Operand<iPTR>;
101
102// Branch targets have OtherVT type.
91def brtarget : Operand<OtherVT>;
92def calltarget : Operand<i32>;
103def brtarget : Operand<OtherVT> {
104 let EncoderMethod = "getBranchTargetOpValue";
105}
93
106
107def calltarget : Operand<i32> {
108 let EncoderMethod = "getCallTargetOpValue";
109}
110
94// Operand for printing out a condition code.
95let PrintMethod = "printCCOperand" in
96 def CCOp : Operand<i32>;
97
98def SDTSPcmpicc :
99SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
100def SDTSPcmpfcc :
101SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;

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158 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;
159
160def tlsadd : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>;
161def tlsld : SDNode<"SPISD::TLS_LD", SDTSPtlsld>;
162def tlscall : SDNode<"SPISD::TLS_CALL", SDT_SPCall,
163 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
164 SDNPVariadic]>;
165
111// Operand for printing out a condition code.
112let PrintMethod = "printCCOperand" in
113 def CCOp : Operand<i32>;
114
115def SDTSPcmpicc :
116SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
117def SDTSPcmpfcc :
118SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;

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175 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;
176
177def tlsadd : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>;
178def tlsld : SDNode<"SPISD::TLS_LD", SDTSPtlsld>;
179def tlscall : SDNode<"SPISD::TLS_CALL", SDT_SPCall,
180 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
181 SDNPVariadic]>;
182
166def getPCX : Operand<i32> {
183def getPCX : Operand<iPTR> {
167 let PrintMethod = "printGetPCX";
168}
169
170//===----------------------------------------------------------------------===//
171// SPARC Flag Conditions
172//===----------------------------------------------------------------------===//
173
174// Note that these values must be kept in sync with the CCOp::CondCode enum

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205def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
206def FCC_O : FCC_VAL<29>; // Ordered
207
208//===----------------------------------------------------------------------===//
209// Instruction Class Templates
210//===----------------------------------------------------------------------===//
211
212/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
184 let PrintMethod = "printGetPCX";
185}
186
187//===----------------------------------------------------------------------===//
188// SPARC Flag Conditions
189//===----------------------------------------------------------------------===//
190
191// Note that these values must be kept in sync with the CCOp::CondCode enum

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222def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
223def FCC_O : FCC_VAL<29>; // Ordered
224
225//===----------------------------------------------------------------------===//
226// Instruction Class Templates
227//===----------------------------------------------------------------------===//
228
229/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
213multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> {
230multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
231 RegisterClass RC, ValueType Ty, Operand immOp> {
214 def rr : F3_1<2, Op3Val,
232 def rr : F3_1<2, Op3Val,
215 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
216 !strconcat(OpcStr, " $b, $c, $dst"),
217 [(set i32:$dst, (OpNode i32:$b, i32:$c))]>;
233 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
234 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
235 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))]>;
218 def ri : F3_2<2, Op3Val,
236 def ri : F3_2<2, Op3Val,
219 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
220 !strconcat(OpcStr, " $b, $c, $dst"),
221 [(set i32:$dst, (OpNode i32:$b, (i32 simm13:$c)))]>;
237 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
238 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
239 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))]>;
222}
223
224/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
225/// pattern.
226multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
227 def rr : F3_1<2, Op3Val,
240}
241
242/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
243/// pattern.
244multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
245 def rr : F3_1<2, Op3Val,
228 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
229 !strconcat(OpcStr, " $b, $c, $dst"), []>;
246 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
247 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
230 def ri : F3_2<2, Op3Val,
248 def ri : F3_2<2, Op3Val,
231 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
232 !strconcat(OpcStr, " $b, $c, $dst"), []>;
249 (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
250 !strconcat(OpcStr, " $rs1, $simm13, $rd"), []>;
233}
234
251}
252
253// Load multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
254multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
255 RegisterClass RC, ValueType Ty> {
256 def rr : F3_1<3, Op3Val,
257 (outs RC:$dst), (ins MEMrr:$addr),
258 !strconcat(OpcStr, " [$addr], $dst"),
259 [(set Ty:$dst, (OpNode ADDRrr:$addr))]>;
260 def ri : F3_2<3, Op3Val,
261 (outs RC:$dst), (ins MEMri:$addr),
262 !strconcat(OpcStr, " [$addr], $dst"),
263 [(set Ty:$dst, (OpNode ADDRri:$addr))]>;
264}
265
266// Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
267multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
268 RegisterClass RC, ValueType Ty> {
269 def rr : F3_1<3, Op3Val,
270 (outs), (ins MEMrr:$addr, RC:$rd),
271 !strconcat(OpcStr, " $rd, [$addr]"),
272 [(OpNode Ty:$rd, ADDRrr:$addr)]>;
273 def ri : F3_2<3, Op3Val,
274 (outs), (ins MEMri:$addr, RC:$rd),
275 !strconcat(OpcStr, " $rd, [$addr]"),
276 [(OpNode Ty:$rd, ADDRri:$addr)]>;
277}
278
235//===----------------------------------------------------------------------===//
236// Instructions
237//===----------------------------------------------------------------------===//
238
239// Pseudo instructions.
240class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
279//===----------------------------------------------------------------------===//
280// Instructions
281//===----------------------------------------------------------------------===//
282
283// Pseudo instructions.
284class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
241 : InstSP<outs, ins, asmstr, pattern>;
285 : InstSP<outs, ins, asmstr, pattern> {
286 let isCodeGenOnly = 1;
287 let isPseudo = 1;
288}
242
243// GETPCX for PIC
244let Defs = [O7] in {
245 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
246}
247
248let Defs = [O6], Uses = [O6] in {
249def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),

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260 "flushw",
261 [(flushw)]>, Requires<[HasV9]>;
262 let rd = 0, rs1 = 1, simm13 = 3 in
263 def TA3 : F3_2<0b10, 0b111010, (outs), (ins),
264 "ta 3",
265 [(flushw)]>;
266}
267
289
290// GETPCX for PIC
291let Defs = [O7] in {
292 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
293}
294
295let Defs = [O6], Uses = [O6] in {
296def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),

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307 "flushw",
308 [(flushw)]>, Requires<[HasV9]>;
309 let rd = 0, rs1 = 1, simm13 = 3 in
310 def TA3 : F3_2<0b10, 0b111010, (outs), (ins),
311 "ta 3",
312 [(flushw)]>;
313}
314
315let isBarrier = 1, isTerminator = 1, rd = 0b1000, rs1 = 0, simm13 = 5 in
316 def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>;
317
268let rd = 0 in
269 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val),
270 "unimp $val", []>;
271
272// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
273// instruction selection into a branch sequence. This has to handle all
274// permutations of selection between i32/f32/f64 on ICC and FCC.
275// Expanded after instruction selection.

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310 "; SELECT_CC_DFP_FCC PSEUDO!",
311 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>;
312 def SELECT_CC_QFP_FCC
313 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
314 "; SELECT_CC_QFP_FCC PSEUDO!",
315 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
316}
317
318let rd = 0 in
319 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val),
320 "unimp $val", []>;
321
322// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
323// instruction selection into a branch sequence. This has to handle all
324// permutations of selection between i32/f32/f64 on ICC and FCC.
325// Expanded after instruction selection.

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360 "; SELECT_CC_DFP_FCC PSEUDO!",
361 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>;
362 def SELECT_CC_QFP_FCC
363 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
364 "; SELECT_CC_QFP_FCC PSEUDO!",
365 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
366}
367
368// JMPL Instruction.
369let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in {
370 def JMPLrr: F3_1<2, 0b111000, (outs IntRegs:$dst), (ins MEMrr:$addr),
371 "jmpl $addr, $dst", []>;
372 def JMPLri: F3_2<2, 0b111000, (outs IntRegs:$dst), (ins MEMri:$addr),
373 "jmpl $addr, $dst", []>;
374}
318
319// Section A.3 - Synthetic Instructions, p. 85
320// special cases of JMPL:
375
376// Section A.3 - Synthetic Instructions, p. 85
377// special cases of JMPL:
321let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in {
378let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
379 isCodeGenOnly = 1 in {
322 let rd = 0, rs1 = 15 in
323 def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
324 "jmp %o7+$val", [(retflag simm13:$val)]>;
325
326 let rd = 0, rs1 = 31 in
327 def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
328 "jmp %i7+$val", []>;
329}
330
331// Section B.1 - Load Integer Instructions, p. 90
380 let rd = 0, rs1 = 15 in
381 def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
382 "jmp %o7+$val", [(retflag simm13:$val)]>;
383
384 let rd = 0, rs1 = 31 in
385 def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
386 "jmp %i7+$val", []>;
387}
388
389// Section B.1 - Load Integer Instructions, p. 90
332def LDSBrr : F3_1<3, 0b001001,
333 (outs IntRegs:$dst), (ins MEMrr:$addr),
334 "ldsb [$addr], $dst",
335 [(set i32:$dst, (sextloadi8 ADDRrr:$addr))]>;
336def LDSBri : F3_2<3, 0b001001,
337 (outs IntRegs:$dst), (ins MEMri:$addr),
338 "ldsb [$addr], $dst",
339 [(set i32:$dst, (sextloadi8 ADDRri:$addr))]>;
340def LDSHrr : F3_1<3, 0b001010,
341 (outs IntRegs:$dst), (ins MEMrr:$addr),
342 "ldsh [$addr], $dst",
343 [(set i32:$dst, (sextloadi16 ADDRrr:$addr))]>;
344def LDSHri : F3_2<3, 0b001010,
345 (outs IntRegs:$dst), (ins MEMri:$addr),
346 "ldsh [$addr], $dst",
347 [(set i32:$dst, (sextloadi16 ADDRri:$addr))]>;
348def LDUBrr : F3_1<3, 0b000001,
349 (outs IntRegs:$dst), (ins MEMrr:$addr),
350 "ldub [$addr], $dst",
351 [(set i32:$dst, (zextloadi8 ADDRrr:$addr))]>;
352def LDUBri : F3_2<3, 0b000001,
353 (outs IntRegs:$dst), (ins MEMri:$addr),
354 "ldub [$addr], $dst",
355 [(set i32:$dst, (zextloadi8 ADDRri:$addr))]>;
356def LDUHrr : F3_1<3, 0b000010,
357 (outs IntRegs:$dst), (ins MEMrr:$addr),
358 "lduh [$addr], $dst",
359 [(set i32:$dst, (zextloadi16 ADDRrr:$addr))]>;
360def LDUHri : F3_2<3, 0b000010,
361 (outs IntRegs:$dst), (ins MEMri:$addr),
362 "lduh [$addr], $dst",
363 [(set i32:$dst, (zextloadi16 ADDRri:$addr))]>;
364def LDrr : F3_1<3, 0b000000,
365 (outs IntRegs:$dst), (ins MEMrr:$addr),
366 "ld [$addr], $dst",
367 [(set i32:$dst, (load ADDRrr:$addr))]>;
368def LDri : F3_2<3, 0b000000,
369 (outs IntRegs:$dst), (ins MEMri:$addr),
370 "ld [$addr], $dst",
371 [(set i32:$dst, (load ADDRri:$addr))]>;
390defm LDSB : Load<"ldsb", 0b001001, sextloadi8, IntRegs, i32>;
391defm LDSH : Load<"ldsh", 0b001010, sextloadi16, IntRegs, i32>;
392defm LDUB : Load<"ldub", 0b000001, zextloadi8, IntRegs, i32>;
393defm LDUH : Load<"lduh", 0b000010, zextloadi16, IntRegs, i32>;
394defm LD : Load<"ld", 0b000000, load, IntRegs, i32>;
372
373// Section B.2 - Load Floating-point Instructions, p. 92
395
396// Section B.2 - Load Floating-point Instructions, p. 92
374def LDFrr : F3_1<3, 0b100000,
375 (outs FPRegs:$dst), (ins MEMrr:$addr),
376 "ld [$addr], $dst",
377 [(set f32:$dst, (load ADDRrr:$addr))]>;
378def LDFri : F3_2<3, 0b100000,
379 (outs FPRegs:$dst), (ins MEMri:$addr),
380 "ld [$addr], $dst",
381 [(set f32:$dst, (load ADDRri:$addr))]>;
382def LDDFrr : F3_1<3, 0b100011,
383 (outs DFPRegs:$dst), (ins MEMrr:$addr),
384 "ldd [$addr], $dst",
385 [(set f64:$dst, (load ADDRrr:$addr))]>;
386def LDDFri : F3_2<3, 0b100011,
387 (outs DFPRegs:$dst), (ins MEMri:$addr),
388 "ldd [$addr], $dst",
389 [(set f64:$dst, (load ADDRri:$addr))]>;
390def LDQFrr : F3_1<3, 0b100010,
391 (outs QFPRegs:$dst), (ins MEMrr:$addr),
392 "ldq [$addr], $dst",
393 [(set f128:$dst, (load ADDRrr:$addr))]>,
394 Requires<[HasV9, HasHardQuad]>;
395def LDQFri : F3_2<3, 0b100010,
396 (outs QFPRegs:$dst), (ins MEMri:$addr),
397 "ldq [$addr], $dst",
398 [(set f128:$dst, (load ADDRri:$addr))]>,
399 Requires<[HasV9, HasHardQuad]>;
397defm LDF : Load<"ld", 0b100000, load, FPRegs, f32>;
398defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64>;
399defm LDQF : Load<"ldq", 0b100010, load, QFPRegs, f128>,
400 Requires<[HasV9, HasHardQuad]>;
400
401// Section B.4 - Store Integer Instructions, p. 95
401
402// Section B.4 - Store Integer Instructions, p. 95
402def STBrr : F3_1<3, 0b000101,
403 (outs), (ins MEMrr:$addr, IntRegs:$rd),
404 "stb $rd, [$addr]",
405 [(truncstorei8 i32:$rd, ADDRrr:$addr)]>;
406def STBri : F3_2<3, 0b000101,
407 (outs), (ins MEMri:$addr, IntRegs:$rd),
408 "stb $rd, [$addr]",
409 [(truncstorei8 i32:$rd, ADDRri:$addr)]>;
410def STHrr : F3_1<3, 0b000110,
411 (outs), (ins MEMrr:$addr, IntRegs:$rd),
412 "sth $rd, [$addr]",
413 [(truncstorei16 i32:$rd, ADDRrr:$addr)]>;
414def STHri : F3_2<3, 0b000110,
415 (outs), (ins MEMri:$addr, IntRegs:$rd),
416 "sth $rd, [$addr]",
417 [(truncstorei16 i32:$rd, ADDRri:$addr)]>;
418def STrr : F3_1<3, 0b000100,
419 (outs), (ins MEMrr:$addr, IntRegs:$rd),
420 "st $rd, [$addr]",
421 [(store i32:$rd, ADDRrr:$addr)]>;
422def STri : F3_2<3, 0b000100,
423 (outs), (ins MEMri:$addr, IntRegs:$rd),
424 "st $rd, [$addr]",
425 [(store i32:$rd, ADDRri:$addr)]>;
403defm STB : Store<"stb", 0b000101, truncstorei8, IntRegs, i32>;
404defm STH : Store<"sth", 0b000110, truncstorei16, IntRegs, i32>;
405defm ST : Store<"st", 0b000100, store, IntRegs, i32>;
426
427// Section B.5 - Store Floating-point Instructions, p. 97
406
407// Section B.5 - Store Floating-point Instructions, p. 97
428def STFrr : F3_1<3, 0b100100,
429 (outs), (ins MEMrr:$addr, FPRegs:$rd),
430 "st $rd, [$addr]",
431 [(store f32:$rd, ADDRrr:$addr)]>;
432def STFri : F3_2<3, 0b100100,
433 (outs), (ins MEMri:$addr, FPRegs:$rd),
434 "st $rd, [$addr]",
435 [(store f32:$rd, ADDRri:$addr)]>;
436def STDFrr : F3_1<3, 0b100111,
437 (outs), (ins MEMrr:$addr, DFPRegs:$rd),
438 "std $rd, [$addr]",
439 [(store f64:$rd, ADDRrr:$addr)]>;
440def STDFri : F3_2<3, 0b100111,
441 (outs), (ins MEMri:$addr, DFPRegs:$rd),
442 "std $rd, [$addr]",
443 [(store f64:$rd, ADDRri:$addr)]>;
444def STQFrr : F3_1<3, 0b100110,
445 (outs), (ins MEMrr:$addr, QFPRegs:$rd),
446 "stq $rd, [$addr]",
447 [(store f128:$rd, ADDRrr:$addr)]>,
448 Requires<[HasV9, HasHardQuad]>;
449def STQFri : F3_2<3, 0b100110,
450 (outs), (ins MEMri:$addr, QFPRegs:$rd),
451 "stq $rd, [$addr]",
452 [(store f128:$rd, ADDRri:$addr)]>,
453 Requires<[HasV9, HasHardQuad]>;
408defm STF : Store<"st", 0b100100, store, FPRegs, f32>;
409defm STDF : Store<"std", 0b100111, store, DFPRegs, f64>;
410defm STQF : Store<"stq", 0b100110, store, QFPRegs, f128>,
411 Requires<[HasV9, HasHardQuad]>;
454
455// Section B.9 - SETHI Instruction, p. 104
456def SETHIi: F2_1<0b100,
457 (outs IntRegs:$rd), (ins i32imm:$imm22),
458 "sethi $imm22, $rd",
459 [(set i32:$rd, SETHIimm:$imm22)]>;
460
461// Section B.10 - NOP Instruction, p. 105
462// (It's a special case of SETHI)
463let rd = 0, imm22 = 0 in
464 def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
465
466// Section B.11 - Logical Instructions, p. 106
412
413// Section B.9 - SETHI Instruction, p. 104
414def SETHIi: F2_1<0b100,
415 (outs IntRegs:$rd), (ins i32imm:$imm22),
416 "sethi $imm22, $rd",
417 [(set i32:$rd, SETHIimm:$imm22)]>;
418
419// Section B.10 - NOP Instruction, p. 105
420// (It's a special case of SETHI)
421let rd = 0, imm22 = 0 in
422 def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
423
424// Section B.11 - Logical Instructions, p. 106
467defm AND : F3_12<"and", 0b000001, and>;
425defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, i32imm>;
468
469def ANDNrr : F3_1<2, 0b000101,
426
427def ANDNrr : F3_1<2, 0b000101,
470 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
471 "andn $b, $c, $dst",
472 [(set i32:$dst, (and i32:$b, (not i32:$c)))]>;
428 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
429 "andn $rs1, $rs2, $rd",
430 [(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>;
473def ANDNri : F3_2<2, 0b000101,
431def ANDNri : F3_2<2, 0b000101,
474 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
475 "andn $b, $c, $dst", []>;
432 (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
433 "andn $rs1, $simm13, $rd", []>;
476
434
477defm OR : F3_12<"or", 0b000010, or>;
435defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, i32imm>;
478
479def ORNrr : F3_1<2, 0b000110,
436
437def ORNrr : F3_1<2, 0b000110,
480 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
481 "orn $b, $c, $dst",
482 [(set i32:$dst, (or i32:$b, (not i32:$c)))]>;
438 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
439 "orn $rs1, $rs2, $rd",
440 [(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>;
483def ORNri : F3_2<2, 0b000110,
441def ORNri : F3_2<2, 0b000110,
484 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
485 "orn $b, $c, $dst", []>;
486defm XOR : F3_12<"xor", 0b000011, xor>;
442 (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
443 "orn $rs1, $simm13, $rd", []>;
444defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, i32imm>;
487
488def XNORrr : F3_1<2, 0b000111,
445
446def XNORrr : F3_1<2, 0b000111,
489 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
490 "xnor $b, $c, $dst",
491 [(set i32:$dst, (not (xor i32:$b, i32:$c)))]>;
447 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
448 "xnor $rs1, $rs2, $rd",
449 [(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>;
492def XNORri : F3_2<2, 0b000111,
450def XNORri : F3_2<2, 0b000111,
493 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
494 "xnor $b, $c, $dst", []>;
451 (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
452 "xnor $rs1, $simm13, $rd", []>;
495
496// Section B.12 - Shift Instructions, p. 107
453
454// Section B.12 - Shift Instructions, p. 107
497defm SLL : F3_12<"sll", 0b100101, shl>;
498defm SRL : F3_12<"srl", 0b100110, srl>;
499defm SRA : F3_12<"sra", 0b100111, sra>;
455defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, i32imm>;
456defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, i32imm>;
457defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, i32imm>;
500
501// Section B.13 - Add Instructions, p. 108
458
459// Section B.13 - Add Instructions, p. 108
502defm ADD : F3_12<"add", 0b000000, add>;
460defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, i32imm>;
503
504// "LEA" forms of add (patterns to make tblgen happy)
461
462// "LEA" forms of add (patterns to make tblgen happy)
505let Predicates = [Is32Bit] in
463let Predicates = [Is32Bit], isCodeGenOnly = 1 in
506 def LEA_ADDri : F3_2<2, 0b000000,
507 (outs IntRegs:$dst), (ins MEMri:$addr),
508 "add ${addr:arith}, $dst",
509 [(set iPTR:$dst, ADDRri:$addr)]>;
510
511let Defs = [ICC] in
464 def LEA_ADDri : F3_2<2, 0b000000,
465 (outs IntRegs:$dst), (ins MEMri:$addr),
466 "add ${addr:arith}, $dst",
467 [(set iPTR:$dst, ADDRri:$addr)]>;
468
469let Defs = [ICC] in
512 defm ADDCC : F3_12<"addcc", 0b010000, addc>;
470 defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, i32imm>;
513
514let Uses = [ICC], Defs = [ICC] in
471
472let Uses = [ICC], Defs = [ICC] in
515 defm ADDX : F3_12<"addxcc", 0b011000, adde>;
473 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, i32imm>;
516
517// Section B.15 - Subtract Instructions, p. 110
474
475// Section B.15 - Subtract Instructions, p. 110
518defm SUB : F3_12 <"sub" , 0b000100, sub>;
476defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, i32imm>;
519let Uses = [ICC], Defs = [ICC] in
477let Uses = [ICC], Defs = [ICC] in
520 defm SUBX : F3_12 <"subxcc" , 0b011100, sube>;
478 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, i32imm>;
521
522let Defs = [ICC] in
479
480let Defs = [ICC] in
523 defm SUBCC : F3_12 <"subcc", 0b010100, subc>;
481 defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, i32imm>;
524
525let Defs = [ICC], rd = 0 in {
526 def CMPrr : F3_1<2, 0b010100,
482
483let Defs = [ICC], rd = 0 in {
484 def CMPrr : F3_1<2, 0b010100,
527 (outs), (ins IntRegs:$b, IntRegs:$c),
528 "cmp $b, $c",
529 [(SPcmpicc i32:$b, i32:$c)]>;
485 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
486 "cmp $rs1, $rs2",
487 [(SPcmpicc i32:$rs1, i32:$rs2)]>;
530 def CMPri : F3_2<2, 0b010100,
488 def CMPri : F3_2<2, 0b010100,
531 (outs), (ins IntRegs:$b, i32imm:$c),
532 "cmp $b, $c",
533 [(SPcmpicc i32:$b, (i32 simm13:$c))]>;
489 (outs), (ins IntRegs:$rs1, i32imm:$simm13),
490 "cmp $rs1, $simm13",
491 [(SPcmpicc i32:$rs1, (i32 simm13:$simm13))]>;
534}
535
492}
493
536let Uses = [ICC], Defs = [ICC] in
537 def SUBXCCrr: F3_1<2, 0b011100,
538 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
539 "subxcc $b, $c, $dst", []>;
540
541
542// Section B.18 - Multiply Instructions, p. 113
543let Defs = [Y] in {
544 defm UMUL : F3_12np<"umul", 0b001010>;
494// Section B.18 - Multiply Instructions, p. 113
495let Defs = [Y] in {
496 defm UMUL : F3_12np<"umul", 0b001010>;
545 defm SMUL : F3_12 <"smul", 0b001011, mul>;
497 defm SMUL : F3_12 <"smul", 0b001011, mul, IntRegs, i32, i32imm>;
546}
547
548// Section B.19 - Divide Instructions, p. 115
549let Defs = [Y] in {
550 defm UDIV : F3_12np<"udiv", 0b001110>;
551 defm SDIV : F3_12np<"sdiv", 0b001111>;
552}
553

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573class BranchSP<dag ins, string asmstr, list<dag> pattern>
574 : F2_2<0b010, (outs), ins, asmstr, pattern> {
575 let isBranch = 1;
576 let isTerminator = 1;
577 let hasDelaySlot = 1;
578}
579
580// Indirect branch instructions.
498}
499
500// Section B.19 - Divide Instructions, p. 115
501let Defs = [Y] in {
502 defm UDIV : F3_12np<"udiv", 0b001110>;
503 defm SDIV : F3_12np<"sdiv", 0b001111>;
504}
505

--- 19 unchanged lines hidden (view full) ---

525class BranchSP<dag ins, string asmstr, list<dag> pattern>
526 : F2_2<0b010, (outs), ins, asmstr, pattern> {
527 let isBranch = 1;
528 let isTerminator = 1;
529 let hasDelaySlot = 1;
530}
531
532// Indirect branch instructions.
581let isTerminator = 1, isBarrier = 1,
582 hasDelaySlot = 1, isBranch =1,
583 isIndirectBranch = 1, rd = 0 in {
533let isTerminator = 1, isBarrier = 1, hasDelaySlot = 1, isBranch =1,
534 isIndirectBranch = 1, rd = 0, isCodeGenOnly = 1 in {
584 def BINDrr : F3_1<2, 0b111000,
585 (outs), (ins MEMrr:$ptr),
586 "jmp $ptr",
587 [(brind ADDRrr:$ptr)]>;
588 def BINDri : F3_2<2, 0b111000,
589 (outs), (ins MEMri:$ptr),
590 "jmp $ptr",
591 [(brind ADDRri:$ptr)]>;

--- 26 unchanged lines hidden (view full) ---

618 hasDelaySlot = 1, isCall = 1 in {
619 def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops),
620 "call $dst", []> {
621 bits<30> disp;
622 let op = 1;
623 let Inst{29-0} = disp;
624 }
625
535 def BINDrr : F3_1<2, 0b111000,
536 (outs), (ins MEMrr:$ptr),
537 "jmp $ptr",
538 [(brind ADDRrr:$ptr)]>;
539 def BINDri : F3_2<2, 0b111000,
540 (outs), (ins MEMri:$ptr),
541 "jmp $ptr",
542 [(brind ADDRri:$ptr)]>;

--- 26 unchanged lines hidden (view full) ---

569 hasDelaySlot = 1, isCall = 1 in {
570 def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops),
571 "call $dst", []> {
572 bits<30> disp;
573 let op = 1;
574 let Inst{29-0} = disp;
575 }
576
626 // indirect calls
627 def JMPLrr : F3_1<2, 0b111000,
628 (outs), (ins MEMrr:$ptr, variable_ops),
629 "call $ptr",
630 [(call ADDRrr:$ptr)]> { let rd = 15; }
631 def JMPLri : F3_2<2, 0b111000,
632 (outs), (ins MEMri:$ptr, variable_ops),
633 "call $ptr",
634 [(call ADDRri:$ptr)]> { let rd = 15; }
577 // indirect calls: special cases of JMPL.
578 let isCodeGenOnly = 1, rd = 15 in {
579 def CALLrr : F3_1<2, 0b111000,
580 (outs), (ins MEMrr:$ptr, variable_ops),
581 "call $ptr",
582 [(call ADDRrr:$ptr)]>;
583 def CALLri : F3_2<2, 0b111000,
584 (outs), (ins MEMri:$ptr, variable_ops),
585 "call $ptr",
586 [(call ADDRri:$ptr)]>;
587 }
635}
636
637// Section B.28 - Read State Register Instructions
638let Uses = [Y], rs1 = 0, rs2 = 0 in
639 def RDY : F3_1<2, 0b101000,
640 (outs IntRegs:$dst), (ins),
641 "rd %y, $dst", []>;
642
643// Section B.29 - Write State Register Instructions
644let Defs = [Y], rd = 0 in {
645 def WRYrr : F3_1<2, 0b110000,
646 (outs), (ins IntRegs:$b, IntRegs:$c),
647 "wr $b, $c, %y", []>;
648 def WRYri : F3_2<2, 0b110000,
649 (outs), (ins IntRegs:$b, i32imm:$c),
650 "wr $b, $c, %y", []>;
651}
652// Convert Integer to Floating-point Instructions, p. 141
653def FITOS : F3_3u<2, 0b110100, 0b011000100,
588}
589
590// Section B.28 - Read State Register Instructions
591let Uses = [Y], rs1 = 0, rs2 = 0 in
592 def RDY : F3_1<2, 0b101000,
593 (outs IntRegs:$dst), (ins),
594 "rd %y, $dst", []>;
595
596// Section B.29 - Write State Register Instructions
597let Defs = [Y], rd = 0 in {
598 def WRYrr : F3_1<2, 0b110000,
599 (outs), (ins IntRegs:$b, IntRegs:$c),
600 "wr $b, $c, %y", []>;
601 def WRYri : F3_2<2, 0b110000,
602 (outs), (ins IntRegs:$b, i32imm:$c),
603 "wr $b, $c, %y", []>;
604}
605// Convert Integer to Floating-point Instructions, p. 141
606def FITOS : F3_3u<2, 0b110100, 0b011000100,
654 (outs FPRegs:$dst), (ins FPRegs:$src),
655 "fitos $src, $dst",
656 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>;
607 (outs FPRegs:$rd), (ins FPRegs:$rs2),
608 "fitos $rs2, $rd",
609 [(set FPRegs:$rd, (SPitof FPRegs:$rs2))]>;
657def FITOD : F3_3u<2, 0b110100, 0b011001000,
610def FITOD : F3_3u<2, 0b110100, 0b011001000,
658 (outs DFPRegs:$dst), (ins FPRegs:$src),
659 "fitod $src, $dst",
660 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>;
611 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
612 "fitod $rs2, $rd",
613 [(set DFPRegs:$rd, (SPitof FPRegs:$rs2))]>;
661def FITOQ : F3_3u<2, 0b110100, 0b011001100,
614def FITOQ : F3_3u<2, 0b110100, 0b011001100,
662 (outs QFPRegs:$dst), (ins FPRegs:$src),
663 "fitoq $src, $dst",
664 [(set QFPRegs:$dst, (SPitof FPRegs:$src))]>,
615 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
616 "fitoq $rs2, $rd",
617 [(set QFPRegs:$rd, (SPitof FPRegs:$rs2))]>,
665 Requires<[HasHardQuad]>;
666
667// Convert Floating-point to Integer Instructions, p. 142
668def FSTOI : F3_3u<2, 0b110100, 0b011010001,
618 Requires<[HasHardQuad]>;
619
620// Convert Floating-point to Integer Instructions, p. 142
621def FSTOI : F3_3u<2, 0b110100, 0b011010001,
669 (outs FPRegs:$dst), (ins FPRegs:$src),
670 "fstoi $src, $dst",
671 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>;
622 (outs FPRegs:$rd), (ins FPRegs:$rs2),
623 "fstoi $rs2, $rd",
624 [(set FPRegs:$rd, (SPftoi FPRegs:$rs2))]>;
672def FDTOI : F3_3u<2, 0b110100, 0b011010010,
625def FDTOI : F3_3u<2, 0b110100, 0b011010010,
673 (outs FPRegs:$dst), (ins DFPRegs:$src),
674 "fdtoi $src, $dst",
675 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>;
626 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
627 "fdtoi $rs2, $rd",
628 [(set FPRegs:$rd, (SPftoi DFPRegs:$rs2))]>;
676def FQTOI : F3_3u<2, 0b110100, 0b011010011,
629def FQTOI : F3_3u<2, 0b110100, 0b011010011,
677 (outs FPRegs:$dst), (ins QFPRegs:$src),
678 "fqtoi $src, $dst",
679 [(set FPRegs:$dst, (SPftoi QFPRegs:$src))]>,
630 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
631 "fqtoi $rs2, $rd",
632 [(set FPRegs:$rd, (SPftoi QFPRegs:$rs2))]>,
680 Requires<[HasHardQuad]>;
681
682// Convert between Floating-point Formats Instructions, p. 143
683def FSTOD : F3_3u<2, 0b110100, 0b011001001,
633 Requires<[HasHardQuad]>;
634
635// Convert between Floating-point Formats Instructions, p. 143
636def FSTOD : F3_3u<2, 0b110100, 0b011001001,
684 (outs DFPRegs:$dst), (ins FPRegs:$src),
685 "fstod $src, $dst",
686 [(set f64:$dst, (fextend f32:$src))]>;
637 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
638 "fstod $rs2, $rd",
639 [(set f64:$rd, (fextend f32:$rs2))]>;
687def FSTOQ : F3_3u<2, 0b110100, 0b011001101,
640def FSTOQ : F3_3u<2, 0b110100, 0b011001101,
688 (outs QFPRegs:$dst), (ins FPRegs:$src),
689 "fstoq $src, $dst",
690 [(set f128:$dst, (fextend f32:$src))]>,
641 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
642 "fstoq $rs2, $rd",
643 [(set f128:$rd, (fextend f32:$rs2))]>,
691 Requires<[HasHardQuad]>;
692def FDTOS : F3_3u<2, 0b110100, 0b011000110,
644 Requires<[HasHardQuad]>;
645def FDTOS : F3_3u<2, 0b110100, 0b011000110,
693 (outs FPRegs:$dst), (ins DFPRegs:$src),
694 "fdtos $src, $dst",
695 [(set f32:$dst, (fround f64:$src))]>;
696def FDTOQ : F3_3u<2, 0b110100, 0b01101110,
697 (outs QFPRegs:$dst), (ins DFPRegs:$src),
698 "fdtoq $src, $dst",
699 [(set f128:$dst, (fextend f64:$src))]>,
646 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
647 "fdtos $rs2, $rd",
648 [(set f32:$rd, (fround f64:$rs2))]>;
649def FDTOQ : F3_3u<2, 0b110100, 0b011001110,
650 (outs QFPRegs:$rd), (ins DFPRegs:$rs2),
651 "fdtoq $rs2, $rd",
652 [(set f128:$rd, (fextend f64:$rs2))]>,
700 Requires<[HasHardQuad]>;
701def FQTOS : F3_3u<2, 0b110100, 0b011000111,
653 Requires<[HasHardQuad]>;
654def FQTOS : F3_3u<2, 0b110100, 0b011000111,
702 (outs FPRegs:$dst), (ins QFPRegs:$src),
703 "fqtos $src, $dst",
704 [(set f32:$dst, (fround f128:$src))]>,
655 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
656 "fqtos $rs2, $rd",
657 [(set f32:$rd, (fround f128:$rs2))]>,
705 Requires<[HasHardQuad]>;
706def FQTOD : F3_3u<2, 0b110100, 0b011001011,
658 Requires<[HasHardQuad]>;
659def FQTOD : F3_3u<2, 0b110100, 0b011001011,
707 (outs DFPRegs:$dst), (ins QFPRegs:$src),
708 "fqtod $src, $dst",
709 [(set f64:$dst, (fround f128:$src))]>,
660 (outs DFPRegs:$rd), (ins QFPRegs:$rs2),
661 "fqtod $rs2, $rd",
662 [(set f64:$rd, (fround f128:$rs2))]>,
710 Requires<[HasHardQuad]>;
711
712// Floating-point Move Instructions, p. 144
713def FMOVS : F3_3u<2, 0b110100, 0b000000001,
663 Requires<[HasHardQuad]>;
664
665// Floating-point Move Instructions, p. 144
666def FMOVS : F3_3u<2, 0b110100, 0b000000001,
714 (outs FPRegs:$dst), (ins FPRegs:$src),
715 "fmovs $src, $dst", []>;
667 (outs FPRegs:$rd), (ins FPRegs:$rs2),
668 "fmovs $rs2, $rd", []>;
716def FNEGS : F3_3u<2, 0b110100, 0b000000101,
669def FNEGS : F3_3u<2, 0b110100, 0b000000101,
717 (outs FPRegs:$dst), (ins FPRegs:$src),
718 "fnegs $src, $dst",
719 [(set f32:$dst, (fneg f32:$src))]>;
670 (outs FPRegs:$rd), (ins FPRegs:$rs2),
671 "fnegs $rs2, $rd",
672 [(set f32:$rd, (fneg f32:$rs2))]>;
720def FABSS : F3_3u<2, 0b110100, 0b000001001,
673def FABSS : F3_3u<2, 0b110100, 0b000001001,
721 (outs FPRegs:$dst), (ins FPRegs:$src),
722 "fabss $src, $dst",
723 [(set f32:$dst, (fabs f32:$src))]>;
674 (outs FPRegs:$rd), (ins FPRegs:$rs2),
675 "fabss $rs2, $rd",
676 [(set f32:$rd, (fabs f32:$rs2))]>;
724
725
726// Floating-point Square Root Instructions, p.145
727def FSQRTS : F3_3u<2, 0b110100, 0b000101001,
677
678
679// Floating-point Square Root Instructions, p.145
680def FSQRTS : F3_3u<2, 0b110100, 0b000101001,
728 (outs FPRegs:$dst), (ins FPRegs:$src),
729 "fsqrts $src, $dst",
730 [(set f32:$dst, (fsqrt f32:$src))]>;
681 (outs FPRegs:$rd), (ins FPRegs:$rs2),
682 "fsqrts $rs2, $rd",
683 [(set f32:$rd, (fsqrt f32:$rs2))]>;
731def FSQRTD : F3_3u<2, 0b110100, 0b000101010,
684def FSQRTD : F3_3u<2, 0b110100, 0b000101010,
732 (outs DFPRegs:$dst), (ins DFPRegs:$src),
733 "fsqrtd $src, $dst",
734 [(set f64:$dst, (fsqrt f64:$src))]>;
685 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
686 "fsqrtd $rs2, $rd",
687 [(set f64:$rd, (fsqrt f64:$rs2))]>;
735def FSQRTQ : F3_3u<2, 0b110100, 0b000101011,
688def FSQRTQ : F3_3u<2, 0b110100, 0b000101011,
736 (outs QFPRegs:$dst), (ins QFPRegs:$src),
737 "fsqrtq $src, $dst",
738 [(set f128:$dst, (fsqrt f128:$src))]>,
689 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
690 "fsqrtq $rs2, $rd",
691 [(set f128:$rd, (fsqrt f128:$rs2))]>,
739 Requires<[HasHardQuad]>;
740
741
742
743// Floating-point Add and Subtract Instructions, p. 146
744def FADDS : F3_3<2, 0b110100, 0b001000001,
692 Requires<[HasHardQuad]>;
693
694
695
696// Floating-point Add and Subtract Instructions, p. 146
697def FADDS : F3_3<2, 0b110100, 0b001000001,
745 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
746 "fadds $src1, $src2, $dst",
747 [(set f32:$dst, (fadd f32:$src1, f32:$src2))]>;
698 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
699 "fadds $rs1, $rs2, $rd",
700 [(set f32:$rd, (fadd f32:$rs1, f32:$rs2))]>;
748def FADDD : F3_3<2, 0b110100, 0b001000010,
701def FADDD : F3_3<2, 0b110100, 0b001000010,
749 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
750 "faddd $src1, $src2, $dst",
751 [(set f64:$dst, (fadd f64:$src1, f64:$src2))]>;
702 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
703 "faddd $rs1, $rs2, $rd",
704 [(set f64:$rd, (fadd f64:$rs1, f64:$rs2))]>;
752def FADDQ : F3_3<2, 0b110100, 0b001000011,
705def FADDQ : F3_3<2, 0b110100, 0b001000011,
753 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
754 "faddq $src1, $src2, $dst",
755 [(set f128:$dst, (fadd f128:$src1, f128:$src2))]>,
706 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
707 "faddq $rs1, $rs2, $rd",
708 [(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>,
756 Requires<[HasHardQuad]>;
757
758def FSUBS : F3_3<2, 0b110100, 0b001000101,
709 Requires<[HasHardQuad]>;
710
711def FSUBS : F3_3<2, 0b110100, 0b001000101,
759 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
760 "fsubs $src1, $src2, $dst",
761 [(set f32:$dst, (fsub f32:$src1, f32:$src2))]>;
712 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
713 "fsubs $rs1, $rs2, $rd",
714 [(set f32:$rd, (fsub f32:$rs1, f32:$rs2))]>;
762def FSUBD : F3_3<2, 0b110100, 0b001000110,
715def FSUBD : F3_3<2, 0b110100, 0b001000110,
763 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
764 "fsubd $src1, $src2, $dst",
765 [(set f64:$dst, (fsub f64:$src1, f64:$src2))]>;
716 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
717 "fsubd $rs1, $rs2, $rd",
718 [(set f64:$rd, (fsub f64:$rs1, f64:$rs2))]>;
766def FSUBQ : F3_3<2, 0b110100, 0b001000111,
719def FSUBQ : F3_3<2, 0b110100, 0b001000111,
767 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
768 "fsubq $src1, $src2, $dst",
769 [(set f128:$dst, (fsub f128:$src1, f128:$src2))]>,
720 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
721 "fsubq $rs1, $rs2, $rd",
722 [(set f128:$rd, (fsub f128:$rs1, f128:$rs2))]>,
770 Requires<[HasHardQuad]>;
771
772
773// Floating-point Multiply and Divide Instructions, p. 147
774def FMULS : F3_3<2, 0b110100, 0b001001001,
723 Requires<[HasHardQuad]>;
724
725
726// Floating-point Multiply and Divide Instructions, p. 147
727def FMULS : F3_3<2, 0b110100, 0b001001001,
775 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
776 "fmuls $src1, $src2, $dst",
777 [(set f32:$dst, (fmul f32:$src1, f32:$src2))]>;
728 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
729 "fmuls $rs1, $rs2, $rd",
730 [(set f32:$rd, (fmul f32:$rs1, f32:$rs2))]>;
778def FMULD : F3_3<2, 0b110100, 0b001001010,
731def FMULD : F3_3<2, 0b110100, 0b001001010,
779 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
780 "fmuld $src1, $src2, $dst",
781 [(set f64:$dst, (fmul f64:$src1, f64:$src2))]>;
732 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
733 "fmuld $rs1, $rs2, $rd",
734 [(set f64:$rd, (fmul f64:$rs1, f64:$rs2))]>;
782def FMULQ : F3_3<2, 0b110100, 0b001001011,
735def FMULQ : F3_3<2, 0b110100, 0b001001011,
783 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
784 "fmulq $src1, $src2, $dst",
785 [(set f128:$dst, (fmul f128:$src1, f128:$src2))]>,
736 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
737 "fmulq $rs1, $rs2, $rd",
738 [(set f128:$rd, (fmul f128:$rs1, f128:$rs2))]>,
786 Requires<[HasHardQuad]>;
787
788def FSMULD : F3_3<2, 0b110100, 0b001101001,
739 Requires<[HasHardQuad]>;
740
741def FSMULD : F3_3<2, 0b110100, 0b001101001,
789 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
790 "fsmuld $src1, $src2, $dst",
791 [(set f64:$dst, (fmul (fextend f32:$src1),
792 (fextend f32:$src2)))]>;
742 (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
743 "fsmuld $rs1, $rs2, $rd",
744 [(set f64:$rd, (fmul (fextend f32:$rs1),
745 (fextend f32:$rs2)))]>;
793def FDMULQ : F3_3<2, 0b110100, 0b001101110,
746def FDMULQ : F3_3<2, 0b110100, 0b001101110,
794 (outs QFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
795 "fdmulq $src1, $src2, $dst",
796 [(set f128:$dst, (fmul (fextend f64:$src1),
797 (fextend f64:$src2)))]>,
747 (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
748 "fdmulq $rs1, $rs2, $rd",
749 [(set f128:$rd, (fmul (fextend f64:$rs1),
750 (fextend f64:$rs2)))]>,
798 Requires<[HasHardQuad]>;
799
800def FDIVS : F3_3<2, 0b110100, 0b001001101,
751 Requires<[HasHardQuad]>;
752
753def FDIVS : F3_3<2, 0b110100, 0b001001101,
801 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
802 "fdivs $src1, $src2, $dst",
803 [(set f32:$dst, (fdiv f32:$src1, f32:$src2))]>;
754 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
755 "fdivs $rs1, $rs2, $rd",
756 [(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))]>;
804def FDIVD : F3_3<2, 0b110100, 0b001001110,
757def FDIVD : F3_3<2, 0b110100, 0b001001110,
805 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
806 "fdivd $src1, $src2, $dst",
807 [(set f64:$dst, (fdiv f64:$src1, f64:$src2))]>;
758 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
759 "fdivd $rs1, $rs2, $rd",
760 [(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))]>;
808def FDIVQ : F3_3<2, 0b110100, 0b001001111,
761def FDIVQ : F3_3<2, 0b110100, 0b001001111,
809 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
810 "fdivq $src1, $src2, $dst",
811 [(set f128:$dst, (fdiv f128:$src1, f128:$src2))]>,
762 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
763 "fdivq $rs1, $rs2, $rd",
764 [(set f128:$rd, (fdiv f128:$rs1, f128:$rs2))]>,
812 Requires<[HasHardQuad]>;
813
814// Floating-point Compare Instructions, p. 148
815// Note: the 2nd template arg is different for these guys.
816// Note 2: the result of a FCMP is not available until the 2nd cycle
817// after the instr is retired, but there is no interlock in Sparc V8.
818// This behavior is modeled with a forced noop after the instruction in
819// DelaySlotFiller.
820
821let Defs = [FCC] in {
822 def FCMPS : F3_3c<2, 0b110101, 0b001010001,
765 Requires<[HasHardQuad]>;
766
767// Floating-point Compare Instructions, p. 148
768// Note: the 2nd template arg is different for these guys.
769// Note 2: the result of a FCMP is not available until the 2nd cycle
770// after the instr is retired, but there is no interlock in Sparc V8.
771// This behavior is modeled with a forced noop after the instruction in
772// DelaySlotFiller.
773
774let Defs = [FCC] in {
775 def FCMPS : F3_3c<2, 0b110101, 0b001010001,
823 (outs), (ins FPRegs:$src1, FPRegs:$src2),
824 "fcmps $src1, $src2",
825 [(SPcmpfcc f32:$src1, f32:$src2)]>;
776 (outs), (ins FPRegs:$rs1, FPRegs:$rs2),
777 "fcmps $rs1, $rs2",
778 [(SPcmpfcc f32:$rs1, f32:$rs2)]>;
826 def FCMPD : F3_3c<2, 0b110101, 0b001010010,
779 def FCMPD : F3_3c<2, 0b110101, 0b001010010,
827 (outs), (ins DFPRegs:$src1, DFPRegs:$src2),
828 "fcmpd $src1, $src2",
829 [(SPcmpfcc f64:$src1, f64:$src2)]>;
780 (outs), (ins DFPRegs:$rs1, DFPRegs:$rs2),
781 "fcmpd $rs1, $rs2",
782 [(SPcmpfcc f64:$rs1, f64:$rs2)]>;
830 def FCMPQ : F3_3c<2, 0b110101, 0b001010011,
783 def FCMPQ : F3_3c<2, 0b110101, 0b001010011,
831 (outs), (ins QFPRegs:$src1, QFPRegs:$src2),
832 "fcmpq $src1, $src2",
833 [(SPcmpfcc f128:$src1, f128:$src2)]>,
784 (outs), (ins QFPRegs:$rs1, QFPRegs:$rs2),
785 "fcmpq $rs1, $rs2",
786 [(SPcmpfcc f128:$rs1, f128:$rs2)]>,
834 Requires<[HasHardQuad]>;
835}
836
837//===----------------------------------------------------------------------===//
838// Instructions for Thread Local Storage(TLS).
839//===----------------------------------------------------------------------===//
787 Requires<[HasHardQuad]>;
788}
789
790//===----------------------------------------------------------------------===//
791// Instructions for Thread Local Storage(TLS).
792//===----------------------------------------------------------------------===//
840
793let isCodeGenOnly = 1, isAsmParserOnly = 1 in {
841def TLS_ADDrr : F3_1<2, 0b000000,
842 (outs IntRegs:$rd),
843 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym),
844 "add $rs1, $rs2, $rd, $sym",
845 [(set i32:$rd,
846 (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>;
847
848let mayLoad = 1 in

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856 def TLS_CALL : InstSP<(outs),
857 (ins calltarget:$disp, TLSSym:$sym, variable_ops),
858 "call $disp, $sym",
859 [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)]> {
860 bits<30> disp;
861 let op = 1;
862 let Inst{29-0} = disp;
863}
794def TLS_ADDrr : F3_1<2, 0b000000,
795 (outs IntRegs:$rd),
796 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym),
797 "add $rs1, $rs2, $rd, $sym",
798 [(set i32:$rd,
799 (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>;
800
801let mayLoad = 1 in

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809 def TLS_CALL : InstSP<(outs),
810 (ins calltarget:$disp, TLSSym:$sym, variable_ops),
811 "call $disp, $sym",
812 [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)]> {
813 bits<30> disp;
814 let op = 1;
815 let Inst{29-0} = disp;
816}
817}
864
865//===----------------------------------------------------------------------===//
866// V9 Instructions
867//===----------------------------------------------------------------------===//
868
869// V9 Conditional Moves.
870let Predicates = [HasV9], Constraints = "$f = $rd" in {
871 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.

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907 def FMOVD_ICC
908 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
909 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
910 "fmovd$cond %icc, $rs2, $rd",
911 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>;
912 def FMOVQ_ICC
913 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
914 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
818
819//===----------------------------------------------------------------------===//
820// V9 Instructions
821//===----------------------------------------------------------------------===//
822
823// V9 Conditional Moves.
824let Predicates = [HasV9], Constraints = "$f = $rd" in {
825 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.

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861 def FMOVD_ICC
862 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
863 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
864 "fmovd$cond %icc, $rs2, $rd",
865 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>;
866 def FMOVQ_ICC
867 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
868 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
915 "fmovd$cond %icc, $rs2, $rd",
916 [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>;
869 "fmovq$cond %icc, $rs2, $rd",
870 [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>,
871 Requires<[HasHardQuad]>;
917 }
918
919 let Uses = [FCC], opf_cc = 0b000 in {
920 def FMOVS_FCC
921 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
922 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
923 "fmovs$cond %fcc0, $rs2, $rd",
924 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>;
925 def FMOVD_FCC
926 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
927 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
928 "fmovd$cond %fcc0, $rs2, $rd",
929 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>;
930 def FMOVQ_FCC
931 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
932 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
872 }
873
874 let Uses = [FCC], opf_cc = 0b000 in {
875 def FMOVS_FCC
876 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
877 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
878 "fmovs$cond %fcc0, $rs2, $rd",
879 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>;
880 def FMOVD_FCC
881 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
882 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
883 "fmovd$cond %fcc0, $rs2, $rd",
884 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>;
885 def FMOVQ_FCC
886 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
887 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
933 "fmovd$cond %fcc0, $rs2, $rd",
934 [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>;
888 "fmovq$cond %fcc0, $rs2, $rd",
889 [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>,
890 Requires<[HasHardQuad]>;
935 }
936
937}
938
939// Floating-Point Move Instructions, p. 164 of the V9 manual.
940let Predicates = [HasV9] in {
941 def FMOVD : F3_3u<2, 0b110100, 0b000000010,
891 }
892
893}
894
895// Floating-Point Move Instructions, p. 164 of the V9 manual.
896let Predicates = [HasV9] in {
897 def FMOVD : F3_3u<2, 0b110100, 0b000000010,
942 (outs DFPRegs:$dst), (ins DFPRegs:$src),
943 "fmovd $src, $dst", []>;
898 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
899 "fmovd $rs2, $rd", []>;
944 def FMOVQ : F3_3u<2, 0b110100, 0b000000011,
900 def FMOVQ : F3_3u<2, 0b110100, 0b000000011,
945 (outs QFPRegs:$dst), (ins QFPRegs:$src),
946 "fmovq $src, $dst", []>,
901 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
902 "fmovq $rs2, $rd", []>,
947 Requires<[HasHardQuad]>;
948 def FNEGD : F3_3u<2, 0b110100, 0b000000110,
903 Requires<[HasHardQuad]>;
904 def FNEGD : F3_3u<2, 0b110100, 0b000000110,
949 (outs DFPRegs:$dst), (ins DFPRegs:$src),
950 "fnegd $src, $dst",
951 [(set f64:$dst, (fneg f64:$src))]>;
905 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
906 "fnegd $rs2, $rd",
907 [(set f64:$rd, (fneg f64:$rs2))]>;
952 def FNEGQ : F3_3u<2, 0b110100, 0b000000111,
908 def FNEGQ : F3_3u<2, 0b110100, 0b000000111,
953 (outs QFPRegs:$dst), (ins QFPRegs:$src),
954 "fnegq $src, $dst",
955 [(set f128:$dst, (fneg f128:$src))]>,
909 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
910 "fnegq $rs2, $rd",
911 [(set f128:$rd, (fneg f128:$rs2))]>,
956 Requires<[HasHardQuad]>;
957 def FABSD : F3_3u<2, 0b110100, 0b000001010,
912 Requires<[HasHardQuad]>;
913 def FABSD : F3_3u<2, 0b110100, 0b000001010,
958 (outs DFPRegs:$dst), (ins DFPRegs:$src),
959 "fabsd $src, $dst",
960 [(set f64:$dst, (fabs f64:$src))]>;
914 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
915 "fabsd $rs2, $rd",
916 [(set f64:$rd, (fabs f64:$rs2))]>;
961 def FABSQ : F3_3u<2, 0b110100, 0b000001011,
917 def FABSQ : F3_3u<2, 0b110100, 0b000001011,
962 (outs QFPRegs:$dst), (ins QFPRegs:$src),
963 "fabsq $src, $dst",
964 [(set f128:$dst, (fabs f128:$src))]>,
918 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
919 "fabsq $rs2, $rd",
920 [(set f128:$rd, (fabs f128:$rs2))]>,
965 Requires<[HasHardQuad]>;
966}
967
968// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
921 Requires<[HasHardQuad]>;
922}
923
924// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
969// the top 32-bits before using it. To do this clearing, we use a SLLri X,0.
925// the top 32-bits before using it. To do this clearing, we use a SRLri X,0.
970let rs1 = 0 in
971 def POPCrr : F3_1<2, 0b101110,
972 (outs IntRegs:$dst), (ins IntRegs:$src),
973 "popc $src, $dst", []>, Requires<[HasV9]>;
974def : Pat<(ctpop i32:$src),
926let rs1 = 0 in
927 def POPCrr : F3_1<2, 0b101110,
928 (outs IntRegs:$dst), (ins IntRegs:$src),
929 "popc $src, $dst", []>, Requires<[HasV9]>;
930def : Pat<(ctpop i32:$src),
975 (POPCrr (SLLri $src, 0))>;
931 (POPCrr (SRLri $src, 0))>;
976
932
933// Atomic swap.
934let hasSideEffects =1, rd = 0, rs1 = 0b01111, rs2 = 0 in
935 def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>;
936
937let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
938 def MEMBARi : F3_2<2, 0b101000, (outs), (ins i32imm:$simm13),
939 "membar $simm13", []>;
940
941let Constraints = "$val = $dst" in {
942 def SWAPrr : F3_1<3, 0b001111,
943 (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val),
944 "swap [$addr], $dst",
945 [(set i32:$dst, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>;
946 def SWAPri : F3_2<3, 0b001111,
947 (outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val),
948 "swap [$addr], $dst",
949 [(set i32:$dst, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
950}
951
952let Predicates = [HasV9], Constraints = "$swap = $rd" in
953 def CASrr: F3_1_asi<3, 0b111100, 0b10000000,
954 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
955 IntRegs:$swap),
956 "cas [$rs1], $rs2, $rd",
957 [(set i32:$rd,
958 (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>;
959
977//===----------------------------------------------------------------------===//
978// Non-Instruction Patterns
979//===----------------------------------------------------------------------===//
980
981// Small immediates.
982def : Pat<(i32 simm13:$val),
983 (ORri (i32 G0), imm:$val)>;
984// Arbitrary immediates.
985def : Pat<(i32 imm:$val),
986 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
987
988
989// Global addresses, constant pool entries
960//===----------------------------------------------------------------------===//
961// Non-Instruction Patterns
962//===----------------------------------------------------------------------===//
963
964// Small immediates.
965def : Pat<(i32 simm13:$val),
966 (ORri (i32 G0), imm:$val)>;
967// Arbitrary immediates.
968def : Pat<(i32 imm:$val),
969 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
970
971
972// Global addresses, constant pool entries
973let Predicates = [Is32Bit] in {
974
990def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
991def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>;
992def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
993def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>;
994
995// GlobalTLS addresses
996def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>;
997def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i32 G0), tglobaltlsaddr:$in)>;

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1004def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;
1005def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>;
1006
1007// Add reg, lo. This is used when taking the addr of a global/constpool entry.
1008def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
1009def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>;
1010def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
1011 (ADDri $r, tblockaddress:$in)>;
975def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
976def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>;
977def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
978def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>;
979
980// GlobalTLS addresses
981def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>;
982def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i32 G0), tglobaltlsaddr:$in)>;

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989def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;
990def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>;
991
992// Add reg, lo. This is used when taking the addr of a global/constpool entry.
993def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
994def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>;
995def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
996 (ADDri $r, tblockaddress:$in)>;
997}
1012
1013// Calls:
1014def : Pat<(call tglobaladdr:$dst),
1015 (CALL tglobaladdr:$dst)>;
1016def : Pat<(call texternalsym:$dst),
1017 (CALL texternalsym:$dst)>;
1018
1019// Map integer extload's to zextloads.

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1027// zextload bool -> zextload byte
1028def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1029def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1030
1031// store 0, addr -> store %g0, addr
1032def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>;
1033def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;
1034
998
999// Calls:
1000def : Pat<(call tglobaladdr:$dst),
1001 (CALL tglobaladdr:$dst)>;
1002def : Pat<(call texternalsym:$dst),
1003 (CALL texternalsym:$dst)>;
1004
1005// Map integer extload's to zextloads.

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1013// zextload bool -> zextload byte
1014def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1015def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1016
1017// store 0, addr -> store %g0, addr
1018def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>;
1019def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;
1020
1021// store bar for all atomic_fence in V8.
1022let Predicates = [HasNoV9] in
1023 def : Pat<(atomic_fence imm, imm), (STBAR)>;
1024
1025// atomic_load_32 addr -> load addr
1026def : Pat<(i32 (atomic_load ADDRrr:$src)), (LDrr ADDRrr:$src)>;
1027def : Pat<(i32 (atomic_load ADDRri:$src)), (LDri ADDRri:$src)>;
1028
1029// atomic_store_32 val, addr -> store val, addr
1030def : Pat<(atomic_store ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>;
1031def : Pat<(atomic_store ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>;
1032
1033
1035include "SparcInstr64Bit.td"
1034include "SparcInstr64Bit.td"
1035include "SparcInstrAliases.td"