1//===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 62 unchanged lines hidden (view full) --- 71 return isShiftedUInt<22, 10>(N->getZExtValue()); 72}], HI22>; 73 74// Addressing modes. 75def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>; 76def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>; 77 78// Address operands |
79def SparcMEMrrAsmOperand : AsmOperandClass { 80 let Name = "MEMrr"; 81 let ParserMethod = "parseMEMOperand"; 82} 83 84def SparcMEMriAsmOperand : AsmOperandClass { 85 let Name = "MEMri"; 86 let ParserMethod = "parseMEMOperand"; 87} 88 |
89def MEMrr : Operand<iPTR> { 90 let PrintMethod = "printMemOperand"; 91 let MIOperandInfo = (ops ptr_rc, ptr_rc); |
92 let ParserMatchClass = SparcMEMrrAsmOperand; |
93} 94def MEMri : Operand<iPTR> { 95 let PrintMethod = "printMemOperand"; 96 let MIOperandInfo = (ops ptr_rc, i32imm); |
97 let ParserMatchClass = SparcMEMriAsmOperand; |
98} 99 100def TLSSym : Operand<iPTR>; 101 102// Branch targets have OtherVT type. |
103def brtarget : Operand<OtherVT> { 104 let EncoderMethod = "getBranchTargetOpValue"; 105} |
106 |
107def calltarget : Operand<i32> { 108 let EncoderMethod = "getCallTargetOpValue"; 109} 110 |
111// Operand for printing out a condition code. 112let PrintMethod = "printCCOperand" in 113 def CCOp : Operand<i32>; 114 115def SDTSPcmpicc : 116SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 117def SDTSPcmpfcc : 118SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; --- 56 unchanged lines hidden (view full) --- 175 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>; 176 177def tlsadd : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>; 178def tlsld : SDNode<"SPISD::TLS_LD", SDTSPtlsld>; 179def tlscall : SDNode<"SPISD::TLS_CALL", SDT_SPCall, 180 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 181 SDNPVariadic]>; 182 |
183def getPCX : Operand<iPTR> { |
184 let PrintMethod = "printGetPCX"; 185} 186 187//===----------------------------------------------------------------------===// 188// SPARC Flag Conditions 189//===----------------------------------------------------------------------===// 190 191// Note that these values must be kept in sync with the CCOp::CondCode enum --- 30 unchanged lines hidden (view full) --- 222def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal 223def FCC_O : FCC_VAL<29>; // Ordered 224 225//===----------------------------------------------------------------------===// 226// Instruction Class Templates 227//===----------------------------------------------------------------------===// 228 229/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. |
230multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode, 231 RegisterClass RC, ValueType Ty, Operand immOp> { |
232 def rr : F3_1<2, Op3Val, |
233 (outs RC:$rd), (ins RC:$rs1, RC:$rs2), 234 !strconcat(OpcStr, " $rs1, $rs2, $rd"), 235 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))]>; |
236 def ri : F3_2<2, Op3Val, |
237 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13), 238 !strconcat(OpcStr, " $rs1, $simm13, $rd"), 239 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))]>; |
240} 241 242/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no 243/// pattern. 244multiclass F3_12np<string OpcStr, bits<6> Op3Val> { 245 def rr : F3_1<2, Op3Val, |
246 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 247 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>; |
248 def ri : F3_2<2, Op3Val, |
249 (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13), 250 !strconcat(OpcStr, " $rs1, $simm13, $rd"), []>; |
251} 252 |
253// Load multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot. 254multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode, 255 RegisterClass RC, ValueType Ty> { 256 def rr : F3_1<3, Op3Val, 257 (outs RC:$dst), (ins MEMrr:$addr), 258 !strconcat(OpcStr, " [$addr], $dst"), 259 [(set Ty:$dst, (OpNode ADDRrr:$addr))]>; 260 def ri : F3_2<3, Op3Val, 261 (outs RC:$dst), (ins MEMri:$addr), 262 !strconcat(OpcStr, " [$addr], $dst"), 263 [(set Ty:$dst, (OpNode ADDRri:$addr))]>; 264} 265 266// Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot. 267multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode, 268 RegisterClass RC, ValueType Ty> { 269 def rr : F3_1<3, Op3Val, 270 (outs), (ins MEMrr:$addr, RC:$rd), 271 !strconcat(OpcStr, " $rd, [$addr]"), 272 [(OpNode Ty:$rd, ADDRrr:$addr)]>; 273 def ri : F3_2<3, Op3Val, 274 (outs), (ins MEMri:$addr, RC:$rd), 275 !strconcat(OpcStr, " $rd, [$addr]"), 276 [(OpNode Ty:$rd, ADDRri:$addr)]>; 277} 278 |
279//===----------------------------------------------------------------------===// 280// Instructions 281//===----------------------------------------------------------------------===// 282 283// Pseudo instructions. 284class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> |
285 : InstSP<outs, ins, asmstr, pattern> { 286 let isCodeGenOnly = 1; 287 let isPseudo = 1; 288} |
289 290// GETPCX for PIC 291let Defs = [O7] in { 292 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >; 293} 294 295let Defs = [O6], Uses = [O6] in { 296def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), --- 10 unchanged lines hidden (view full) --- 307 "flushw", 308 [(flushw)]>, Requires<[HasV9]>; 309 let rd = 0, rs1 = 1, simm13 = 3 in 310 def TA3 : F3_2<0b10, 0b111010, (outs), (ins), 311 "ta 3", 312 [(flushw)]>; 313} 314 |
315let isBarrier = 1, isTerminator = 1, rd = 0b1000, rs1 = 0, simm13 = 5 in 316 def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>; 317 |
318let rd = 0 in 319 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val), 320 "unimp $val", []>; 321 322// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 323// instruction selection into a branch sequence. This has to handle all 324// permutations of selection between i32/f32/f64 on ICC and FCC. 325// Expanded after instruction selection. --- 34 unchanged lines hidden (view full) --- 360 "; SELECT_CC_DFP_FCC PSEUDO!", 361 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>; 362 def SELECT_CC_QFP_FCC 363 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond), 364 "; SELECT_CC_QFP_FCC PSEUDO!", 365 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>; 366} 367 |
368// JMPL Instruction. 369let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in { 370 def JMPLrr: F3_1<2, 0b111000, (outs IntRegs:$dst), (ins MEMrr:$addr), 371 "jmpl $addr, $dst", []>; 372 def JMPLri: F3_2<2, 0b111000, (outs IntRegs:$dst), (ins MEMri:$addr), 373 "jmpl $addr, $dst", []>; 374} |
375 376// Section A.3 - Synthetic Instructions, p. 85 377// special cases of JMPL: |
378let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1, 379 isCodeGenOnly = 1 in { |
380 let rd = 0, rs1 = 15 in 381 def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val), 382 "jmp %o7+$val", [(retflag simm13:$val)]>; 383 384 let rd = 0, rs1 = 31 in 385 def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val), 386 "jmp %i7+$val", []>; 387} 388 389// Section B.1 - Load Integer Instructions, p. 90 |
390defm LDSB : Load<"ldsb", 0b001001, sextloadi8, IntRegs, i32>; 391defm LDSH : Load<"ldsh", 0b001010, sextloadi16, IntRegs, i32>; 392defm LDUB : Load<"ldub", 0b000001, zextloadi8, IntRegs, i32>; 393defm LDUH : Load<"lduh", 0b000010, zextloadi16, IntRegs, i32>; 394defm LD : Load<"ld", 0b000000, load, IntRegs, i32>; |
395 396// Section B.2 - Load Floating-point Instructions, p. 92 |
397defm LDF : Load<"ld", 0b100000, load, FPRegs, f32>; 398defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64>; 399defm LDQF : Load<"ldq", 0b100010, load, QFPRegs, f128>, 400 Requires<[HasV9, HasHardQuad]>; |
401 402// Section B.4 - Store Integer Instructions, p. 95 |
403defm STB : Store<"stb", 0b000101, truncstorei8, IntRegs, i32>; 404defm STH : Store<"sth", 0b000110, truncstorei16, IntRegs, i32>; 405defm ST : Store<"st", 0b000100, store, IntRegs, i32>; |
406 407// Section B.5 - Store Floating-point Instructions, p. 97 |
408defm STF : Store<"st", 0b100100, store, FPRegs, f32>; 409defm STDF : Store<"std", 0b100111, store, DFPRegs, f64>; 410defm STQF : Store<"stq", 0b100110, store, QFPRegs, f128>, 411 Requires<[HasV9, HasHardQuad]>; |
412 413// Section B.9 - SETHI Instruction, p. 104 414def SETHIi: F2_1<0b100, 415 (outs IntRegs:$rd), (ins i32imm:$imm22), 416 "sethi $imm22, $rd", 417 [(set i32:$rd, SETHIimm:$imm22)]>; 418 419// Section B.10 - NOP Instruction, p. 105 420// (It's a special case of SETHI) 421let rd = 0, imm22 = 0 in 422 def NOP : F2_1<0b100, (outs), (ins), "nop", []>; 423 424// Section B.11 - Logical Instructions, p. 106 |
425defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, i32imm>; |
426 427def ANDNrr : F3_1<2, 0b000101, |
428 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 429 "andn $rs1, $rs2, $rd", 430 [(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>; |
431def ANDNri : F3_2<2, 0b000101, |
432 (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13), 433 "andn $rs1, $simm13, $rd", []>; |
434 |
435defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, i32imm>; |
436 437def ORNrr : F3_1<2, 0b000110, |
438 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 439 "orn $rs1, $rs2, $rd", 440 [(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>; |
441def ORNri : F3_2<2, 0b000110, |
442 (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13), 443 "orn $rs1, $simm13, $rd", []>; 444defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, i32imm>; |
445 446def XNORrr : F3_1<2, 0b000111, |
447 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 448 "xnor $rs1, $rs2, $rd", 449 [(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>; |
450def XNORri : F3_2<2, 0b000111, |
451 (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13), 452 "xnor $rs1, $simm13, $rd", []>; |
453 454// Section B.12 - Shift Instructions, p. 107 |
455defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, i32imm>; 456defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, i32imm>; 457defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, i32imm>; |
458 459// Section B.13 - Add Instructions, p. 108 |
460defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, i32imm>; |
461 462// "LEA" forms of add (patterns to make tblgen happy) |
463let Predicates = [Is32Bit], isCodeGenOnly = 1 in |
464 def LEA_ADDri : F3_2<2, 0b000000, 465 (outs IntRegs:$dst), (ins MEMri:$addr), 466 "add ${addr:arith}, $dst", 467 [(set iPTR:$dst, ADDRri:$addr)]>; 468 469let Defs = [ICC] in |
470 defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, i32imm>; |
471 472let Uses = [ICC], Defs = [ICC] in |
473 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, i32imm>; |
474 475// Section B.15 - Subtract Instructions, p. 110 |
476defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, i32imm>; |
477let Uses = [ICC], Defs = [ICC] in |
478 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, i32imm>; |
479 480let Defs = [ICC] in |
481 defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, i32imm>; |
482 483let Defs = [ICC], rd = 0 in { 484 def CMPrr : F3_1<2, 0b010100, |
485 (outs), (ins IntRegs:$rs1, IntRegs:$rs2), 486 "cmp $rs1, $rs2", 487 [(SPcmpicc i32:$rs1, i32:$rs2)]>; |
488 def CMPri : F3_2<2, 0b010100, |
489 (outs), (ins IntRegs:$rs1, i32imm:$simm13), 490 "cmp $rs1, $simm13", 491 [(SPcmpicc i32:$rs1, (i32 simm13:$simm13))]>; |
492} 493 |
494// Section B.18 - Multiply Instructions, p. 113 495let Defs = [Y] in { 496 defm UMUL : F3_12np<"umul", 0b001010>; |
497 defm SMUL : F3_12 <"smul", 0b001011, mul, IntRegs, i32, i32imm>; |
498} 499 500// Section B.19 - Divide Instructions, p. 115 501let Defs = [Y] in { 502 defm UDIV : F3_12np<"udiv", 0b001110>; 503 defm SDIV : F3_12np<"sdiv", 0b001111>; 504} 505 --- 19 unchanged lines hidden (view full) --- 525class BranchSP<dag ins, string asmstr, list<dag> pattern> 526 : F2_2<0b010, (outs), ins, asmstr, pattern> { 527 let isBranch = 1; 528 let isTerminator = 1; 529 let hasDelaySlot = 1; 530} 531 532// Indirect branch instructions. |
533let isTerminator = 1, isBarrier = 1, hasDelaySlot = 1, isBranch =1, 534 isIndirectBranch = 1, rd = 0, isCodeGenOnly = 1 in { |
535 def BINDrr : F3_1<2, 0b111000, 536 (outs), (ins MEMrr:$ptr), 537 "jmp $ptr", 538 [(brind ADDRrr:$ptr)]>; 539 def BINDri : F3_2<2, 0b111000, 540 (outs), (ins MEMri:$ptr), 541 "jmp $ptr", 542 [(brind ADDRri:$ptr)]>; --- 26 unchanged lines hidden (view full) --- 569 hasDelaySlot = 1, isCall = 1 in { 570 def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops), 571 "call $dst", []> { 572 bits<30> disp; 573 let op = 1; 574 let Inst{29-0} = disp; 575 } 576 |
577 // indirect calls: special cases of JMPL. 578 let isCodeGenOnly = 1, rd = 15 in { 579 def CALLrr : F3_1<2, 0b111000, 580 (outs), (ins MEMrr:$ptr, variable_ops), 581 "call $ptr", 582 [(call ADDRrr:$ptr)]>; 583 def CALLri : F3_2<2, 0b111000, 584 (outs), (ins MEMri:$ptr, variable_ops), 585 "call $ptr", 586 [(call ADDRri:$ptr)]>; 587 } |
588} 589 590// Section B.28 - Read State Register Instructions 591let Uses = [Y], rs1 = 0, rs2 = 0 in 592 def RDY : F3_1<2, 0b101000, 593 (outs IntRegs:$dst), (ins), 594 "rd %y, $dst", []>; 595 596// Section B.29 - Write State Register Instructions 597let Defs = [Y], rd = 0 in { 598 def WRYrr : F3_1<2, 0b110000, 599 (outs), (ins IntRegs:$b, IntRegs:$c), 600 "wr $b, $c, %y", []>; 601 def WRYri : F3_2<2, 0b110000, 602 (outs), (ins IntRegs:$b, i32imm:$c), 603 "wr $b, $c, %y", []>; 604} 605// Convert Integer to Floating-point Instructions, p. 141 606def FITOS : F3_3u<2, 0b110100, 0b011000100, |
607 (outs FPRegs:$rd), (ins FPRegs:$rs2), 608 "fitos $rs2, $rd", 609 [(set FPRegs:$rd, (SPitof FPRegs:$rs2))]>; |
610def FITOD : F3_3u<2, 0b110100, 0b011001000, |
611 (outs DFPRegs:$rd), (ins FPRegs:$rs2), 612 "fitod $rs2, $rd", 613 [(set DFPRegs:$rd, (SPitof FPRegs:$rs2))]>; |
614def FITOQ : F3_3u<2, 0b110100, 0b011001100, |
615 (outs QFPRegs:$rd), (ins FPRegs:$rs2), 616 "fitoq $rs2, $rd", 617 [(set QFPRegs:$rd, (SPitof FPRegs:$rs2))]>, |
618 Requires<[HasHardQuad]>; 619 620// Convert Floating-point to Integer Instructions, p. 142 621def FSTOI : F3_3u<2, 0b110100, 0b011010001, |
622 (outs FPRegs:$rd), (ins FPRegs:$rs2), 623 "fstoi $rs2, $rd", 624 [(set FPRegs:$rd, (SPftoi FPRegs:$rs2))]>; |
625def FDTOI : F3_3u<2, 0b110100, 0b011010010, |
626 (outs FPRegs:$rd), (ins DFPRegs:$rs2), 627 "fdtoi $rs2, $rd", 628 [(set FPRegs:$rd, (SPftoi DFPRegs:$rs2))]>; |
629def FQTOI : F3_3u<2, 0b110100, 0b011010011, |
630 (outs FPRegs:$rd), (ins QFPRegs:$rs2), 631 "fqtoi $rs2, $rd", 632 [(set FPRegs:$rd, (SPftoi QFPRegs:$rs2))]>, |
633 Requires<[HasHardQuad]>; 634 635// Convert between Floating-point Formats Instructions, p. 143 636def FSTOD : F3_3u<2, 0b110100, 0b011001001, |
637 (outs DFPRegs:$rd), (ins FPRegs:$rs2), 638 "fstod $rs2, $rd", 639 [(set f64:$rd, (fextend f32:$rs2))]>; |
640def FSTOQ : F3_3u<2, 0b110100, 0b011001101, |
641 (outs QFPRegs:$rd), (ins FPRegs:$rs2), 642 "fstoq $rs2, $rd", 643 [(set f128:$rd, (fextend f32:$rs2))]>, |
644 Requires<[HasHardQuad]>; 645def FDTOS : F3_3u<2, 0b110100, 0b011000110, |
646 (outs FPRegs:$rd), (ins DFPRegs:$rs2), 647 "fdtos $rs2, $rd", 648 [(set f32:$rd, (fround f64:$rs2))]>; 649def FDTOQ : F3_3u<2, 0b110100, 0b011001110, 650 (outs QFPRegs:$rd), (ins DFPRegs:$rs2), 651 "fdtoq $rs2, $rd", 652 [(set f128:$rd, (fextend f64:$rs2))]>, |
653 Requires<[HasHardQuad]>; 654def FQTOS : F3_3u<2, 0b110100, 0b011000111, |
655 (outs FPRegs:$rd), (ins QFPRegs:$rs2), 656 "fqtos $rs2, $rd", 657 [(set f32:$rd, (fround f128:$rs2))]>, |
658 Requires<[HasHardQuad]>; 659def FQTOD : F3_3u<2, 0b110100, 0b011001011, |
660 (outs DFPRegs:$rd), (ins QFPRegs:$rs2), 661 "fqtod $rs2, $rd", 662 [(set f64:$rd, (fround f128:$rs2))]>, |
663 Requires<[HasHardQuad]>; 664 665// Floating-point Move Instructions, p. 144 666def FMOVS : F3_3u<2, 0b110100, 0b000000001, |
667 (outs FPRegs:$rd), (ins FPRegs:$rs2), 668 "fmovs $rs2, $rd", []>; |
669def FNEGS : F3_3u<2, 0b110100, 0b000000101, |
670 (outs FPRegs:$rd), (ins FPRegs:$rs2), 671 "fnegs $rs2, $rd", 672 [(set f32:$rd, (fneg f32:$rs2))]>; |
673def FABSS : F3_3u<2, 0b110100, 0b000001001, |
674 (outs FPRegs:$rd), (ins FPRegs:$rs2), 675 "fabss $rs2, $rd", 676 [(set f32:$rd, (fabs f32:$rs2))]>; |
677 678 679// Floating-point Square Root Instructions, p.145 680def FSQRTS : F3_3u<2, 0b110100, 0b000101001, |
681 (outs FPRegs:$rd), (ins FPRegs:$rs2), 682 "fsqrts $rs2, $rd", 683 [(set f32:$rd, (fsqrt f32:$rs2))]>; |
684def FSQRTD : F3_3u<2, 0b110100, 0b000101010, |
685 (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 686 "fsqrtd $rs2, $rd", 687 [(set f64:$rd, (fsqrt f64:$rs2))]>; |
688def FSQRTQ : F3_3u<2, 0b110100, 0b000101011, |
689 (outs QFPRegs:$rd), (ins QFPRegs:$rs2), 690 "fsqrtq $rs2, $rd", 691 [(set f128:$rd, (fsqrt f128:$rs2))]>, |
692 Requires<[HasHardQuad]>; 693 694 695 696// Floating-point Add and Subtract Instructions, p. 146 697def FADDS : F3_3<2, 0b110100, 0b001000001, |
698 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 699 "fadds $rs1, $rs2, $rd", 700 [(set f32:$rd, (fadd f32:$rs1, f32:$rs2))]>; |
701def FADDD : F3_3<2, 0b110100, 0b001000010, |
702 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 703 "faddd $rs1, $rs2, $rd", 704 [(set f64:$rd, (fadd f64:$rs1, f64:$rs2))]>; |
705def FADDQ : F3_3<2, 0b110100, 0b001000011, |
706 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), 707 "faddq $rs1, $rs2, $rd", 708 [(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>, |
709 Requires<[HasHardQuad]>; 710 711def FSUBS : F3_3<2, 0b110100, 0b001000101, |
712 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 713 "fsubs $rs1, $rs2, $rd", 714 [(set f32:$rd, (fsub f32:$rs1, f32:$rs2))]>; |
715def FSUBD : F3_3<2, 0b110100, 0b001000110, |
716 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 717 "fsubd $rs1, $rs2, $rd", 718 [(set f64:$rd, (fsub f64:$rs1, f64:$rs2))]>; |
719def FSUBQ : F3_3<2, 0b110100, 0b001000111, |
720 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), 721 "fsubq $rs1, $rs2, $rd", 722 [(set f128:$rd, (fsub f128:$rs1, f128:$rs2))]>, |
723 Requires<[HasHardQuad]>; 724 725 726// Floating-point Multiply and Divide Instructions, p. 147 727def FMULS : F3_3<2, 0b110100, 0b001001001, |
728 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 729 "fmuls $rs1, $rs2, $rd", 730 [(set f32:$rd, (fmul f32:$rs1, f32:$rs2))]>; |
731def FMULD : F3_3<2, 0b110100, 0b001001010, |
732 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 733 "fmuld $rs1, $rs2, $rd", 734 [(set f64:$rd, (fmul f64:$rs1, f64:$rs2))]>; |
735def FMULQ : F3_3<2, 0b110100, 0b001001011, |
736 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), 737 "fmulq $rs1, $rs2, $rd", 738 [(set f128:$rd, (fmul f128:$rs1, f128:$rs2))]>, |
739 Requires<[HasHardQuad]>; 740 741def FSMULD : F3_3<2, 0b110100, 0b001101001, |
742 (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 743 "fsmuld $rs1, $rs2, $rd", 744 [(set f64:$rd, (fmul (fextend f32:$rs1), 745 (fextend f32:$rs2)))]>; |
746def FDMULQ : F3_3<2, 0b110100, 0b001101110, |
747 (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 748 "fdmulq $rs1, $rs2, $rd", 749 [(set f128:$rd, (fmul (fextend f64:$rs1), 750 (fextend f64:$rs2)))]>, |
751 Requires<[HasHardQuad]>; 752 753def FDIVS : F3_3<2, 0b110100, 0b001001101, |
754 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 755 "fdivs $rs1, $rs2, $rd", 756 [(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))]>; |
757def FDIVD : F3_3<2, 0b110100, 0b001001110, |
758 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 759 "fdivd $rs1, $rs2, $rd", 760 [(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))]>; |
761def FDIVQ : F3_3<2, 0b110100, 0b001001111, |
762 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), 763 "fdivq $rs1, $rs2, $rd", 764 [(set f128:$rd, (fdiv f128:$rs1, f128:$rs2))]>, |
765 Requires<[HasHardQuad]>; 766 767// Floating-point Compare Instructions, p. 148 768// Note: the 2nd template arg is different for these guys. 769// Note 2: the result of a FCMP is not available until the 2nd cycle 770// after the instr is retired, but there is no interlock in Sparc V8. 771// This behavior is modeled with a forced noop after the instruction in 772// DelaySlotFiller. 773 774let Defs = [FCC] in { 775 def FCMPS : F3_3c<2, 0b110101, 0b001010001, |
776 (outs), (ins FPRegs:$rs1, FPRegs:$rs2), 777 "fcmps $rs1, $rs2", 778 [(SPcmpfcc f32:$rs1, f32:$rs2)]>; |
779 def FCMPD : F3_3c<2, 0b110101, 0b001010010, |
780 (outs), (ins DFPRegs:$rs1, DFPRegs:$rs2), 781 "fcmpd $rs1, $rs2", 782 [(SPcmpfcc f64:$rs1, f64:$rs2)]>; |
783 def FCMPQ : F3_3c<2, 0b110101, 0b001010011, |
784 (outs), (ins QFPRegs:$rs1, QFPRegs:$rs2), 785 "fcmpq $rs1, $rs2", 786 [(SPcmpfcc f128:$rs1, f128:$rs2)]>, |
787 Requires<[HasHardQuad]>; 788} 789 790//===----------------------------------------------------------------------===// 791// Instructions for Thread Local Storage(TLS). 792//===----------------------------------------------------------------------===// |
793let isCodeGenOnly = 1, isAsmParserOnly = 1 in { |
794def TLS_ADDrr : F3_1<2, 0b000000, 795 (outs IntRegs:$rd), 796 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym), 797 "add $rs1, $rs2, $rd, $sym", 798 [(set i32:$rd, 799 (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>; 800 801let mayLoad = 1 in --- 7 unchanged lines hidden (view full) --- 809 def TLS_CALL : InstSP<(outs), 810 (ins calltarget:$disp, TLSSym:$sym, variable_ops), 811 "call $disp, $sym", 812 [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)]> { 813 bits<30> disp; 814 let op = 1; 815 let Inst{29-0} = disp; 816} |
817} |
818 819//===----------------------------------------------------------------------===// 820// V9 Instructions 821//===----------------------------------------------------------------------===// 822 823// V9 Conditional Moves. 824let Predicates = [HasV9], Constraints = "$f = $rd" in { 825 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. --- 35 unchanged lines hidden (view full) --- 861 def FMOVD_ICC 862 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd), 863 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond), 864 "fmovd$cond %icc, $rs2, $rd", 865 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>; 866 def FMOVQ_ICC 867 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd), 868 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond), |
869 "fmovq$cond %icc, $rs2, $rd", 870 [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>, 871 Requires<[HasHardQuad]>; |
872 } 873 874 let Uses = [FCC], opf_cc = 0b000 in { 875 def FMOVS_FCC 876 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd), 877 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond), 878 "fmovs$cond %fcc0, $rs2, $rd", 879 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>; 880 def FMOVD_FCC 881 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd), 882 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond), 883 "fmovd$cond %fcc0, $rs2, $rd", 884 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>; 885 def FMOVQ_FCC 886 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd), 887 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond), |
888 "fmovq$cond %fcc0, $rs2, $rd", 889 [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>, 890 Requires<[HasHardQuad]>; |
891 } 892 893} 894 895// Floating-Point Move Instructions, p. 164 of the V9 manual. 896let Predicates = [HasV9] in { 897 def FMOVD : F3_3u<2, 0b110100, 0b000000010, |
898 (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 899 "fmovd $rs2, $rd", []>; |
900 def FMOVQ : F3_3u<2, 0b110100, 0b000000011, |
901 (outs QFPRegs:$rd), (ins QFPRegs:$rs2), 902 "fmovq $rs2, $rd", []>, |
903 Requires<[HasHardQuad]>; 904 def FNEGD : F3_3u<2, 0b110100, 0b000000110, |
905 (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 906 "fnegd $rs2, $rd", 907 [(set f64:$rd, (fneg f64:$rs2))]>; |
908 def FNEGQ : F3_3u<2, 0b110100, 0b000000111, |
909 (outs QFPRegs:$rd), (ins QFPRegs:$rs2), 910 "fnegq $rs2, $rd", 911 [(set f128:$rd, (fneg f128:$rs2))]>, |
912 Requires<[HasHardQuad]>; 913 def FABSD : F3_3u<2, 0b110100, 0b000001010, |
914 (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 915 "fabsd $rs2, $rd", 916 [(set f64:$rd, (fabs f64:$rs2))]>; |
917 def FABSQ : F3_3u<2, 0b110100, 0b000001011, |
918 (outs QFPRegs:$rd), (ins QFPRegs:$rs2), 919 "fabsq $rs2, $rd", 920 [(set f128:$rd, (fabs f128:$rs2))]>, |
921 Requires<[HasHardQuad]>; 922} 923 924// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear |
925// the top 32-bits before using it. To do this clearing, we use a SRLri X,0. |
926let rs1 = 0 in 927 def POPCrr : F3_1<2, 0b101110, 928 (outs IntRegs:$dst), (ins IntRegs:$src), 929 "popc $src, $dst", []>, Requires<[HasV9]>; 930def : Pat<(ctpop i32:$src), |
931 (POPCrr (SRLri $src, 0))>; |
932 |
933// Atomic swap. 934let hasSideEffects =1, rd = 0, rs1 = 0b01111, rs2 = 0 in 935 def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>; 936 937let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in 938 def MEMBARi : F3_2<2, 0b101000, (outs), (ins i32imm:$simm13), 939 "membar $simm13", []>; 940 941let Constraints = "$val = $dst" in { 942 def SWAPrr : F3_1<3, 0b001111, 943 (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val), 944 "swap [$addr], $dst", 945 [(set i32:$dst, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>; 946 def SWAPri : F3_2<3, 0b001111, 947 (outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val), 948 "swap [$addr], $dst", 949 [(set i32:$dst, (atomic_swap_32 ADDRri:$addr, i32:$val))]>; 950} 951 952let Predicates = [HasV9], Constraints = "$swap = $rd" in 953 def CASrr: F3_1_asi<3, 0b111100, 0b10000000, 954 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, 955 IntRegs:$swap), 956 "cas [$rs1], $rs2, $rd", 957 [(set i32:$rd, 958 (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>; 959 |
960//===----------------------------------------------------------------------===// 961// Non-Instruction Patterns 962//===----------------------------------------------------------------------===// 963 964// Small immediates. 965def : Pat<(i32 simm13:$val), 966 (ORri (i32 G0), imm:$val)>; 967// Arbitrary immediates. 968def : Pat<(i32 imm:$val), 969 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 970 971 972// Global addresses, constant pool entries |
973let Predicates = [Is32Bit] in { 974 |
975def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 976def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>; 977def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 978def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>; 979 980// GlobalTLS addresses 981def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>; 982def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i32 G0), tglobaltlsaddr:$in)>; --- 6 unchanged lines hidden (view full) --- 989def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>; 990def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>; 991 992// Add reg, lo. This is used when taking the addr of a global/constpool entry. 993def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>; 994def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>; 995def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)), 996 (ADDri $r, tblockaddress:$in)>; |
997} |
998 999// Calls: 1000def : Pat<(call tglobaladdr:$dst), 1001 (CALL tglobaladdr:$dst)>; 1002def : Pat<(call texternalsym:$dst), 1003 (CALL texternalsym:$dst)>; 1004 1005// Map integer extload's to zextloads. --- 7 unchanged lines hidden (view full) --- 1013// zextload bool -> zextload byte 1014def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 1015def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 1016 1017// store 0, addr -> store %g0, addr 1018def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>; 1019def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>; 1020 |
1021// store bar for all atomic_fence in V8. 1022let Predicates = [HasNoV9] in 1023 def : Pat<(atomic_fence imm, imm), (STBAR)>; 1024 1025// atomic_load_32 addr -> load addr 1026def : Pat<(i32 (atomic_load ADDRrr:$src)), (LDrr ADDRrr:$src)>; 1027def : Pat<(i32 (atomic_load ADDRri:$src)), (LDri ADDRri:$src)>; 1028 1029// atomic_store_32 val, addr -> store val, addr 1030def : Pat<(atomic_store ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>; 1031def : Pat<(atomic_store ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>; 1032 1033 |
1034include "SparcInstr64Bit.td" |
1035include "SparcInstrAliases.td" |