| SparcISelLowering.h (261991) | SparcISelLowering.h (262613) |
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| 1//===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 59 unchanged lines hidden (view full) --- 68 69 virtual MachineBasicBlock * 70 EmitInstrWithCustomInserter(MachineInstr *MI, 71 MachineBasicBlock *MBB) const; 72 73 virtual const char *getTargetNodeName(unsigned Opcode) const; 74 75 ConstraintType getConstraintType(const std::string &Constraint) const; | 1//===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 59 unchanged lines hidden (view full) --- 68 69 virtual MachineBasicBlock * 70 EmitInstrWithCustomInserter(MachineInstr *MI, 71 MachineBasicBlock *MBB) const; 72 73 virtual const char *getTargetNodeName(unsigned Opcode) const; 74 75 ConstraintType getConstraintType(const std::string &Constraint) const; |
| 76 ConstraintWeight 77 getSingleConstraintMatchWeight(AsmOperandInfo &info, 78 const char *constraint) const; 79 void LowerAsmOperandForConstraint(SDValue Op, 80 std::string &Constraint, 81 std::vector<SDValue> &Ops, 82 SelectionDAG &DAG) const; |
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| 76 std::pair<unsigned, const TargetRegisterClass*> 77 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const; 78 79 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 80 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; } 81 82 /// getSetCCResultType - Return the ISD::SETCC ValueType 83 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const; --- 69 unchanged lines hidden (view full) --- 153 // Do not shrink FP constpool if VT == MVT::f128. 154 // (ldd, call _Q_fdtoq) is more expensive than two ldds. 155 return VT != MVT::f128; 156 } 157 158 virtual void ReplaceNodeResults(SDNode *N, 159 SmallVectorImpl<SDValue>& Results, 160 SelectionDAG &DAG) const; | 83 std::pair<unsigned, const TargetRegisterClass*> 84 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const; 85 86 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 87 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; } 88 89 /// getSetCCResultType - Return the ISD::SETCC ValueType 90 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const; --- 69 unchanged lines hidden (view full) --- 160 // Do not shrink FP constpool if VT == MVT::f128. 161 // (ldd, call _Q_fdtoq) is more expensive than two ldds. 162 return VT != MVT::f128; 163 } 164 165 virtual void ReplaceNodeResults(SDNode *N, 166 SmallVectorImpl<SDValue>& Results, 167 SelectionDAG &DAG) const; |
| 168 169 MachineBasicBlock *expandSelectCC(MachineInstr *MI, MachineBasicBlock *BB, 170 unsigned BROpcode) const; 171 MachineBasicBlock *expandAtomicRMW(MachineInstr *MI, 172 MachineBasicBlock *BB, 173 unsigned Opcode, 174 unsigned CondCode = 0) const; |
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| 161 }; 162} // end namespace llvm 163 164#endif // SPARC_ISELLOWERING_H | 175 }; 176} // end namespace llvm 177 178#endif // SPARC_ISELLOWERING_H |