1//===-- SparcAsmPrinter.cpp - Sparc LLVM assembly writer ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains a printer that converts from our internal representation 11// of machine-dependent LLVM code to GAS-format SPARC assembly language. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "asm-printer" 16#include "Sparc.h" 17#include "SparcInstrInfo.h" 18#include "SparcTargetMachine.h"
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19#include "MCTargetDesc/SparcBaseInfo.h"
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19#include "SparcTargetStreamer.h" 20#include "InstPrinter/SparcInstPrinter.h" 21#include "MCTargetDesc/SparcMCExpr.h" |
22#include "llvm/ADT/SmallString.h" 23#include "llvm/CodeGen/AsmPrinter.h" 24#include "llvm/CodeGen/MachineInstr.h"
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25#include "llvm/CodeGen/MachineModuleInfoImpls.h" |
26#include "llvm/CodeGen/MachineRegisterInfo.h"
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27#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" |
28#include "llvm/MC/MCAsmInfo.h"
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29#include "llvm/MC/MCContext.h" 30#include "llvm/MC/MCInst.h" |
31#include "llvm/MC/MCStreamer.h" 32#include "llvm/MC/MCSymbol.h" 33#include "llvm/Support/TargetRegistry.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/Target/Mangler.h" 36using namespace llvm; 37 38namespace { 39 class SparcAsmPrinter : public AsmPrinter {
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40 SparcTargetStreamer &getTargetStreamer() { 41 return static_cast<SparcTargetStreamer&>(OutStreamer.getTargetStreamer()); 42 } |
43 public: 44 explicit SparcAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) 45 : AsmPrinter(TM, Streamer) {} 46 47 virtual const char *getPassName() const { 48 return "Sparc Assembly Printer"; 49 } 50 51 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS); 52 void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS, 53 const char *Modifier = 0); 54 void printCCOperand(const MachineInstr *MI, int opNum, raw_ostream &OS); 55 56 virtual void EmitFunctionBodyStart();
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48 virtual void EmitInstruction(const MachineInstr *MI) {
49 SmallString<128> Str;
50 raw_svector_ostream OS(Str);
51 printInstruction(MI, OS);
52 OutStreamer.EmitRawText(OS.str());
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57 virtual void EmitInstruction(const MachineInstr *MI); 58 virtual void EmitEndOfAsmFile(Module &M); 59 60 static const char *getRegisterName(unsigned RegNo) { 61 return SparcInstPrinter::getRegisterName(RegNo); |
62 }
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54 void printInstruction(const MachineInstr *MI, raw_ostream &OS);// autogen'd.
55 static const char *getRegisterName(unsigned RegNo);
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63 64 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, 65 unsigned AsmVariant, const char *ExtraCode, 66 raw_ostream &O); 67 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, 68 unsigned AsmVariant, const char *ExtraCode, 69 raw_ostream &O); 70
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64 bool printGetPCX(const MachineInstr *MI, unsigned OpNo, raw_ostream &OS);
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71 void LowerGETPCXAndEmitMCInsts(const MachineInstr *MI); |
72
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66 virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB)
67 const;
68 void EmitGlobalRegisterDecl(unsigned reg) {
69 SmallString<128> Str;
70 raw_svector_ostream OS(Str);
71 OS << "\t.register "
72 << "%" << StringRef(getRegisterName(reg)).lower()
73 << ", "
74 << ((reg == SP::G6 || reg == SP::G7)? "#ignore" : "#scratch");
75 OutStreamer.EmitRawText(OS.str());
76 }
77
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73 }; 74} // end of anonymous namespace 75
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81#include "SparcGenAsmWriter.inc"
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76static MCOperand createSparcMCOperand(SparcMCExpr::VariantKind Kind, 77 MCSymbol *Sym, MCContext &OutContext) { 78 const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::Create(Sym, 79 OutContext); 80 const SparcMCExpr *expr = SparcMCExpr::Create(Kind, MCSym, OutContext); 81 return MCOperand::CreateExpr(expr); |
82
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83} 84static MCOperand createPCXCallOP(MCSymbol *Label, 85 MCContext &OutContext) { 86 return createSparcMCOperand(SparcMCExpr::VK_Sparc_None, Label, OutContext); 87} 88 89static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind, 90 MCSymbol *GOTLabel, MCSymbol *StartLabel, 91 MCSymbol *CurLabel, 92 MCContext &OutContext) 93{ 94 const MCSymbolRefExpr *GOT = MCSymbolRefExpr::Create(GOTLabel, OutContext); 95 const MCSymbolRefExpr *Start = MCSymbolRefExpr::Create(StartLabel, 96 OutContext); 97 const MCSymbolRefExpr *Cur = MCSymbolRefExpr::Create(CurLabel, 98 OutContext); 99 100 const MCBinaryExpr *Sub = MCBinaryExpr::CreateSub(Cur, Start, OutContext); 101 const MCBinaryExpr *Add = MCBinaryExpr::CreateAdd(GOT, Sub, OutContext); 102 const SparcMCExpr *expr = SparcMCExpr::Create(Kind, 103 Add, OutContext); 104 return MCOperand::CreateExpr(expr); 105} 106 107static void EmitCall(MCStreamer &OutStreamer, 108 MCOperand &Callee) 109{ 110 MCInst CallInst; 111 CallInst.setOpcode(SP::CALL); 112 CallInst.addOperand(Callee); 113 OutStreamer.EmitInstruction(CallInst); 114} 115 116static void EmitSETHI(MCStreamer &OutStreamer, 117 MCOperand &Imm, MCOperand &RD) 118{ 119 MCInst SETHIInst; 120 SETHIInst.setOpcode(SP::SETHIi); 121 SETHIInst.addOperand(RD); 122 SETHIInst.addOperand(Imm); 123 OutStreamer.EmitInstruction(SETHIInst); 124} 125 126static void EmitBinary(MCStreamer &OutStreamer, unsigned Opcode, 127 MCOperand &RS1, MCOperand &Src2, MCOperand &RD) 128{ 129 MCInst Inst; 130 Inst.setOpcode(Opcode); 131 Inst.addOperand(RD); 132 Inst.addOperand(RS1); 133 Inst.addOperand(Src2); 134 OutStreamer.EmitInstruction(Inst); 135} 136 137static void EmitOR(MCStreamer &OutStreamer, 138 MCOperand &RS1, MCOperand &Imm, MCOperand &RD) { 139 EmitBinary(OutStreamer, SP::ORri, RS1, Imm, RD); 140} 141 142static void EmitADD(MCStreamer &OutStreamer, 143 MCOperand &RS1, MCOperand &RS2, MCOperand &RD) { 144 EmitBinary(OutStreamer, SP::ADDrr, RS1, RS2, RD); 145} 146 147static void EmitSHL(MCStreamer &OutStreamer, 148 MCOperand &RS1, MCOperand &Imm, MCOperand &RD) { 149 EmitBinary(OutStreamer, SP::SLLri, RS1, Imm, RD); 150} 151 152 153static void EmitHiLo(MCStreamer &OutStreamer, MCSymbol *GOTSym, 154 SparcMCExpr::VariantKind HiKind, 155 SparcMCExpr::VariantKind LoKind, 156 MCOperand &RD, 157 MCContext &OutContext) { 158 159 MCOperand hi = createSparcMCOperand(HiKind, GOTSym, OutContext); 160 MCOperand lo = createSparcMCOperand(LoKind, GOTSym, OutContext); 161 EmitSETHI(OutStreamer, hi, RD); 162 EmitOR(OutStreamer, RD, lo, RD); 163} 164 165void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI) 166{ 167 MCSymbol *GOTLabel = 168 OutContext.GetOrCreateSymbol(Twine("_GLOBAL_OFFSET_TABLE_")); 169 170 const MachineOperand &MO = MI->getOperand(0); 171 assert(MO.getReg() != SP::O7 && 172 "%o7 is assigned as destination for getpcx!"); 173 174 MCOperand MCRegOP = MCOperand::CreateReg(MO.getReg()); 175 176 177 if (TM.getRelocationModel() != Reloc::PIC_) { 178 // Just load the address of GOT to MCRegOP. 179 switch(TM.getCodeModel()) { 180 default: 181 llvm_unreachable("Unsupported absolute code model"); 182 case CodeModel::Small: 183 EmitHiLo(OutStreamer, GOTLabel, 184 SparcMCExpr::VK_Sparc_HI, SparcMCExpr::VK_Sparc_LO, 185 MCRegOP, OutContext); 186 break; 187 case CodeModel::Medium: { 188 EmitHiLo(OutStreamer, GOTLabel, 189 SparcMCExpr::VK_Sparc_H44, SparcMCExpr::VK_Sparc_M44, 190 MCRegOP, OutContext); 191 MCOperand imm = MCOperand::CreateExpr(MCConstantExpr::Create(12, 192 OutContext)); 193 EmitSHL(OutStreamer, MCRegOP, imm, MCRegOP); 194 MCOperand lo = createSparcMCOperand(SparcMCExpr::VK_Sparc_L44, 195 GOTLabel, OutContext); 196 EmitOR(OutStreamer, MCRegOP, lo, MCRegOP); 197 break; 198 } 199 case CodeModel::Large: { 200 EmitHiLo(OutStreamer, GOTLabel, 201 SparcMCExpr::VK_Sparc_HH, SparcMCExpr::VK_Sparc_HM, 202 MCRegOP, OutContext); 203 MCOperand imm = MCOperand::CreateExpr(MCConstantExpr::Create(32, 204 OutContext)); 205 EmitSHL(OutStreamer, MCRegOP, imm, MCRegOP); 206 // Use register %o7 to load the lower 32 bits. 207 MCOperand RegO7 = MCOperand::CreateReg(SP::O7); 208 EmitHiLo(OutStreamer, GOTLabel, 209 SparcMCExpr::VK_Sparc_HI, SparcMCExpr::VK_Sparc_LO, 210 RegO7, OutContext); 211 EmitADD(OutStreamer, MCRegOP, RegO7, MCRegOP); 212 } 213 } 214 return; 215 } 216 217 MCSymbol *StartLabel = OutContext.CreateTempSymbol(); 218 MCSymbol *EndLabel = OutContext.CreateTempSymbol(); 219 MCSymbol *SethiLabel = OutContext.CreateTempSymbol(); 220 221 MCOperand RegO7 = MCOperand::CreateReg(SP::O7); 222 223 // <StartLabel>: 224 // call <EndLabel> 225 // <SethiLabel>: 226 // sethi %hi(_GLOBAL_OFFSET_TABLE_+(<SethiLabel>-<StartLabel>)), <MO> 227 // <EndLabel>: 228 // or <MO>, %lo(_GLOBAL_OFFSET_TABLE_+(<EndLabel>-<StartLabel>))), <MO> 229 // add <MO>, %o7, <MO> 230 231 OutStreamer.EmitLabel(StartLabel); 232 MCOperand Callee = createPCXCallOP(EndLabel, OutContext); 233 EmitCall(OutStreamer, Callee); 234 OutStreamer.EmitLabel(SethiLabel); 235 MCOperand hiImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_PC22, 236 GOTLabel, StartLabel, SethiLabel, 237 OutContext); 238 EmitSETHI(OutStreamer, hiImm, MCRegOP); 239 OutStreamer.EmitLabel(EndLabel); 240 MCOperand loImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_PC10, 241 GOTLabel, StartLabel, EndLabel, 242 OutContext); 243 EmitOR(OutStreamer, MCRegOP, loImm, MCRegOP); 244 EmitADD(OutStreamer, MCRegOP, RegO7, MCRegOP); 245} 246 247void SparcAsmPrinter::EmitInstruction(const MachineInstr *MI) 248{ 249 250 switch (MI->getOpcode()) { 251 default: break; 252 case TargetOpcode::DBG_VALUE: 253 // FIXME: Debug Value. 254 return; 255 case SP::GETPCX: 256 LowerGETPCXAndEmitMCInsts(MI); 257 return; 258 } 259 MachineBasicBlock::const_instr_iterator I = MI; 260 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 261 do { 262 MCInst TmpInst; 263 LowerSparcMachineInstrToMCInst(I, TmpInst, *this); 264 OutStreamer.EmitInstruction(TmpInst); 265 } while ((++I != E) && I->isInsideBundle()); // Delay slot check. 266} 267 |
268void SparcAsmPrinter::EmitFunctionBodyStart() { 269 if (!TM.getSubtarget<SparcSubtarget>().is64Bit()) 270 return; 271 272 const MachineRegisterInfo &MRI = MF->getRegInfo(); 273 const unsigned globalRegs[] = { SP::G2, SP::G3, SP::G6, SP::G7, 0 }; 274 for (unsigned i = 0; globalRegs[i] != 0; ++i) { 275 unsigned reg = globalRegs[i]; 276 if (MRI.use_empty(reg)) 277 continue;
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93 EmitGlobalRegisterDecl(reg);
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278 279 if (reg == SP::G6 || reg == SP::G7) 280 getTargetStreamer().emitSparcRegisterIgnore(reg); 281 else 282 getTargetStreamer().emitSparcRegisterScratch(reg); |
283 } 284} 285 286void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum, 287 raw_ostream &O) { 288 const MachineOperand &MO = MI->getOperand (opNum);
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100 unsigned TF = MO.getTargetFlags();
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289 SparcMCExpr::VariantKind TF = (SparcMCExpr::VariantKind) MO.getTargetFlags(); 290 |
291#ifndef NDEBUG 292 // Verify the target flags. 293 if (MO.isGlobal() || MO.isSymbol() || MO.isCPI()) { 294 if (MI->getOpcode() == SP::CALL)
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105 assert(TF == SPII::MO_NO_FLAG &&
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295 assert(TF == SparcMCExpr::VK_Sparc_None && |
296 "Cannot handle target flags on call address");
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107 else if (MI->getOpcode() == SP::SETHIi)
108 assert((TF == SPII::MO_HI || TF == SPII::MO_H44 || TF == SPII::MO_HH
109 || TF == SPII::MO_TLS_GD_HI22
110 || TF == SPII::MO_TLS_LDM_HI22
111 || TF == SPII::MO_TLS_LDO_HIX22
112 || TF == SPII::MO_TLS_IE_HI22
113 || TF == SPII::MO_TLS_LE_HIX22) &&
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297 else if (MI->getOpcode() == SP::SETHIi || MI->getOpcode() == SP::SETHIXi) 298 assert((TF == SparcMCExpr::VK_Sparc_HI 299 || TF == SparcMCExpr::VK_Sparc_H44 300 || TF == SparcMCExpr::VK_Sparc_HH 301 || TF == SparcMCExpr::VK_Sparc_TLS_GD_HI22 302 || TF == SparcMCExpr::VK_Sparc_TLS_LDM_HI22 303 || TF == SparcMCExpr::VK_Sparc_TLS_LDO_HIX22 304 || TF == SparcMCExpr::VK_Sparc_TLS_IE_HI22 305 || TF == SparcMCExpr::VK_Sparc_TLS_LE_HIX22) && |
306 "Invalid target flags for address operand on sethi"); 307 else if (MI->getOpcode() == SP::TLS_CALL)
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116 assert((TF == SPII::MO_NO_FLAG
117 || TF == SPII::MO_TLS_GD_CALL
118 || TF == SPII::MO_TLS_LDM_CALL) &&
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308 assert((TF == SparcMCExpr::VK_Sparc_None 309 || TF == SparcMCExpr::VK_Sparc_TLS_GD_CALL 310 || TF == SparcMCExpr::VK_Sparc_TLS_LDM_CALL) && |
311 "Cannot handle target flags on tls call address"); 312 else if (MI->getOpcode() == SP::TLS_ADDrr)
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121 assert((TF == SPII::MO_TLS_GD_ADD || TF == SPII::MO_TLS_LDM_ADD
122 || TF == SPII::MO_TLS_LDO_ADD || TF == SPII::MO_TLS_IE_ADD) &&
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313 assert((TF == SparcMCExpr::VK_Sparc_TLS_GD_ADD 314 || TF == SparcMCExpr::VK_Sparc_TLS_LDM_ADD 315 || TF == SparcMCExpr::VK_Sparc_TLS_LDO_ADD 316 || TF == SparcMCExpr::VK_Sparc_TLS_IE_ADD) && |
317 "Cannot handle target flags on add for TLS"); 318 else if (MI->getOpcode() == SP::TLS_LDrr)
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125 assert(TF == SPII::MO_TLS_IE_LD &&
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319 assert(TF == SparcMCExpr::VK_Sparc_TLS_IE_LD && |
320 "Cannot handle target flags on ld for TLS"); 321 else if (MI->getOpcode() == SP::TLS_LDXrr)
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128 assert(TF == SPII::MO_TLS_IE_LDX &&
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322 assert(TF == SparcMCExpr::VK_Sparc_TLS_IE_LDX && |
323 "Cannot handle target flags on ldx for TLS");
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130 else if (MI->getOpcode() == SP::XORri)
131 assert((TF == SPII::MO_TLS_LDO_LOX10 || TF == SPII::MO_TLS_LE_LOX10) &&
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324 else if (MI->getOpcode() == SP::XORri || MI->getOpcode() == SP::XORXri) 325 assert((TF == SparcMCExpr::VK_Sparc_TLS_LDO_LOX10 326 || TF == SparcMCExpr::VK_Sparc_TLS_LE_LOX10) && |
327 "Cannot handle target flags on xor for TLS"); 328 else
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134 assert((TF == SPII::MO_LO || TF == SPII::MO_M44 || TF == SPII::MO_L44
135 || TF == SPII::MO_HM
136 || TF == SPII::MO_TLS_GD_LO10
137 || TF == SPII::MO_TLS_LDM_LO10
138 || TF == SPII::MO_TLS_IE_LO10 ) &&
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329 assert((TF == SparcMCExpr::VK_Sparc_LO 330 || TF == SparcMCExpr::VK_Sparc_M44 331 || TF == SparcMCExpr::VK_Sparc_L44 332 || TF == SparcMCExpr::VK_Sparc_HM 333 || TF == SparcMCExpr::VK_Sparc_TLS_GD_LO10 334 || TF == SparcMCExpr::VK_Sparc_TLS_LDM_LO10 335 || TF == SparcMCExpr::VK_Sparc_TLS_IE_LO10 ) && |
336 "Invalid target flags for small address operand"); 337 } 338#endif 339
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143 bool CloseParen = true;
144 switch (TF) {
145 default:
146 llvm_unreachable("Unknown target flags on operand");
147 case SPII::MO_NO_FLAG:
148 CloseParen = false;
149 break;
150 case SPII::MO_LO: O << "%lo("; break;
151 case SPII::MO_HI: O << "%hi("; break;
152 case SPII::MO_H44: O << "%h44("; break;
153 case SPII::MO_M44: O << "%m44("; break;
154 case SPII::MO_L44: O << "%l44("; break;
155 case SPII::MO_HH: O << "%hh("; break;
156 case SPII::MO_HM: O << "%hm("; break;
157 case SPII::MO_TLS_GD_HI22: O << "%tgd_hi22("; break;
158 case SPII::MO_TLS_GD_LO10: O << "%tgd_lo10("; break;
159 case SPII::MO_TLS_GD_ADD: O << "%tgd_add("; break;
160 case SPII::MO_TLS_GD_CALL: O << "%tgd_call("; break;
161 case SPII::MO_TLS_LDM_HI22: O << "%tldm_hi22("; break;
162 case SPII::MO_TLS_LDM_LO10: O << "%tldm_lo10("; break;
163 case SPII::MO_TLS_LDM_ADD: O << "%tldm_add("; break;
164 case SPII::MO_TLS_LDM_CALL: O << "%tldm_call("; break;
165 case SPII::MO_TLS_LDO_HIX22: O << "%tldo_hix22("; break;
166 case SPII::MO_TLS_LDO_LOX10: O << "%tldo_lox10("; break;
167 case SPII::MO_TLS_LDO_ADD: O << "%tldo_add("; break;
168 case SPII::MO_TLS_IE_HI22: O << "%tie_hi22("; break;
169 case SPII::MO_TLS_IE_LO10: O << "%tie_lo10("; break;
170 case SPII::MO_TLS_IE_LD: O << "%tie_ld("; break;
171 case SPII::MO_TLS_IE_LDX: O << "%tie_ldx("; break;
172 case SPII::MO_TLS_IE_ADD: O << "%tie_add("; break;
173 case SPII::MO_TLS_LE_HIX22: O << "%tle_hix22("; break;
174 case SPII::MO_TLS_LE_LOX10: O << "%tle_lox10("; break;
175 }
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340
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341 bool CloseParen = SparcMCExpr::printVariantKind(O, TF); 342 |
343 switch (MO.getType()) { 344 case MachineOperand::MO_Register: 345 O << "%" << StringRef(getRegisterName(MO.getReg())).lower(); 346 break; 347 348 case MachineOperand::MO_Immediate: 349 O << (int)MO.getImm(); 350 break; 351 case MachineOperand::MO_MachineBasicBlock: 352 O << *MO.getMBB()->getSymbol(); 353 return; 354 case MachineOperand::MO_GlobalAddress: 355 O << *getSymbol(MO.getGlobal()); 356 break; 357 case MachineOperand::MO_BlockAddress: 358 O << GetBlockAddressSymbol(MO.getBlockAddress())->getName(); 359 break; 360 case MachineOperand::MO_ExternalSymbol: 361 O << MO.getSymbolName(); 362 break; 363 case MachineOperand::MO_ConstantPoolIndex: 364 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_" 365 << MO.getIndex(); 366 break; 367 default: 368 llvm_unreachable("<unknown operand type>"); 369 } 370 if (CloseParen) O << ")"; 371} 372 373void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum, 374 raw_ostream &O, const char *Modifier) { 375 printOperand(MI, opNum, O); 376 377 // If this is an ADD operand, emit it like normal operands. 378 if (Modifier && !strcmp(Modifier, "arith")) { 379 O << ", "; 380 printOperand(MI, opNum+1, O); 381 return; 382 } 383 384 if (MI->getOperand(opNum+1).isReg() && 385 MI->getOperand(opNum+1).getReg() == SP::G0) 386 return; // don't print "+%g0" 387 if (MI->getOperand(opNum+1).isImm() && 388 MI->getOperand(opNum+1).getImm() == 0) 389 return; // don't print "+0" 390 391 O << "+"; 392 printOperand(MI, opNum+1, O); 393} 394
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229bool SparcAsmPrinter::printGetPCX(const MachineInstr *MI, unsigned opNum,
230 raw_ostream &O) {
231 std::string operand = "";
232 const MachineOperand &MO = MI->getOperand(opNum);
233 switch (MO.getType()) {
234 default: llvm_unreachable("Operand is not a register");
235 case MachineOperand::MO_Register:
236 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
237 "Operand is not a physical register ");
238 assert(MO.getReg() != SP::O7 &&
239 "%o7 is assigned as destination for getpcx!");
240 operand = "%" + StringRef(getRegisterName(MO.getReg())).lower();
241 break;
242 }
243
244 unsigned mfNum = MI->getParent()->getParent()->getFunctionNumber();
245 unsigned bbNum = MI->getParent()->getNumber();
246
247 O << '\n' << ".LLGETPCH" << mfNum << '_' << bbNum << ":\n";
248 O << "\tcall\t.LLGETPC" << mfNum << '_' << bbNum << '\n' ;
249
250 O << "\t sethi\t"
251 << "%hi(_GLOBAL_OFFSET_TABLE_+(.-.LLGETPCH" << mfNum << '_' << bbNum
252 << ")), " << operand << '\n' ;
253
254 O << ".LLGETPC" << mfNum << '_' << bbNum << ":\n" ;
255 O << "\tor\t" << operand
256 << ", %lo(_GLOBAL_OFFSET_TABLE_+(.-.LLGETPCH" << mfNum << '_' << bbNum
257 << ")), " << operand << '\n';
258 O << "\tadd\t" << operand << ", %o7, " << operand << '\n';
259
260 return true;
261}
262
263void SparcAsmPrinter::printCCOperand(const MachineInstr *MI, int opNum,
264 raw_ostream &O) {
265 int CC = (int)MI->getOperand(opNum).getImm();
266 O << SPARCCondCodeToString((SPCC::CondCodes)CC);
267}
268
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395/// PrintAsmOperand - Print out an operand for an inline asm expression. 396/// 397bool SparcAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, 398 unsigned AsmVariant, 399 const char *ExtraCode, 400 raw_ostream &O) { 401 if (ExtraCode && ExtraCode[0]) { 402 if (ExtraCode[1] != 0) return true; // Unknown modifier. 403 404 switch (ExtraCode[0]) { 405 default: 406 // See if this is a generic print operand 407 return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O); 408 case 'r': 409 break; 410 } 411 } 412 413 printOperand(MI, OpNo, O); 414 415 return false; 416} 417 418bool SparcAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, 419 unsigned OpNo, unsigned AsmVariant, 420 const char *ExtraCode, 421 raw_ostream &O) { 422 if (ExtraCode && ExtraCode[0]) 423 return true; // Unknown modifier 424 425 O << '['; 426 printMemOperand(MI, OpNo, O); 427 O << ']'; 428 429 return false; 430} 431
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306/// isBlockOnlyReachableByFallthough - Return true if the basic block has
307/// exactly one predecessor and the control transfer mechanism between
308/// the predecessor and this block is a fall-through.
309///
310/// This overrides AsmPrinter's implementation to handle delay slots.
311bool SparcAsmPrinter::
312isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const {
313 // If this is a landing pad, it isn't a fall through. If it has no preds,
314 // then nothing falls through to it.
315 if (MBB->isLandingPad() || MBB->pred_empty())
316 return false;
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432void SparcAsmPrinter::EmitEndOfAsmFile(Module &M) { 433 const TargetLoweringObjectFileELF &TLOFELF = 434 static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering()); 435 MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>(); |
436
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318 // If there isn't exactly one predecessor, it can't be a fall through.
319 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
320 ++PI2;
321 if (PI2 != MBB->pred_end())
322 return false;
323
324 // The predecessor has to be immediately before this block.
325 const MachineBasicBlock *Pred = *PI;
326
327 if (!Pred->isLayoutSuccessor(MBB))
328 return false;
329
330 // Check if the last terminator is an unconditional branch.
331 MachineBasicBlock::const_iterator I = Pred->end();
332 while (I != Pred->begin() && !(--I)->isTerminator())
333 ; // Noop
334 return I == Pred->end() || !I->isBarrier();
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437 // Generate stubs for global variables. 438 MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList(); 439 if (!Stubs.empty()) { 440 OutStreamer.SwitchSection(TLOFELF.getDataSection()); 441 unsigned PtrSize = TM.getDataLayout()->getPointerSize(0); 442 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) { 443 OutStreamer.EmitLabel(Stubs[i].first); 444 OutStreamer.EmitSymbolValue(Stubs[i].second.getPointer(), PtrSize); 445 } 446 } |
447} 448 449// Force static initialization. 450extern "C" void LLVMInitializeSparcAsmPrinter() { 451 RegisterAsmPrinter<SparcAsmPrinter> X(TheSparcTarget); 452 RegisterAsmPrinter<SparcAsmPrinter> Y(TheSparcV9Target); 453}
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