19c19,21
< #include "MCTargetDesc/SparcBaseInfo.h"
---
> #include "SparcTargetStreamer.h"
> #include "InstPrinter/SparcInstPrinter.h"
> #include "MCTargetDesc/SparcMCExpr.h"
22a25
> #include "llvm/CodeGen/MachineModuleInfoImpls.h"
23a27
> #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
24a29,30
> #include "llvm/MC/MCContext.h"
> #include "llvm/MC/MCInst.h"
33a40,42
> SparcTargetStreamer &getTargetStreamer() {
> return static_cast<SparcTargetStreamer&>(OutStreamer.getTargetStreamer());
> }
48,52c57,61
< virtual void EmitInstruction(const MachineInstr *MI) {
< SmallString<128> Str;
< raw_svector_ostream OS(Str);
< printInstruction(MI, OS);
< OutStreamer.EmitRawText(OS.str());
---
> virtual void EmitInstruction(const MachineInstr *MI);
> virtual void EmitEndOfAsmFile(Module &M);
>
> static const char *getRegisterName(unsigned RegNo) {
> return SparcInstPrinter::getRegisterName(RegNo);
54,55d62
< void printInstruction(const MachineInstr *MI, raw_ostream &OS);// autogen'd.
< static const char *getRegisterName(unsigned RegNo);
64c71
< bool printGetPCX(const MachineInstr *MI, unsigned OpNo, raw_ostream &OS);
---
> void LowerGETPCXAndEmitMCInsts(const MachineInstr *MI);
66,77d72
< virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB)
< const;
< void EmitGlobalRegisterDecl(unsigned reg) {
< SmallString<128> Str;
< raw_svector_ostream OS(Str);
< OS << "\t.register "
< << "%" << StringRef(getRegisterName(reg)).lower()
< << ", "
< << ((reg == SP::G6 || reg == SP::G7)? "#ignore" : "#scratch");
< OutStreamer.EmitRawText(OS.str());
< }
<
81c76,81
< #include "SparcGenAsmWriter.inc"
---
> static MCOperand createSparcMCOperand(SparcMCExpr::VariantKind Kind,
> MCSymbol *Sym, MCContext &OutContext) {
> const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::Create(Sym,
> OutContext);
> const SparcMCExpr *expr = SparcMCExpr::Create(Kind, MCSym, OutContext);
> return MCOperand::CreateExpr(expr);
82a83,267
> }
> static MCOperand createPCXCallOP(MCSymbol *Label,
> MCContext &OutContext) {
> return createSparcMCOperand(SparcMCExpr::VK_Sparc_None, Label, OutContext);
> }
>
> static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind,
> MCSymbol *GOTLabel, MCSymbol *StartLabel,
> MCSymbol *CurLabel,
> MCContext &OutContext)
> {
> const MCSymbolRefExpr *GOT = MCSymbolRefExpr::Create(GOTLabel, OutContext);
> const MCSymbolRefExpr *Start = MCSymbolRefExpr::Create(StartLabel,
> OutContext);
> const MCSymbolRefExpr *Cur = MCSymbolRefExpr::Create(CurLabel,
> OutContext);
>
> const MCBinaryExpr *Sub = MCBinaryExpr::CreateSub(Cur, Start, OutContext);
> const MCBinaryExpr *Add = MCBinaryExpr::CreateAdd(GOT, Sub, OutContext);
> const SparcMCExpr *expr = SparcMCExpr::Create(Kind,
> Add, OutContext);
> return MCOperand::CreateExpr(expr);
> }
>
> static void EmitCall(MCStreamer &OutStreamer,
> MCOperand &Callee)
> {
> MCInst CallInst;
> CallInst.setOpcode(SP::CALL);
> CallInst.addOperand(Callee);
> OutStreamer.EmitInstruction(CallInst);
> }
>
> static void EmitSETHI(MCStreamer &OutStreamer,
> MCOperand &Imm, MCOperand &RD)
> {
> MCInst SETHIInst;
> SETHIInst.setOpcode(SP::SETHIi);
> SETHIInst.addOperand(RD);
> SETHIInst.addOperand(Imm);
> OutStreamer.EmitInstruction(SETHIInst);
> }
>
> static void EmitBinary(MCStreamer &OutStreamer, unsigned Opcode,
> MCOperand &RS1, MCOperand &Src2, MCOperand &RD)
> {
> MCInst Inst;
> Inst.setOpcode(Opcode);
> Inst.addOperand(RD);
> Inst.addOperand(RS1);
> Inst.addOperand(Src2);
> OutStreamer.EmitInstruction(Inst);
> }
>
> static void EmitOR(MCStreamer &OutStreamer,
> MCOperand &RS1, MCOperand &Imm, MCOperand &RD) {
> EmitBinary(OutStreamer, SP::ORri, RS1, Imm, RD);
> }
>
> static void EmitADD(MCStreamer &OutStreamer,
> MCOperand &RS1, MCOperand &RS2, MCOperand &RD) {
> EmitBinary(OutStreamer, SP::ADDrr, RS1, RS2, RD);
> }
>
> static void EmitSHL(MCStreamer &OutStreamer,
> MCOperand &RS1, MCOperand &Imm, MCOperand &RD) {
> EmitBinary(OutStreamer, SP::SLLri, RS1, Imm, RD);
> }
>
>
> static void EmitHiLo(MCStreamer &OutStreamer, MCSymbol *GOTSym,
> SparcMCExpr::VariantKind HiKind,
> SparcMCExpr::VariantKind LoKind,
> MCOperand &RD,
> MCContext &OutContext) {
>
> MCOperand hi = createSparcMCOperand(HiKind, GOTSym, OutContext);
> MCOperand lo = createSparcMCOperand(LoKind, GOTSym, OutContext);
> EmitSETHI(OutStreamer, hi, RD);
> EmitOR(OutStreamer, RD, lo, RD);
> }
>
> void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI)
> {
> MCSymbol *GOTLabel =
> OutContext.GetOrCreateSymbol(Twine("_GLOBAL_OFFSET_TABLE_"));
>
> const MachineOperand &MO = MI->getOperand(0);
> assert(MO.getReg() != SP::O7 &&
> "%o7 is assigned as destination for getpcx!");
>
> MCOperand MCRegOP = MCOperand::CreateReg(MO.getReg());
>
>
> if (TM.getRelocationModel() != Reloc::PIC_) {
> // Just load the address of GOT to MCRegOP.
> switch(TM.getCodeModel()) {
> default:
> llvm_unreachable("Unsupported absolute code model");
> case CodeModel::Small:
> EmitHiLo(OutStreamer, GOTLabel,
> SparcMCExpr::VK_Sparc_HI, SparcMCExpr::VK_Sparc_LO,
> MCRegOP, OutContext);
> break;
> case CodeModel::Medium: {
> EmitHiLo(OutStreamer, GOTLabel,
> SparcMCExpr::VK_Sparc_H44, SparcMCExpr::VK_Sparc_M44,
> MCRegOP, OutContext);
> MCOperand imm = MCOperand::CreateExpr(MCConstantExpr::Create(12,
> OutContext));
> EmitSHL(OutStreamer, MCRegOP, imm, MCRegOP);
> MCOperand lo = createSparcMCOperand(SparcMCExpr::VK_Sparc_L44,
> GOTLabel, OutContext);
> EmitOR(OutStreamer, MCRegOP, lo, MCRegOP);
> break;
> }
> case CodeModel::Large: {
> EmitHiLo(OutStreamer, GOTLabel,
> SparcMCExpr::VK_Sparc_HH, SparcMCExpr::VK_Sparc_HM,
> MCRegOP, OutContext);
> MCOperand imm = MCOperand::CreateExpr(MCConstantExpr::Create(32,
> OutContext));
> EmitSHL(OutStreamer, MCRegOP, imm, MCRegOP);
> // Use register %o7 to load the lower 32 bits.
> MCOperand RegO7 = MCOperand::CreateReg(SP::O7);
> EmitHiLo(OutStreamer, GOTLabel,
> SparcMCExpr::VK_Sparc_HI, SparcMCExpr::VK_Sparc_LO,
> RegO7, OutContext);
> EmitADD(OutStreamer, MCRegOP, RegO7, MCRegOP);
> }
> }
> return;
> }
>
> MCSymbol *StartLabel = OutContext.CreateTempSymbol();
> MCSymbol *EndLabel = OutContext.CreateTempSymbol();
> MCSymbol *SethiLabel = OutContext.CreateTempSymbol();
>
> MCOperand RegO7 = MCOperand::CreateReg(SP::O7);
>
> // <StartLabel>:
> // call <EndLabel>
> // <SethiLabel>:
> // sethi %hi(_GLOBAL_OFFSET_TABLE_+(<SethiLabel>-<StartLabel>)), <MO>
> // <EndLabel>:
> // or <MO>, %lo(_GLOBAL_OFFSET_TABLE_+(<EndLabel>-<StartLabel>))), <MO>
> // add <MO>, %o7, <MO>
>
> OutStreamer.EmitLabel(StartLabel);
> MCOperand Callee = createPCXCallOP(EndLabel, OutContext);
> EmitCall(OutStreamer, Callee);
> OutStreamer.EmitLabel(SethiLabel);
> MCOperand hiImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_PC22,
> GOTLabel, StartLabel, SethiLabel,
> OutContext);
> EmitSETHI(OutStreamer, hiImm, MCRegOP);
> OutStreamer.EmitLabel(EndLabel);
> MCOperand loImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_PC10,
> GOTLabel, StartLabel, EndLabel,
> OutContext);
> EmitOR(OutStreamer, MCRegOP, loImm, MCRegOP);
> EmitADD(OutStreamer, MCRegOP, RegO7, MCRegOP);
> }
>
> void SparcAsmPrinter::EmitInstruction(const MachineInstr *MI)
> {
>
> switch (MI->getOpcode()) {
> default: break;
> case TargetOpcode::DBG_VALUE:
> // FIXME: Debug Value.
> return;
> case SP::GETPCX:
> LowerGETPCXAndEmitMCInsts(MI);
> return;
> }
> MachineBasicBlock::const_instr_iterator I = MI;
> MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
> do {
> MCInst TmpInst;
> LowerSparcMachineInstrToMCInst(I, TmpInst, *this);
> OutStreamer.EmitInstruction(TmpInst);
> } while ((++I != E) && I->isInsideBundle()); // Delay slot check.
> }
>
93c278,282
< EmitGlobalRegisterDecl(reg);
---
>
> if (reg == SP::G6 || reg == SP::G7)
> getTargetStreamer().emitSparcRegisterIgnore(reg);
> else
> getTargetStreamer().emitSparcRegisterScratch(reg);
100c289,290
< unsigned TF = MO.getTargetFlags();
---
> SparcMCExpr::VariantKind TF = (SparcMCExpr::VariantKind) MO.getTargetFlags();
>
105c295
< assert(TF == SPII::MO_NO_FLAG &&
---
> assert(TF == SparcMCExpr::VK_Sparc_None &&
107,113c297,305
< else if (MI->getOpcode() == SP::SETHIi)
< assert((TF == SPII::MO_HI || TF == SPII::MO_H44 || TF == SPII::MO_HH
< || TF == SPII::MO_TLS_GD_HI22
< || TF == SPII::MO_TLS_LDM_HI22
< || TF == SPII::MO_TLS_LDO_HIX22
< || TF == SPII::MO_TLS_IE_HI22
< || TF == SPII::MO_TLS_LE_HIX22) &&
---
> else if (MI->getOpcode() == SP::SETHIi || MI->getOpcode() == SP::SETHIXi)
> assert((TF == SparcMCExpr::VK_Sparc_HI
> || TF == SparcMCExpr::VK_Sparc_H44
> || TF == SparcMCExpr::VK_Sparc_HH
> || TF == SparcMCExpr::VK_Sparc_TLS_GD_HI22
> || TF == SparcMCExpr::VK_Sparc_TLS_LDM_HI22
> || TF == SparcMCExpr::VK_Sparc_TLS_LDO_HIX22
> || TF == SparcMCExpr::VK_Sparc_TLS_IE_HI22
> || TF == SparcMCExpr::VK_Sparc_TLS_LE_HIX22) &&
116,118c308,310
< assert((TF == SPII::MO_NO_FLAG
< || TF == SPII::MO_TLS_GD_CALL
< || TF == SPII::MO_TLS_LDM_CALL) &&
---
> assert((TF == SparcMCExpr::VK_Sparc_None
> || TF == SparcMCExpr::VK_Sparc_TLS_GD_CALL
> || TF == SparcMCExpr::VK_Sparc_TLS_LDM_CALL) &&
121,122c313,316
< assert((TF == SPII::MO_TLS_GD_ADD || TF == SPII::MO_TLS_LDM_ADD
< || TF == SPII::MO_TLS_LDO_ADD || TF == SPII::MO_TLS_IE_ADD) &&
---
> assert((TF == SparcMCExpr::VK_Sparc_TLS_GD_ADD
> || TF == SparcMCExpr::VK_Sparc_TLS_LDM_ADD
> || TF == SparcMCExpr::VK_Sparc_TLS_LDO_ADD
> || TF == SparcMCExpr::VK_Sparc_TLS_IE_ADD) &&
125c319
< assert(TF == SPII::MO_TLS_IE_LD &&
---
> assert(TF == SparcMCExpr::VK_Sparc_TLS_IE_LD &&
128c322
< assert(TF == SPII::MO_TLS_IE_LDX &&
---
> assert(TF == SparcMCExpr::VK_Sparc_TLS_IE_LDX &&
130,131c324,326
< else if (MI->getOpcode() == SP::XORri)
< assert((TF == SPII::MO_TLS_LDO_LOX10 || TF == SPII::MO_TLS_LE_LOX10) &&
---
> else if (MI->getOpcode() == SP::XORri || MI->getOpcode() == SP::XORXri)
> assert((TF == SparcMCExpr::VK_Sparc_TLS_LDO_LOX10
> || TF == SparcMCExpr::VK_Sparc_TLS_LE_LOX10) &&
134,138c329,335
< assert((TF == SPII::MO_LO || TF == SPII::MO_M44 || TF == SPII::MO_L44
< || TF == SPII::MO_HM
< || TF == SPII::MO_TLS_GD_LO10
< || TF == SPII::MO_TLS_LDM_LO10
< || TF == SPII::MO_TLS_IE_LO10 ) &&
---
> assert((TF == SparcMCExpr::VK_Sparc_LO
> || TF == SparcMCExpr::VK_Sparc_M44
> || TF == SparcMCExpr::VK_Sparc_L44
> || TF == SparcMCExpr::VK_Sparc_HM
> || TF == SparcMCExpr::VK_Sparc_TLS_GD_LO10
> || TF == SparcMCExpr::VK_Sparc_TLS_LDM_LO10
> || TF == SparcMCExpr::VK_Sparc_TLS_IE_LO10 ) &&
143,175d339
< bool CloseParen = true;
< switch (TF) {
< default:
< llvm_unreachable("Unknown target flags on operand");
< case SPII::MO_NO_FLAG:
< CloseParen = false;
< break;
< case SPII::MO_LO: O << "%lo("; break;
< case SPII::MO_HI: O << "%hi("; break;
< case SPII::MO_H44: O << "%h44("; break;
< case SPII::MO_M44: O << "%m44("; break;
< case SPII::MO_L44: O << "%l44("; break;
< case SPII::MO_HH: O << "%hh("; break;
< case SPII::MO_HM: O << "%hm("; break;
< case SPII::MO_TLS_GD_HI22: O << "%tgd_hi22("; break;
< case SPII::MO_TLS_GD_LO10: O << "%tgd_lo10("; break;
< case SPII::MO_TLS_GD_ADD: O << "%tgd_add("; break;
< case SPII::MO_TLS_GD_CALL: O << "%tgd_call("; break;
< case SPII::MO_TLS_LDM_HI22: O << "%tldm_hi22("; break;
< case SPII::MO_TLS_LDM_LO10: O << "%tldm_lo10("; break;
< case SPII::MO_TLS_LDM_ADD: O << "%tldm_add("; break;
< case SPII::MO_TLS_LDM_CALL: O << "%tldm_call("; break;
< case SPII::MO_TLS_LDO_HIX22: O << "%tldo_hix22("; break;
< case SPII::MO_TLS_LDO_LOX10: O << "%tldo_lox10("; break;
< case SPII::MO_TLS_LDO_ADD: O << "%tldo_add("; break;
< case SPII::MO_TLS_IE_HI22: O << "%tie_hi22("; break;
< case SPII::MO_TLS_IE_LO10: O << "%tie_lo10("; break;
< case SPII::MO_TLS_IE_LD: O << "%tie_ld("; break;
< case SPII::MO_TLS_IE_LDX: O << "%tie_ldx("; break;
< case SPII::MO_TLS_IE_ADD: O << "%tie_add("; break;
< case SPII::MO_TLS_LE_HIX22: O << "%tle_hix22("; break;
< case SPII::MO_TLS_LE_LOX10: O << "%tle_lox10("; break;
< }
176a341,342
> bool CloseParen = SparcMCExpr::printVariantKind(O, TF);
>
229,268d394
< bool SparcAsmPrinter::printGetPCX(const MachineInstr *MI, unsigned opNum,
< raw_ostream &O) {
< std::string operand = "";
< const MachineOperand &MO = MI->getOperand(opNum);
< switch (MO.getType()) {
< default: llvm_unreachable("Operand is not a register");
< case MachineOperand::MO_Register:
< assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
< "Operand is not a physical register ");
< assert(MO.getReg() != SP::O7 &&
< "%o7 is assigned as destination for getpcx!");
< operand = "%" + StringRef(getRegisterName(MO.getReg())).lower();
< break;
< }
<
< unsigned mfNum = MI->getParent()->getParent()->getFunctionNumber();
< unsigned bbNum = MI->getParent()->getNumber();
<
< O << '\n' << ".LLGETPCH" << mfNum << '_' << bbNum << ":\n";
< O << "\tcall\t.LLGETPC" << mfNum << '_' << bbNum << '\n' ;
<
< O << "\t sethi\t"
< << "%hi(_GLOBAL_OFFSET_TABLE_+(.-.LLGETPCH" << mfNum << '_' << bbNum
< << ")), " << operand << '\n' ;
<
< O << ".LLGETPC" << mfNum << '_' << bbNum << ":\n" ;
< O << "\tor\t" << operand
< << ", %lo(_GLOBAL_OFFSET_TABLE_+(.-.LLGETPCH" << mfNum << '_' << bbNum
< << ")), " << operand << '\n';
< O << "\tadd\t" << operand << ", %o7, " << operand << '\n';
<
< return true;
< }
<
< void SparcAsmPrinter::printCCOperand(const MachineInstr *MI, int opNum,
< raw_ostream &O) {
< int CC = (int)MI->getOperand(opNum).getImm();
< O << SPARCCondCodeToString((SPCC::CondCodes)CC);
< }
<
306,316c432,435
< /// isBlockOnlyReachableByFallthough - Return true if the basic block has
< /// exactly one predecessor and the control transfer mechanism between
< /// the predecessor and this block is a fall-through.
< ///
< /// This overrides AsmPrinter's implementation to handle delay slots.
< bool SparcAsmPrinter::
< isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const {
< // If this is a landing pad, it isn't a fall through. If it has no preds,
< // then nothing falls through to it.
< if (MBB->isLandingPad() || MBB->pred_empty())
< return false;
---
> void SparcAsmPrinter::EmitEndOfAsmFile(Module &M) {
> const TargetLoweringObjectFileELF &TLOFELF =
> static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering());
> MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>();
318,334c437,446
< // If there isn't exactly one predecessor, it can't be a fall through.
< MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
< ++PI2;
< if (PI2 != MBB->pred_end())
< return false;
<
< // The predecessor has to be immediately before this block.
< const MachineBasicBlock *Pred = *PI;
<
< if (!Pred->isLayoutSuccessor(MBB))
< return false;
<
< // Check if the last terminator is an unconditional branch.
< MachineBasicBlock::const_iterator I = Pred->end();
< while (I != Pred->begin() && !(--I)->isTerminator())
< ; // Noop
< return I == Pred->end() || !I->isBarrier();
---
> // Generate stubs for global variables.
> MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList();
> if (!Stubs.empty()) {
> OutStreamer.SwitchSection(TLOFELF.getDataSection());
> unsigned PtrSize = TM.getDataLayout()->getPointerSize(0);
> for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
> OutStreamer.EmitLabel(Stubs[i].first);
> OutStreamer.EmitSymbolValue(Stubs[i].second.getPointer(), PtrSize);
> }
> }
< #include "MCTargetDesc/SparcBaseInfo.h"
---
> #include "SparcTargetStreamer.h"
> #include "InstPrinter/SparcInstPrinter.h"
> #include "MCTargetDesc/SparcMCExpr.h"
22a25
> #include "llvm/CodeGen/MachineModuleInfoImpls.h"
23a27
> #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
24a29,30
> #include "llvm/MC/MCContext.h"
> #include "llvm/MC/MCInst.h"
33a40,42
> SparcTargetStreamer &getTargetStreamer() {
> return static_cast<SparcTargetStreamer&>(OutStreamer.getTargetStreamer());
> }
48,52c57,61
< virtual void EmitInstruction(const MachineInstr *MI) {
< SmallString<128> Str;
< raw_svector_ostream OS(Str);
< printInstruction(MI, OS);
< OutStreamer.EmitRawText(OS.str());
---
> virtual void EmitInstruction(const MachineInstr *MI);
> virtual void EmitEndOfAsmFile(Module &M);
>
> static const char *getRegisterName(unsigned RegNo) {
> return SparcInstPrinter::getRegisterName(RegNo);
54,55d62
< void printInstruction(const MachineInstr *MI, raw_ostream &OS);// autogen'd.
< static const char *getRegisterName(unsigned RegNo);
64c71
< bool printGetPCX(const MachineInstr *MI, unsigned OpNo, raw_ostream &OS);
---
> void LowerGETPCXAndEmitMCInsts(const MachineInstr *MI);
66,77d72
< virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB)
< const;
< void EmitGlobalRegisterDecl(unsigned reg) {
< SmallString<128> Str;
< raw_svector_ostream OS(Str);
< OS << "\t.register "
< << "%" << StringRef(getRegisterName(reg)).lower()
< << ", "
< << ((reg == SP::G6 || reg == SP::G7)? "#ignore" : "#scratch");
< OutStreamer.EmitRawText(OS.str());
< }
<
81c76,81
< #include "SparcGenAsmWriter.inc"
---
> static MCOperand createSparcMCOperand(SparcMCExpr::VariantKind Kind,
> MCSymbol *Sym, MCContext &OutContext) {
> const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::Create(Sym,
> OutContext);
> const SparcMCExpr *expr = SparcMCExpr::Create(Kind, MCSym, OutContext);
> return MCOperand::CreateExpr(expr);
82a83,267
> }
> static MCOperand createPCXCallOP(MCSymbol *Label,
> MCContext &OutContext) {
> return createSparcMCOperand(SparcMCExpr::VK_Sparc_None, Label, OutContext);
> }
>
> static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind,
> MCSymbol *GOTLabel, MCSymbol *StartLabel,
> MCSymbol *CurLabel,
> MCContext &OutContext)
> {
> const MCSymbolRefExpr *GOT = MCSymbolRefExpr::Create(GOTLabel, OutContext);
> const MCSymbolRefExpr *Start = MCSymbolRefExpr::Create(StartLabel,
> OutContext);
> const MCSymbolRefExpr *Cur = MCSymbolRefExpr::Create(CurLabel,
> OutContext);
>
> const MCBinaryExpr *Sub = MCBinaryExpr::CreateSub(Cur, Start, OutContext);
> const MCBinaryExpr *Add = MCBinaryExpr::CreateAdd(GOT, Sub, OutContext);
> const SparcMCExpr *expr = SparcMCExpr::Create(Kind,
> Add, OutContext);
> return MCOperand::CreateExpr(expr);
> }
>
> static void EmitCall(MCStreamer &OutStreamer,
> MCOperand &Callee)
> {
> MCInst CallInst;
> CallInst.setOpcode(SP::CALL);
> CallInst.addOperand(Callee);
> OutStreamer.EmitInstruction(CallInst);
> }
>
> static void EmitSETHI(MCStreamer &OutStreamer,
> MCOperand &Imm, MCOperand &RD)
> {
> MCInst SETHIInst;
> SETHIInst.setOpcode(SP::SETHIi);
> SETHIInst.addOperand(RD);
> SETHIInst.addOperand(Imm);
> OutStreamer.EmitInstruction(SETHIInst);
> }
>
> static void EmitBinary(MCStreamer &OutStreamer, unsigned Opcode,
> MCOperand &RS1, MCOperand &Src2, MCOperand &RD)
> {
> MCInst Inst;
> Inst.setOpcode(Opcode);
> Inst.addOperand(RD);
> Inst.addOperand(RS1);
> Inst.addOperand(Src2);
> OutStreamer.EmitInstruction(Inst);
> }
>
> static void EmitOR(MCStreamer &OutStreamer,
> MCOperand &RS1, MCOperand &Imm, MCOperand &RD) {
> EmitBinary(OutStreamer, SP::ORri, RS1, Imm, RD);
> }
>
> static void EmitADD(MCStreamer &OutStreamer,
> MCOperand &RS1, MCOperand &RS2, MCOperand &RD) {
> EmitBinary(OutStreamer, SP::ADDrr, RS1, RS2, RD);
> }
>
> static void EmitSHL(MCStreamer &OutStreamer,
> MCOperand &RS1, MCOperand &Imm, MCOperand &RD) {
> EmitBinary(OutStreamer, SP::SLLri, RS1, Imm, RD);
> }
>
>
> static void EmitHiLo(MCStreamer &OutStreamer, MCSymbol *GOTSym,
> SparcMCExpr::VariantKind HiKind,
> SparcMCExpr::VariantKind LoKind,
> MCOperand &RD,
> MCContext &OutContext) {
>
> MCOperand hi = createSparcMCOperand(HiKind, GOTSym, OutContext);
> MCOperand lo = createSparcMCOperand(LoKind, GOTSym, OutContext);
> EmitSETHI(OutStreamer, hi, RD);
> EmitOR(OutStreamer, RD, lo, RD);
> }
>
> void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI)
> {
> MCSymbol *GOTLabel =
> OutContext.GetOrCreateSymbol(Twine("_GLOBAL_OFFSET_TABLE_"));
>
> const MachineOperand &MO = MI->getOperand(0);
> assert(MO.getReg() != SP::O7 &&
> "%o7 is assigned as destination for getpcx!");
>
> MCOperand MCRegOP = MCOperand::CreateReg(MO.getReg());
>
>
> if (TM.getRelocationModel() != Reloc::PIC_) {
> // Just load the address of GOT to MCRegOP.
> switch(TM.getCodeModel()) {
> default:
> llvm_unreachable("Unsupported absolute code model");
> case CodeModel::Small:
> EmitHiLo(OutStreamer, GOTLabel,
> SparcMCExpr::VK_Sparc_HI, SparcMCExpr::VK_Sparc_LO,
> MCRegOP, OutContext);
> break;
> case CodeModel::Medium: {
> EmitHiLo(OutStreamer, GOTLabel,
> SparcMCExpr::VK_Sparc_H44, SparcMCExpr::VK_Sparc_M44,
> MCRegOP, OutContext);
> MCOperand imm = MCOperand::CreateExpr(MCConstantExpr::Create(12,
> OutContext));
> EmitSHL(OutStreamer, MCRegOP, imm, MCRegOP);
> MCOperand lo = createSparcMCOperand(SparcMCExpr::VK_Sparc_L44,
> GOTLabel, OutContext);
> EmitOR(OutStreamer, MCRegOP, lo, MCRegOP);
> break;
> }
> case CodeModel::Large: {
> EmitHiLo(OutStreamer, GOTLabel,
> SparcMCExpr::VK_Sparc_HH, SparcMCExpr::VK_Sparc_HM,
> MCRegOP, OutContext);
> MCOperand imm = MCOperand::CreateExpr(MCConstantExpr::Create(32,
> OutContext));
> EmitSHL(OutStreamer, MCRegOP, imm, MCRegOP);
> // Use register %o7 to load the lower 32 bits.
> MCOperand RegO7 = MCOperand::CreateReg(SP::O7);
> EmitHiLo(OutStreamer, GOTLabel,
> SparcMCExpr::VK_Sparc_HI, SparcMCExpr::VK_Sparc_LO,
> RegO7, OutContext);
> EmitADD(OutStreamer, MCRegOP, RegO7, MCRegOP);
> }
> }
> return;
> }
>
> MCSymbol *StartLabel = OutContext.CreateTempSymbol();
> MCSymbol *EndLabel = OutContext.CreateTempSymbol();
> MCSymbol *SethiLabel = OutContext.CreateTempSymbol();
>
> MCOperand RegO7 = MCOperand::CreateReg(SP::O7);
>
> // <StartLabel>:
> // call <EndLabel>
> // <SethiLabel>:
> // sethi %hi(_GLOBAL_OFFSET_TABLE_+(<SethiLabel>-<StartLabel>)), <MO>
> // <EndLabel>:
> // or <MO>, %lo(_GLOBAL_OFFSET_TABLE_+(<EndLabel>-<StartLabel>))), <MO>
> // add <MO>, %o7, <MO>
>
> OutStreamer.EmitLabel(StartLabel);
> MCOperand Callee = createPCXCallOP(EndLabel, OutContext);
> EmitCall(OutStreamer, Callee);
> OutStreamer.EmitLabel(SethiLabel);
> MCOperand hiImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_PC22,
> GOTLabel, StartLabel, SethiLabel,
> OutContext);
> EmitSETHI(OutStreamer, hiImm, MCRegOP);
> OutStreamer.EmitLabel(EndLabel);
> MCOperand loImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_PC10,
> GOTLabel, StartLabel, EndLabel,
> OutContext);
> EmitOR(OutStreamer, MCRegOP, loImm, MCRegOP);
> EmitADD(OutStreamer, MCRegOP, RegO7, MCRegOP);
> }
>
> void SparcAsmPrinter::EmitInstruction(const MachineInstr *MI)
> {
>
> switch (MI->getOpcode()) {
> default: break;
> case TargetOpcode::DBG_VALUE:
> // FIXME: Debug Value.
> return;
> case SP::GETPCX:
> LowerGETPCXAndEmitMCInsts(MI);
> return;
> }
> MachineBasicBlock::const_instr_iterator I = MI;
> MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
> do {
> MCInst TmpInst;
> LowerSparcMachineInstrToMCInst(I, TmpInst, *this);
> OutStreamer.EmitInstruction(TmpInst);
> } while ((++I != E) && I->isInsideBundle()); // Delay slot check.
> }
>
93c278,282
< EmitGlobalRegisterDecl(reg);
---
>
> if (reg == SP::G6 || reg == SP::G7)
> getTargetStreamer().emitSparcRegisterIgnore(reg);
> else
> getTargetStreamer().emitSparcRegisterScratch(reg);
100c289,290
< unsigned TF = MO.getTargetFlags();
---
> SparcMCExpr::VariantKind TF = (SparcMCExpr::VariantKind) MO.getTargetFlags();
>
105c295
< assert(TF == SPII::MO_NO_FLAG &&
---
> assert(TF == SparcMCExpr::VK_Sparc_None &&
107,113c297,305
< else if (MI->getOpcode() == SP::SETHIi)
< assert((TF == SPII::MO_HI || TF == SPII::MO_H44 || TF == SPII::MO_HH
< || TF == SPII::MO_TLS_GD_HI22
< || TF == SPII::MO_TLS_LDM_HI22
< || TF == SPII::MO_TLS_LDO_HIX22
< || TF == SPII::MO_TLS_IE_HI22
< || TF == SPII::MO_TLS_LE_HIX22) &&
---
> else if (MI->getOpcode() == SP::SETHIi || MI->getOpcode() == SP::SETHIXi)
> assert((TF == SparcMCExpr::VK_Sparc_HI
> || TF == SparcMCExpr::VK_Sparc_H44
> || TF == SparcMCExpr::VK_Sparc_HH
> || TF == SparcMCExpr::VK_Sparc_TLS_GD_HI22
> || TF == SparcMCExpr::VK_Sparc_TLS_LDM_HI22
> || TF == SparcMCExpr::VK_Sparc_TLS_LDO_HIX22
> || TF == SparcMCExpr::VK_Sparc_TLS_IE_HI22
> || TF == SparcMCExpr::VK_Sparc_TLS_LE_HIX22) &&
116,118c308,310
< assert((TF == SPII::MO_NO_FLAG
< || TF == SPII::MO_TLS_GD_CALL
< || TF == SPII::MO_TLS_LDM_CALL) &&
---
> assert((TF == SparcMCExpr::VK_Sparc_None
> || TF == SparcMCExpr::VK_Sparc_TLS_GD_CALL
> || TF == SparcMCExpr::VK_Sparc_TLS_LDM_CALL) &&
121,122c313,316
< assert((TF == SPII::MO_TLS_GD_ADD || TF == SPII::MO_TLS_LDM_ADD
< || TF == SPII::MO_TLS_LDO_ADD || TF == SPII::MO_TLS_IE_ADD) &&
---
> assert((TF == SparcMCExpr::VK_Sparc_TLS_GD_ADD
> || TF == SparcMCExpr::VK_Sparc_TLS_LDM_ADD
> || TF == SparcMCExpr::VK_Sparc_TLS_LDO_ADD
> || TF == SparcMCExpr::VK_Sparc_TLS_IE_ADD) &&
125c319
< assert(TF == SPII::MO_TLS_IE_LD &&
---
> assert(TF == SparcMCExpr::VK_Sparc_TLS_IE_LD &&
128c322
< assert(TF == SPII::MO_TLS_IE_LDX &&
---
> assert(TF == SparcMCExpr::VK_Sparc_TLS_IE_LDX &&
130,131c324,326
< else if (MI->getOpcode() == SP::XORri)
< assert((TF == SPII::MO_TLS_LDO_LOX10 || TF == SPII::MO_TLS_LE_LOX10) &&
---
> else if (MI->getOpcode() == SP::XORri || MI->getOpcode() == SP::XORXri)
> assert((TF == SparcMCExpr::VK_Sparc_TLS_LDO_LOX10
> || TF == SparcMCExpr::VK_Sparc_TLS_LE_LOX10) &&
134,138c329,335
< assert((TF == SPII::MO_LO || TF == SPII::MO_M44 || TF == SPII::MO_L44
< || TF == SPII::MO_HM
< || TF == SPII::MO_TLS_GD_LO10
< || TF == SPII::MO_TLS_LDM_LO10
< || TF == SPII::MO_TLS_IE_LO10 ) &&
---
> assert((TF == SparcMCExpr::VK_Sparc_LO
> || TF == SparcMCExpr::VK_Sparc_M44
> || TF == SparcMCExpr::VK_Sparc_L44
> || TF == SparcMCExpr::VK_Sparc_HM
> || TF == SparcMCExpr::VK_Sparc_TLS_GD_LO10
> || TF == SparcMCExpr::VK_Sparc_TLS_LDM_LO10
> || TF == SparcMCExpr::VK_Sparc_TLS_IE_LO10 ) &&
143,175d339
< bool CloseParen = true;
< switch (TF) {
< default:
< llvm_unreachable("Unknown target flags on operand");
< case SPII::MO_NO_FLAG:
< CloseParen = false;
< break;
< case SPII::MO_LO: O << "%lo("; break;
< case SPII::MO_HI: O << "%hi("; break;
< case SPII::MO_H44: O << "%h44("; break;
< case SPII::MO_M44: O << "%m44("; break;
< case SPII::MO_L44: O << "%l44("; break;
< case SPII::MO_HH: O << "%hh("; break;
< case SPII::MO_HM: O << "%hm("; break;
< case SPII::MO_TLS_GD_HI22: O << "%tgd_hi22("; break;
< case SPII::MO_TLS_GD_LO10: O << "%tgd_lo10("; break;
< case SPII::MO_TLS_GD_ADD: O << "%tgd_add("; break;
< case SPII::MO_TLS_GD_CALL: O << "%tgd_call("; break;
< case SPII::MO_TLS_LDM_HI22: O << "%tldm_hi22("; break;
< case SPII::MO_TLS_LDM_LO10: O << "%tldm_lo10("; break;
< case SPII::MO_TLS_LDM_ADD: O << "%tldm_add("; break;
< case SPII::MO_TLS_LDM_CALL: O << "%tldm_call("; break;
< case SPII::MO_TLS_LDO_HIX22: O << "%tldo_hix22("; break;
< case SPII::MO_TLS_LDO_LOX10: O << "%tldo_lox10("; break;
< case SPII::MO_TLS_LDO_ADD: O << "%tldo_add("; break;
< case SPII::MO_TLS_IE_HI22: O << "%tie_hi22("; break;
< case SPII::MO_TLS_IE_LO10: O << "%tie_lo10("; break;
< case SPII::MO_TLS_IE_LD: O << "%tie_ld("; break;
< case SPII::MO_TLS_IE_LDX: O << "%tie_ldx("; break;
< case SPII::MO_TLS_IE_ADD: O << "%tie_add("; break;
< case SPII::MO_TLS_LE_HIX22: O << "%tle_hix22("; break;
< case SPII::MO_TLS_LE_LOX10: O << "%tle_lox10("; break;
< }
176a341,342
> bool CloseParen = SparcMCExpr::printVariantKind(O, TF);
>
229,268d394
< bool SparcAsmPrinter::printGetPCX(const MachineInstr *MI, unsigned opNum,
< raw_ostream &O) {
< std::string operand = "";
< const MachineOperand &MO = MI->getOperand(opNum);
< switch (MO.getType()) {
< default: llvm_unreachable("Operand is not a register");
< case MachineOperand::MO_Register:
< assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
< "Operand is not a physical register ");
< assert(MO.getReg() != SP::O7 &&
< "%o7 is assigned as destination for getpcx!");
< operand = "%" + StringRef(getRegisterName(MO.getReg())).lower();
< break;
< }
<
< unsigned mfNum = MI->getParent()->getParent()->getFunctionNumber();
< unsigned bbNum = MI->getParent()->getNumber();
<
< O << '\n' << ".LLGETPCH" << mfNum << '_' << bbNum << ":\n";
< O << "\tcall\t.LLGETPC" << mfNum << '_' << bbNum << '\n' ;
<
< O << "\t sethi\t"
< << "%hi(_GLOBAL_OFFSET_TABLE_+(.-.LLGETPCH" << mfNum << '_' << bbNum
< << ")), " << operand << '\n' ;
<
< O << ".LLGETPC" << mfNum << '_' << bbNum << ":\n" ;
< O << "\tor\t" << operand
< << ", %lo(_GLOBAL_OFFSET_TABLE_+(.-.LLGETPCH" << mfNum << '_' << bbNum
< << ")), " << operand << '\n';
< O << "\tadd\t" << operand << ", %o7, " << operand << '\n';
<
< return true;
< }
<
< void SparcAsmPrinter::printCCOperand(const MachineInstr *MI, int opNum,
< raw_ostream &O) {
< int CC = (int)MI->getOperand(opNum).getImm();
< O << SPARCCondCodeToString((SPCC::CondCodes)CC);
< }
<
306,316c432,435
< /// isBlockOnlyReachableByFallthough - Return true if the basic block has
< /// exactly one predecessor and the control transfer mechanism between
< /// the predecessor and this block is a fall-through.
< ///
< /// This overrides AsmPrinter's implementation to handle delay slots.
< bool SparcAsmPrinter::
< isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const {
< // If this is a landing pad, it isn't a fall through. If it has no preds,
< // then nothing falls through to it.
< if (MBB->isLandingPad() || MBB->pred_empty())
< return false;
---
> void SparcAsmPrinter::EmitEndOfAsmFile(Module &M) {
> const TargetLoweringObjectFileELF &TLOFELF =
> static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering());
> MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>();
318,334c437,446
< // If there isn't exactly one predecessor, it can't be a fall through.
< MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
< ++PI2;
< if (PI2 != MBB->pred_end())
< return false;
<
< // The predecessor has to be immediately before this block.
< const MachineBasicBlock *Pred = *PI;
<
< if (!Pred->isLayoutSuccessor(MBB))
< return false;
<
< // Check if the last terminator is an unconditional branch.
< MachineBasicBlock::const_iterator I = Pred->end();
< while (I != Pred->begin() && !(--I)->isTerminator())
< ; // Noop
< return I == Pred->end() || !I->isBarrier();
---
> // Generate stubs for global variables.
> MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList();
> if (!Stubs.empty()) {
> OutStreamer.SwitchSection(TLOFELF.getDataSection());
> unsigned PtrSize = TM.getDataLayout()->getPointerSize(0);
> for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
> OutStreamer.EmitLabel(Stubs[i].first);
> OutStreamer.EmitSymbolValue(Stubs[i].second.getPointer(), PtrSize);
> }
> }