1//===-- SparcAsmPrinter.cpp - Sparc LLVM assembly writer ------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains a printer that converts from our internal representation
11// of machine-dependent LLVM code to GAS-format SPARC assembly language.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "asm-printer"
16#include "Sparc.h"
17#include "SparcInstrInfo.h"
18#include "SparcTargetMachine.h"
19#include "MCTargetDesc/SparcBaseInfo.h"
20#include "llvm/ADT/SmallString.h"
21#include "llvm/CodeGen/AsmPrinter.h"
22#include "llvm/CodeGen/MachineInstr.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/MC/MCAsmInfo.h"
25#include "llvm/MC/MCStreamer.h"
26#include "llvm/MC/MCSymbol.h"
27#include "llvm/Support/TargetRegistry.h"
28#include "llvm/Support/raw_ostream.h"
29#include "llvm/Target/Mangler.h"
30using namespace llvm;
31
32namespace {
33 class SparcAsmPrinter : public AsmPrinter {
34 public:
35 explicit SparcAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
36 : AsmPrinter(TM, Streamer) {}
37
38 virtual const char *getPassName() const {
39 return "Sparc Assembly Printer";
40 }
41
42 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
43 void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS,
44 const char *Modifier = 0);
45 void printCCOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
46
47 virtual void EmitFunctionBodyStart();
48 virtual void EmitInstruction(const MachineInstr *MI) {
49 SmallString<128> Str;
50 raw_svector_ostream OS(Str);
51 printInstruction(MI, OS);
52 OutStreamer.EmitRawText(OS.str());
53 }
54 void printInstruction(const MachineInstr *MI, raw_ostream &OS);// autogen'd.
55 static const char *getRegisterName(unsigned RegNo);
56
57 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
58 unsigned AsmVariant, const char *ExtraCode,
59 raw_ostream &O);
60 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
61 unsigned AsmVariant, const char *ExtraCode,
62 raw_ostream &O);
63
64 bool printGetPCX(const MachineInstr *MI, unsigned OpNo, raw_ostream &OS);
65
66 virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB)
67 const;
68 void EmitGlobalRegisterDecl(unsigned reg) {
69 SmallString<128> Str;
70 raw_svector_ostream OS(Str);
71 OS << "\t.register "
72 << "%" << StringRef(getRegisterName(reg)).lower()
73 << ", "
74 << ((reg == SP::G6 || reg == SP::G7)? "#ignore" : "#scratch");
75 OutStreamer.EmitRawText(OS.str());
76 }
77
78 };
79} // end of anonymous namespace
80
81#include "SparcGenAsmWriter.inc"
82
83void SparcAsmPrinter::EmitFunctionBodyStart() {
84 if (!TM.getSubtarget<SparcSubtarget>().is64Bit())
85 return;
86
87 const MachineRegisterInfo &MRI = MF->getRegInfo();
88 const unsigned globalRegs[] = { SP::G2, SP::G3, SP::G6, SP::G7, 0 };
89 for (unsigned i = 0; globalRegs[i] != 0; ++i) {
90 unsigned reg = globalRegs[i];
91 if (MRI.use_empty(reg))
92 continue;
93 EmitGlobalRegisterDecl(reg);
94 }
95}
96
97void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
98 raw_ostream &O) {
99 const MachineOperand &MO = MI->getOperand (opNum);
100 unsigned TF = MO.getTargetFlags();
101#ifndef NDEBUG
102 // Verify the target flags.
103 if (MO.isGlobal() || MO.isSymbol() || MO.isCPI()) {
104 if (MI->getOpcode() == SP::CALL)
105 assert(TF == SPII::MO_NO_FLAG &&
106 "Cannot handle target flags on call address");
107 else if (MI->getOpcode() == SP::SETHIi)
108 assert((TF == SPII::MO_HI || TF == SPII::MO_H44 || TF == SPII::MO_HH
109 || TF == SPII::MO_TLS_GD_HI22
110 || TF == SPII::MO_TLS_LDM_HI22
111 || TF == SPII::MO_TLS_LDO_HIX22
112 || TF == SPII::MO_TLS_IE_HI22
113 || TF == SPII::MO_TLS_LE_HIX22) &&
114 "Invalid target flags for address operand on sethi");
115 else if (MI->getOpcode() == SP::TLS_CALL)
116 assert((TF == SPII::MO_NO_FLAG
117 || TF == SPII::MO_TLS_GD_CALL
118 || TF == SPII::MO_TLS_LDM_CALL) &&
119 "Cannot handle target flags on tls call address");
120 else if (MI->getOpcode() == SP::TLS_ADDrr)
121 assert((TF == SPII::MO_TLS_GD_ADD || TF == SPII::MO_TLS_LDM_ADD
122 || TF == SPII::MO_TLS_LDO_ADD || TF == SPII::MO_TLS_IE_ADD) &&
123 "Cannot handle target flags on add for TLS");
124 else if (MI->getOpcode() == SP::TLS_LDrr)
125 assert(TF == SPII::MO_TLS_IE_LD &&
126 "Cannot handle target flags on ld for TLS");
127 else if (MI->getOpcode() == SP::TLS_LDXrr)
128 assert(TF == SPII::MO_TLS_IE_LDX &&
129 "Cannot handle target flags on ldx for TLS");
130 else if (MI->getOpcode() == SP::XORri)
131 assert((TF == SPII::MO_TLS_LDO_LOX10 || TF == SPII::MO_TLS_LE_LOX10) &&
132 "Cannot handle target flags on xor for TLS");
133 else
134 assert((TF == SPII::MO_LO || TF == SPII::MO_M44 || TF == SPII::MO_L44
135 || TF == SPII::MO_HM
136 || TF == SPII::MO_TLS_GD_LO10
137 || TF == SPII::MO_TLS_LDM_LO10
138 || TF == SPII::MO_TLS_IE_LO10 ) &&
139 "Invalid target flags for small address operand");
140 }
141#endif
142
143 bool CloseParen = true;
144 switch (TF) {
145 default:
146 llvm_unreachable("Unknown target flags on operand");
147 case SPII::MO_NO_FLAG:
148 CloseParen = false;
149 break;
150 case SPII::MO_LO: O << "%lo("; break;
151 case SPII::MO_HI: O << "%hi("; break;
152 case SPII::MO_H44: O << "%h44("; break;
153 case SPII::MO_M44: O << "%m44("; break;
154 case SPII::MO_L44: O << "%l44("; break;
155 case SPII::MO_HH: O << "%hh("; break;
156 case SPII::MO_HM: O << "%hm("; break;
157 case SPII::MO_TLS_GD_HI22: O << "%tgd_hi22("; break;
158 case SPII::MO_TLS_GD_LO10: O << "%tgd_lo10("; break;
159 case SPII::MO_TLS_GD_ADD: O << "%tgd_add("; break;
160 case SPII::MO_TLS_GD_CALL: O << "%tgd_call("; break;
161 case SPII::MO_TLS_LDM_HI22: O << "%tldm_hi22("; break;
162 case SPII::MO_TLS_LDM_LO10: O << "%tldm_lo10("; break;
163 case SPII::MO_TLS_LDM_ADD: O << "%tldm_add("; break;
164 case SPII::MO_TLS_LDM_CALL: O << "%tldm_call("; break;
165 case SPII::MO_TLS_LDO_HIX22: O << "%tldo_hix22("; break;
166 case SPII::MO_TLS_LDO_LOX10: O << "%tldo_lox10("; break;
167 case SPII::MO_TLS_LDO_ADD: O << "%tldo_add("; break;
168 case SPII::MO_TLS_IE_HI22: O << "%tie_hi22("; break;
169 case SPII::MO_TLS_IE_LO10: O << "%tie_lo10("; break;
170 case SPII::MO_TLS_IE_LD: O << "%tie_ld("; break;
171 case SPII::MO_TLS_IE_LDX: O << "%tie_ldx("; break;
172 case SPII::MO_TLS_IE_ADD: O << "%tie_add("; break;
173 case SPII::MO_TLS_LE_HIX22: O << "%tle_hix22("; break;
174 case SPII::MO_TLS_LE_LOX10: O << "%tle_lox10("; break;
175 }
176
177 switch (MO.getType()) {
178 case MachineOperand::MO_Register:
179 O << "%" << StringRef(getRegisterName(MO.getReg())).lower();
180 break;
181
182 case MachineOperand::MO_Immediate:
183 O << (int)MO.getImm();
184 break;

--- 36 unchanged lines hidden (view full) ---

221 if (MI->getOperand(opNum+1).isImm() &&
222 MI->getOperand(opNum+1).getImm() == 0)
223 return; // don't print "+0"
224
225 O << "+";
226 printOperand(MI, opNum+1, O);
227}
228
229bool SparcAsmPrinter::printGetPCX(const MachineInstr *MI, unsigned opNum,
230 raw_ostream &O) {
231 std::string operand = "";
232 const MachineOperand &MO = MI->getOperand(opNum);
233 switch (MO.getType()) {
234 default: llvm_unreachable("Operand is not a register");
235 case MachineOperand::MO_Register:
236 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
237 "Operand is not a physical register ");
238 assert(MO.getReg() != SP::O7 &&
239 "%o7 is assigned as destination for getpcx!");
240 operand = "%" + StringRef(getRegisterName(MO.getReg())).lower();
241 break;
242 }
243
244 unsigned mfNum = MI->getParent()->getParent()->getFunctionNumber();
245 unsigned bbNum = MI->getParent()->getNumber();
246
247 O << '\n' << ".LLGETPCH" << mfNum << '_' << bbNum << ":\n";
248 O << "\tcall\t.LLGETPC" << mfNum << '_' << bbNum << '\n' ;
249
250 O << "\t sethi\t"
251 << "%hi(_GLOBAL_OFFSET_TABLE_+(.-.LLGETPCH" << mfNum << '_' << bbNum
252 << ")), " << operand << '\n' ;
253
254 O << ".LLGETPC" << mfNum << '_' << bbNum << ":\n" ;
255 O << "\tor\t" << operand
256 << ", %lo(_GLOBAL_OFFSET_TABLE_+(.-.LLGETPCH" << mfNum << '_' << bbNum
257 << ")), " << operand << '\n';
258 O << "\tadd\t" << operand << ", %o7, " << operand << '\n';
259
260 return true;
261}
262
263void SparcAsmPrinter::printCCOperand(const MachineInstr *MI, int opNum,
264 raw_ostream &O) {
265 int CC = (int)MI->getOperand(opNum).getImm();
266 O << SPARCCondCodeToString((SPCC::CondCodes)CC);
267}
268
269/// PrintAsmOperand - Print out an operand for an inline asm expression.
270///
271bool SparcAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
272 unsigned AsmVariant,
273 const char *ExtraCode,
274 raw_ostream &O) {
275 if (ExtraCode && ExtraCode[0]) {
276 if (ExtraCode[1] != 0) return true; // Unknown modifier.

--- 21 unchanged lines hidden (view full) ---

298
299 O << '[';
300 printMemOperand(MI, OpNo, O);
301 O << ']';
302
303 return false;
304}
305
306/// isBlockOnlyReachableByFallthough - Return true if the basic block has
307/// exactly one predecessor and the control transfer mechanism between
308/// the predecessor and this block is a fall-through.
309///
310/// This overrides AsmPrinter's implementation to handle delay slots.
311bool SparcAsmPrinter::
312isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const {
313 // If this is a landing pad, it isn't a fall through. If it has no preds,
314 // then nothing falls through to it.
315 if (MBB->isLandingPad() || MBB->pred_empty())
316 return false;
317
318 // If there isn't exactly one predecessor, it can't be a fall through.
319 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
320 ++PI2;
321 if (PI2 != MBB->pred_end())
322 return false;
323
324 // The predecessor has to be immediately before this block.
325 const MachineBasicBlock *Pred = *PI;
326
327 if (!Pred->isLayoutSuccessor(MBB))
328 return false;
329
330 // Check if the last terminator is an unconditional branch.
331 MachineBasicBlock::const_iterator I = Pred->end();
332 while (I != Pred->begin() && !(--I)->isTerminator())
333 ; // Noop
334 return I == Pred->end() || !I->isBarrier();
335}
336
337// Force static initialization.
338extern "C" void LLVMInitializeSparcAsmPrinter() {
339 RegisterAsmPrinter<SparcAsmPrinter> X(TheSparcTarget);
340 RegisterAsmPrinter<SparcAsmPrinter> Y(TheSparcV9Target);
341}