1//===-- PPCMCTargetDesc.h - PowerPC Target Descriptions ---------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file provides PowerPC specific target descriptions. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef PPCMCTARGETDESC_H 15#define PPCMCTARGETDESC_H 16 17#include "llvm/Support/DataTypes.h" 18 19namespace llvm { 20class MCAsmBackend; 21class MCCodeEmitter; 22class MCContext; 23class MCInstrInfo; 24class MCObjectWriter; 25class MCRegisterInfo; 26class MCSubtargetInfo; 27class Target; 28class StringRef; 29class raw_ostream; 30 31extern Target ThePPC32Target; 32extern Target ThePPC64Target; 33 34MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII, 35 const MCRegisterInfo &MRI, 36 const MCSubtargetInfo &STI, 37 MCContext &Ctx); 38
| 1//===-- PPCMCTargetDesc.h - PowerPC Target Descriptions ---------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file provides PowerPC specific target descriptions. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef PPCMCTARGETDESC_H 15#define PPCMCTARGETDESC_H 16 17#include "llvm/Support/DataTypes.h" 18 19namespace llvm { 20class MCAsmBackend; 21class MCCodeEmitter; 22class MCContext; 23class MCInstrInfo; 24class MCObjectWriter; 25class MCRegisterInfo; 26class MCSubtargetInfo; 27class Target; 28class StringRef; 29class raw_ostream; 30 31extern Target ThePPC32Target; 32extern Target ThePPC64Target; 33 34MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII, 35 const MCRegisterInfo &MRI, 36 const MCSubtargetInfo &STI, 37 MCContext &Ctx); 38
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39MCAsmBackend *createPPCAsmBackend(const Target &T, StringRef TT);
| 39MCAsmBackend *createPPCAsmBackend(const Target &T, StringRef TT, StringRef CPU);
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40 41/// createPPCELFObjectWriter - Construct an PPC ELF object writer. 42MCObjectWriter *createPPCELFObjectWriter(raw_ostream &OS, 43 bool Is64Bit, 44 uint8_t OSABI); 45} // End llvm namespace 46 47// Defines symbolic names for PowerPC registers. This defines a mapping from 48// register name to register number. 49// 50#define GET_REGINFO_ENUM 51#include "PPCGenRegisterInfo.inc" 52 53// Defines symbolic names for the PowerPC instructions. 54// 55#define GET_INSTRINFO_ENUM 56#include "PPCGenInstrInfo.inc" 57 58#define GET_SUBTARGETINFO_ENUM 59#include "PPCGenSubtargetInfo.inc" 60 61#endif
| 40 41/// createPPCELFObjectWriter - Construct an PPC ELF object writer. 42MCObjectWriter *createPPCELFObjectWriter(raw_ostream &OS, 43 bool Is64Bit, 44 uint8_t OSABI); 45} // End llvm namespace 46 47// Defines symbolic names for PowerPC registers. This defines a mapping from 48// register name to register number. 49// 50#define GET_REGINFO_ENUM 51#include "PPCGenRegisterInfo.inc" 52 53// Defines symbolic names for the PowerPC instructions. 54// 55#define GET_INSTRINFO_ENUM 56#include "PPCGenInstrInfo.inc" 57 58#define GET_SUBTARGETINFO_ENUM 59#include "PPCGenSubtargetInfo.inc" 60 61#endif
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