2886,2889c2886,2891
< if (Lane == 0)
< BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_lo);
< else {
< unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
---
> if (Lane == 0) {
> unsigned Wt = Ws;
> if (!Subtarget.useOddSPReg()) {
> // We must copy to an even-numbered MSA register so that the
> // single-precision sub-register is also guaranteed to be even-numbered.
> Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass);
2890a2893,2901
> BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws);
> }
>
> BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
> } else {
> unsigned Wt = RegInfo.createVirtualRegister(
> Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
> &Mips::MSA128WEvensRegClass);
>
2951c2962,2964
< unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
---
> unsigned Wt = RegInfo.createVirtualRegister(
> Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
> &Mips::MSA128WEvensRegClass);