1//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsTargetLowering specialized for mips32/64.
11//
12//===----------------------------------------------------------------------===//
13#include "MipsSEISelLowering.h"
14#include "MipsMachineFunction.h"
15#include "MipsRegisterInfo.h"
16#include "MipsTargetMachine.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/CodeGen/MachineRegisterInfo.h"
19#include "llvm/IR/Intrinsics.h"
20#include "llvm/Support/CommandLine.h"
21#include "llvm/Support/Debug.h"
22#include "llvm/Support/raw_ostream.h"
23#include "llvm/Target/TargetInstrInfo.h"
24
25using namespace llvm;
26
27#define DEBUG_TYPE "mips-isel"
28
29static cl::opt<bool>
30EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
31 cl::desc("MIPS: Enable tail calls."), cl::init(false));
32
33static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
34 cl::desc("Expand double precision loads and "
35 "stores to their single precision "
36 "counterparts"));
37
38MipsSETargetLowering::MipsSETargetLowering(const MipsTargetMachine &TM,
39 const MipsSubtarget &STI)
40 : MipsTargetLowering(TM, STI) {
41 // Set up the register classes
42 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
43
44 if (Subtarget.isGP64bit())
45 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
46
47 if (Subtarget.hasDSP() || Subtarget.hasMSA()) {
48 // Expand all truncating stores and extending loads.
49 for (MVT VT0 : MVT::vector_valuetypes()) {
50 for (MVT VT1 : MVT::vector_valuetypes()) {
51 setTruncStoreAction(VT0, VT1, Expand);
52 setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand);
53 setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand);
54 setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand);
55 }
56 }
57 }
58
59 if (Subtarget.hasDSP()) {
60 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
61
62 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
63 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
64
65 // Expand all builtin opcodes.
66 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
67 setOperationAction(Opc, VecTys[i], Expand);
68
69 setOperationAction(ISD::ADD, VecTys[i], Legal);
70 setOperationAction(ISD::SUB, VecTys[i], Legal);
71 setOperationAction(ISD::LOAD, VecTys[i], Legal);
72 setOperationAction(ISD::STORE, VecTys[i], Legal);
73 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
74 }
75
76 setTargetDAGCombine(ISD::SHL);
77 setTargetDAGCombine(ISD::SRA);
78 setTargetDAGCombine(ISD::SRL);
79 setTargetDAGCombine(ISD::SETCC);
80 setTargetDAGCombine(ISD::VSELECT);
81 }
82
83 if (Subtarget.hasDSPR2())
84 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
85
86 if (Subtarget.hasMSA()) {
87 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
88 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
89 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
90 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
91 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
92 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
93 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
94
95 setTargetDAGCombine(ISD::AND);
96 setTargetDAGCombine(ISD::OR);
97 setTargetDAGCombine(ISD::SRA);
98 setTargetDAGCombine(ISD::VSELECT);
99 setTargetDAGCombine(ISD::XOR);
100 }
101
102 if (!Subtarget.abiUsesSoftFloat()) {
103 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
104
105 // When dealing with single precision only, use libcalls
106 if (!Subtarget.isSingleFloat()) {
107 if (Subtarget.isFP64bit())
108 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
109 else
110 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
111 }
112 }
113
114 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
115 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
116 setOperationAction(ISD::MULHS, MVT::i32, Custom);
117 setOperationAction(ISD::MULHU, MVT::i32, Custom);
118
119 if (Subtarget.hasCnMips())
120 setOperationAction(ISD::MUL, MVT::i64, Legal);
121 else if (Subtarget.isGP64bit())
122 setOperationAction(ISD::MUL, MVT::i64, Custom);
123
124 if (Subtarget.isGP64bit()) {
125 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Custom);
126 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Custom);
127 setOperationAction(ISD::MULHS, MVT::i64, Custom);
128 setOperationAction(ISD::MULHU, MVT::i64, Custom);
129 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
130 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
131 }
132
133 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
134 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
135
136 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
137 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
138 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
139 setOperationAction(ISD::LOAD, MVT::i32, Custom);
140 setOperationAction(ISD::STORE, MVT::i32, Custom);
141
142 setTargetDAGCombine(ISD::ADDE);
143 setTargetDAGCombine(ISD::SUBE);
144 setTargetDAGCombine(ISD::MUL);
145
146 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
147 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
148 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
149
150 if (NoDPLoadStore) {
151 setOperationAction(ISD::LOAD, MVT::f64, Custom);
152 setOperationAction(ISD::STORE, MVT::f64, Custom);
153 }
154
155 if (Subtarget.hasMips32r6()) {
156 // MIPS32r6 replaces the accumulator-based multiplies with a three register
157 // instruction
158 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
159 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
160 setOperationAction(ISD::MUL, MVT::i32, Legal);
161 setOperationAction(ISD::MULHS, MVT::i32, Legal);
162 setOperationAction(ISD::MULHU, MVT::i32, Legal);
163
164 // MIPS32r6 replaces the accumulator-based division/remainder with separate
165 // three register division and remainder instructions.
166 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
167 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
168 setOperationAction(ISD::SDIV, MVT::i32, Legal);
169 setOperationAction(ISD::UDIV, MVT::i32, Legal);
170 setOperationAction(ISD::SREM, MVT::i32, Legal);
171 setOperationAction(ISD::UREM, MVT::i32, Legal);
172
173 // MIPS32r6 replaces conditional moves with an equivalent that removes the
174 // need for three GPR read ports.
175 setOperationAction(ISD::SETCC, MVT::i32, Legal);
176 setOperationAction(ISD::SELECT, MVT::i32, Legal);
177 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
178
179 setOperationAction(ISD::SETCC, MVT::f32, Legal);
180 setOperationAction(ISD::SELECT, MVT::f32, Legal);
181 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
182
183 assert(Subtarget.isFP64bit() && "FR=1 is required for MIPS32r6");
184 setOperationAction(ISD::SETCC, MVT::f64, Legal);
185 setOperationAction(ISD::SELECT, MVT::f64, Legal);
186 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
187
188 setOperationAction(ISD::BRCOND, MVT::Other, Legal);
189
190 // Floating point > and >= are supported via < and <=
191 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
192 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand);
193 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
194 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
195
196 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
197 setCondCodeAction(ISD::SETOGT, MVT::f64, Expand);
198 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand);
199 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
200 }
201
202 if (Subtarget.hasMips64r6()) {
203 // MIPS64r6 replaces the accumulator-based multiplies with a three register
204 // instruction
205 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
206 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
207 setOperationAction(ISD::MUL, MVT::i64, Legal);
208 setOperationAction(ISD::MULHS, MVT::i64, Legal);
209 setOperationAction(ISD::MULHU, MVT::i64, Legal);
210
211 // MIPS32r6 replaces the accumulator-based division/remainder with separate
212 // three register division and remainder instructions.
213 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
214 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
215 setOperationAction(ISD::SDIV, MVT::i64, Legal);
216 setOperationAction(ISD::UDIV, MVT::i64, Legal);
217 setOperationAction(ISD::SREM, MVT::i64, Legal);
218 setOperationAction(ISD::UREM, MVT::i64, Legal);
219
220 // MIPS64r6 replaces conditional moves with an equivalent that removes the
221 // need for three GPR read ports.
222 setOperationAction(ISD::SETCC, MVT::i64, Legal);
223 setOperationAction(ISD::SELECT, MVT::i64, Legal);
224 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
225 }
226
227 computeRegisterProperties();
228}
229
230const MipsTargetLowering *
231llvm::createMipsSETargetLowering(const MipsTargetMachine &TM,
232 const MipsSubtarget &STI) {
233 return new MipsSETargetLowering(TM, STI);
234}
235
236const TargetRegisterClass *
237MipsSETargetLowering::getRepRegClassFor(MVT VT) const {
238 if (VT == MVT::Untyped)
239 return Subtarget.hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass;
240
241 return TargetLowering::getRepRegClassFor(VT);
242}
243
244// Enable MSA support for the given integer type and Register class.
245void MipsSETargetLowering::
246addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
247 addRegisterClass(Ty, RC);
248
249 // Expand all builtin opcodes.
250 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
251 setOperationAction(Opc, Ty, Expand);
252
253 setOperationAction(ISD::BITCAST, Ty, Legal);
254 setOperationAction(ISD::LOAD, Ty, Legal);
255 setOperationAction(ISD::STORE, Ty, Legal);
256 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
257 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
258 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
259
260 setOperationAction(ISD::ADD, Ty, Legal);
261 setOperationAction(ISD::AND, Ty, Legal);
262 setOperationAction(ISD::CTLZ, Ty, Legal);
263 setOperationAction(ISD::CTPOP, Ty, Legal);
264 setOperationAction(ISD::MUL, Ty, Legal);
265 setOperationAction(ISD::OR, Ty, Legal);
266 setOperationAction(ISD::SDIV, Ty, Legal);
267 setOperationAction(ISD::SREM, Ty, Legal);
268 setOperationAction(ISD::SHL, Ty, Legal);
269 setOperationAction(ISD::SRA, Ty, Legal);
270 setOperationAction(ISD::SRL, Ty, Legal);
271 setOperationAction(ISD::SUB, Ty, Legal);
272 setOperationAction(ISD::UDIV, Ty, Legal);
273 setOperationAction(ISD::UREM, Ty, Legal);
274 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom);
275 setOperationAction(ISD::VSELECT, Ty, Legal);
276 setOperationAction(ISD::XOR, Ty, Legal);
277
278 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
279 setOperationAction(ISD::FP_TO_SINT, Ty, Legal);
280 setOperationAction(ISD::FP_TO_UINT, Ty, Legal);
281 setOperationAction(ISD::SINT_TO_FP, Ty, Legal);
282 setOperationAction(ISD::UINT_TO_FP, Ty, Legal);
283 }
284
285 setOperationAction(ISD::SETCC, Ty, Legal);
286 setCondCodeAction(ISD::SETNE, Ty, Expand);
287 setCondCodeAction(ISD::SETGE, Ty, Expand);
288 setCondCodeAction(ISD::SETGT, Ty, Expand);
289 setCondCodeAction(ISD::SETUGE, Ty, Expand);
290 setCondCodeAction(ISD::SETUGT, Ty, Expand);
291}
292
293// Enable MSA support for the given floating-point type and Register class.
294void MipsSETargetLowering::
295addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
296 addRegisterClass(Ty, RC);
297
298 // Expand all builtin opcodes.
299 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
300 setOperationAction(Opc, Ty, Expand);
301
302 setOperationAction(ISD::LOAD, Ty, Legal);
303 setOperationAction(ISD::STORE, Ty, Legal);
304 setOperationAction(ISD::BITCAST, Ty, Legal);
305 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
306 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
307 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
308
309 if (Ty != MVT::v8f16) {
310 setOperationAction(ISD::FABS, Ty, Legal);
311 setOperationAction(ISD::FADD, Ty, Legal);
312 setOperationAction(ISD::FDIV, Ty, Legal);
313 setOperationAction(ISD::FEXP2, Ty, Legal);
314 setOperationAction(ISD::FLOG2, Ty, Legal);
315 setOperationAction(ISD::FMA, Ty, Legal);
316 setOperationAction(ISD::FMUL, Ty, Legal);
317 setOperationAction(ISD::FRINT, Ty, Legal);
318 setOperationAction(ISD::FSQRT, Ty, Legal);
319 setOperationAction(ISD::FSUB, Ty, Legal);
320 setOperationAction(ISD::VSELECT, Ty, Legal);
321
322 setOperationAction(ISD::SETCC, Ty, Legal);
323 setCondCodeAction(ISD::SETOGE, Ty, Expand);
324 setCondCodeAction(ISD::SETOGT, Ty, Expand);
325 setCondCodeAction(ISD::SETUGE, Ty, Expand);
326 setCondCodeAction(ISD::SETUGT, Ty, Expand);
327 setCondCodeAction(ISD::SETGE, Ty, Expand);
328 setCondCodeAction(ISD::SETGT, Ty, Expand);
329 }
330}
331
332bool
333MipsSETargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
334 unsigned,
335 unsigned,
336 bool *Fast) const {
337 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
338
339 if (Subtarget.systemSupportsUnalignedAccess()) {
340 // MIPS32r6/MIPS64r6 is required to support unaligned access. It's
341 // implementation defined whether this is handled by hardware, software, or
342 // a hybrid of the two but it's expected that most implementations will
343 // handle the majority of cases in hardware.
344 if (Fast)
345 *Fast = true;
346 return true;
347 }
348
349 switch (SVT) {
350 case MVT::i64:
351 case MVT::i32:
352 if (Fast)
353 *Fast = true;
354 return true;
355 default:
356 return false;
357 }
358}
359
360SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
361 SelectionDAG &DAG) const {
362 switch(Op.getOpcode()) {
363 case ISD::LOAD: return lowerLOAD(Op, DAG);
364 case ISD::STORE: return lowerSTORE(Op, DAG);
365 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
366 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
367 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
368 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
369 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
370 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
371 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
372 DAG);
373 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
374 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
375 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
376 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
377 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
378 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG);
379 }
380
381 return MipsTargetLowering::LowerOperation(Op, DAG);
382}
383
384// selectMADD -
385// Transforms a subgraph in CurDAG if the following pattern is found:
386// (addc multLo, Lo0), (adde multHi, Hi0),
387// where,
388// multHi/Lo: product of multiplication
389// Lo0: initial value of Lo register
390// Hi0: initial value of Hi register
391// Return true if pattern matching was successful.
392static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
393 // ADDENode's second operand must be a flag output of an ADDC node in order
394 // for the matching to be successful.
395 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
396
397 if (ADDCNode->getOpcode() != ISD::ADDC)
398 return false;
399
400 SDValue MultHi = ADDENode->getOperand(0);
401 SDValue MultLo = ADDCNode->getOperand(0);
402 SDNode *MultNode = MultHi.getNode();
403 unsigned MultOpc = MultHi.getOpcode();
404
405 // MultHi and MultLo must be generated by the same node,
406 if (MultLo.getNode() != MultNode)
407 return false;
408
409 // and it must be a multiplication.
410 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
411 return false;
412
413 // MultLo amd MultHi must be the first and second output of MultNode
414 // respectively.
415 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
416 return false;
417
418 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
419 // of the values of MultNode, in which case MultNode will be removed in later
420 // phases.
421 // If there exist users other than ADDENode or ADDCNode, this function returns
422 // here, which will result in MultNode being mapped to a single MULT
423 // instruction node rather than a pair of MULT and MADD instructions being
424 // produced.
425 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
426 return false;
427
428 SDLoc DL(ADDENode);
429
430 // Initialize accumulator.
431 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
432 ADDCNode->getOperand(1),
433 ADDENode->getOperand(1));
434
435 // create MipsMAdd(u) node
436 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
437
438 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
439 MultNode->getOperand(0),// Factor 0
440 MultNode->getOperand(1),// Factor 1
441 ACCIn);
442
443 // replace uses of adde and addc here
444 if (!SDValue(ADDCNode, 0).use_empty()) {
445 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
446 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
447 }
448 if (!SDValue(ADDENode, 0).use_empty()) {
449 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
450 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
451 }
452
453 return true;
454}
455
456// selectMSUB -
457// Transforms a subgraph in CurDAG if the following pattern is found:
458// (addc Lo0, multLo), (sube Hi0, multHi),
459// where,
460// multHi/Lo: product of multiplication
461// Lo0: initial value of Lo register
462// Hi0: initial value of Hi register
463// Return true if pattern matching was successful.
464static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
465 // SUBENode's second operand must be a flag output of an SUBC node in order
466 // for the matching to be successful.
467 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
468
469 if (SUBCNode->getOpcode() != ISD::SUBC)
470 return false;
471
472 SDValue MultHi = SUBENode->getOperand(1);
473 SDValue MultLo = SUBCNode->getOperand(1);
474 SDNode *MultNode = MultHi.getNode();
475 unsigned MultOpc = MultHi.getOpcode();
476
477 // MultHi and MultLo must be generated by the same node,
478 if (MultLo.getNode() != MultNode)
479 return false;
480
481 // and it must be a multiplication.
482 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
483 return false;
484
485 // MultLo amd MultHi must be the first and second output of MultNode
486 // respectively.
487 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
488 return false;
489
490 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
491 // of the values of MultNode, in which case MultNode will be removed in later
492 // phases.
493 // If there exist users other than SUBENode or SUBCNode, this function returns
494 // here, which will result in MultNode being mapped to a single MULT
495 // instruction node rather than a pair of MULT and MSUB instructions being
496 // produced.
497 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
498 return false;
499
500 SDLoc DL(SUBENode);
501
502 // Initialize accumulator.
503 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
504 SUBCNode->getOperand(0),
505 SUBENode->getOperand(0));
506
507 // create MipsSub(u) node
508 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
509
510 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
511 MultNode->getOperand(0),// Factor 0
512 MultNode->getOperand(1),// Factor 1
513 ACCIn);
514
515 // replace uses of sube and subc here
516 if (!SDValue(SUBCNode, 0).use_empty()) {
517 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub);
518 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
519 }
520 if (!SDValue(SUBENode, 0).use_empty()) {
521 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MSub);
522 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
523 }
524
525 return true;
526}
527
528static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
529 TargetLowering::DAGCombinerInfo &DCI,
530 const MipsSubtarget &Subtarget) {
531 if (DCI.isBeforeLegalize())
532 return SDValue();
533
534 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
535 N->getValueType(0) == MVT::i32 && selectMADD(N, &DAG))
536 return SDValue(N, 0);
537
538 return SDValue();
539}
540
541// Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
542//
543// Performs the following transformations:
544// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
545// sign/zero-extension is completely overwritten by the new one performed by
546// the ISD::AND.
547// - Removes redundant zero extensions performed by an ISD::AND.
548static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
549 TargetLowering::DAGCombinerInfo &DCI,
550 const MipsSubtarget &Subtarget) {
551 if (!Subtarget.hasMSA())
552 return SDValue();
553
554 SDValue Op0 = N->getOperand(0);
555 SDValue Op1 = N->getOperand(1);
556 unsigned Op0Opcode = Op0->getOpcode();
557
558 // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
559 // where $d + 1 == 2^n and n == 32
560 // or $d + 1 == 2^n and n <= 32 and ZExt
561 // -> (MipsVExtractZExt $a, $b, $c)
562 if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
563 Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
564 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
565
566 if (!Mask)
567 return SDValue();
568
569 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
570
571 if (Log2IfPositive <= 0)
572 return SDValue(); // Mask+1 is not a power of 2
573
574 SDValue Op0Op2 = Op0->getOperand(2);
575 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
576 unsigned ExtendTySize = ExtendTy.getSizeInBits();
577 unsigned Log2 = Log2IfPositive;
578
579 if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
580 Log2 == ExtendTySize) {
581 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
582 return DAG.getNode(MipsISD::VEXTRACT_ZEXT_ELT, SDLoc(Op0),
583 Op0->getVTList(),
584 makeArrayRef(Ops, Op0->getNumOperands()));
585 }
586 }
587
588 return SDValue();
589}
590
591// Determine if the specified node is a constant vector splat.
592//
593// Returns true and sets Imm if:
594// * N is a ISD::BUILD_VECTOR representing a constant splat
595//
596// This function is quite similar to MipsSEDAGToDAGISel::selectVSplat. The
597// differences are that it assumes the MSA has already been checked and the
598// arbitrary requirement for a maximum of 32-bit integers isn't applied (and
599// must not be in order for binsri.d to be selectable).
600static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) {
601 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N.getNode());
602
603 if (!Node)
604 return false;
605
606 APInt SplatValue, SplatUndef;
607 unsigned SplatBitSize;
608 bool HasAnyUndefs;
609
610 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
611 8, !IsLittleEndian))
612 return false;
613
614 Imm = SplatValue;
615
616 return true;
617}
618
619// Test whether the given node is an all-ones build_vector.
620static bool isVectorAllOnes(SDValue N) {
621 // Look through bitcasts. Endianness doesn't matter because we are looking
622 // for an all-ones value.
623 if (N->getOpcode() == ISD::BITCAST)
624 N = N->getOperand(0);
625
626 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
627
628 if (!BVN)
629 return false;
630
631 APInt SplatValue, SplatUndef;
632 unsigned SplatBitSize;
633 bool HasAnyUndefs;
634
635 // Endianness doesn't matter in this context because we are looking for
636 // an all-ones value.
637 if (BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs))
638 return SplatValue.isAllOnesValue();
639
640 return false;
641}
642
643// Test whether N is the bitwise inverse of OfNode.
644static bool isBitwiseInverse(SDValue N, SDValue OfNode) {
645 if (N->getOpcode() != ISD::XOR)
646 return false;
647
648 if (isVectorAllOnes(N->getOperand(0)))
649 return N->getOperand(1) == OfNode;
650
651 if (isVectorAllOnes(N->getOperand(1)))
652 return N->getOperand(0) == OfNode;
653
654 return false;
655}
656
657// Perform combines where ISD::OR is the root node.
658//
659// Performs the following transformations:
660// - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
661// where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
662// vector type.
663static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
664 TargetLowering::DAGCombinerInfo &DCI,
665 const MipsSubtarget &Subtarget) {
666 if (!Subtarget.hasMSA())
667 return SDValue();
668
669 EVT Ty = N->getValueType(0);
670
671 if (!Ty.is128BitVector())
672 return SDValue();
673
674 SDValue Op0 = N->getOperand(0);
675 SDValue Op1 = N->getOperand(1);
676
677 if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
678 SDValue Op0Op0 = Op0->getOperand(0);
679 SDValue Op0Op1 = Op0->getOperand(1);
680 SDValue Op1Op0 = Op1->getOperand(0);
681 SDValue Op1Op1 = Op1->getOperand(1);
682 bool IsLittleEndian = !Subtarget.isLittle();
683
684 SDValue IfSet, IfClr, Cond;
685 bool IsConstantMask = false;
686 APInt Mask, InvMask;
687
688 // If Op0Op0 is an appropriate mask, try to find it's inverse in either
689 // Op1Op0, or Op1Op1. Keep track of the Cond, IfSet, and IfClr nodes, while
690 // looking.
691 // IfClr will be set if we find a valid match.
692 if (isVSplat(Op0Op0, Mask, IsLittleEndian)) {
693 Cond = Op0Op0;
694 IfSet = Op0Op1;
695
696 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
697 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
698 IfClr = Op1Op1;
699 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
700 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
701 IfClr = Op1Op0;
702
703 IsConstantMask = true;
704 }
705
706 // If IfClr is not yet set, and Op0Op1 is an appropriate mask, try the same
707 // thing again using this mask.
708 // IfClr will be set if we find a valid match.
709 if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) {
710 Cond = Op0Op1;
711 IfSet = Op0Op0;
712
713 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
714 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
715 IfClr = Op1Op1;
716 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
717 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
718 IfClr = Op1Op0;
719
720 IsConstantMask = true;
721 }
722
723 // If IfClr is not yet set, try looking for a non-constant match.
724 // IfClr will be set if we find a valid match amongst the eight
725 // possibilities.
726 if (!IfClr.getNode()) {
727 if (isBitwiseInverse(Op0Op0, Op1Op0)) {
728 Cond = Op1Op0;
729 IfSet = Op1Op1;
730 IfClr = Op0Op1;
731 } else if (isBitwiseInverse(Op0Op1, Op1Op0)) {
732 Cond = Op1Op0;
733 IfSet = Op1Op1;
734 IfClr = Op0Op0;
735 } else if (isBitwiseInverse(Op0Op0, Op1Op1)) {
736 Cond = Op1Op1;
737 IfSet = Op1Op0;
738 IfClr = Op0Op1;
739 } else if (isBitwiseInverse(Op0Op1, Op1Op1)) {
740 Cond = Op1Op1;
741 IfSet = Op1Op0;
742 IfClr = Op0Op0;
743 } else if (isBitwiseInverse(Op1Op0, Op0Op0)) {
744 Cond = Op0Op0;
745 IfSet = Op0Op1;
746 IfClr = Op1Op1;
747 } else if (isBitwiseInverse(Op1Op1, Op0Op0)) {
748 Cond = Op0Op0;
749 IfSet = Op0Op1;
750 IfClr = Op1Op0;
751 } else if (isBitwiseInverse(Op1Op0, Op0Op1)) {
752 Cond = Op0Op1;
753 IfSet = Op0Op0;
754 IfClr = Op1Op1;
755 } else if (isBitwiseInverse(Op1Op1, Op0Op1)) {
756 Cond = Op0Op1;
757 IfSet = Op0Op0;
758 IfClr = Op1Op0;
759 }
760 }
761
762 // At this point, IfClr will be set if we have a valid match.
763 if (!IfClr.getNode())
764 return SDValue();
765
766 assert(Cond.getNode() && IfSet.getNode());
767
768 // Fold degenerate cases.
769 if (IsConstantMask) {
770 if (Mask.isAllOnesValue())
771 return IfSet;
772 else if (Mask == 0)
773 return IfClr;
774 }
775
776 // Transform the DAG into an equivalent VSELECT.
777 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr);
778 }
779
780 return SDValue();
781}
782
783static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
784 TargetLowering::DAGCombinerInfo &DCI,
785 const MipsSubtarget &Subtarget) {
786 if (DCI.isBeforeLegalize())
787 return SDValue();
788
789 if (Subtarget.hasMips32() && N->getValueType(0) == MVT::i32 &&
790 selectMSUB(N, &DAG))
791 return SDValue(N, 0);
792
793 return SDValue();
794}
795
796static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
797 EVT ShiftTy, SelectionDAG &DAG) {
798 // Clear the upper (64 - VT.sizeInBits) bits.
799 C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
800
801 // Return 0.
802 if (C == 0)
803 return DAG.getConstant(0, VT);
804
805 // Return x.
806 if (C == 1)
807 return X;
808
809 // If c is power of 2, return (shl x, log2(c)).
810 if (isPowerOf2_64(C))
811 return DAG.getNode(ISD::SHL, DL, VT, X,
812 DAG.getConstant(Log2_64(C), ShiftTy));
813
814 unsigned Log2Ceil = Log2_64_Ceil(C);
815 uint64_t Floor = 1LL << Log2_64(C);
816 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
817
818 // If |c - floor_c| <= |c - ceil_c|,
819 // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
820 // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
821 if (C - Floor <= Ceil - C) {
822 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
823 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
824 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
825 }
826
827 // If |c - floor_c| > |c - ceil_c|,
828 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
829 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
830 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
831 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
832}
833
834static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
835 const TargetLowering::DAGCombinerInfo &DCI,
836 const MipsSETargetLowering *TL) {
837 EVT VT = N->getValueType(0);
838
839 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
840 if (!VT.isVector())
841 return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N),
842 VT, TL->getScalarShiftAmountTy(VT), DAG);
843
844 return SDValue(N, 0);
845}
846
847static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
848 SelectionDAG &DAG,
849 const MipsSubtarget &Subtarget) {
850 // See if this is a vector splat immediate node.
851 APInt SplatValue, SplatUndef;
852 unsigned SplatBitSize;
853 bool HasAnyUndefs;
854 unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
855 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
856
857 if (!Subtarget.hasDSP())
858 return SDValue();
859
860 if (!BV ||
861 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
862 EltSize, !Subtarget.isLittle()) ||
863 (SplatBitSize != EltSize) ||
864 (SplatValue.getZExtValue() >= EltSize))
865 return SDValue();
866
867 return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
868 DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
869}
870
871static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
872 TargetLowering::DAGCombinerInfo &DCI,
873 const MipsSubtarget &Subtarget) {
874 EVT Ty = N->getValueType(0);
875
876 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
877 return SDValue();
878
879 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
880}
881
882// Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
883// constant splats into MipsISD::SHRA_DSP for DSPr2.
884//
885// Performs the following transformations:
886// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
887// sign/zero-extension is completely overwritten by the new one performed by
888// the ISD::SRA and ISD::SHL nodes.
889// - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
890// sequence.
891//
892// See performDSPShiftCombine for more information about the transformation
893// used for DSPr2.
894static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
895 TargetLowering::DAGCombinerInfo &DCI,
896 const MipsSubtarget &Subtarget) {
897 EVT Ty = N->getValueType(0);
898
899 if (Subtarget.hasMSA()) {
900 SDValue Op0 = N->getOperand(0);
901 SDValue Op1 = N->getOperand(1);
902
903 // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
904 // where $d + sizeof($c) == 32
905 // or $d + sizeof($c) <= 32 and SExt
906 // -> (MipsVExtractSExt $a, $b, $c)
907 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
908 SDValue Op0Op0 = Op0->getOperand(0);
909 ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
910
911 if (!ShAmount)
912 return SDValue();
913
914 if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
915 Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT)
916 return SDValue();
917
918 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
919 unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
920
921 if (TotalBits == 32 ||
922 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
923 TotalBits <= 32)) {
924 SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
925 Op0Op0->getOperand(2) };
926 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, SDLoc(Op0Op0),
927 Op0Op0->getVTList(),
928 makeArrayRef(Ops, Op0Op0->getNumOperands()));
929 }
930 }
931 }
932
933 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2()))
934 return SDValue();
935
936 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
937}
938
939
940static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
941 TargetLowering::DAGCombinerInfo &DCI,
942 const MipsSubtarget &Subtarget) {
943 EVT Ty = N->getValueType(0);
944
945 if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8))
946 return SDValue();
947
948 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
949}
950
951static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
952 bool IsV216 = (Ty == MVT::v2i16);
953
954 switch (CC) {
955 case ISD::SETEQ:
956 case ISD::SETNE: return true;
957 case ISD::SETLT:
958 case ISD::SETLE:
959 case ISD::SETGT:
960 case ISD::SETGE: return IsV216;
961 case ISD::SETULT:
962 case ISD::SETULE:
963 case ISD::SETUGT:
964 case ISD::SETUGE: return !IsV216;
965 default: return false;
966 }
967}
968
969static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
970 EVT Ty = N->getValueType(0);
971
972 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
973 return SDValue();
974
975 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
976 return SDValue();
977
978 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
979 N->getOperand(1), N->getOperand(2));
980}
981
982static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
983 EVT Ty = N->getValueType(0);
984
985 if (Ty.is128BitVector() && Ty.isInteger()) {
986 // Try the following combines:
987 // (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b)
988 // (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b)
989 // (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b)
990 // (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b)
991 // (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b)
992 // (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b)
993 // (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b)
994 // (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b)
995 // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but
996 // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the
997 // legalizer.
998 SDValue Op0 = N->getOperand(0);
999
1000 if (Op0->getOpcode() != ISD::SETCC)
1001 return SDValue();
1002
1003 ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get();
1004 bool Signed;
1005
1006 if (CondCode == ISD::SETLT || CondCode == ISD::SETLE)
1007 Signed = true;
1008 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE)
1009 Signed = false;
1010 else
1011 return SDValue();
1012
1013 SDValue Op1 = N->getOperand(1);
1014 SDValue Op2 = N->getOperand(2);
1015 SDValue Op0Op0 = Op0->getOperand(0);
1016 SDValue Op0Op1 = Op0->getOperand(1);
1017
1018 if (Op1 == Op0Op0 && Op2 == Op0Op1)
1019 return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N),
1020 Ty, Op1, Op2);
1021 else if (Op1 == Op0Op1 && Op2 == Op0Op0)
1022 return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N),
1023 Ty, Op1, Op2);
1024 } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) {
1025 SDValue SetCC = N->getOperand(0);
1026
1027 if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
1028 return SDValue();
1029
1030 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
1031 SetCC.getOperand(0), SetCC.getOperand(1),
1032 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
1033 }
1034
1035 return SDValue();
1036}
1037
1038static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
1039 const MipsSubtarget &Subtarget) {
1040 EVT Ty = N->getValueType(0);
1041
1042 if (Subtarget.hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
1043 // Try the following combines:
1044 // (xor (or $a, $b), (build_vector allones))
1045 // (xor (or $a, $b), (bitcast (build_vector allones)))
1046 SDValue Op0 = N->getOperand(0);
1047 SDValue Op1 = N->getOperand(1);
1048 SDValue NotOp;
1049
1050 if (ISD::isBuildVectorAllOnes(Op0.getNode()))
1051 NotOp = Op1;
1052 else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
1053 NotOp = Op0;
1054 else
1055 return SDValue();
1056
1057 if (NotOp->getOpcode() == ISD::OR)
1058 return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
1059 NotOp->getOperand(1));
1060 }
1061
1062 return SDValue();
1063}
1064
1065SDValue
1066MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1067 SelectionDAG &DAG = DCI.DAG;
1068 SDValue Val;
1069
1070 switch (N->getOpcode()) {
1071 case ISD::ADDE:
1072 return performADDECombine(N, DAG, DCI, Subtarget);
1073 case ISD::AND:
1074 Val = performANDCombine(N, DAG, DCI, Subtarget);
1075 break;
1076 case ISD::OR:
1077 Val = performORCombine(N, DAG, DCI, Subtarget);
1078 break;
1079 case ISD::SUBE:
1080 return performSUBECombine(N, DAG, DCI, Subtarget);
1081 case ISD::MUL:
1082 return performMULCombine(N, DAG, DCI, this);
1083 case ISD::SHL:
1084 return performSHLCombine(N, DAG, DCI, Subtarget);
1085 case ISD::SRA:
1086 return performSRACombine(N, DAG, DCI, Subtarget);
1087 case ISD::SRL:
1088 return performSRLCombine(N, DAG, DCI, Subtarget);
1089 case ISD::VSELECT:
1090 return performVSELECTCombine(N, DAG);
1091 case ISD::XOR:
1092 Val = performXORCombine(N, DAG, Subtarget);
1093 break;
1094 case ISD::SETCC:
1095 Val = performSETCCCombine(N, DAG);
1096 break;
1097 }
1098
1099 if (Val.getNode()) {
1100 DEBUG(dbgs() << "\nMipsSE DAG Combine:\n";
1101 N->printrWithDepth(dbgs(), &DAG);
1102 dbgs() << "\n=> \n";
1103 Val.getNode()->printrWithDepth(dbgs(), &DAG);
1104 dbgs() << "\n");
1105 return Val;
1106 }
1107
1108 return MipsTargetLowering::PerformDAGCombine(N, DCI);
1109}
1110
1111MachineBasicBlock *
1112MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1113 MachineBasicBlock *BB) const {
1114 switch (MI->getOpcode()) {
1115 default:
1116 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
1117 case Mips::BPOSGE32_PSEUDO:
1118 return emitBPOSGE32(MI, BB);
1119 case Mips::SNZ_B_PSEUDO:
1120 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
1121 case Mips::SNZ_H_PSEUDO:
1122 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
1123 case Mips::SNZ_W_PSEUDO:
1124 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
1125 case Mips::SNZ_D_PSEUDO:
1126 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
1127 case Mips::SNZ_V_PSEUDO:
1128 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
1129 case Mips::SZ_B_PSEUDO:
1130 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
1131 case Mips::SZ_H_PSEUDO:
1132 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
1133 case Mips::SZ_W_PSEUDO:
1134 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
1135 case Mips::SZ_D_PSEUDO:
1136 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
1137 case Mips::SZ_V_PSEUDO:
1138 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
1139 case Mips::COPY_FW_PSEUDO:
1140 return emitCOPY_FW(MI, BB);
1141 case Mips::COPY_FD_PSEUDO:
1142 return emitCOPY_FD(MI, BB);
1143 case Mips::INSERT_FW_PSEUDO:
1144 return emitINSERT_FW(MI, BB);
1145 case Mips::INSERT_FD_PSEUDO:
1146 return emitINSERT_FD(MI, BB);
1147 case Mips::INSERT_B_VIDX_PSEUDO:
1148 return emitINSERT_DF_VIDX(MI, BB, 1, false);
1149 case Mips::INSERT_H_VIDX_PSEUDO:
1150 return emitINSERT_DF_VIDX(MI, BB, 2, false);
1151 case Mips::INSERT_W_VIDX_PSEUDO:
1152 return emitINSERT_DF_VIDX(MI, BB, 4, false);
1153 case Mips::INSERT_D_VIDX_PSEUDO:
1154 return emitINSERT_DF_VIDX(MI, BB, 8, false);
1155 case Mips::INSERT_FW_VIDX_PSEUDO:
1156 return emitINSERT_DF_VIDX(MI, BB, 4, true);
1157 case Mips::INSERT_FD_VIDX_PSEUDO:
1158 return emitINSERT_DF_VIDX(MI, BB, 8, true);
1159 case Mips::FILL_FW_PSEUDO:
1160 return emitFILL_FW(MI, BB);
1161 case Mips::FILL_FD_PSEUDO:
1162 return emitFILL_FD(MI, BB);
1163 case Mips::FEXP2_W_1_PSEUDO:
1164 return emitFEXP2_W_1(MI, BB);
1165 case Mips::FEXP2_D_1_PSEUDO:
1166 return emitFEXP2_D_1(MI, BB);
1167 }
1168}
1169
1170bool MipsSETargetLowering::isEligibleForTailCallOptimization(
1171 const CCState &CCInfo, unsigned NextStackOffset,
1172 const MipsFunctionInfo &FI) const {
1173 if (!EnableMipsTailCalls)
1174 return false;
1175
1176 // Return false if either the callee or caller has a byval argument.
1177 if (CCInfo.getInRegsParamsCount() > 0 || FI.hasByvalArg())
1178 return false;
1179
1180 // Return true if the callee's argument area is no larger than the
1181 // caller's.
1182 return NextStackOffset <= FI.getIncomingArgSize();
1183}
1184
1185void MipsSETargetLowering::
1186getOpndList(SmallVectorImpl<SDValue> &Ops,
1187 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
1188 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
1189 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
1190 SDValue Chain) const {
1191 Ops.push_back(Callee);
1192 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
1193 InternalLinkage, IsCallReloc, CLI, Callee,
1194 Chain);
1195}
1196
1197SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1198 LoadSDNode &Nd = *cast<LoadSDNode>(Op);
1199
1200 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1201 return MipsTargetLowering::lowerLOAD(Op, DAG);
1202
1203 // Replace a double precision load with two i32 loads and a buildpair64.
1204 SDLoc DL(Op);
1205 SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1206 EVT PtrVT = Ptr.getValueType();
1207
1208 // i32 load from lower address.
1209 SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
1210 MachinePointerInfo(), Nd.isVolatile(),
1211 Nd.isNonTemporal(), Nd.isInvariant(),
1212 Nd.getAlignment());
1213
1214 // i32 load from higher address.
1215 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
1216 SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
1217 MachinePointerInfo(), Nd.isVolatile(),
1218 Nd.isNonTemporal(), Nd.isInvariant(),
1219 std::min(Nd.getAlignment(), 4U));
1220
1221 if (!Subtarget.isLittle())
1222 std::swap(Lo, Hi);
1223
1224 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
1225 SDValue Ops[2] = {BP, Hi.getValue(1)};
1226 return DAG.getMergeValues(Ops, DL);
1227}
1228
1229SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1230 StoreSDNode &Nd = *cast<StoreSDNode>(Op);
1231
1232 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1233 return MipsTargetLowering::lowerSTORE(Op, DAG);
1234
1235 // Replace a double precision store with two extractelement64s and i32 stores.
1236 SDLoc DL(Op);
1237 SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1238 EVT PtrVT = Ptr.getValueType();
1239 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1240 Val, DAG.getConstant(0, MVT::i32));
1241 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1242 Val, DAG.getConstant(1, MVT::i32));
1243
1244 if (!Subtarget.isLittle())
1245 std::swap(Lo, Hi);
1246
1247 // i32 store to lower address.
1248 Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
1249 Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
1250 Nd.getAAInfo());
1251
1252 // i32 store to higher address.
1253 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
1254 return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
1255 Nd.isVolatile(), Nd.isNonTemporal(),
1256 std::min(Nd.getAlignment(), 4U), Nd.getAAInfo());
1257}
1258
1259SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
1260 bool HasLo, bool HasHi,
1261 SelectionDAG &DAG) const {
1262 // MIPS32r6/MIPS64r6 removed accumulator based multiplies.
1263 assert(!Subtarget.hasMips32r6());
1264
1265 EVT Ty = Op.getOperand(0).getValueType();
1266 SDLoc DL(Op);
1267 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
1268 Op.getOperand(0), Op.getOperand(1));
1269 SDValue Lo, Hi;
1270
1271 if (HasLo)
1272 Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult);
1273 if (HasHi)
1274 Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult);
1275
1276 if (!HasLo || !HasHi)
1277 return HasLo ? Lo : Hi;
1278
1279 SDValue Vals[] = { Lo, Hi };
1280 return DAG.getMergeValues(Vals, DL);
1281}
1282
1283
1284static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
1285 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1286 DAG.getConstant(0, MVT::i32));
1287 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1288 DAG.getConstant(1, MVT::i32));
1289 return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
1290}
1291
1292static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
1293 SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op);
1294 SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op);
1295 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
1296}
1297
1298// This function expands mips intrinsic nodes which have 64-bit input operands
1299// or output values.
1300//
1301// out64 = intrinsic-node in64
1302// =>
1303// lo = copy (extract-element (in64, 0))
1304// hi = copy (extract-element (in64, 1))
1305// mips-specific-node
1306// v0 = copy lo
1307// v1 = copy hi
1308// out64 = merge-values (v0, v1)
1309//
1310static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1311 SDLoc DL(Op);
1312 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
1313 SmallVector<SDValue, 3> Ops;
1314 unsigned OpNo = 0;
1315
1316 // See if Op has a chain input.
1317 if (HasChainIn)
1318 Ops.push_back(Op->getOperand(OpNo++));
1319
1320 // The next operand is the intrinsic opcode.
1321 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
1322
1323 // See if the next operand has type i64.
1324 SDValue Opnd = Op->getOperand(++OpNo), In64;
1325
1326 if (Opnd.getValueType() == MVT::i64)
1327 In64 = initAccumulator(Opnd, DL, DAG);
1328 else
1329 Ops.push_back(Opnd);
1330
1331 // Push the remaining operands.
1332 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
1333 Ops.push_back(Op->getOperand(OpNo));
1334
1335 // Add In64 to the end of the list.
1336 if (In64.getNode())
1337 Ops.push_back(In64);
1338
1339 // Scan output.
1340 SmallVector<EVT, 2> ResTys;
1341
1342 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1343 I != E; ++I)
1344 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
1345
1346 // Create node.
1347 SDValue Val = DAG.getNode(Opc, DL, ResTys, Ops);
1348 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
1349
1350 if (!HasChainIn)
1351 return Out;
1352
1353 assert(Val->getValueType(1) == MVT::Other);
1354 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
1355 return DAG.getMergeValues(Vals, DL);
1356}
1357
1358// Lower an MSA copy intrinsic into the specified SelectionDAG node
1359static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1360 SDLoc DL(Op);
1361 SDValue Vec = Op->getOperand(1);
1362 SDValue Idx = Op->getOperand(2);
1363 EVT ResTy = Op->getValueType(0);
1364 EVT EltTy = Vec->getValueType(0).getVectorElementType();
1365
1366 SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1367 DAG.getValueType(EltTy));
1368
1369 return Result;
1370}
1371
1372static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) {
1373 EVT ResVecTy = Op->getValueType(0);
1374 EVT ViaVecTy = ResVecTy;
1375 SDLoc DL(Op);
1376
1377 // When ResVecTy == MVT::v2i64, LaneA is the upper 32 bits of the lane and
1378 // LaneB is the lower 32-bits. Otherwise LaneA and LaneB are alternating
1379 // lanes.
1380 SDValue LaneA;
1381 SDValue LaneB = Op->getOperand(2);
1382
1383 if (ResVecTy == MVT::v2i64) {
1384 LaneA = DAG.getConstant(0, MVT::i32);
1385 ViaVecTy = MVT::v4i32;
1386 } else
1387 LaneA = LaneB;
1388
1389 SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,
1390 LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
1391
1392 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy,
1393 makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
1394
1395 if (ViaVecTy != ResVecTy)
1396 Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, Result);
1397
1398 return Result;
1399}
1400
1401static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) {
1402 return DAG.getConstant(Op->getConstantOperandVal(ImmOp), Op->getValueType(0));
1403}
1404
1405static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue,
1406 bool BigEndian, SelectionDAG &DAG) {
1407 EVT ViaVecTy = VecTy;
1408 SDValue SplatValueA = SplatValue;
1409 SDValue SplatValueB = SplatValue;
1410 SDLoc DL(SplatValue);
1411
1412 if (VecTy == MVT::v2i64) {
1413 // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's.
1414 ViaVecTy = MVT::v4i32;
1415
1416 SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue);
1417 SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue,
1418 DAG.getConstant(32, MVT::i32));
1419 SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB);
1420 }
1421
1422 // We currently hold the parts in little endian order. Swap them if
1423 // necessary.
1424 if (BigEndian)
1425 std::swap(SplatValueA, SplatValueB);
1426
1427 SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1428 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1429 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1430 SplatValueA, SplatValueB, SplatValueA, SplatValueB };
1431
1432 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy,
1433 makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
1434
1435 if (VecTy != ViaVecTy)
1436 Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);
1437
1438 return Result;
1439}
1440
1441static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG,
1442 unsigned Opc, SDValue Imm,
1443 bool BigEndian) {
1444 EVT VecTy = Op->getValueType(0);
1445 SDValue Exp2Imm;
1446 SDLoc DL(Op);
1447
1448 // The DAG Combiner can't constant fold bitcasted vectors yet so we must do it
1449 // here for now.
1450 if (VecTy == MVT::v2i64) {
1451 if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) {
1452 APInt BitImm = APInt(64, 1) << CImm->getAPIntValue();
1453
1454 SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), MVT::i32);
1455 SDValue BitImmLoOp = DAG.getConstant(BitImm.trunc(32), MVT::i32);
1456
1457 if (BigEndian)
1458 std::swap(BitImmLoOp, BitImmHiOp);
1459
1460 Exp2Imm =
1461 DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
1462 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, BitImmLoOp,
1463 BitImmHiOp, BitImmLoOp, BitImmHiOp));
1464 }
1465 }
1466
1467 if (!Exp2Imm.getNode()) {
1468 // We couldnt constant fold, do a vector shift instead
1469
1470 // Extend i32 to i64 if necessary. Sign or zero extend doesn't matter since
1471 // only values 0-63 are valid.
1472 if (VecTy == MVT::v2i64)
1473 Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm);
1474
1475 Exp2Imm = getBuildVectorSplat(VecTy, Imm, BigEndian, DAG);
1476
1477 Exp2Imm =
1478 DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, VecTy), Exp2Imm);
1479 }
1480
1481 return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm);
1482}
1483
1484static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG) {
1485 EVT ResTy = Op->getValueType(0);
1486 SDLoc DL(Op);
1487 SDValue One = DAG.getConstant(1, ResTy);
1488 SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, Op->getOperand(2));
1489
1490 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
1491 DAG.getNOT(DL, Bit, ResTy));
1492}
1493
1494static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) {
1495 SDLoc DL(Op);
1496 EVT ResTy = Op->getValueType(0);
1497 APInt BitImm = APInt(ResTy.getVectorElementType().getSizeInBits(), 1)
1498 << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue();
1499 SDValue BitMask = DAG.getConstant(~BitImm, ResTy);
1500
1501 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
1502}
1503
1504SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1505 SelectionDAG &DAG) const {
1506 SDLoc DL(Op);
1507
1508 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
1509 default:
1510 return SDValue();
1511 case Intrinsic::mips_shilo:
1512 return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1513 case Intrinsic::mips_dpau_h_qbl:
1514 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1515 case Intrinsic::mips_dpau_h_qbr:
1516 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1517 case Intrinsic::mips_dpsu_h_qbl:
1518 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1519 case Intrinsic::mips_dpsu_h_qbr:
1520 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1521 case Intrinsic::mips_dpa_w_ph:
1522 return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1523 case Intrinsic::mips_dps_w_ph:
1524 return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1525 case Intrinsic::mips_dpax_w_ph:
1526 return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1527 case Intrinsic::mips_dpsx_w_ph:
1528 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1529 case Intrinsic::mips_mulsa_w_ph:
1530 return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1531 case Intrinsic::mips_mult:
1532 return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1533 case Intrinsic::mips_multu:
1534 return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1535 case Intrinsic::mips_madd:
1536 return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1537 case Intrinsic::mips_maddu:
1538 return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1539 case Intrinsic::mips_msub:
1540 return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1541 case Intrinsic::mips_msubu:
1542 return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
1543 case Intrinsic::mips_addv_b:
1544 case Intrinsic::mips_addv_h:
1545 case Intrinsic::mips_addv_w:
1546 case Intrinsic::mips_addv_d:
1547 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1548 Op->getOperand(2));
1549 case Intrinsic::mips_addvi_b:
1550 case Intrinsic::mips_addvi_h:
1551 case Intrinsic::mips_addvi_w:
1552 case Intrinsic::mips_addvi_d:
1553 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1554 lowerMSASplatImm(Op, 2, DAG));
1555 case Intrinsic::mips_and_v:
1556 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1557 Op->getOperand(2));
1558 case Intrinsic::mips_andi_b:
1559 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1560 lowerMSASplatImm(Op, 2, DAG));
1561 case Intrinsic::mips_bclr_b:
1562 case Intrinsic::mips_bclr_h:
1563 case Intrinsic::mips_bclr_w:
1564 case Intrinsic::mips_bclr_d:
1565 return lowerMSABitClear(Op, DAG);
1566 case Intrinsic::mips_bclri_b:
1567 case Intrinsic::mips_bclri_h:
1568 case Intrinsic::mips_bclri_w:
1569 case Intrinsic::mips_bclri_d:
1570 return lowerMSABitClearImm(Op, DAG);
1571 case Intrinsic::mips_binsli_b:
1572 case Intrinsic::mips_binsli_h:
1573 case Intrinsic::mips_binsli_w:
1574 case Intrinsic::mips_binsli_d: {
1575 // binsli_x(IfClear, IfSet, nbits) -> (vselect LBitsMask, IfSet, IfClear)
1576 EVT VecTy = Op->getValueType(0);
1577 EVT EltTy = VecTy.getVectorElementType();
1578 APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(),
1579 Op->getConstantOperandVal(3));
1580 return DAG.getNode(ISD::VSELECT, DL, VecTy,
1581 DAG.getConstant(Mask, VecTy, true), Op->getOperand(2),
1582 Op->getOperand(1));
1583 }
1584 case Intrinsic::mips_binsri_b:
1585 case Intrinsic::mips_binsri_h:
1586 case Intrinsic::mips_binsri_w:
1587 case Intrinsic::mips_binsri_d: {
1588 // binsri_x(IfClear, IfSet, nbits) -> (vselect RBitsMask, IfSet, IfClear)
1589 EVT VecTy = Op->getValueType(0);
1590 EVT EltTy = VecTy.getVectorElementType();
1591 APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(),
1592 Op->getConstantOperandVal(3));
1593 return DAG.getNode(ISD::VSELECT, DL, VecTy,
1594 DAG.getConstant(Mask, VecTy, true), Op->getOperand(2),
1595 Op->getOperand(1));
1596 }
1597 case Intrinsic::mips_bmnz_v:
1598 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1599 Op->getOperand(2), Op->getOperand(1));
1600 case Intrinsic::mips_bmnzi_b:
1601 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1602 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2),
1603 Op->getOperand(1));
1604 case Intrinsic::mips_bmz_v:
1605 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1606 Op->getOperand(1), Op->getOperand(2));
1607 case Intrinsic::mips_bmzi_b:
1608 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1609 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1),
1610 Op->getOperand(2));
1611 case Intrinsic::mips_bneg_b:
1612 case Intrinsic::mips_bneg_h:
1613 case Intrinsic::mips_bneg_w:
1614 case Intrinsic::mips_bneg_d: {
1615 EVT VecTy = Op->getValueType(0);
1616 SDValue One = DAG.getConstant(1, VecTy);
1617
1618 return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),
1619 DAG.getNode(ISD::SHL, DL, VecTy, One,
1620 Op->getOperand(2)));
1621 }
1622 case Intrinsic::mips_bnegi_b:
1623 case Intrinsic::mips_bnegi_h:
1624 case Intrinsic::mips_bnegi_w:
1625 case Intrinsic::mips_bnegi_d:
1626 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2),
1627 !Subtarget.isLittle());
1628 case Intrinsic::mips_bnz_b:
1629 case Intrinsic::mips_bnz_h:
1630 case Intrinsic::mips_bnz_w:
1631 case Intrinsic::mips_bnz_d:
1632 return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),
1633 Op->getOperand(1));
1634 case Intrinsic::mips_bnz_v:
1635 return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),
1636 Op->getOperand(1));
1637 case Intrinsic::mips_bsel_v:
1638 // bsel_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1639 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1640 Op->getOperand(1), Op->getOperand(3),
1641 Op->getOperand(2));
1642 case Intrinsic::mips_bseli_b:
1643 // bseli_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1644 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1645 Op->getOperand(1), lowerMSASplatImm(Op, 3, DAG),
1646 Op->getOperand(2));
1647 case Intrinsic::mips_bset_b:
1648 case Intrinsic::mips_bset_h:
1649 case Intrinsic::mips_bset_w:
1650 case Intrinsic::mips_bset_d: {
1651 EVT VecTy = Op->getValueType(0);
1652 SDValue One = DAG.getConstant(1, VecTy);
1653
1654 return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),
1655 DAG.getNode(ISD::SHL, DL, VecTy, One,
1656 Op->getOperand(2)));
1657 }
1658 case Intrinsic::mips_bseti_b:
1659 case Intrinsic::mips_bseti_h:
1660 case Intrinsic::mips_bseti_w:
1661 case Intrinsic::mips_bseti_d:
1662 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2),
1663 !Subtarget.isLittle());
1664 case Intrinsic::mips_bz_b:
1665 case Intrinsic::mips_bz_h:
1666 case Intrinsic::mips_bz_w:
1667 case Intrinsic::mips_bz_d:
1668 return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),
1669 Op->getOperand(1));
1670 case Intrinsic::mips_bz_v:
1671 return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),
1672 Op->getOperand(1));
1673 case Intrinsic::mips_ceq_b:
1674 case Intrinsic::mips_ceq_h:
1675 case Intrinsic::mips_ceq_w:
1676 case Intrinsic::mips_ceq_d:
1677 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1678 Op->getOperand(2), ISD::SETEQ);
1679 case Intrinsic::mips_ceqi_b:
1680 case Intrinsic::mips_ceqi_h:
1681 case Intrinsic::mips_ceqi_w:
1682 case Intrinsic::mips_ceqi_d:
1683 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1684 lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ);
1685 case Intrinsic::mips_cle_s_b:
1686 case Intrinsic::mips_cle_s_h:
1687 case Intrinsic::mips_cle_s_w:
1688 case Intrinsic::mips_cle_s_d:
1689 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1690 Op->getOperand(2), ISD::SETLE);
1691 case Intrinsic::mips_clei_s_b:
1692 case Intrinsic::mips_clei_s_h:
1693 case Intrinsic::mips_clei_s_w:
1694 case Intrinsic::mips_clei_s_d:
1695 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1696 lowerMSASplatImm(Op, 2, DAG), ISD::SETLE);
1697 case Intrinsic::mips_cle_u_b:
1698 case Intrinsic::mips_cle_u_h:
1699 case Intrinsic::mips_cle_u_w:
1700 case Intrinsic::mips_cle_u_d:
1701 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1702 Op->getOperand(2), ISD::SETULE);
1703 case Intrinsic::mips_clei_u_b:
1704 case Intrinsic::mips_clei_u_h:
1705 case Intrinsic::mips_clei_u_w:
1706 case Intrinsic::mips_clei_u_d:
1707 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1708 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1709 case Intrinsic::mips_clt_s_b:
1710 case Intrinsic::mips_clt_s_h:
1711 case Intrinsic::mips_clt_s_w:
1712 case Intrinsic::mips_clt_s_d:
1713 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1714 Op->getOperand(2), ISD::SETLT);
1715 case Intrinsic::mips_clti_s_b:
1716 case Intrinsic::mips_clti_s_h:
1717 case Intrinsic::mips_clti_s_w:
1718 case Intrinsic::mips_clti_s_d:
1719 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1720 lowerMSASplatImm(Op, 2, DAG), ISD::SETLT);
1721 case Intrinsic::mips_clt_u_b:
1722 case Intrinsic::mips_clt_u_h:
1723 case Intrinsic::mips_clt_u_w:
1724 case Intrinsic::mips_clt_u_d:
1725 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1726 Op->getOperand(2), ISD::SETULT);
1727 case Intrinsic::mips_clti_u_b:
1728 case Intrinsic::mips_clti_u_h:
1729 case Intrinsic::mips_clti_u_w:
1730 case Intrinsic::mips_clti_u_d:
1731 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1732 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
1733 case Intrinsic::mips_copy_s_b:
1734 case Intrinsic::mips_copy_s_h:
1735 case Intrinsic::mips_copy_s_w:
1736 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1737 case Intrinsic::mips_copy_s_d:
1738 if (Subtarget.hasMips64())
1739 // Lower directly into VEXTRACT_SEXT_ELT since i64 is legal on Mips64.
1740 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1741 else {
1742 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1743 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1744 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1745 Op->getValueType(0), Op->getOperand(1),
1746 Op->getOperand(2));
1747 }
1748 case Intrinsic::mips_copy_u_b:
1749 case Intrinsic::mips_copy_u_h:
1750 case Intrinsic::mips_copy_u_w:
1751 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1752 case Intrinsic::mips_copy_u_d:
1753 if (Subtarget.hasMips64())
1754 // Lower directly into VEXTRACT_ZEXT_ELT since i64 is legal on Mips64.
1755 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1756 else {
1757 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1758 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1759 // Note: When i64 is illegal, this results in copy_s.w instructions
1760 // instead of copy_u.w instructions. This makes no difference to the
1761 // behaviour since i64 is only illegal when the register file is 32-bit.
1762 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1763 Op->getValueType(0), Op->getOperand(1),
1764 Op->getOperand(2));
1765 }
1766 case Intrinsic::mips_div_s_b:
1767 case Intrinsic::mips_div_s_h:
1768 case Intrinsic::mips_div_s_w:
1769 case Intrinsic::mips_div_s_d:
1770 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1771 Op->getOperand(2));
1772 case Intrinsic::mips_div_u_b:
1773 case Intrinsic::mips_div_u_h:
1774 case Intrinsic::mips_div_u_w:
1775 case Intrinsic::mips_div_u_d:
1776 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1777 Op->getOperand(2));
1778 case Intrinsic::mips_fadd_w:
1779 case Intrinsic::mips_fadd_d:
1780 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1781 Op->getOperand(2));
1782 // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1783 case Intrinsic::mips_fceq_w:
1784 case Intrinsic::mips_fceq_d:
1785 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1786 Op->getOperand(2), ISD::SETOEQ);
1787 case Intrinsic::mips_fcle_w:
1788 case Intrinsic::mips_fcle_d:
1789 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1790 Op->getOperand(2), ISD::SETOLE);
1791 case Intrinsic::mips_fclt_w:
1792 case Intrinsic::mips_fclt_d:
1793 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1794 Op->getOperand(2), ISD::SETOLT);
1795 case Intrinsic::mips_fcne_w:
1796 case Intrinsic::mips_fcne_d:
1797 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1798 Op->getOperand(2), ISD::SETONE);
1799 case Intrinsic::mips_fcor_w:
1800 case Intrinsic::mips_fcor_d:
1801 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1802 Op->getOperand(2), ISD::SETO);
1803 case Intrinsic::mips_fcueq_w:
1804 case Intrinsic::mips_fcueq_d:
1805 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1806 Op->getOperand(2), ISD::SETUEQ);
1807 case Intrinsic::mips_fcule_w:
1808 case Intrinsic::mips_fcule_d:
1809 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1810 Op->getOperand(2), ISD::SETULE);
1811 case Intrinsic::mips_fcult_w:
1812 case Intrinsic::mips_fcult_d:
1813 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1814 Op->getOperand(2), ISD::SETULT);
1815 case Intrinsic::mips_fcun_w:
1816 case Intrinsic::mips_fcun_d:
1817 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1818 Op->getOperand(2), ISD::SETUO);
1819 case Intrinsic::mips_fcune_w:
1820 case Intrinsic::mips_fcune_d:
1821 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1822 Op->getOperand(2), ISD::SETUNE);
1823 case Intrinsic::mips_fdiv_w:
1824 case Intrinsic::mips_fdiv_d:
1825 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1826 Op->getOperand(2));
1827 case Intrinsic::mips_ffint_u_w:
1828 case Intrinsic::mips_ffint_u_d:
1829 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
1830 Op->getOperand(1));
1831 case Intrinsic::mips_ffint_s_w:
1832 case Intrinsic::mips_ffint_s_d:
1833 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
1834 Op->getOperand(1));
1835 case Intrinsic::mips_fill_b:
1836 case Intrinsic::mips_fill_h:
1837 case Intrinsic::mips_fill_w:
1838 case Intrinsic::mips_fill_d: {
1839 SmallVector<SDValue, 16> Ops;
1840 EVT ResTy = Op->getValueType(0);
1841
1842 for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i)
1843 Ops.push_back(Op->getOperand(1));
1844
1845 // If ResTy is v2i64 then the type legalizer will break this node down into
1846 // an equivalent v4i32.
1847 return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, Ops);
1848 }
1849 case Intrinsic::mips_fexp2_w:
1850 case Intrinsic::mips_fexp2_d: {
1851 EVT ResTy = Op->getValueType(0);
1852 return DAG.getNode(
1853 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1854 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
1855 }
1856 case Intrinsic::mips_flog2_w:
1857 case Intrinsic::mips_flog2_d:
1858 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
1859 case Intrinsic::mips_fmadd_w:
1860 case Intrinsic::mips_fmadd_d:
1861 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
1862 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1863 case Intrinsic::mips_fmul_w:
1864 case Intrinsic::mips_fmul_d:
1865 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1866 Op->getOperand(2));
1867 case Intrinsic::mips_fmsub_w:
1868 case Intrinsic::mips_fmsub_d: {
1869 EVT ResTy = Op->getValueType(0);
1870 return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1),
1871 DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy,
1872 Op->getOperand(2), Op->getOperand(3)));
1873 }
1874 case Intrinsic::mips_frint_w:
1875 case Intrinsic::mips_frint_d:
1876 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
1877 case Intrinsic::mips_fsqrt_w:
1878 case Intrinsic::mips_fsqrt_d:
1879 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
1880 case Intrinsic::mips_fsub_w:
1881 case Intrinsic::mips_fsub_d:
1882 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1883 Op->getOperand(2));
1884 case Intrinsic::mips_ftrunc_u_w:
1885 case Intrinsic::mips_ftrunc_u_d:
1886 return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
1887 Op->getOperand(1));
1888 case Intrinsic::mips_ftrunc_s_w:
1889 case Intrinsic::mips_ftrunc_s_d:
1890 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
1891 Op->getOperand(1));
1892 case Intrinsic::mips_ilvev_b:
1893 case Intrinsic::mips_ilvev_h:
1894 case Intrinsic::mips_ilvev_w:
1895 case Intrinsic::mips_ilvev_d:
1896 return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),
1897 Op->getOperand(1), Op->getOperand(2));
1898 case Intrinsic::mips_ilvl_b:
1899 case Intrinsic::mips_ilvl_h:
1900 case Intrinsic::mips_ilvl_w:
1901 case Intrinsic::mips_ilvl_d:
1902 return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),
1903 Op->getOperand(1), Op->getOperand(2));
1904 case Intrinsic::mips_ilvod_b:
1905 case Intrinsic::mips_ilvod_h:
1906 case Intrinsic::mips_ilvod_w:
1907 case Intrinsic::mips_ilvod_d:
1908 return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),
1909 Op->getOperand(1), Op->getOperand(2));
1910 case Intrinsic::mips_ilvr_b:
1911 case Intrinsic::mips_ilvr_h:
1912 case Intrinsic::mips_ilvr_w:
1913 case Intrinsic::mips_ilvr_d:
1914 return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),
1915 Op->getOperand(1), Op->getOperand(2));
1916 case Intrinsic::mips_insert_b:
1917 case Intrinsic::mips_insert_h:
1918 case Intrinsic::mips_insert_w:
1919 case Intrinsic::mips_insert_d:
1920 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1921 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
1922 case Intrinsic::mips_insve_b:
1923 case Intrinsic::mips_insve_h:
1924 case Intrinsic::mips_insve_w:
1925 case Intrinsic::mips_insve_d:
1926 return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0),
1927 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3),
1928 DAG.getConstant(0, MVT::i32));
1929 case Intrinsic::mips_ldi_b:
1930 case Intrinsic::mips_ldi_h:
1931 case Intrinsic::mips_ldi_w:
1932 case Intrinsic::mips_ldi_d:
1933 return lowerMSASplatImm(Op, 1, DAG);
1934 case Intrinsic::mips_lsa:
1935 case Intrinsic::mips_dlsa: {
1936 EVT ResTy = Op->getValueType(0);
1937 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1938 DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
1939 Op->getOperand(2), Op->getOperand(3)));
1940 }
1941 case Intrinsic::mips_maddv_b:
1942 case Intrinsic::mips_maddv_h:
1943 case Intrinsic::mips_maddv_w:
1944 case Intrinsic::mips_maddv_d: {
1945 EVT ResTy = Op->getValueType(0);
1946 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1947 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1948 Op->getOperand(2), Op->getOperand(3)));
1949 }
1950 case Intrinsic::mips_max_s_b:
1951 case Intrinsic::mips_max_s_h:
1952 case Intrinsic::mips_max_s_w:
1953 case Intrinsic::mips_max_s_d:
1954 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1955 Op->getOperand(1), Op->getOperand(2));
1956 case Intrinsic::mips_max_u_b:
1957 case Intrinsic::mips_max_u_h:
1958 case Intrinsic::mips_max_u_w:
1959 case Intrinsic::mips_max_u_d:
1960 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1961 Op->getOperand(1), Op->getOperand(2));
1962 case Intrinsic::mips_maxi_s_b:
1963 case Intrinsic::mips_maxi_s_h:
1964 case Intrinsic::mips_maxi_s_w:
1965 case Intrinsic::mips_maxi_s_d:
1966 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1967 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1968 case Intrinsic::mips_maxi_u_b:
1969 case Intrinsic::mips_maxi_u_h:
1970 case Intrinsic::mips_maxi_u_w:
1971 case Intrinsic::mips_maxi_u_d:
1972 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1973 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1974 case Intrinsic::mips_min_s_b:
1975 case Intrinsic::mips_min_s_h:
1976 case Intrinsic::mips_min_s_w:
1977 case Intrinsic::mips_min_s_d:
1978 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1979 Op->getOperand(1), Op->getOperand(2));
1980 case Intrinsic::mips_min_u_b:
1981 case Intrinsic::mips_min_u_h:
1982 case Intrinsic::mips_min_u_w:
1983 case Intrinsic::mips_min_u_d:
1984 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1985 Op->getOperand(1), Op->getOperand(2));
1986 case Intrinsic::mips_mini_s_b:
1987 case Intrinsic::mips_mini_s_h:
1988 case Intrinsic::mips_mini_s_w:
1989 case Intrinsic::mips_mini_s_d:
1990 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1991 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1992 case Intrinsic::mips_mini_u_b:
1993 case Intrinsic::mips_mini_u_h:
1994 case Intrinsic::mips_mini_u_w:
1995 case Intrinsic::mips_mini_u_d:
1996 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1997 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1998 case Intrinsic::mips_mod_s_b:
1999 case Intrinsic::mips_mod_s_h:
2000 case Intrinsic::mips_mod_s_w:
2001 case Intrinsic::mips_mod_s_d:
2002 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
2003 Op->getOperand(2));
2004 case Intrinsic::mips_mod_u_b:
2005 case Intrinsic::mips_mod_u_h:
2006 case Intrinsic::mips_mod_u_w:
2007 case Intrinsic::mips_mod_u_d:
2008 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
2009 Op->getOperand(2));
2010 case Intrinsic::mips_mulv_b:
2011 case Intrinsic::mips_mulv_h:
2012 case Intrinsic::mips_mulv_w:
2013 case Intrinsic::mips_mulv_d:
2014 return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
2015 Op->getOperand(2));
2016 case Intrinsic::mips_msubv_b:
2017 case Intrinsic::mips_msubv_h:
2018 case Intrinsic::mips_msubv_w:
2019 case Intrinsic::mips_msubv_d: {
2020 EVT ResTy = Op->getValueType(0);
2021 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
2022 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
2023 Op->getOperand(2), Op->getOperand(3)));
2024 }
2025 case Intrinsic::mips_nlzc_b:
2026 case Intrinsic::mips_nlzc_h:
2027 case Intrinsic::mips_nlzc_w:
2028 case Intrinsic::mips_nlzc_d:
2029 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
2030 case Intrinsic::mips_nor_v: {
2031 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2032 Op->getOperand(1), Op->getOperand(2));
2033 return DAG.getNOT(DL, Res, Res->getValueType(0));
2034 }
2035 case Intrinsic::mips_nori_b: {
2036 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2037 Op->getOperand(1),
2038 lowerMSASplatImm(Op, 2, DAG));
2039 return DAG.getNOT(DL, Res, Res->getValueType(0));
2040 }
2041 case Intrinsic::mips_or_v:
2042 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
2043 Op->getOperand(2));
2044 case Intrinsic::mips_ori_b:
2045 return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2046 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2047 case Intrinsic::mips_pckev_b:
2048 case Intrinsic::mips_pckev_h:
2049 case Intrinsic::mips_pckev_w:
2050 case Intrinsic::mips_pckev_d:
2051 return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),
2052 Op->getOperand(1), Op->getOperand(2));
2053 case Intrinsic::mips_pckod_b:
2054 case Intrinsic::mips_pckod_h:
2055 case Intrinsic::mips_pckod_w:
2056 case Intrinsic::mips_pckod_d:
2057 return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),
2058 Op->getOperand(1), Op->getOperand(2));
2059 case Intrinsic::mips_pcnt_b:
2060 case Intrinsic::mips_pcnt_h:
2061 case Intrinsic::mips_pcnt_w:
2062 case Intrinsic::mips_pcnt_d:
2063 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
2064 case Intrinsic::mips_shf_b:
2065 case Intrinsic::mips_shf_h:
2066 case Intrinsic::mips_shf_w:
2067 return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),
2068 Op->getOperand(2), Op->getOperand(1));
2069 case Intrinsic::mips_sll_b:
2070 case Intrinsic::mips_sll_h:
2071 case Intrinsic::mips_sll_w:
2072 case Intrinsic::mips_sll_d:
2073 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
2074 Op->getOperand(2));
2075 case Intrinsic::mips_slli_b:
2076 case Intrinsic::mips_slli_h:
2077 case Intrinsic::mips_slli_w:
2078 case Intrinsic::mips_slli_d:
2079 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
2080 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2081 case Intrinsic::mips_splat_b:
2082 case Intrinsic::mips_splat_h:
2083 case Intrinsic::mips_splat_w:
2084 case Intrinsic::mips_splat_d:
2085 // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle
2086 // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because
2087 // EXTRACT_VECTOR_ELT can't extract i64's on MIPS32.
2088 // Instead we lower to MipsISD::VSHF and match from there.
2089 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2090 lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1),
2091 Op->getOperand(1));
2092 case Intrinsic::mips_splati_b:
2093 case Intrinsic::mips_splati_h:
2094 case Intrinsic::mips_splati_w:
2095 case Intrinsic::mips_splati_d:
2096 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2097 lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
2098 Op->getOperand(1));
2099 case Intrinsic::mips_sra_b:
2100 case Intrinsic::mips_sra_h:
2101 case Intrinsic::mips_sra_w:
2102 case Intrinsic::mips_sra_d:
2103 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
2104 Op->getOperand(2));
2105 case Intrinsic::mips_srai_b:
2106 case Intrinsic::mips_srai_h:
2107 case Intrinsic::mips_srai_w:
2108 case Intrinsic::mips_srai_d:
2109 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
2110 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2111 case Intrinsic::mips_srl_b:
2112 case Intrinsic::mips_srl_h:
2113 case Intrinsic::mips_srl_w:
2114 case Intrinsic::mips_srl_d:
2115 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
2116 Op->getOperand(2));
2117 case Intrinsic::mips_srli_b:
2118 case Intrinsic::mips_srli_h:
2119 case Intrinsic::mips_srli_w:
2120 case Intrinsic::mips_srli_d:
2121 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
2122 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2123 case Intrinsic::mips_subv_b:
2124 case Intrinsic::mips_subv_h:
2125 case Intrinsic::mips_subv_w:
2126 case Intrinsic::mips_subv_d:
2127 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
2128 Op->getOperand(2));
2129 case Intrinsic::mips_subvi_b:
2130 case Intrinsic::mips_subvi_h:
2131 case Intrinsic::mips_subvi_w:
2132 case Intrinsic::mips_subvi_d:
2133 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
2134 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2135 case Intrinsic::mips_vshf_b:
2136 case Intrinsic::mips_vshf_h:
2137 case Intrinsic::mips_vshf_w:
2138 case Intrinsic::mips_vshf_d:
2139 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2140 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
2141 case Intrinsic::mips_xor_v:
2142 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
2143 Op->getOperand(2));
2144 case Intrinsic::mips_xori_b:
2145 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
2146 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2147 }
2148}
2149
2150static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
2151 SDLoc DL(Op);
2152 SDValue ChainIn = Op->getOperand(0);
2153 SDValue Address = Op->getOperand(2);
2154 SDValue Offset = Op->getOperand(3);
2155 EVT ResTy = Op->getValueType(0);
2156 EVT PtrTy = Address->getValueType(0);
2157
2158 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2159
2160 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
2161 false, false, 16);
2162}
2163
2164SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
2165 SelectionDAG &DAG) const {
2166 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2167 switch (Intr) {
2168 default:
2169 return SDValue();
2170 case Intrinsic::mips_extp:
2171 return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
2172 case Intrinsic::mips_extpdp:
2173 return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
2174 case Intrinsic::mips_extr_w:
2175 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
2176 case Intrinsic::mips_extr_r_w:
2177 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
2178 case Intrinsic::mips_extr_rs_w:
2179 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
2180 case Intrinsic::mips_extr_s_h:
2181 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
2182 case Intrinsic::mips_mthlip:
2183 return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
2184 case Intrinsic::mips_mulsaq_s_w_ph:
2185 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
2186 case Intrinsic::mips_maq_s_w_phl:
2187 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
2188 case Intrinsic::mips_maq_s_w_phr:
2189 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
2190 case Intrinsic::mips_maq_sa_w_phl:
2191 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
2192 case Intrinsic::mips_maq_sa_w_phr:
2193 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
2194 case Intrinsic::mips_dpaq_s_w_ph:
2195 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
2196 case Intrinsic::mips_dpsq_s_w_ph:
2197 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
2198 case Intrinsic::mips_dpaq_sa_l_w:
2199 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
2200 case Intrinsic::mips_dpsq_sa_l_w:
2201 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
2202 case Intrinsic::mips_dpaqx_s_w_ph:
2203 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
2204 case Intrinsic::mips_dpaqx_sa_w_ph:
2205 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
2206 case Intrinsic::mips_dpsqx_s_w_ph:
2207 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
2208 case Intrinsic::mips_dpsqx_sa_w_ph:
2209 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
2210 case Intrinsic::mips_ld_b:
2211 case Intrinsic::mips_ld_h:
2212 case Intrinsic::mips_ld_w:
2213 case Intrinsic::mips_ld_d:
2214 return lowerMSALoadIntr(Op, DAG, Intr);
2215 }
2216}
2217
2218static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
2219 SDLoc DL(Op);
2220 SDValue ChainIn = Op->getOperand(0);
2221 SDValue Value = Op->getOperand(2);
2222 SDValue Address = Op->getOperand(3);
2223 SDValue Offset = Op->getOperand(4);
2224 EVT PtrTy = Address->getValueType(0);
2225
2226 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2227
2228 return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
2229 false, 16);
2230}
2231
2232SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
2233 SelectionDAG &DAG) const {
2234 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2235 switch (Intr) {
2236 default:
2237 return SDValue();
2238 case Intrinsic::mips_st_b:
2239 case Intrinsic::mips_st_h:
2240 case Intrinsic::mips_st_w:
2241 case Intrinsic::mips_st_d:
2242 return lowerMSAStoreIntr(Op, DAG, Intr);
2243 }
2244}
2245
2246/// \brief Check if the given BuildVectorSDNode is a splat.
2247/// This method currently relies on DAG nodes being reused when equivalent,
2248/// so it's possible for this to return false even when isConstantSplat returns
2249/// true.
2250static bool isSplatVector(const BuildVectorSDNode *N) {
2251 unsigned int nOps = N->getNumOperands();
2252 assert(nOps > 1 && "isSplatVector has 0 or 1 sized build vector");
2253
2254 SDValue Operand0 = N->getOperand(0);
2255
2256 for (unsigned int i = 1; i < nOps; ++i) {
2257 if (N->getOperand(i) != Operand0)
2258 return false;
2259 }
2260
2261 return true;
2262}
2263
2264// Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
2265//
2266// The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
2267// choose to sign-extend but we could have equally chosen zero-extend. The
2268// DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
2269// result into this node later (possibly changing it to a zero-extend in the
2270// process).
2271SDValue MipsSETargetLowering::
2272lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
2273 SDLoc DL(Op);
2274 EVT ResTy = Op->getValueType(0);
2275 SDValue Op0 = Op->getOperand(0);
2276 EVT VecTy = Op0->getValueType(0);
2277
2278 if (!VecTy.is128BitVector())
2279 return SDValue();
2280
2281 if (ResTy.isInteger()) {
2282 SDValue Op1 = Op->getOperand(1);
2283 EVT EltTy = VecTy.getVectorElementType();
2284 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
2285 DAG.getValueType(EltTy));
2286 }
2287
2288 return Op;
2289}
2290
2291static bool isConstantOrUndef(const SDValue Op) {
2292 if (Op->getOpcode() == ISD::UNDEF)
2293 return true;
2294 if (dyn_cast<ConstantSDNode>(Op))
2295 return true;
2296 if (dyn_cast<ConstantFPSDNode>(Op))
2297 return true;
2298 return false;
2299}
2300
2301static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) {
2302 for (unsigned i = 0; i < Op->getNumOperands(); ++i)
2303 if (isConstantOrUndef(Op->getOperand(i)))
2304 return true;
2305 return false;
2306}
2307
2308// Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
2309// backend.
2310//
2311// Lowers according to the following rules:
2312// - Constant splats are legal as-is as long as the SplatBitSize is a power of
2313// 2 less than or equal to 64 and the value fits into a signed 10-bit
2314// immediate
2315// - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
2316// is a power of 2 less than or equal to 64 and the value does not fit into a
2317// signed 10-bit immediate
2318// - Non-constant splats are legal as-is.
2319// - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
2320// - All others are illegal and must be expanded.
2321SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
2322 SelectionDAG &DAG) const {
2323 BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
2324 EVT ResTy = Op->getValueType(0);
2325 SDLoc DL(Op);
2326 APInt SplatValue, SplatUndef;
2327 unsigned SplatBitSize;
2328 bool HasAnyUndefs;
2329
2330 if (!Subtarget.hasMSA() || !ResTy.is128BitVector())
2331 return SDValue();
2332
2333 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
2334 HasAnyUndefs, 8,
2335 !Subtarget.isLittle()) && SplatBitSize <= 64) {
2336 // We can only cope with 8, 16, 32, or 64-bit elements
2337 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
2338 SplatBitSize != 64)
2339 return SDValue();
2340
2341 // If the value fits into a simm10 then we can use ldi.[bhwd]
2342 // However, if it isn't an integer type we will have to bitcast from an
2343 // integer type first. Also, if there are any undefs, we must lower them
2344 // to defined values first.
2345 if (ResTy.isInteger() && !HasAnyUndefs && SplatValue.isSignedIntN(10))
2346 return Op;
2347
2348 EVT ViaVecTy;
2349
2350 switch (SplatBitSize) {
2351 default:
2352 return SDValue();
2353 case 8:
2354 ViaVecTy = MVT::v16i8;
2355 break;
2356 case 16:
2357 ViaVecTy = MVT::v8i16;
2358 break;
2359 case 32:
2360 ViaVecTy = MVT::v4i32;
2361 break;
2362 case 64:
2363 // There's no fill.d to fall back on for 64-bit values
2364 return SDValue();
2365 }
2366
2367 // SelectionDAG::getConstant will promote SplatValue appropriately.
2368 SDValue Result = DAG.getConstant(SplatValue, ViaVecTy);
2369
2370 // Bitcast to the type we originally wanted
2371 if (ViaVecTy != ResTy)
2372 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
2373
2374 return Result;
2375 } else if (isSplatVector(Node))
2376 return Op;
2377 else if (!isConstantOrUndefBUILD_VECTOR(Node)) {
2378 // Use INSERT_VECTOR_ELT operations rather than expand to stores.
2379 // The resulting code is the same length as the expansion, but it doesn't
2380 // use memory operations
2381 EVT ResTy = Node->getValueType(0);
2382
2383 assert(ResTy.isVector());
2384
2385 unsigned NumElts = ResTy.getVectorNumElements();
2386 SDValue Vector = DAG.getUNDEF(ResTy);
2387 for (unsigned i = 0; i < NumElts; ++i) {
2388 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
2389 Node->getOperand(i),
2390 DAG.getConstant(i, MVT::i32));
2391 }
2392 return Vector;
2393 }
2394
2395 return SDValue();
2396}
2397
2398// Lower VECTOR_SHUFFLE into SHF (if possible).
2399//
2400// SHF splits the vector into blocks of four elements, then shuffles these
2401// elements according to a <4 x i2> constant (encoded as an integer immediate).
2402//
2403// It is therefore possible to lower into SHF when the mask takes the form:
2404// <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...>
2405// When undef's appear they are treated as if they were whatever value is
2406// necessary in order to fit the above form.
2407//
2408// For example:
2409// %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
2410// <8 x i32> <i32 3, i32 2, i32 1, i32 0,
2411// i32 7, i32 6, i32 5, i32 4>
2412// is lowered to:
2413// (SHF_H $w0, $w1, 27)
2414// where the 27 comes from:
2415// 3 + (2 << 2) + (1 << 4) + (0 << 6)
2416static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy,
2417 SmallVector<int, 16> Indices,
2418 SelectionDAG &DAG) {
2419 int SHFIndices[4] = { -1, -1, -1, -1 };
2420
2421 if (Indices.size() < 4)
2422 return SDValue();
2423
2424 for (unsigned i = 0; i < 4; ++i) {
2425 for (unsigned j = i; j < Indices.size(); j += 4) {
2426 int Idx = Indices[j];
2427
2428 // Convert from vector index to 4-element subvector index
2429 // If an index refers to an element outside of the subvector then give up
2430 if (Idx != -1) {
2431 Idx -= 4 * (j / 4);
2432 if (Idx < 0 || Idx >= 4)
2433 return SDValue();
2434 }
2435
2436 // If the mask has an undef, replace it with the current index.
2437 // Note that it might still be undef if the current index is also undef
2438 if (SHFIndices[i] == -1)
2439 SHFIndices[i] = Idx;
2440
2441 // Check that non-undef values are the same as in the mask. If they
2442 // aren't then give up
2443 if (!(Idx == -1 || Idx == SHFIndices[i]))
2444 return SDValue();
2445 }
2446 }
2447
2448 // Calculate the immediate. Replace any remaining undefs with zero
2449 APInt Imm(32, 0);
2450 for (int i = 3; i >= 0; --i) {
2451 int Idx = SHFIndices[i];
2452
2453 if (Idx == -1)
2454 Idx = 0;
2455
2456 Imm <<= 2;
2457 Imm |= Idx & 0x3;
2458 }
2459
2460 return DAG.getNode(MipsISD::SHF, SDLoc(Op), ResTy,
2461 DAG.getConstant(Imm, MVT::i32), Op->getOperand(0));
2462}
2463
2464// Lower VECTOR_SHUFFLE into ILVEV (if possible).
2465//
2466// ILVEV interleaves the even elements from each vector.
2467//
2468// It is possible to lower into ILVEV when the mask takes the form:
2469// <0, n, 2, n+2, 4, n+4, ...>
2470// where n is the number of elements in the vector.
2471//
2472// When undef's appear in the mask they are treated as if they were whatever
2473// value is necessary in order to fit the above form.
2474static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy,
2475 SmallVector<int, 16> Indices,
2476 SelectionDAG &DAG) {
2477 assert ((Indices.size() % 2) == 0);
2478 int WsIdx = 0;
2479 int WtIdx = ResTy.getVectorNumElements();
2480
2481 for (unsigned i = 0; i < Indices.size(); i += 2) {
2482 if (Indices[i] != -1 && Indices[i] != WsIdx)
2483 return SDValue();
2484 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2485 return SDValue();
2486 WsIdx += 2;
2487 WtIdx += 2;
2488 }
2489
2490 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Op->getOperand(0),
2491 Op->getOperand(1));
2492}
2493
2494// Lower VECTOR_SHUFFLE into ILVOD (if possible).
2495//
2496// ILVOD interleaves the odd elements from each vector.
2497//
2498// It is possible to lower into ILVOD when the mask takes the form:
2499// <1, n+1, 3, n+3, 5, n+5, ...>
2500// where n is the number of elements in the vector.
2501//
2502// When undef's appear in the mask they are treated as if they were whatever
2503// value is necessary in order to fit the above form.
2504static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy,
2505 SmallVector<int, 16> Indices,
2506 SelectionDAG &DAG) {
2507 assert ((Indices.size() % 2) == 0);
2508 int WsIdx = 1;
2509 int WtIdx = ResTy.getVectorNumElements() + 1;
2510
2511 for (unsigned i = 0; i < Indices.size(); i += 2) {
2512 if (Indices[i] != -1 && Indices[i] != WsIdx)
2513 return SDValue();
2514 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2515 return SDValue();
2516 WsIdx += 2;
2517 WtIdx += 2;
2518 }
2519
2520 return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Op->getOperand(0),
2521 Op->getOperand(1));
2522}
2523
2524// Lower VECTOR_SHUFFLE into ILVL (if possible).
2525//
2526// ILVL interleaves consecutive elements from the left half of each vector.
2527//
2528// It is possible to lower into ILVL when the mask takes the form:
2529// <0, n, 1, n+1, 2, n+2, ...>
2530// where n is the number of elements in the vector.
2531//
2532// When undef's appear in the mask they are treated as if they were whatever
2533// value is necessary in order to fit the above form.
2534static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy,
2535 SmallVector<int, 16> Indices,
2536 SelectionDAG &DAG) {
2537 assert ((Indices.size() % 2) == 0);
2538 int WsIdx = 0;
2539 int WtIdx = ResTy.getVectorNumElements();
2540
2541 for (unsigned i = 0; i < Indices.size(); i += 2) {
2542 if (Indices[i] != -1 && Indices[i] != WsIdx)
2543 return SDValue();
2544 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2545 return SDValue();
2546 WsIdx ++;
2547 WtIdx ++;
2548 }
2549
2550 return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Op->getOperand(0),
2551 Op->getOperand(1));
2552}
2553
2554// Lower VECTOR_SHUFFLE into ILVR (if possible).
2555//
2556// ILVR interleaves consecutive elements from the right half of each vector.
2557//
2558// It is possible to lower into ILVR when the mask takes the form:
2559// <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>
2560// where n is the number of elements in the vector and x is half n.
2561//
2562// When undef's appear in the mask they are treated as if they were whatever
2563// value is necessary in order to fit the above form.
2564static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy,
2565 SmallVector<int, 16> Indices,
2566 SelectionDAG &DAG) {
2567 assert ((Indices.size() % 2) == 0);
2568 unsigned NumElts = ResTy.getVectorNumElements();
2569 int WsIdx = NumElts / 2;
2570 int WtIdx = NumElts + NumElts / 2;
2571
2572 for (unsigned i = 0; i < Indices.size(); i += 2) {
2573 if (Indices[i] != -1 && Indices[i] != WsIdx)
2574 return SDValue();
2575 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2576 return SDValue();
2577 WsIdx ++;
2578 WtIdx ++;
2579 }
2580
2581 return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Op->getOperand(0),
2582 Op->getOperand(1));
2583}
2584
2585// Lower VECTOR_SHUFFLE into PCKEV (if possible).
2586//
2587// PCKEV copies the even elements of each vector into the result vector.
2588//
2589// It is possible to lower into PCKEV when the mask takes the form:
2590// <0, 2, 4, ..., n, n+2, n+4, ...>
2591// where n is the number of elements in the vector.
2592//
2593// When undef's appear in the mask they are treated as if they were whatever
2594// value is necessary in order to fit the above form.
2595static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy,
2596 SmallVector<int, 16> Indices,
2597 SelectionDAG &DAG) {
2598 assert ((Indices.size() % 2) == 0);
2599 int Idx = 0;
2600
2601 for (unsigned i = 0; i < Indices.size(); ++i) {
2602 if (Indices[i] != -1 && Indices[i] != Idx)
2603 return SDValue();
2604 Idx += 2;
2605 }
2606
2607 return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Op->getOperand(0),
2608 Op->getOperand(1));
2609}
2610
2611// Lower VECTOR_SHUFFLE into PCKOD (if possible).
2612//
2613// PCKOD copies the odd elements of each vector into the result vector.
2614//
2615// It is possible to lower into PCKOD when the mask takes the form:
2616// <1, 3, 5, ..., n+1, n+3, n+5, ...>
2617// where n is the number of elements in the vector.
2618//
2619// When undef's appear in the mask they are treated as if they were whatever
2620// value is necessary in order to fit the above form.
2621static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy,
2622 SmallVector<int, 16> Indices,
2623 SelectionDAG &DAG) {
2624 assert ((Indices.size() % 2) == 0);
2625 int Idx = 1;
2626
2627 for (unsigned i = 0; i < Indices.size(); ++i) {
2628 if (Indices[i] != -1 && Indices[i] != Idx)
2629 return SDValue();
2630 Idx += 2;
2631 }
2632
2633 return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Op->getOperand(0),
2634 Op->getOperand(1));
2635}
2636
2637// Lower VECTOR_SHUFFLE into VSHF.
2638//
2639// This mostly consists of converting the shuffle indices in Indices into a
2640// BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is
2641// also code to eliminate unused operands of the VECTOR_SHUFFLE. For example,
2642// if the type is v8i16 and all the indices are less than 8 then the second
2643// operand is unused and can be replaced with anything. We choose to replace it
2644// with the used operand since this reduces the number of instructions overall.
2645static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
2646 SmallVector<int, 16> Indices,
2647 SelectionDAG &DAG) {
2648 SmallVector<SDValue, 16> Ops;
2649 SDValue Op0;
2650 SDValue Op1;
2651 EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2652 EVT MaskEltTy = MaskVecTy.getVectorElementType();
2653 bool Using1stVec = false;
2654 bool Using2ndVec = false;
2655 SDLoc DL(Op);
2656 int ResTyNumElts = ResTy.getVectorNumElements();
2657
2658 for (int i = 0; i < ResTyNumElts; ++i) {
2659 // Idx == -1 means UNDEF
2660 int Idx = Indices[i];
2661
2662 if (0 <= Idx && Idx < ResTyNumElts)
2663 Using1stVec = true;
2664 if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
2665 Using2ndVec = true;
2666 }
2667
2668 for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
2669 ++I)
2670 Ops.push_back(DAG.getTargetConstant(*I, MaskEltTy));
2671
2672 SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, Ops);
2673
2674 if (Using1stVec && Using2ndVec) {
2675 Op0 = Op->getOperand(0);
2676 Op1 = Op->getOperand(1);
2677 } else if (Using1stVec)
2678 Op0 = Op1 = Op->getOperand(0);
2679 else if (Using2ndVec)
2680 Op0 = Op1 = Op->getOperand(1);
2681 else
2682 llvm_unreachable("shuffle vector mask references neither vector operand?");
2683
2684 // VECTOR_SHUFFLE concatenates the vectors in an vectorwise fashion.
2685 // <0b00, 0b01> + <0b10, 0b11> -> <0b00, 0b01, 0b10, 0b11>
2686 // VSHF concatenates the vectors in a bitwise fashion:
2687 // <0b00, 0b01> + <0b10, 0b11> ->
2688 // 0b0100 + 0b1110 -> 0b01001110
2689 // <0b10, 0b11, 0b00, 0b01>
2690 // We must therefore swap the operands to get the correct result.
2691 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op1, Op0);
2692}
2693
2694// Lower VECTOR_SHUFFLE into one of a number of instructions depending on the
2695// indices in the shuffle.
2696SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
2697 SelectionDAG &DAG) const {
2698 ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
2699 EVT ResTy = Op->getValueType(0);
2700
2701 if (!ResTy.is128BitVector())
2702 return SDValue();
2703
2704 int ResTyNumElts = ResTy.getVectorNumElements();
2705 SmallVector<int, 16> Indices;
2706
2707 for (int i = 0; i < ResTyNumElts; ++i)
2708 Indices.push_back(Node->getMaskElt(i));
2709
2710 SDValue Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG);
2711 if (Result.getNode())
2712 return Result;
2713 Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG);
2714 if (Result.getNode())
2715 return Result;
2716 Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG);
2717 if (Result.getNode())
2718 return Result;
2719 Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG);
2720 if (Result.getNode())
2721 return Result;
2722 Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG);
2723 if (Result.getNode())
2724 return Result;
2725 Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG);
2726 if (Result.getNode())
2727 return Result;
2728 Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG);
2729 if (Result.getNode())
2730 return Result;
2731 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2732}
2733
2734MachineBasicBlock * MipsSETargetLowering::
2735emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
2736 // $bb:
2737 // bposge32_pseudo $vr0
2738 // =>
2739 // $bb:
2740 // bposge32 $tbb
2741 // $fbb:
2742 // li $vr2, 0
2743 // b $sink
2744 // $tbb:
2745 // li $vr1, 1
2746 // $sink:
2747 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
2748
2749 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2750 const TargetInstrInfo *TII =
2751 getTargetMachine().getSubtargetImpl()->getInstrInfo();
2752 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2753 DebugLoc DL = MI->getDebugLoc();
2754 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2755 MachineFunction::iterator It = std::next(MachineFunction::iterator(BB));
2756 MachineFunction *F = BB->getParent();
2757 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2758 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2759 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
2760 F->insert(It, FBB);
2761 F->insert(It, TBB);
2762 F->insert(It, Sink);
2763
2764 // Transfer the remainder of BB and its successor edges to Sink.
2765 Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
2766 BB->end());
2767 Sink->transferSuccessorsAndUpdatePHIs(BB);
2768
2769 // Add successors.
2770 BB->addSuccessor(FBB);
2771 BB->addSuccessor(TBB);
2772 FBB->addSuccessor(Sink);
2773 TBB->addSuccessor(Sink);
2774
2775 // Insert the real bposge32 instruction to $BB.
2776 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
2777
2778 // Fill $FBB.
2779 unsigned VR2 = RegInfo.createVirtualRegister(RC);
2780 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
2781 .addReg(Mips::ZERO).addImm(0);
2782 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2783
2784 // Fill $TBB.
2785 unsigned VR1 = RegInfo.createVirtualRegister(RC);
2786 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
2787 .addReg(Mips::ZERO).addImm(1);
2788
2789 // Insert phi function to $Sink.
2790 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2791 MI->getOperand(0).getReg())
2792 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
2793
2794 MI->eraseFromParent(); // The pseudo instruction is gone now.
2795 return Sink;
2796}
2797
2798MachineBasicBlock * MipsSETargetLowering::
2799emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
2800 unsigned BranchOp) const{
2801 // $bb:
2802 // vany_nonzero $rd, $ws
2803 // =>
2804 // $bb:
2805 // bnz.b $ws, $tbb
2806 // b $fbb
2807 // $fbb:
2808 // li $rd1, 0
2809 // b $sink
2810 // $tbb:
2811 // li $rd2, 1
2812 // $sink:
2813 // $rd = phi($rd1, $fbb, $rd2, $tbb)
2814
2815 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2816 const TargetInstrInfo *TII =
2817 getTargetMachine().getSubtargetImpl()->getInstrInfo();
2818 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2819 DebugLoc DL = MI->getDebugLoc();
2820 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2821 MachineFunction::iterator It = std::next(MachineFunction::iterator(BB));
2822 MachineFunction *F = BB->getParent();
2823 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2824 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2825 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
2826 F->insert(It, FBB);
2827 F->insert(It, TBB);
2828 F->insert(It, Sink);
2829
2830 // Transfer the remainder of BB and its successor edges to Sink.
2831 Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
2832 BB->end());
2833 Sink->transferSuccessorsAndUpdatePHIs(BB);
2834
2835 // Add successors.
2836 BB->addSuccessor(FBB);
2837 BB->addSuccessor(TBB);
2838 FBB->addSuccessor(Sink);
2839 TBB->addSuccessor(Sink);
2840
2841 // Insert the real bnz.b instruction to $BB.
2842 BuildMI(BB, DL, TII->get(BranchOp))
2843 .addReg(MI->getOperand(1).getReg())
2844 .addMBB(TBB);
2845
2846 // Fill $FBB.
2847 unsigned RD1 = RegInfo.createVirtualRegister(RC);
2848 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
2849 .addReg(Mips::ZERO).addImm(0);
2850 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2851
2852 // Fill $TBB.
2853 unsigned RD2 = RegInfo.createVirtualRegister(RC);
2854 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
2855 .addReg(Mips::ZERO).addImm(1);
2856
2857 // Insert phi function to $Sink.
2858 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2859 MI->getOperand(0).getReg())
2860 .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
2861
2862 MI->eraseFromParent(); // The pseudo instruction is gone now.
2863 return Sink;
2864}
2865
2866// Emit the COPY_FW pseudo instruction.
2867//
2868// copy_fw_pseudo $fd, $ws, n
2869// =>
2870// copy_u_w $rt, $ws, $n
2871// mtc1 $rt, $fd
2872//
2873// When n is zero, the equivalent operation can be performed with (potentially)
2874// zero instructions due to register overlaps. This optimization is never valid
2875// for lane 1 because it would require FR=0 mode which isn't supported by MSA.
2876MachineBasicBlock * MipsSETargetLowering::
2877emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{
2878 const TargetInstrInfo *TII =
2879 getTargetMachine().getSubtargetImpl()->getInstrInfo();
2880 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2881 DebugLoc DL = MI->getDebugLoc();
2882 unsigned Fd = MI->getOperand(0).getReg();
2883 unsigned Ws = MI->getOperand(1).getReg();
2884 unsigned Lane = MI->getOperand(2).getImm();
2885
| 1//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsTargetLowering specialized for mips32/64.
11//
12//===----------------------------------------------------------------------===//
13#include "MipsSEISelLowering.h"
14#include "MipsMachineFunction.h"
15#include "MipsRegisterInfo.h"
16#include "MipsTargetMachine.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/CodeGen/MachineRegisterInfo.h"
19#include "llvm/IR/Intrinsics.h"
20#include "llvm/Support/CommandLine.h"
21#include "llvm/Support/Debug.h"
22#include "llvm/Support/raw_ostream.h"
23#include "llvm/Target/TargetInstrInfo.h"
24
25using namespace llvm;
26
27#define DEBUG_TYPE "mips-isel"
28
29static cl::opt<bool>
30EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
31 cl::desc("MIPS: Enable tail calls."), cl::init(false));
32
33static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
34 cl::desc("Expand double precision loads and "
35 "stores to their single precision "
36 "counterparts"));
37
38MipsSETargetLowering::MipsSETargetLowering(const MipsTargetMachine &TM,
39 const MipsSubtarget &STI)
40 : MipsTargetLowering(TM, STI) {
41 // Set up the register classes
42 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
43
44 if (Subtarget.isGP64bit())
45 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
46
47 if (Subtarget.hasDSP() || Subtarget.hasMSA()) {
48 // Expand all truncating stores and extending loads.
49 for (MVT VT0 : MVT::vector_valuetypes()) {
50 for (MVT VT1 : MVT::vector_valuetypes()) {
51 setTruncStoreAction(VT0, VT1, Expand);
52 setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand);
53 setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand);
54 setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand);
55 }
56 }
57 }
58
59 if (Subtarget.hasDSP()) {
60 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
61
62 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
63 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
64
65 // Expand all builtin opcodes.
66 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
67 setOperationAction(Opc, VecTys[i], Expand);
68
69 setOperationAction(ISD::ADD, VecTys[i], Legal);
70 setOperationAction(ISD::SUB, VecTys[i], Legal);
71 setOperationAction(ISD::LOAD, VecTys[i], Legal);
72 setOperationAction(ISD::STORE, VecTys[i], Legal);
73 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
74 }
75
76 setTargetDAGCombine(ISD::SHL);
77 setTargetDAGCombine(ISD::SRA);
78 setTargetDAGCombine(ISD::SRL);
79 setTargetDAGCombine(ISD::SETCC);
80 setTargetDAGCombine(ISD::VSELECT);
81 }
82
83 if (Subtarget.hasDSPR2())
84 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
85
86 if (Subtarget.hasMSA()) {
87 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
88 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
89 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
90 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
91 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
92 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
93 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
94
95 setTargetDAGCombine(ISD::AND);
96 setTargetDAGCombine(ISD::OR);
97 setTargetDAGCombine(ISD::SRA);
98 setTargetDAGCombine(ISD::VSELECT);
99 setTargetDAGCombine(ISD::XOR);
100 }
101
102 if (!Subtarget.abiUsesSoftFloat()) {
103 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
104
105 // When dealing with single precision only, use libcalls
106 if (!Subtarget.isSingleFloat()) {
107 if (Subtarget.isFP64bit())
108 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
109 else
110 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
111 }
112 }
113
114 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
115 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
116 setOperationAction(ISD::MULHS, MVT::i32, Custom);
117 setOperationAction(ISD::MULHU, MVT::i32, Custom);
118
119 if (Subtarget.hasCnMips())
120 setOperationAction(ISD::MUL, MVT::i64, Legal);
121 else if (Subtarget.isGP64bit())
122 setOperationAction(ISD::MUL, MVT::i64, Custom);
123
124 if (Subtarget.isGP64bit()) {
125 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Custom);
126 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Custom);
127 setOperationAction(ISD::MULHS, MVT::i64, Custom);
128 setOperationAction(ISD::MULHU, MVT::i64, Custom);
129 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
130 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
131 }
132
133 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
134 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
135
136 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
137 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
138 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
139 setOperationAction(ISD::LOAD, MVT::i32, Custom);
140 setOperationAction(ISD::STORE, MVT::i32, Custom);
141
142 setTargetDAGCombine(ISD::ADDE);
143 setTargetDAGCombine(ISD::SUBE);
144 setTargetDAGCombine(ISD::MUL);
145
146 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
147 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
148 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
149
150 if (NoDPLoadStore) {
151 setOperationAction(ISD::LOAD, MVT::f64, Custom);
152 setOperationAction(ISD::STORE, MVT::f64, Custom);
153 }
154
155 if (Subtarget.hasMips32r6()) {
156 // MIPS32r6 replaces the accumulator-based multiplies with a three register
157 // instruction
158 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
159 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
160 setOperationAction(ISD::MUL, MVT::i32, Legal);
161 setOperationAction(ISD::MULHS, MVT::i32, Legal);
162 setOperationAction(ISD::MULHU, MVT::i32, Legal);
163
164 // MIPS32r6 replaces the accumulator-based division/remainder with separate
165 // three register division and remainder instructions.
166 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
167 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
168 setOperationAction(ISD::SDIV, MVT::i32, Legal);
169 setOperationAction(ISD::UDIV, MVT::i32, Legal);
170 setOperationAction(ISD::SREM, MVT::i32, Legal);
171 setOperationAction(ISD::UREM, MVT::i32, Legal);
172
173 // MIPS32r6 replaces conditional moves with an equivalent that removes the
174 // need for three GPR read ports.
175 setOperationAction(ISD::SETCC, MVT::i32, Legal);
176 setOperationAction(ISD::SELECT, MVT::i32, Legal);
177 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
178
179 setOperationAction(ISD::SETCC, MVT::f32, Legal);
180 setOperationAction(ISD::SELECT, MVT::f32, Legal);
181 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
182
183 assert(Subtarget.isFP64bit() && "FR=1 is required for MIPS32r6");
184 setOperationAction(ISD::SETCC, MVT::f64, Legal);
185 setOperationAction(ISD::SELECT, MVT::f64, Legal);
186 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
187
188 setOperationAction(ISD::BRCOND, MVT::Other, Legal);
189
190 // Floating point > and >= are supported via < and <=
191 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
192 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand);
193 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
194 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
195
196 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
197 setCondCodeAction(ISD::SETOGT, MVT::f64, Expand);
198 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand);
199 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
200 }
201
202 if (Subtarget.hasMips64r6()) {
203 // MIPS64r6 replaces the accumulator-based multiplies with a three register
204 // instruction
205 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
206 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
207 setOperationAction(ISD::MUL, MVT::i64, Legal);
208 setOperationAction(ISD::MULHS, MVT::i64, Legal);
209 setOperationAction(ISD::MULHU, MVT::i64, Legal);
210
211 // MIPS32r6 replaces the accumulator-based division/remainder with separate
212 // three register division and remainder instructions.
213 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
214 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
215 setOperationAction(ISD::SDIV, MVT::i64, Legal);
216 setOperationAction(ISD::UDIV, MVT::i64, Legal);
217 setOperationAction(ISD::SREM, MVT::i64, Legal);
218 setOperationAction(ISD::UREM, MVT::i64, Legal);
219
220 // MIPS64r6 replaces conditional moves with an equivalent that removes the
221 // need for three GPR read ports.
222 setOperationAction(ISD::SETCC, MVT::i64, Legal);
223 setOperationAction(ISD::SELECT, MVT::i64, Legal);
224 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
225 }
226
227 computeRegisterProperties();
228}
229
230const MipsTargetLowering *
231llvm::createMipsSETargetLowering(const MipsTargetMachine &TM,
232 const MipsSubtarget &STI) {
233 return new MipsSETargetLowering(TM, STI);
234}
235
236const TargetRegisterClass *
237MipsSETargetLowering::getRepRegClassFor(MVT VT) const {
238 if (VT == MVT::Untyped)
239 return Subtarget.hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass;
240
241 return TargetLowering::getRepRegClassFor(VT);
242}
243
244// Enable MSA support for the given integer type and Register class.
245void MipsSETargetLowering::
246addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
247 addRegisterClass(Ty, RC);
248
249 // Expand all builtin opcodes.
250 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
251 setOperationAction(Opc, Ty, Expand);
252
253 setOperationAction(ISD::BITCAST, Ty, Legal);
254 setOperationAction(ISD::LOAD, Ty, Legal);
255 setOperationAction(ISD::STORE, Ty, Legal);
256 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
257 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
258 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
259
260 setOperationAction(ISD::ADD, Ty, Legal);
261 setOperationAction(ISD::AND, Ty, Legal);
262 setOperationAction(ISD::CTLZ, Ty, Legal);
263 setOperationAction(ISD::CTPOP, Ty, Legal);
264 setOperationAction(ISD::MUL, Ty, Legal);
265 setOperationAction(ISD::OR, Ty, Legal);
266 setOperationAction(ISD::SDIV, Ty, Legal);
267 setOperationAction(ISD::SREM, Ty, Legal);
268 setOperationAction(ISD::SHL, Ty, Legal);
269 setOperationAction(ISD::SRA, Ty, Legal);
270 setOperationAction(ISD::SRL, Ty, Legal);
271 setOperationAction(ISD::SUB, Ty, Legal);
272 setOperationAction(ISD::UDIV, Ty, Legal);
273 setOperationAction(ISD::UREM, Ty, Legal);
274 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom);
275 setOperationAction(ISD::VSELECT, Ty, Legal);
276 setOperationAction(ISD::XOR, Ty, Legal);
277
278 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
279 setOperationAction(ISD::FP_TO_SINT, Ty, Legal);
280 setOperationAction(ISD::FP_TO_UINT, Ty, Legal);
281 setOperationAction(ISD::SINT_TO_FP, Ty, Legal);
282 setOperationAction(ISD::UINT_TO_FP, Ty, Legal);
283 }
284
285 setOperationAction(ISD::SETCC, Ty, Legal);
286 setCondCodeAction(ISD::SETNE, Ty, Expand);
287 setCondCodeAction(ISD::SETGE, Ty, Expand);
288 setCondCodeAction(ISD::SETGT, Ty, Expand);
289 setCondCodeAction(ISD::SETUGE, Ty, Expand);
290 setCondCodeAction(ISD::SETUGT, Ty, Expand);
291}
292
293// Enable MSA support for the given floating-point type and Register class.
294void MipsSETargetLowering::
295addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
296 addRegisterClass(Ty, RC);
297
298 // Expand all builtin opcodes.
299 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
300 setOperationAction(Opc, Ty, Expand);
301
302 setOperationAction(ISD::LOAD, Ty, Legal);
303 setOperationAction(ISD::STORE, Ty, Legal);
304 setOperationAction(ISD::BITCAST, Ty, Legal);
305 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
306 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
307 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
308
309 if (Ty != MVT::v8f16) {
310 setOperationAction(ISD::FABS, Ty, Legal);
311 setOperationAction(ISD::FADD, Ty, Legal);
312 setOperationAction(ISD::FDIV, Ty, Legal);
313 setOperationAction(ISD::FEXP2, Ty, Legal);
314 setOperationAction(ISD::FLOG2, Ty, Legal);
315 setOperationAction(ISD::FMA, Ty, Legal);
316 setOperationAction(ISD::FMUL, Ty, Legal);
317 setOperationAction(ISD::FRINT, Ty, Legal);
318 setOperationAction(ISD::FSQRT, Ty, Legal);
319 setOperationAction(ISD::FSUB, Ty, Legal);
320 setOperationAction(ISD::VSELECT, Ty, Legal);
321
322 setOperationAction(ISD::SETCC, Ty, Legal);
323 setCondCodeAction(ISD::SETOGE, Ty, Expand);
324 setCondCodeAction(ISD::SETOGT, Ty, Expand);
325 setCondCodeAction(ISD::SETUGE, Ty, Expand);
326 setCondCodeAction(ISD::SETUGT, Ty, Expand);
327 setCondCodeAction(ISD::SETGE, Ty, Expand);
328 setCondCodeAction(ISD::SETGT, Ty, Expand);
329 }
330}
331
332bool
333MipsSETargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
334 unsigned,
335 unsigned,
336 bool *Fast) const {
337 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
338
339 if (Subtarget.systemSupportsUnalignedAccess()) {
340 // MIPS32r6/MIPS64r6 is required to support unaligned access. It's
341 // implementation defined whether this is handled by hardware, software, or
342 // a hybrid of the two but it's expected that most implementations will
343 // handle the majority of cases in hardware.
344 if (Fast)
345 *Fast = true;
346 return true;
347 }
348
349 switch (SVT) {
350 case MVT::i64:
351 case MVT::i32:
352 if (Fast)
353 *Fast = true;
354 return true;
355 default:
356 return false;
357 }
358}
359
360SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
361 SelectionDAG &DAG) const {
362 switch(Op.getOpcode()) {
363 case ISD::LOAD: return lowerLOAD(Op, DAG);
364 case ISD::STORE: return lowerSTORE(Op, DAG);
365 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
366 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
367 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
368 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
369 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
370 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
371 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
372 DAG);
373 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
374 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
375 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
376 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
377 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
378 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG);
379 }
380
381 return MipsTargetLowering::LowerOperation(Op, DAG);
382}
383
384// selectMADD -
385// Transforms a subgraph in CurDAG if the following pattern is found:
386// (addc multLo, Lo0), (adde multHi, Hi0),
387// where,
388// multHi/Lo: product of multiplication
389// Lo0: initial value of Lo register
390// Hi0: initial value of Hi register
391// Return true if pattern matching was successful.
392static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
393 // ADDENode's second operand must be a flag output of an ADDC node in order
394 // for the matching to be successful.
395 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
396
397 if (ADDCNode->getOpcode() != ISD::ADDC)
398 return false;
399
400 SDValue MultHi = ADDENode->getOperand(0);
401 SDValue MultLo = ADDCNode->getOperand(0);
402 SDNode *MultNode = MultHi.getNode();
403 unsigned MultOpc = MultHi.getOpcode();
404
405 // MultHi and MultLo must be generated by the same node,
406 if (MultLo.getNode() != MultNode)
407 return false;
408
409 // and it must be a multiplication.
410 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
411 return false;
412
413 // MultLo amd MultHi must be the first and second output of MultNode
414 // respectively.
415 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
416 return false;
417
418 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
419 // of the values of MultNode, in which case MultNode will be removed in later
420 // phases.
421 // If there exist users other than ADDENode or ADDCNode, this function returns
422 // here, which will result in MultNode being mapped to a single MULT
423 // instruction node rather than a pair of MULT and MADD instructions being
424 // produced.
425 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
426 return false;
427
428 SDLoc DL(ADDENode);
429
430 // Initialize accumulator.
431 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
432 ADDCNode->getOperand(1),
433 ADDENode->getOperand(1));
434
435 // create MipsMAdd(u) node
436 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
437
438 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
439 MultNode->getOperand(0),// Factor 0
440 MultNode->getOperand(1),// Factor 1
441 ACCIn);
442
443 // replace uses of adde and addc here
444 if (!SDValue(ADDCNode, 0).use_empty()) {
445 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
446 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
447 }
448 if (!SDValue(ADDENode, 0).use_empty()) {
449 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
450 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
451 }
452
453 return true;
454}
455
456// selectMSUB -
457// Transforms a subgraph in CurDAG if the following pattern is found:
458// (addc Lo0, multLo), (sube Hi0, multHi),
459// where,
460// multHi/Lo: product of multiplication
461// Lo0: initial value of Lo register
462// Hi0: initial value of Hi register
463// Return true if pattern matching was successful.
464static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
465 // SUBENode's second operand must be a flag output of an SUBC node in order
466 // for the matching to be successful.
467 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
468
469 if (SUBCNode->getOpcode() != ISD::SUBC)
470 return false;
471
472 SDValue MultHi = SUBENode->getOperand(1);
473 SDValue MultLo = SUBCNode->getOperand(1);
474 SDNode *MultNode = MultHi.getNode();
475 unsigned MultOpc = MultHi.getOpcode();
476
477 // MultHi and MultLo must be generated by the same node,
478 if (MultLo.getNode() != MultNode)
479 return false;
480
481 // and it must be a multiplication.
482 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
483 return false;
484
485 // MultLo amd MultHi must be the first and second output of MultNode
486 // respectively.
487 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
488 return false;
489
490 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
491 // of the values of MultNode, in which case MultNode will be removed in later
492 // phases.
493 // If there exist users other than SUBENode or SUBCNode, this function returns
494 // here, which will result in MultNode being mapped to a single MULT
495 // instruction node rather than a pair of MULT and MSUB instructions being
496 // produced.
497 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
498 return false;
499
500 SDLoc DL(SUBENode);
501
502 // Initialize accumulator.
503 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
504 SUBCNode->getOperand(0),
505 SUBENode->getOperand(0));
506
507 // create MipsSub(u) node
508 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
509
510 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
511 MultNode->getOperand(0),// Factor 0
512 MultNode->getOperand(1),// Factor 1
513 ACCIn);
514
515 // replace uses of sube and subc here
516 if (!SDValue(SUBCNode, 0).use_empty()) {
517 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub);
518 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
519 }
520 if (!SDValue(SUBENode, 0).use_empty()) {
521 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MSub);
522 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
523 }
524
525 return true;
526}
527
528static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
529 TargetLowering::DAGCombinerInfo &DCI,
530 const MipsSubtarget &Subtarget) {
531 if (DCI.isBeforeLegalize())
532 return SDValue();
533
534 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
535 N->getValueType(0) == MVT::i32 && selectMADD(N, &DAG))
536 return SDValue(N, 0);
537
538 return SDValue();
539}
540
541// Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
542//
543// Performs the following transformations:
544// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
545// sign/zero-extension is completely overwritten by the new one performed by
546// the ISD::AND.
547// - Removes redundant zero extensions performed by an ISD::AND.
548static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
549 TargetLowering::DAGCombinerInfo &DCI,
550 const MipsSubtarget &Subtarget) {
551 if (!Subtarget.hasMSA())
552 return SDValue();
553
554 SDValue Op0 = N->getOperand(0);
555 SDValue Op1 = N->getOperand(1);
556 unsigned Op0Opcode = Op0->getOpcode();
557
558 // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
559 // where $d + 1 == 2^n and n == 32
560 // or $d + 1 == 2^n and n <= 32 and ZExt
561 // -> (MipsVExtractZExt $a, $b, $c)
562 if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
563 Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
564 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
565
566 if (!Mask)
567 return SDValue();
568
569 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
570
571 if (Log2IfPositive <= 0)
572 return SDValue(); // Mask+1 is not a power of 2
573
574 SDValue Op0Op2 = Op0->getOperand(2);
575 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
576 unsigned ExtendTySize = ExtendTy.getSizeInBits();
577 unsigned Log2 = Log2IfPositive;
578
579 if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
580 Log2 == ExtendTySize) {
581 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
582 return DAG.getNode(MipsISD::VEXTRACT_ZEXT_ELT, SDLoc(Op0),
583 Op0->getVTList(),
584 makeArrayRef(Ops, Op0->getNumOperands()));
585 }
586 }
587
588 return SDValue();
589}
590
591// Determine if the specified node is a constant vector splat.
592//
593// Returns true and sets Imm if:
594// * N is a ISD::BUILD_VECTOR representing a constant splat
595//
596// This function is quite similar to MipsSEDAGToDAGISel::selectVSplat. The
597// differences are that it assumes the MSA has already been checked and the
598// arbitrary requirement for a maximum of 32-bit integers isn't applied (and
599// must not be in order for binsri.d to be selectable).
600static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) {
601 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N.getNode());
602
603 if (!Node)
604 return false;
605
606 APInt SplatValue, SplatUndef;
607 unsigned SplatBitSize;
608 bool HasAnyUndefs;
609
610 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
611 8, !IsLittleEndian))
612 return false;
613
614 Imm = SplatValue;
615
616 return true;
617}
618
619// Test whether the given node is an all-ones build_vector.
620static bool isVectorAllOnes(SDValue N) {
621 // Look through bitcasts. Endianness doesn't matter because we are looking
622 // for an all-ones value.
623 if (N->getOpcode() == ISD::BITCAST)
624 N = N->getOperand(0);
625
626 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
627
628 if (!BVN)
629 return false;
630
631 APInt SplatValue, SplatUndef;
632 unsigned SplatBitSize;
633 bool HasAnyUndefs;
634
635 // Endianness doesn't matter in this context because we are looking for
636 // an all-ones value.
637 if (BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs))
638 return SplatValue.isAllOnesValue();
639
640 return false;
641}
642
643// Test whether N is the bitwise inverse of OfNode.
644static bool isBitwiseInverse(SDValue N, SDValue OfNode) {
645 if (N->getOpcode() != ISD::XOR)
646 return false;
647
648 if (isVectorAllOnes(N->getOperand(0)))
649 return N->getOperand(1) == OfNode;
650
651 if (isVectorAllOnes(N->getOperand(1)))
652 return N->getOperand(0) == OfNode;
653
654 return false;
655}
656
657// Perform combines where ISD::OR is the root node.
658//
659// Performs the following transformations:
660// - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
661// where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
662// vector type.
663static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
664 TargetLowering::DAGCombinerInfo &DCI,
665 const MipsSubtarget &Subtarget) {
666 if (!Subtarget.hasMSA())
667 return SDValue();
668
669 EVT Ty = N->getValueType(0);
670
671 if (!Ty.is128BitVector())
672 return SDValue();
673
674 SDValue Op0 = N->getOperand(0);
675 SDValue Op1 = N->getOperand(1);
676
677 if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
678 SDValue Op0Op0 = Op0->getOperand(0);
679 SDValue Op0Op1 = Op0->getOperand(1);
680 SDValue Op1Op0 = Op1->getOperand(0);
681 SDValue Op1Op1 = Op1->getOperand(1);
682 bool IsLittleEndian = !Subtarget.isLittle();
683
684 SDValue IfSet, IfClr, Cond;
685 bool IsConstantMask = false;
686 APInt Mask, InvMask;
687
688 // If Op0Op0 is an appropriate mask, try to find it's inverse in either
689 // Op1Op0, or Op1Op1. Keep track of the Cond, IfSet, and IfClr nodes, while
690 // looking.
691 // IfClr will be set if we find a valid match.
692 if (isVSplat(Op0Op0, Mask, IsLittleEndian)) {
693 Cond = Op0Op0;
694 IfSet = Op0Op1;
695
696 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
697 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
698 IfClr = Op1Op1;
699 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
700 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
701 IfClr = Op1Op0;
702
703 IsConstantMask = true;
704 }
705
706 // If IfClr is not yet set, and Op0Op1 is an appropriate mask, try the same
707 // thing again using this mask.
708 // IfClr will be set if we find a valid match.
709 if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) {
710 Cond = Op0Op1;
711 IfSet = Op0Op0;
712
713 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
714 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
715 IfClr = Op1Op1;
716 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
717 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
718 IfClr = Op1Op0;
719
720 IsConstantMask = true;
721 }
722
723 // If IfClr is not yet set, try looking for a non-constant match.
724 // IfClr will be set if we find a valid match amongst the eight
725 // possibilities.
726 if (!IfClr.getNode()) {
727 if (isBitwiseInverse(Op0Op0, Op1Op0)) {
728 Cond = Op1Op0;
729 IfSet = Op1Op1;
730 IfClr = Op0Op1;
731 } else if (isBitwiseInverse(Op0Op1, Op1Op0)) {
732 Cond = Op1Op0;
733 IfSet = Op1Op1;
734 IfClr = Op0Op0;
735 } else if (isBitwiseInverse(Op0Op0, Op1Op1)) {
736 Cond = Op1Op1;
737 IfSet = Op1Op0;
738 IfClr = Op0Op1;
739 } else if (isBitwiseInverse(Op0Op1, Op1Op1)) {
740 Cond = Op1Op1;
741 IfSet = Op1Op0;
742 IfClr = Op0Op0;
743 } else if (isBitwiseInverse(Op1Op0, Op0Op0)) {
744 Cond = Op0Op0;
745 IfSet = Op0Op1;
746 IfClr = Op1Op1;
747 } else if (isBitwiseInverse(Op1Op1, Op0Op0)) {
748 Cond = Op0Op0;
749 IfSet = Op0Op1;
750 IfClr = Op1Op0;
751 } else if (isBitwiseInverse(Op1Op0, Op0Op1)) {
752 Cond = Op0Op1;
753 IfSet = Op0Op0;
754 IfClr = Op1Op1;
755 } else if (isBitwiseInverse(Op1Op1, Op0Op1)) {
756 Cond = Op0Op1;
757 IfSet = Op0Op0;
758 IfClr = Op1Op0;
759 }
760 }
761
762 // At this point, IfClr will be set if we have a valid match.
763 if (!IfClr.getNode())
764 return SDValue();
765
766 assert(Cond.getNode() && IfSet.getNode());
767
768 // Fold degenerate cases.
769 if (IsConstantMask) {
770 if (Mask.isAllOnesValue())
771 return IfSet;
772 else if (Mask == 0)
773 return IfClr;
774 }
775
776 // Transform the DAG into an equivalent VSELECT.
777 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr);
778 }
779
780 return SDValue();
781}
782
783static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
784 TargetLowering::DAGCombinerInfo &DCI,
785 const MipsSubtarget &Subtarget) {
786 if (DCI.isBeforeLegalize())
787 return SDValue();
788
789 if (Subtarget.hasMips32() && N->getValueType(0) == MVT::i32 &&
790 selectMSUB(N, &DAG))
791 return SDValue(N, 0);
792
793 return SDValue();
794}
795
796static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
797 EVT ShiftTy, SelectionDAG &DAG) {
798 // Clear the upper (64 - VT.sizeInBits) bits.
799 C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
800
801 // Return 0.
802 if (C == 0)
803 return DAG.getConstant(0, VT);
804
805 // Return x.
806 if (C == 1)
807 return X;
808
809 // If c is power of 2, return (shl x, log2(c)).
810 if (isPowerOf2_64(C))
811 return DAG.getNode(ISD::SHL, DL, VT, X,
812 DAG.getConstant(Log2_64(C), ShiftTy));
813
814 unsigned Log2Ceil = Log2_64_Ceil(C);
815 uint64_t Floor = 1LL << Log2_64(C);
816 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
817
818 // If |c - floor_c| <= |c - ceil_c|,
819 // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
820 // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
821 if (C - Floor <= Ceil - C) {
822 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
823 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
824 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
825 }
826
827 // If |c - floor_c| > |c - ceil_c|,
828 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
829 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
830 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
831 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
832}
833
834static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
835 const TargetLowering::DAGCombinerInfo &DCI,
836 const MipsSETargetLowering *TL) {
837 EVT VT = N->getValueType(0);
838
839 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
840 if (!VT.isVector())
841 return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N),
842 VT, TL->getScalarShiftAmountTy(VT), DAG);
843
844 return SDValue(N, 0);
845}
846
847static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
848 SelectionDAG &DAG,
849 const MipsSubtarget &Subtarget) {
850 // See if this is a vector splat immediate node.
851 APInt SplatValue, SplatUndef;
852 unsigned SplatBitSize;
853 bool HasAnyUndefs;
854 unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
855 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
856
857 if (!Subtarget.hasDSP())
858 return SDValue();
859
860 if (!BV ||
861 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
862 EltSize, !Subtarget.isLittle()) ||
863 (SplatBitSize != EltSize) ||
864 (SplatValue.getZExtValue() >= EltSize))
865 return SDValue();
866
867 return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
868 DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
869}
870
871static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
872 TargetLowering::DAGCombinerInfo &DCI,
873 const MipsSubtarget &Subtarget) {
874 EVT Ty = N->getValueType(0);
875
876 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
877 return SDValue();
878
879 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
880}
881
882// Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
883// constant splats into MipsISD::SHRA_DSP for DSPr2.
884//
885// Performs the following transformations:
886// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
887// sign/zero-extension is completely overwritten by the new one performed by
888// the ISD::SRA and ISD::SHL nodes.
889// - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
890// sequence.
891//
892// See performDSPShiftCombine for more information about the transformation
893// used for DSPr2.
894static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
895 TargetLowering::DAGCombinerInfo &DCI,
896 const MipsSubtarget &Subtarget) {
897 EVT Ty = N->getValueType(0);
898
899 if (Subtarget.hasMSA()) {
900 SDValue Op0 = N->getOperand(0);
901 SDValue Op1 = N->getOperand(1);
902
903 // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
904 // where $d + sizeof($c) == 32
905 // or $d + sizeof($c) <= 32 and SExt
906 // -> (MipsVExtractSExt $a, $b, $c)
907 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
908 SDValue Op0Op0 = Op0->getOperand(0);
909 ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
910
911 if (!ShAmount)
912 return SDValue();
913
914 if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
915 Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT)
916 return SDValue();
917
918 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
919 unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
920
921 if (TotalBits == 32 ||
922 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
923 TotalBits <= 32)) {
924 SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
925 Op0Op0->getOperand(2) };
926 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, SDLoc(Op0Op0),
927 Op0Op0->getVTList(),
928 makeArrayRef(Ops, Op0Op0->getNumOperands()));
929 }
930 }
931 }
932
933 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2()))
934 return SDValue();
935
936 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
937}
938
939
940static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
941 TargetLowering::DAGCombinerInfo &DCI,
942 const MipsSubtarget &Subtarget) {
943 EVT Ty = N->getValueType(0);
944
945 if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8))
946 return SDValue();
947
948 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
949}
950
951static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
952 bool IsV216 = (Ty == MVT::v2i16);
953
954 switch (CC) {
955 case ISD::SETEQ:
956 case ISD::SETNE: return true;
957 case ISD::SETLT:
958 case ISD::SETLE:
959 case ISD::SETGT:
960 case ISD::SETGE: return IsV216;
961 case ISD::SETULT:
962 case ISD::SETULE:
963 case ISD::SETUGT:
964 case ISD::SETUGE: return !IsV216;
965 default: return false;
966 }
967}
968
969static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
970 EVT Ty = N->getValueType(0);
971
972 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
973 return SDValue();
974
975 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
976 return SDValue();
977
978 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
979 N->getOperand(1), N->getOperand(2));
980}
981
982static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
983 EVT Ty = N->getValueType(0);
984
985 if (Ty.is128BitVector() && Ty.isInteger()) {
986 // Try the following combines:
987 // (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b)
988 // (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b)
989 // (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b)
990 // (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b)
991 // (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b)
992 // (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b)
993 // (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b)
994 // (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b)
995 // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but
996 // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the
997 // legalizer.
998 SDValue Op0 = N->getOperand(0);
999
1000 if (Op0->getOpcode() != ISD::SETCC)
1001 return SDValue();
1002
1003 ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get();
1004 bool Signed;
1005
1006 if (CondCode == ISD::SETLT || CondCode == ISD::SETLE)
1007 Signed = true;
1008 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE)
1009 Signed = false;
1010 else
1011 return SDValue();
1012
1013 SDValue Op1 = N->getOperand(1);
1014 SDValue Op2 = N->getOperand(2);
1015 SDValue Op0Op0 = Op0->getOperand(0);
1016 SDValue Op0Op1 = Op0->getOperand(1);
1017
1018 if (Op1 == Op0Op0 && Op2 == Op0Op1)
1019 return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N),
1020 Ty, Op1, Op2);
1021 else if (Op1 == Op0Op1 && Op2 == Op0Op0)
1022 return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N),
1023 Ty, Op1, Op2);
1024 } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) {
1025 SDValue SetCC = N->getOperand(0);
1026
1027 if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
1028 return SDValue();
1029
1030 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
1031 SetCC.getOperand(0), SetCC.getOperand(1),
1032 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
1033 }
1034
1035 return SDValue();
1036}
1037
1038static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
1039 const MipsSubtarget &Subtarget) {
1040 EVT Ty = N->getValueType(0);
1041
1042 if (Subtarget.hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
1043 // Try the following combines:
1044 // (xor (or $a, $b), (build_vector allones))
1045 // (xor (or $a, $b), (bitcast (build_vector allones)))
1046 SDValue Op0 = N->getOperand(0);
1047 SDValue Op1 = N->getOperand(1);
1048 SDValue NotOp;
1049
1050 if (ISD::isBuildVectorAllOnes(Op0.getNode()))
1051 NotOp = Op1;
1052 else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
1053 NotOp = Op0;
1054 else
1055 return SDValue();
1056
1057 if (NotOp->getOpcode() == ISD::OR)
1058 return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
1059 NotOp->getOperand(1));
1060 }
1061
1062 return SDValue();
1063}
1064
1065SDValue
1066MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1067 SelectionDAG &DAG = DCI.DAG;
1068 SDValue Val;
1069
1070 switch (N->getOpcode()) {
1071 case ISD::ADDE:
1072 return performADDECombine(N, DAG, DCI, Subtarget);
1073 case ISD::AND:
1074 Val = performANDCombine(N, DAG, DCI, Subtarget);
1075 break;
1076 case ISD::OR:
1077 Val = performORCombine(N, DAG, DCI, Subtarget);
1078 break;
1079 case ISD::SUBE:
1080 return performSUBECombine(N, DAG, DCI, Subtarget);
1081 case ISD::MUL:
1082 return performMULCombine(N, DAG, DCI, this);
1083 case ISD::SHL:
1084 return performSHLCombine(N, DAG, DCI, Subtarget);
1085 case ISD::SRA:
1086 return performSRACombine(N, DAG, DCI, Subtarget);
1087 case ISD::SRL:
1088 return performSRLCombine(N, DAG, DCI, Subtarget);
1089 case ISD::VSELECT:
1090 return performVSELECTCombine(N, DAG);
1091 case ISD::XOR:
1092 Val = performXORCombine(N, DAG, Subtarget);
1093 break;
1094 case ISD::SETCC:
1095 Val = performSETCCCombine(N, DAG);
1096 break;
1097 }
1098
1099 if (Val.getNode()) {
1100 DEBUG(dbgs() << "\nMipsSE DAG Combine:\n";
1101 N->printrWithDepth(dbgs(), &DAG);
1102 dbgs() << "\n=> \n";
1103 Val.getNode()->printrWithDepth(dbgs(), &DAG);
1104 dbgs() << "\n");
1105 return Val;
1106 }
1107
1108 return MipsTargetLowering::PerformDAGCombine(N, DCI);
1109}
1110
1111MachineBasicBlock *
1112MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1113 MachineBasicBlock *BB) const {
1114 switch (MI->getOpcode()) {
1115 default:
1116 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
1117 case Mips::BPOSGE32_PSEUDO:
1118 return emitBPOSGE32(MI, BB);
1119 case Mips::SNZ_B_PSEUDO:
1120 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
1121 case Mips::SNZ_H_PSEUDO:
1122 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
1123 case Mips::SNZ_W_PSEUDO:
1124 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
1125 case Mips::SNZ_D_PSEUDO:
1126 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
1127 case Mips::SNZ_V_PSEUDO:
1128 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
1129 case Mips::SZ_B_PSEUDO:
1130 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
1131 case Mips::SZ_H_PSEUDO:
1132 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
1133 case Mips::SZ_W_PSEUDO:
1134 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
1135 case Mips::SZ_D_PSEUDO:
1136 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
1137 case Mips::SZ_V_PSEUDO:
1138 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
1139 case Mips::COPY_FW_PSEUDO:
1140 return emitCOPY_FW(MI, BB);
1141 case Mips::COPY_FD_PSEUDO:
1142 return emitCOPY_FD(MI, BB);
1143 case Mips::INSERT_FW_PSEUDO:
1144 return emitINSERT_FW(MI, BB);
1145 case Mips::INSERT_FD_PSEUDO:
1146 return emitINSERT_FD(MI, BB);
1147 case Mips::INSERT_B_VIDX_PSEUDO:
1148 return emitINSERT_DF_VIDX(MI, BB, 1, false);
1149 case Mips::INSERT_H_VIDX_PSEUDO:
1150 return emitINSERT_DF_VIDX(MI, BB, 2, false);
1151 case Mips::INSERT_W_VIDX_PSEUDO:
1152 return emitINSERT_DF_VIDX(MI, BB, 4, false);
1153 case Mips::INSERT_D_VIDX_PSEUDO:
1154 return emitINSERT_DF_VIDX(MI, BB, 8, false);
1155 case Mips::INSERT_FW_VIDX_PSEUDO:
1156 return emitINSERT_DF_VIDX(MI, BB, 4, true);
1157 case Mips::INSERT_FD_VIDX_PSEUDO:
1158 return emitINSERT_DF_VIDX(MI, BB, 8, true);
1159 case Mips::FILL_FW_PSEUDO:
1160 return emitFILL_FW(MI, BB);
1161 case Mips::FILL_FD_PSEUDO:
1162 return emitFILL_FD(MI, BB);
1163 case Mips::FEXP2_W_1_PSEUDO:
1164 return emitFEXP2_W_1(MI, BB);
1165 case Mips::FEXP2_D_1_PSEUDO:
1166 return emitFEXP2_D_1(MI, BB);
1167 }
1168}
1169
1170bool MipsSETargetLowering::isEligibleForTailCallOptimization(
1171 const CCState &CCInfo, unsigned NextStackOffset,
1172 const MipsFunctionInfo &FI) const {
1173 if (!EnableMipsTailCalls)
1174 return false;
1175
1176 // Return false if either the callee or caller has a byval argument.
1177 if (CCInfo.getInRegsParamsCount() > 0 || FI.hasByvalArg())
1178 return false;
1179
1180 // Return true if the callee's argument area is no larger than the
1181 // caller's.
1182 return NextStackOffset <= FI.getIncomingArgSize();
1183}
1184
1185void MipsSETargetLowering::
1186getOpndList(SmallVectorImpl<SDValue> &Ops,
1187 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
1188 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
1189 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
1190 SDValue Chain) const {
1191 Ops.push_back(Callee);
1192 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
1193 InternalLinkage, IsCallReloc, CLI, Callee,
1194 Chain);
1195}
1196
1197SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1198 LoadSDNode &Nd = *cast<LoadSDNode>(Op);
1199
1200 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1201 return MipsTargetLowering::lowerLOAD(Op, DAG);
1202
1203 // Replace a double precision load with two i32 loads and a buildpair64.
1204 SDLoc DL(Op);
1205 SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1206 EVT PtrVT = Ptr.getValueType();
1207
1208 // i32 load from lower address.
1209 SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
1210 MachinePointerInfo(), Nd.isVolatile(),
1211 Nd.isNonTemporal(), Nd.isInvariant(),
1212 Nd.getAlignment());
1213
1214 // i32 load from higher address.
1215 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
1216 SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
1217 MachinePointerInfo(), Nd.isVolatile(),
1218 Nd.isNonTemporal(), Nd.isInvariant(),
1219 std::min(Nd.getAlignment(), 4U));
1220
1221 if (!Subtarget.isLittle())
1222 std::swap(Lo, Hi);
1223
1224 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
1225 SDValue Ops[2] = {BP, Hi.getValue(1)};
1226 return DAG.getMergeValues(Ops, DL);
1227}
1228
1229SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1230 StoreSDNode &Nd = *cast<StoreSDNode>(Op);
1231
1232 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1233 return MipsTargetLowering::lowerSTORE(Op, DAG);
1234
1235 // Replace a double precision store with two extractelement64s and i32 stores.
1236 SDLoc DL(Op);
1237 SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1238 EVT PtrVT = Ptr.getValueType();
1239 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1240 Val, DAG.getConstant(0, MVT::i32));
1241 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1242 Val, DAG.getConstant(1, MVT::i32));
1243
1244 if (!Subtarget.isLittle())
1245 std::swap(Lo, Hi);
1246
1247 // i32 store to lower address.
1248 Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
1249 Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
1250 Nd.getAAInfo());
1251
1252 // i32 store to higher address.
1253 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
1254 return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
1255 Nd.isVolatile(), Nd.isNonTemporal(),
1256 std::min(Nd.getAlignment(), 4U), Nd.getAAInfo());
1257}
1258
1259SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
1260 bool HasLo, bool HasHi,
1261 SelectionDAG &DAG) const {
1262 // MIPS32r6/MIPS64r6 removed accumulator based multiplies.
1263 assert(!Subtarget.hasMips32r6());
1264
1265 EVT Ty = Op.getOperand(0).getValueType();
1266 SDLoc DL(Op);
1267 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
1268 Op.getOperand(0), Op.getOperand(1));
1269 SDValue Lo, Hi;
1270
1271 if (HasLo)
1272 Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult);
1273 if (HasHi)
1274 Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult);
1275
1276 if (!HasLo || !HasHi)
1277 return HasLo ? Lo : Hi;
1278
1279 SDValue Vals[] = { Lo, Hi };
1280 return DAG.getMergeValues(Vals, DL);
1281}
1282
1283
1284static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
1285 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1286 DAG.getConstant(0, MVT::i32));
1287 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1288 DAG.getConstant(1, MVT::i32));
1289 return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
1290}
1291
1292static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
1293 SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op);
1294 SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op);
1295 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
1296}
1297
1298// This function expands mips intrinsic nodes which have 64-bit input operands
1299// or output values.
1300//
1301// out64 = intrinsic-node in64
1302// =>
1303// lo = copy (extract-element (in64, 0))
1304// hi = copy (extract-element (in64, 1))
1305// mips-specific-node
1306// v0 = copy lo
1307// v1 = copy hi
1308// out64 = merge-values (v0, v1)
1309//
1310static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1311 SDLoc DL(Op);
1312 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
1313 SmallVector<SDValue, 3> Ops;
1314 unsigned OpNo = 0;
1315
1316 // See if Op has a chain input.
1317 if (HasChainIn)
1318 Ops.push_back(Op->getOperand(OpNo++));
1319
1320 // The next operand is the intrinsic opcode.
1321 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
1322
1323 // See if the next operand has type i64.
1324 SDValue Opnd = Op->getOperand(++OpNo), In64;
1325
1326 if (Opnd.getValueType() == MVT::i64)
1327 In64 = initAccumulator(Opnd, DL, DAG);
1328 else
1329 Ops.push_back(Opnd);
1330
1331 // Push the remaining operands.
1332 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
1333 Ops.push_back(Op->getOperand(OpNo));
1334
1335 // Add In64 to the end of the list.
1336 if (In64.getNode())
1337 Ops.push_back(In64);
1338
1339 // Scan output.
1340 SmallVector<EVT, 2> ResTys;
1341
1342 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1343 I != E; ++I)
1344 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
1345
1346 // Create node.
1347 SDValue Val = DAG.getNode(Opc, DL, ResTys, Ops);
1348 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
1349
1350 if (!HasChainIn)
1351 return Out;
1352
1353 assert(Val->getValueType(1) == MVT::Other);
1354 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
1355 return DAG.getMergeValues(Vals, DL);
1356}
1357
1358// Lower an MSA copy intrinsic into the specified SelectionDAG node
1359static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1360 SDLoc DL(Op);
1361 SDValue Vec = Op->getOperand(1);
1362 SDValue Idx = Op->getOperand(2);
1363 EVT ResTy = Op->getValueType(0);
1364 EVT EltTy = Vec->getValueType(0).getVectorElementType();
1365
1366 SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1367 DAG.getValueType(EltTy));
1368
1369 return Result;
1370}
1371
1372static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) {
1373 EVT ResVecTy = Op->getValueType(0);
1374 EVT ViaVecTy = ResVecTy;
1375 SDLoc DL(Op);
1376
1377 // When ResVecTy == MVT::v2i64, LaneA is the upper 32 bits of the lane and
1378 // LaneB is the lower 32-bits. Otherwise LaneA and LaneB are alternating
1379 // lanes.
1380 SDValue LaneA;
1381 SDValue LaneB = Op->getOperand(2);
1382
1383 if (ResVecTy == MVT::v2i64) {
1384 LaneA = DAG.getConstant(0, MVT::i32);
1385 ViaVecTy = MVT::v4i32;
1386 } else
1387 LaneA = LaneB;
1388
1389 SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,
1390 LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
1391
1392 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy,
1393 makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
1394
1395 if (ViaVecTy != ResVecTy)
1396 Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, Result);
1397
1398 return Result;
1399}
1400
1401static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) {
1402 return DAG.getConstant(Op->getConstantOperandVal(ImmOp), Op->getValueType(0));
1403}
1404
1405static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue,
1406 bool BigEndian, SelectionDAG &DAG) {
1407 EVT ViaVecTy = VecTy;
1408 SDValue SplatValueA = SplatValue;
1409 SDValue SplatValueB = SplatValue;
1410 SDLoc DL(SplatValue);
1411
1412 if (VecTy == MVT::v2i64) {
1413 // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's.
1414 ViaVecTy = MVT::v4i32;
1415
1416 SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue);
1417 SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue,
1418 DAG.getConstant(32, MVT::i32));
1419 SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB);
1420 }
1421
1422 // We currently hold the parts in little endian order. Swap them if
1423 // necessary.
1424 if (BigEndian)
1425 std::swap(SplatValueA, SplatValueB);
1426
1427 SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1428 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1429 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1430 SplatValueA, SplatValueB, SplatValueA, SplatValueB };
1431
1432 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy,
1433 makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
1434
1435 if (VecTy != ViaVecTy)
1436 Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);
1437
1438 return Result;
1439}
1440
1441static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG,
1442 unsigned Opc, SDValue Imm,
1443 bool BigEndian) {
1444 EVT VecTy = Op->getValueType(0);
1445 SDValue Exp2Imm;
1446 SDLoc DL(Op);
1447
1448 // The DAG Combiner can't constant fold bitcasted vectors yet so we must do it
1449 // here for now.
1450 if (VecTy == MVT::v2i64) {
1451 if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) {
1452 APInt BitImm = APInt(64, 1) << CImm->getAPIntValue();
1453
1454 SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), MVT::i32);
1455 SDValue BitImmLoOp = DAG.getConstant(BitImm.trunc(32), MVT::i32);
1456
1457 if (BigEndian)
1458 std::swap(BitImmLoOp, BitImmHiOp);
1459
1460 Exp2Imm =
1461 DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
1462 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, BitImmLoOp,
1463 BitImmHiOp, BitImmLoOp, BitImmHiOp));
1464 }
1465 }
1466
1467 if (!Exp2Imm.getNode()) {
1468 // We couldnt constant fold, do a vector shift instead
1469
1470 // Extend i32 to i64 if necessary. Sign or zero extend doesn't matter since
1471 // only values 0-63 are valid.
1472 if (VecTy == MVT::v2i64)
1473 Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm);
1474
1475 Exp2Imm = getBuildVectorSplat(VecTy, Imm, BigEndian, DAG);
1476
1477 Exp2Imm =
1478 DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, VecTy), Exp2Imm);
1479 }
1480
1481 return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm);
1482}
1483
1484static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG) {
1485 EVT ResTy = Op->getValueType(0);
1486 SDLoc DL(Op);
1487 SDValue One = DAG.getConstant(1, ResTy);
1488 SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, Op->getOperand(2));
1489
1490 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
1491 DAG.getNOT(DL, Bit, ResTy));
1492}
1493
1494static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) {
1495 SDLoc DL(Op);
1496 EVT ResTy = Op->getValueType(0);
1497 APInt BitImm = APInt(ResTy.getVectorElementType().getSizeInBits(), 1)
1498 << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue();
1499 SDValue BitMask = DAG.getConstant(~BitImm, ResTy);
1500
1501 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
1502}
1503
1504SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1505 SelectionDAG &DAG) const {
1506 SDLoc DL(Op);
1507
1508 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
1509 default:
1510 return SDValue();
1511 case Intrinsic::mips_shilo:
1512 return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1513 case Intrinsic::mips_dpau_h_qbl:
1514 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1515 case Intrinsic::mips_dpau_h_qbr:
1516 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1517 case Intrinsic::mips_dpsu_h_qbl:
1518 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1519 case Intrinsic::mips_dpsu_h_qbr:
1520 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1521 case Intrinsic::mips_dpa_w_ph:
1522 return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1523 case Intrinsic::mips_dps_w_ph:
1524 return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1525 case Intrinsic::mips_dpax_w_ph:
1526 return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1527 case Intrinsic::mips_dpsx_w_ph:
1528 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1529 case Intrinsic::mips_mulsa_w_ph:
1530 return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1531 case Intrinsic::mips_mult:
1532 return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1533 case Intrinsic::mips_multu:
1534 return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1535 case Intrinsic::mips_madd:
1536 return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1537 case Intrinsic::mips_maddu:
1538 return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1539 case Intrinsic::mips_msub:
1540 return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1541 case Intrinsic::mips_msubu:
1542 return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
1543 case Intrinsic::mips_addv_b:
1544 case Intrinsic::mips_addv_h:
1545 case Intrinsic::mips_addv_w:
1546 case Intrinsic::mips_addv_d:
1547 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1548 Op->getOperand(2));
1549 case Intrinsic::mips_addvi_b:
1550 case Intrinsic::mips_addvi_h:
1551 case Intrinsic::mips_addvi_w:
1552 case Intrinsic::mips_addvi_d:
1553 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1554 lowerMSASplatImm(Op, 2, DAG));
1555 case Intrinsic::mips_and_v:
1556 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1557 Op->getOperand(2));
1558 case Intrinsic::mips_andi_b:
1559 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1560 lowerMSASplatImm(Op, 2, DAG));
1561 case Intrinsic::mips_bclr_b:
1562 case Intrinsic::mips_bclr_h:
1563 case Intrinsic::mips_bclr_w:
1564 case Intrinsic::mips_bclr_d:
1565 return lowerMSABitClear(Op, DAG);
1566 case Intrinsic::mips_bclri_b:
1567 case Intrinsic::mips_bclri_h:
1568 case Intrinsic::mips_bclri_w:
1569 case Intrinsic::mips_bclri_d:
1570 return lowerMSABitClearImm(Op, DAG);
1571 case Intrinsic::mips_binsli_b:
1572 case Intrinsic::mips_binsli_h:
1573 case Intrinsic::mips_binsli_w:
1574 case Intrinsic::mips_binsli_d: {
1575 // binsli_x(IfClear, IfSet, nbits) -> (vselect LBitsMask, IfSet, IfClear)
1576 EVT VecTy = Op->getValueType(0);
1577 EVT EltTy = VecTy.getVectorElementType();
1578 APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(),
1579 Op->getConstantOperandVal(3));
1580 return DAG.getNode(ISD::VSELECT, DL, VecTy,
1581 DAG.getConstant(Mask, VecTy, true), Op->getOperand(2),
1582 Op->getOperand(1));
1583 }
1584 case Intrinsic::mips_binsri_b:
1585 case Intrinsic::mips_binsri_h:
1586 case Intrinsic::mips_binsri_w:
1587 case Intrinsic::mips_binsri_d: {
1588 // binsri_x(IfClear, IfSet, nbits) -> (vselect RBitsMask, IfSet, IfClear)
1589 EVT VecTy = Op->getValueType(0);
1590 EVT EltTy = VecTy.getVectorElementType();
1591 APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(),
1592 Op->getConstantOperandVal(3));
1593 return DAG.getNode(ISD::VSELECT, DL, VecTy,
1594 DAG.getConstant(Mask, VecTy, true), Op->getOperand(2),
1595 Op->getOperand(1));
1596 }
1597 case Intrinsic::mips_bmnz_v:
1598 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1599 Op->getOperand(2), Op->getOperand(1));
1600 case Intrinsic::mips_bmnzi_b:
1601 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1602 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2),
1603 Op->getOperand(1));
1604 case Intrinsic::mips_bmz_v:
1605 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1606 Op->getOperand(1), Op->getOperand(2));
1607 case Intrinsic::mips_bmzi_b:
1608 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1609 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1),
1610 Op->getOperand(2));
1611 case Intrinsic::mips_bneg_b:
1612 case Intrinsic::mips_bneg_h:
1613 case Intrinsic::mips_bneg_w:
1614 case Intrinsic::mips_bneg_d: {
1615 EVT VecTy = Op->getValueType(0);
1616 SDValue One = DAG.getConstant(1, VecTy);
1617
1618 return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),
1619 DAG.getNode(ISD::SHL, DL, VecTy, One,
1620 Op->getOperand(2)));
1621 }
1622 case Intrinsic::mips_bnegi_b:
1623 case Intrinsic::mips_bnegi_h:
1624 case Intrinsic::mips_bnegi_w:
1625 case Intrinsic::mips_bnegi_d:
1626 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2),
1627 !Subtarget.isLittle());
1628 case Intrinsic::mips_bnz_b:
1629 case Intrinsic::mips_bnz_h:
1630 case Intrinsic::mips_bnz_w:
1631 case Intrinsic::mips_bnz_d:
1632 return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),
1633 Op->getOperand(1));
1634 case Intrinsic::mips_bnz_v:
1635 return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),
1636 Op->getOperand(1));
1637 case Intrinsic::mips_bsel_v:
1638 // bsel_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1639 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1640 Op->getOperand(1), Op->getOperand(3),
1641 Op->getOperand(2));
1642 case Intrinsic::mips_bseli_b:
1643 // bseli_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1644 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1645 Op->getOperand(1), lowerMSASplatImm(Op, 3, DAG),
1646 Op->getOperand(2));
1647 case Intrinsic::mips_bset_b:
1648 case Intrinsic::mips_bset_h:
1649 case Intrinsic::mips_bset_w:
1650 case Intrinsic::mips_bset_d: {
1651 EVT VecTy = Op->getValueType(0);
1652 SDValue One = DAG.getConstant(1, VecTy);
1653
1654 return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),
1655 DAG.getNode(ISD::SHL, DL, VecTy, One,
1656 Op->getOperand(2)));
1657 }
1658 case Intrinsic::mips_bseti_b:
1659 case Intrinsic::mips_bseti_h:
1660 case Intrinsic::mips_bseti_w:
1661 case Intrinsic::mips_bseti_d:
1662 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2),
1663 !Subtarget.isLittle());
1664 case Intrinsic::mips_bz_b:
1665 case Intrinsic::mips_bz_h:
1666 case Intrinsic::mips_bz_w:
1667 case Intrinsic::mips_bz_d:
1668 return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),
1669 Op->getOperand(1));
1670 case Intrinsic::mips_bz_v:
1671 return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),
1672 Op->getOperand(1));
1673 case Intrinsic::mips_ceq_b:
1674 case Intrinsic::mips_ceq_h:
1675 case Intrinsic::mips_ceq_w:
1676 case Intrinsic::mips_ceq_d:
1677 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1678 Op->getOperand(2), ISD::SETEQ);
1679 case Intrinsic::mips_ceqi_b:
1680 case Intrinsic::mips_ceqi_h:
1681 case Intrinsic::mips_ceqi_w:
1682 case Intrinsic::mips_ceqi_d:
1683 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1684 lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ);
1685 case Intrinsic::mips_cle_s_b:
1686 case Intrinsic::mips_cle_s_h:
1687 case Intrinsic::mips_cle_s_w:
1688 case Intrinsic::mips_cle_s_d:
1689 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1690 Op->getOperand(2), ISD::SETLE);
1691 case Intrinsic::mips_clei_s_b:
1692 case Intrinsic::mips_clei_s_h:
1693 case Intrinsic::mips_clei_s_w:
1694 case Intrinsic::mips_clei_s_d:
1695 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1696 lowerMSASplatImm(Op, 2, DAG), ISD::SETLE);
1697 case Intrinsic::mips_cle_u_b:
1698 case Intrinsic::mips_cle_u_h:
1699 case Intrinsic::mips_cle_u_w:
1700 case Intrinsic::mips_cle_u_d:
1701 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1702 Op->getOperand(2), ISD::SETULE);
1703 case Intrinsic::mips_clei_u_b:
1704 case Intrinsic::mips_clei_u_h:
1705 case Intrinsic::mips_clei_u_w:
1706 case Intrinsic::mips_clei_u_d:
1707 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1708 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1709 case Intrinsic::mips_clt_s_b:
1710 case Intrinsic::mips_clt_s_h:
1711 case Intrinsic::mips_clt_s_w:
1712 case Intrinsic::mips_clt_s_d:
1713 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1714 Op->getOperand(2), ISD::SETLT);
1715 case Intrinsic::mips_clti_s_b:
1716 case Intrinsic::mips_clti_s_h:
1717 case Intrinsic::mips_clti_s_w:
1718 case Intrinsic::mips_clti_s_d:
1719 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1720 lowerMSASplatImm(Op, 2, DAG), ISD::SETLT);
1721 case Intrinsic::mips_clt_u_b:
1722 case Intrinsic::mips_clt_u_h:
1723 case Intrinsic::mips_clt_u_w:
1724 case Intrinsic::mips_clt_u_d:
1725 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1726 Op->getOperand(2), ISD::SETULT);
1727 case Intrinsic::mips_clti_u_b:
1728 case Intrinsic::mips_clti_u_h:
1729 case Intrinsic::mips_clti_u_w:
1730 case Intrinsic::mips_clti_u_d:
1731 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1732 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
1733 case Intrinsic::mips_copy_s_b:
1734 case Intrinsic::mips_copy_s_h:
1735 case Intrinsic::mips_copy_s_w:
1736 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1737 case Intrinsic::mips_copy_s_d:
1738 if (Subtarget.hasMips64())
1739 // Lower directly into VEXTRACT_SEXT_ELT since i64 is legal on Mips64.
1740 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1741 else {
1742 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1743 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1744 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1745 Op->getValueType(0), Op->getOperand(1),
1746 Op->getOperand(2));
1747 }
1748 case Intrinsic::mips_copy_u_b:
1749 case Intrinsic::mips_copy_u_h:
1750 case Intrinsic::mips_copy_u_w:
1751 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1752 case Intrinsic::mips_copy_u_d:
1753 if (Subtarget.hasMips64())
1754 // Lower directly into VEXTRACT_ZEXT_ELT since i64 is legal on Mips64.
1755 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1756 else {
1757 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1758 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1759 // Note: When i64 is illegal, this results in copy_s.w instructions
1760 // instead of copy_u.w instructions. This makes no difference to the
1761 // behaviour since i64 is only illegal when the register file is 32-bit.
1762 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1763 Op->getValueType(0), Op->getOperand(1),
1764 Op->getOperand(2));
1765 }
1766 case Intrinsic::mips_div_s_b:
1767 case Intrinsic::mips_div_s_h:
1768 case Intrinsic::mips_div_s_w:
1769 case Intrinsic::mips_div_s_d:
1770 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1771 Op->getOperand(2));
1772 case Intrinsic::mips_div_u_b:
1773 case Intrinsic::mips_div_u_h:
1774 case Intrinsic::mips_div_u_w:
1775 case Intrinsic::mips_div_u_d:
1776 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1777 Op->getOperand(2));
1778 case Intrinsic::mips_fadd_w:
1779 case Intrinsic::mips_fadd_d:
1780 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1781 Op->getOperand(2));
1782 // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1783 case Intrinsic::mips_fceq_w:
1784 case Intrinsic::mips_fceq_d:
1785 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1786 Op->getOperand(2), ISD::SETOEQ);
1787 case Intrinsic::mips_fcle_w:
1788 case Intrinsic::mips_fcle_d:
1789 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1790 Op->getOperand(2), ISD::SETOLE);
1791 case Intrinsic::mips_fclt_w:
1792 case Intrinsic::mips_fclt_d:
1793 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1794 Op->getOperand(2), ISD::SETOLT);
1795 case Intrinsic::mips_fcne_w:
1796 case Intrinsic::mips_fcne_d:
1797 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1798 Op->getOperand(2), ISD::SETONE);
1799 case Intrinsic::mips_fcor_w:
1800 case Intrinsic::mips_fcor_d:
1801 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1802 Op->getOperand(2), ISD::SETO);
1803 case Intrinsic::mips_fcueq_w:
1804 case Intrinsic::mips_fcueq_d:
1805 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1806 Op->getOperand(2), ISD::SETUEQ);
1807 case Intrinsic::mips_fcule_w:
1808 case Intrinsic::mips_fcule_d:
1809 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1810 Op->getOperand(2), ISD::SETULE);
1811 case Intrinsic::mips_fcult_w:
1812 case Intrinsic::mips_fcult_d:
1813 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1814 Op->getOperand(2), ISD::SETULT);
1815 case Intrinsic::mips_fcun_w:
1816 case Intrinsic::mips_fcun_d:
1817 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1818 Op->getOperand(2), ISD::SETUO);
1819 case Intrinsic::mips_fcune_w:
1820 case Intrinsic::mips_fcune_d:
1821 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1822 Op->getOperand(2), ISD::SETUNE);
1823 case Intrinsic::mips_fdiv_w:
1824 case Intrinsic::mips_fdiv_d:
1825 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1826 Op->getOperand(2));
1827 case Intrinsic::mips_ffint_u_w:
1828 case Intrinsic::mips_ffint_u_d:
1829 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
1830 Op->getOperand(1));
1831 case Intrinsic::mips_ffint_s_w:
1832 case Intrinsic::mips_ffint_s_d:
1833 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
1834 Op->getOperand(1));
1835 case Intrinsic::mips_fill_b:
1836 case Intrinsic::mips_fill_h:
1837 case Intrinsic::mips_fill_w:
1838 case Intrinsic::mips_fill_d: {
1839 SmallVector<SDValue, 16> Ops;
1840 EVT ResTy = Op->getValueType(0);
1841
1842 for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i)
1843 Ops.push_back(Op->getOperand(1));
1844
1845 // If ResTy is v2i64 then the type legalizer will break this node down into
1846 // an equivalent v4i32.
1847 return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, Ops);
1848 }
1849 case Intrinsic::mips_fexp2_w:
1850 case Intrinsic::mips_fexp2_d: {
1851 EVT ResTy = Op->getValueType(0);
1852 return DAG.getNode(
1853 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1854 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
1855 }
1856 case Intrinsic::mips_flog2_w:
1857 case Intrinsic::mips_flog2_d:
1858 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
1859 case Intrinsic::mips_fmadd_w:
1860 case Intrinsic::mips_fmadd_d:
1861 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
1862 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1863 case Intrinsic::mips_fmul_w:
1864 case Intrinsic::mips_fmul_d:
1865 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1866 Op->getOperand(2));
1867 case Intrinsic::mips_fmsub_w:
1868 case Intrinsic::mips_fmsub_d: {
1869 EVT ResTy = Op->getValueType(0);
1870 return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1),
1871 DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy,
1872 Op->getOperand(2), Op->getOperand(3)));
1873 }
1874 case Intrinsic::mips_frint_w:
1875 case Intrinsic::mips_frint_d:
1876 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
1877 case Intrinsic::mips_fsqrt_w:
1878 case Intrinsic::mips_fsqrt_d:
1879 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
1880 case Intrinsic::mips_fsub_w:
1881 case Intrinsic::mips_fsub_d:
1882 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1883 Op->getOperand(2));
1884 case Intrinsic::mips_ftrunc_u_w:
1885 case Intrinsic::mips_ftrunc_u_d:
1886 return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
1887 Op->getOperand(1));
1888 case Intrinsic::mips_ftrunc_s_w:
1889 case Intrinsic::mips_ftrunc_s_d:
1890 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
1891 Op->getOperand(1));
1892 case Intrinsic::mips_ilvev_b:
1893 case Intrinsic::mips_ilvev_h:
1894 case Intrinsic::mips_ilvev_w:
1895 case Intrinsic::mips_ilvev_d:
1896 return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),
1897 Op->getOperand(1), Op->getOperand(2));
1898 case Intrinsic::mips_ilvl_b:
1899 case Intrinsic::mips_ilvl_h:
1900 case Intrinsic::mips_ilvl_w:
1901 case Intrinsic::mips_ilvl_d:
1902 return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),
1903 Op->getOperand(1), Op->getOperand(2));
1904 case Intrinsic::mips_ilvod_b:
1905 case Intrinsic::mips_ilvod_h:
1906 case Intrinsic::mips_ilvod_w:
1907 case Intrinsic::mips_ilvod_d:
1908 return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),
1909 Op->getOperand(1), Op->getOperand(2));
1910 case Intrinsic::mips_ilvr_b:
1911 case Intrinsic::mips_ilvr_h:
1912 case Intrinsic::mips_ilvr_w:
1913 case Intrinsic::mips_ilvr_d:
1914 return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),
1915 Op->getOperand(1), Op->getOperand(2));
1916 case Intrinsic::mips_insert_b:
1917 case Intrinsic::mips_insert_h:
1918 case Intrinsic::mips_insert_w:
1919 case Intrinsic::mips_insert_d:
1920 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1921 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
1922 case Intrinsic::mips_insve_b:
1923 case Intrinsic::mips_insve_h:
1924 case Intrinsic::mips_insve_w:
1925 case Intrinsic::mips_insve_d:
1926 return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0),
1927 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3),
1928 DAG.getConstant(0, MVT::i32));
1929 case Intrinsic::mips_ldi_b:
1930 case Intrinsic::mips_ldi_h:
1931 case Intrinsic::mips_ldi_w:
1932 case Intrinsic::mips_ldi_d:
1933 return lowerMSASplatImm(Op, 1, DAG);
1934 case Intrinsic::mips_lsa:
1935 case Intrinsic::mips_dlsa: {
1936 EVT ResTy = Op->getValueType(0);
1937 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1938 DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
1939 Op->getOperand(2), Op->getOperand(3)));
1940 }
1941 case Intrinsic::mips_maddv_b:
1942 case Intrinsic::mips_maddv_h:
1943 case Intrinsic::mips_maddv_w:
1944 case Intrinsic::mips_maddv_d: {
1945 EVT ResTy = Op->getValueType(0);
1946 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1947 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1948 Op->getOperand(2), Op->getOperand(3)));
1949 }
1950 case Intrinsic::mips_max_s_b:
1951 case Intrinsic::mips_max_s_h:
1952 case Intrinsic::mips_max_s_w:
1953 case Intrinsic::mips_max_s_d:
1954 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1955 Op->getOperand(1), Op->getOperand(2));
1956 case Intrinsic::mips_max_u_b:
1957 case Intrinsic::mips_max_u_h:
1958 case Intrinsic::mips_max_u_w:
1959 case Intrinsic::mips_max_u_d:
1960 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1961 Op->getOperand(1), Op->getOperand(2));
1962 case Intrinsic::mips_maxi_s_b:
1963 case Intrinsic::mips_maxi_s_h:
1964 case Intrinsic::mips_maxi_s_w:
1965 case Intrinsic::mips_maxi_s_d:
1966 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1967 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1968 case Intrinsic::mips_maxi_u_b:
1969 case Intrinsic::mips_maxi_u_h:
1970 case Intrinsic::mips_maxi_u_w:
1971 case Intrinsic::mips_maxi_u_d:
1972 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1973 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1974 case Intrinsic::mips_min_s_b:
1975 case Intrinsic::mips_min_s_h:
1976 case Intrinsic::mips_min_s_w:
1977 case Intrinsic::mips_min_s_d:
1978 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1979 Op->getOperand(1), Op->getOperand(2));
1980 case Intrinsic::mips_min_u_b:
1981 case Intrinsic::mips_min_u_h:
1982 case Intrinsic::mips_min_u_w:
1983 case Intrinsic::mips_min_u_d:
1984 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1985 Op->getOperand(1), Op->getOperand(2));
1986 case Intrinsic::mips_mini_s_b:
1987 case Intrinsic::mips_mini_s_h:
1988 case Intrinsic::mips_mini_s_w:
1989 case Intrinsic::mips_mini_s_d:
1990 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1991 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1992 case Intrinsic::mips_mini_u_b:
1993 case Intrinsic::mips_mini_u_h:
1994 case Intrinsic::mips_mini_u_w:
1995 case Intrinsic::mips_mini_u_d:
1996 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1997 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1998 case Intrinsic::mips_mod_s_b:
1999 case Intrinsic::mips_mod_s_h:
2000 case Intrinsic::mips_mod_s_w:
2001 case Intrinsic::mips_mod_s_d:
2002 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
2003 Op->getOperand(2));
2004 case Intrinsic::mips_mod_u_b:
2005 case Intrinsic::mips_mod_u_h:
2006 case Intrinsic::mips_mod_u_w:
2007 case Intrinsic::mips_mod_u_d:
2008 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
2009 Op->getOperand(2));
2010 case Intrinsic::mips_mulv_b:
2011 case Intrinsic::mips_mulv_h:
2012 case Intrinsic::mips_mulv_w:
2013 case Intrinsic::mips_mulv_d:
2014 return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
2015 Op->getOperand(2));
2016 case Intrinsic::mips_msubv_b:
2017 case Intrinsic::mips_msubv_h:
2018 case Intrinsic::mips_msubv_w:
2019 case Intrinsic::mips_msubv_d: {
2020 EVT ResTy = Op->getValueType(0);
2021 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
2022 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
2023 Op->getOperand(2), Op->getOperand(3)));
2024 }
2025 case Intrinsic::mips_nlzc_b:
2026 case Intrinsic::mips_nlzc_h:
2027 case Intrinsic::mips_nlzc_w:
2028 case Intrinsic::mips_nlzc_d:
2029 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
2030 case Intrinsic::mips_nor_v: {
2031 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2032 Op->getOperand(1), Op->getOperand(2));
2033 return DAG.getNOT(DL, Res, Res->getValueType(0));
2034 }
2035 case Intrinsic::mips_nori_b: {
2036 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2037 Op->getOperand(1),
2038 lowerMSASplatImm(Op, 2, DAG));
2039 return DAG.getNOT(DL, Res, Res->getValueType(0));
2040 }
2041 case Intrinsic::mips_or_v:
2042 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
2043 Op->getOperand(2));
2044 case Intrinsic::mips_ori_b:
2045 return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2046 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2047 case Intrinsic::mips_pckev_b:
2048 case Intrinsic::mips_pckev_h:
2049 case Intrinsic::mips_pckev_w:
2050 case Intrinsic::mips_pckev_d:
2051 return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),
2052 Op->getOperand(1), Op->getOperand(2));
2053 case Intrinsic::mips_pckod_b:
2054 case Intrinsic::mips_pckod_h:
2055 case Intrinsic::mips_pckod_w:
2056 case Intrinsic::mips_pckod_d:
2057 return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),
2058 Op->getOperand(1), Op->getOperand(2));
2059 case Intrinsic::mips_pcnt_b:
2060 case Intrinsic::mips_pcnt_h:
2061 case Intrinsic::mips_pcnt_w:
2062 case Intrinsic::mips_pcnt_d:
2063 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
2064 case Intrinsic::mips_shf_b:
2065 case Intrinsic::mips_shf_h:
2066 case Intrinsic::mips_shf_w:
2067 return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),
2068 Op->getOperand(2), Op->getOperand(1));
2069 case Intrinsic::mips_sll_b:
2070 case Intrinsic::mips_sll_h:
2071 case Intrinsic::mips_sll_w:
2072 case Intrinsic::mips_sll_d:
2073 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
2074 Op->getOperand(2));
2075 case Intrinsic::mips_slli_b:
2076 case Intrinsic::mips_slli_h:
2077 case Intrinsic::mips_slli_w:
2078 case Intrinsic::mips_slli_d:
2079 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
2080 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2081 case Intrinsic::mips_splat_b:
2082 case Intrinsic::mips_splat_h:
2083 case Intrinsic::mips_splat_w:
2084 case Intrinsic::mips_splat_d:
2085 // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle
2086 // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because
2087 // EXTRACT_VECTOR_ELT can't extract i64's on MIPS32.
2088 // Instead we lower to MipsISD::VSHF and match from there.
2089 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2090 lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1),
2091 Op->getOperand(1));
2092 case Intrinsic::mips_splati_b:
2093 case Intrinsic::mips_splati_h:
2094 case Intrinsic::mips_splati_w:
2095 case Intrinsic::mips_splati_d:
2096 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2097 lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
2098 Op->getOperand(1));
2099 case Intrinsic::mips_sra_b:
2100 case Intrinsic::mips_sra_h:
2101 case Intrinsic::mips_sra_w:
2102 case Intrinsic::mips_sra_d:
2103 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
2104 Op->getOperand(2));
2105 case Intrinsic::mips_srai_b:
2106 case Intrinsic::mips_srai_h:
2107 case Intrinsic::mips_srai_w:
2108 case Intrinsic::mips_srai_d:
2109 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
2110 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2111 case Intrinsic::mips_srl_b:
2112 case Intrinsic::mips_srl_h:
2113 case Intrinsic::mips_srl_w:
2114 case Intrinsic::mips_srl_d:
2115 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
2116 Op->getOperand(2));
2117 case Intrinsic::mips_srli_b:
2118 case Intrinsic::mips_srli_h:
2119 case Intrinsic::mips_srli_w:
2120 case Intrinsic::mips_srli_d:
2121 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
2122 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2123 case Intrinsic::mips_subv_b:
2124 case Intrinsic::mips_subv_h:
2125 case Intrinsic::mips_subv_w:
2126 case Intrinsic::mips_subv_d:
2127 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
2128 Op->getOperand(2));
2129 case Intrinsic::mips_subvi_b:
2130 case Intrinsic::mips_subvi_h:
2131 case Intrinsic::mips_subvi_w:
2132 case Intrinsic::mips_subvi_d:
2133 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
2134 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2135 case Intrinsic::mips_vshf_b:
2136 case Intrinsic::mips_vshf_h:
2137 case Intrinsic::mips_vshf_w:
2138 case Intrinsic::mips_vshf_d:
2139 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2140 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
2141 case Intrinsic::mips_xor_v:
2142 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
2143 Op->getOperand(2));
2144 case Intrinsic::mips_xori_b:
2145 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
2146 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2147 }
2148}
2149
2150static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
2151 SDLoc DL(Op);
2152 SDValue ChainIn = Op->getOperand(0);
2153 SDValue Address = Op->getOperand(2);
2154 SDValue Offset = Op->getOperand(3);
2155 EVT ResTy = Op->getValueType(0);
2156 EVT PtrTy = Address->getValueType(0);
2157
2158 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2159
2160 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
2161 false, false, 16);
2162}
2163
2164SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
2165 SelectionDAG &DAG) const {
2166 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2167 switch (Intr) {
2168 default:
2169 return SDValue();
2170 case Intrinsic::mips_extp:
2171 return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
2172 case Intrinsic::mips_extpdp:
2173 return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
2174 case Intrinsic::mips_extr_w:
2175 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
2176 case Intrinsic::mips_extr_r_w:
2177 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
2178 case Intrinsic::mips_extr_rs_w:
2179 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
2180 case Intrinsic::mips_extr_s_h:
2181 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
2182 case Intrinsic::mips_mthlip:
2183 return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
2184 case Intrinsic::mips_mulsaq_s_w_ph:
2185 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
2186 case Intrinsic::mips_maq_s_w_phl:
2187 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
2188 case Intrinsic::mips_maq_s_w_phr:
2189 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
2190 case Intrinsic::mips_maq_sa_w_phl:
2191 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
2192 case Intrinsic::mips_maq_sa_w_phr:
2193 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
2194 case Intrinsic::mips_dpaq_s_w_ph:
2195 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
2196 case Intrinsic::mips_dpsq_s_w_ph:
2197 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
2198 case Intrinsic::mips_dpaq_sa_l_w:
2199 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
2200 case Intrinsic::mips_dpsq_sa_l_w:
2201 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
2202 case Intrinsic::mips_dpaqx_s_w_ph:
2203 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
2204 case Intrinsic::mips_dpaqx_sa_w_ph:
2205 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
2206 case Intrinsic::mips_dpsqx_s_w_ph:
2207 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
2208 case Intrinsic::mips_dpsqx_sa_w_ph:
2209 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
2210 case Intrinsic::mips_ld_b:
2211 case Intrinsic::mips_ld_h:
2212 case Intrinsic::mips_ld_w:
2213 case Intrinsic::mips_ld_d:
2214 return lowerMSALoadIntr(Op, DAG, Intr);
2215 }
2216}
2217
2218static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
2219 SDLoc DL(Op);
2220 SDValue ChainIn = Op->getOperand(0);
2221 SDValue Value = Op->getOperand(2);
2222 SDValue Address = Op->getOperand(3);
2223 SDValue Offset = Op->getOperand(4);
2224 EVT PtrTy = Address->getValueType(0);
2225
2226 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2227
2228 return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
2229 false, 16);
2230}
2231
2232SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
2233 SelectionDAG &DAG) const {
2234 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2235 switch (Intr) {
2236 default:
2237 return SDValue();
2238 case Intrinsic::mips_st_b:
2239 case Intrinsic::mips_st_h:
2240 case Intrinsic::mips_st_w:
2241 case Intrinsic::mips_st_d:
2242 return lowerMSAStoreIntr(Op, DAG, Intr);
2243 }
2244}
2245
2246/// \brief Check if the given BuildVectorSDNode is a splat.
2247/// This method currently relies on DAG nodes being reused when equivalent,
2248/// so it's possible for this to return false even when isConstantSplat returns
2249/// true.
2250static bool isSplatVector(const BuildVectorSDNode *N) {
2251 unsigned int nOps = N->getNumOperands();
2252 assert(nOps > 1 && "isSplatVector has 0 or 1 sized build vector");
2253
2254 SDValue Operand0 = N->getOperand(0);
2255
2256 for (unsigned int i = 1; i < nOps; ++i) {
2257 if (N->getOperand(i) != Operand0)
2258 return false;
2259 }
2260
2261 return true;
2262}
2263
2264// Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
2265//
2266// The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
2267// choose to sign-extend but we could have equally chosen zero-extend. The
2268// DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
2269// result into this node later (possibly changing it to a zero-extend in the
2270// process).
2271SDValue MipsSETargetLowering::
2272lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
2273 SDLoc DL(Op);
2274 EVT ResTy = Op->getValueType(0);
2275 SDValue Op0 = Op->getOperand(0);
2276 EVT VecTy = Op0->getValueType(0);
2277
2278 if (!VecTy.is128BitVector())
2279 return SDValue();
2280
2281 if (ResTy.isInteger()) {
2282 SDValue Op1 = Op->getOperand(1);
2283 EVT EltTy = VecTy.getVectorElementType();
2284 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
2285 DAG.getValueType(EltTy));
2286 }
2287
2288 return Op;
2289}
2290
2291static bool isConstantOrUndef(const SDValue Op) {
2292 if (Op->getOpcode() == ISD::UNDEF)
2293 return true;
2294 if (dyn_cast<ConstantSDNode>(Op))
2295 return true;
2296 if (dyn_cast<ConstantFPSDNode>(Op))
2297 return true;
2298 return false;
2299}
2300
2301static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) {
2302 for (unsigned i = 0; i < Op->getNumOperands(); ++i)
2303 if (isConstantOrUndef(Op->getOperand(i)))
2304 return true;
2305 return false;
2306}
2307
2308// Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
2309// backend.
2310//
2311// Lowers according to the following rules:
2312// - Constant splats are legal as-is as long as the SplatBitSize is a power of
2313// 2 less than or equal to 64 and the value fits into a signed 10-bit
2314// immediate
2315// - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
2316// is a power of 2 less than or equal to 64 and the value does not fit into a
2317// signed 10-bit immediate
2318// - Non-constant splats are legal as-is.
2319// - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
2320// - All others are illegal and must be expanded.
2321SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
2322 SelectionDAG &DAG) const {
2323 BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
2324 EVT ResTy = Op->getValueType(0);
2325 SDLoc DL(Op);
2326 APInt SplatValue, SplatUndef;
2327 unsigned SplatBitSize;
2328 bool HasAnyUndefs;
2329
2330 if (!Subtarget.hasMSA() || !ResTy.is128BitVector())
2331 return SDValue();
2332
2333 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
2334 HasAnyUndefs, 8,
2335 !Subtarget.isLittle()) && SplatBitSize <= 64) {
2336 // We can only cope with 8, 16, 32, or 64-bit elements
2337 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
2338 SplatBitSize != 64)
2339 return SDValue();
2340
2341 // If the value fits into a simm10 then we can use ldi.[bhwd]
2342 // However, if it isn't an integer type we will have to bitcast from an
2343 // integer type first. Also, if there are any undefs, we must lower them
2344 // to defined values first.
2345 if (ResTy.isInteger() && !HasAnyUndefs && SplatValue.isSignedIntN(10))
2346 return Op;
2347
2348 EVT ViaVecTy;
2349
2350 switch (SplatBitSize) {
2351 default:
2352 return SDValue();
2353 case 8:
2354 ViaVecTy = MVT::v16i8;
2355 break;
2356 case 16:
2357 ViaVecTy = MVT::v8i16;
2358 break;
2359 case 32:
2360 ViaVecTy = MVT::v4i32;
2361 break;
2362 case 64:
2363 // There's no fill.d to fall back on for 64-bit values
2364 return SDValue();
2365 }
2366
2367 // SelectionDAG::getConstant will promote SplatValue appropriately.
2368 SDValue Result = DAG.getConstant(SplatValue, ViaVecTy);
2369
2370 // Bitcast to the type we originally wanted
2371 if (ViaVecTy != ResTy)
2372 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
2373
2374 return Result;
2375 } else if (isSplatVector(Node))
2376 return Op;
2377 else if (!isConstantOrUndefBUILD_VECTOR(Node)) {
2378 // Use INSERT_VECTOR_ELT operations rather than expand to stores.
2379 // The resulting code is the same length as the expansion, but it doesn't
2380 // use memory operations
2381 EVT ResTy = Node->getValueType(0);
2382
2383 assert(ResTy.isVector());
2384
2385 unsigned NumElts = ResTy.getVectorNumElements();
2386 SDValue Vector = DAG.getUNDEF(ResTy);
2387 for (unsigned i = 0; i < NumElts; ++i) {
2388 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
2389 Node->getOperand(i),
2390 DAG.getConstant(i, MVT::i32));
2391 }
2392 return Vector;
2393 }
2394
2395 return SDValue();
2396}
2397
2398// Lower VECTOR_SHUFFLE into SHF (if possible).
2399//
2400// SHF splits the vector into blocks of four elements, then shuffles these
2401// elements according to a <4 x i2> constant (encoded as an integer immediate).
2402//
2403// It is therefore possible to lower into SHF when the mask takes the form:
2404// <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...>
2405// When undef's appear they are treated as if they were whatever value is
2406// necessary in order to fit the above form.
2407//
2408// For example:
2409// %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
2410// <8 x i32> <i32 3, i32 2, i32 1, i32 0,
2411// i32 7, i32 6, i32 5, i32 4>
2412// is lowered to:
2413// (SHF_H $w0, $w1, 27)
2414// where the 27 comes from:
2415// 3 + (2 << 2) + (1 << 4) + (0 << 6)
2416static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy,
2417 SmallVector<int, 16> Indices,
2418 SelectionDAG &DAG) {
2419 int SHFIndices[4] = { -1, -1, -1, -1 };
2420
2421 if (Indices.size() < 4)
2422 return SDValue();
2423
2424 for (unsigned i = 0; i < 4; ++i) {
2425 for (unsigned j = i; j < Indices.size(); j += 4) {
2426 int Idx = Indices[j];
2427
2428 // Convert from vector index to 4-element subvector index
2429 // If an index refers to an element outside of the subvector then give up
2430 if (Idx != -1) {
2431 Idx -= 4 * (j / 4);
2432 if (Idx < 0 || Idx >= 4)
2433 return SDValue();
2434 }
2435
2436 // If the mask has an undef, replace it with the current index.
2437 // Note that it might still be undef if the current index is also undef
2438 if (SHFIndices[i] == -1)
2439 SHFIndices[i] = Idx;
2440
2441 // Check that non-undef values are the same as in the mask. If they
2442 // aren't then give up
2443 if (!(Idx == -1 || Idx == SHFIndices[i]))
2444 return SDValue();
2445 }
2446 }
2447
2448 // Calculate the immediate. Replace any remaining undefs with zero
2449 APInt Imm(32, 0);
2450 for (int i = 3; i >= 0; --i) {
2451 int Idx = SHFIndices[i];
2452
2453 if (Idx == -1)
2454 Idx = 0;
2455
2456 Imm <<= 2;
2457 Imm |= Idx & 0x3;
2458 }
2459
2460 return DAG.getNode(MipsISD::SHF, SDLoc(Op), ResTy,
2461 DAG.getConstant(Imm, MVT::i32), Op->getOperand(0));
2462}
2463
2464// Lower VECTOR_SHUFFLE into ILVEV (if possible).
2465//
2466// ILVEV interleaves the even elements from each vector.
2467//
2468// It is possible to lower into ILVEV when the mask takes the form:
2469// <0, n, 2, n+2, 4, n+4, ...>
2470// where n is the number of elements in the vector.
2471//
2472// When undef's appear in the mask they are treated as if they were whatever
2473// value is necessary in order to fit the above form.
2474static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy,
2475 SmallVector<int, 16> Indices,
2476 SelectionDAG &DAG) {
2477 assert ((Indices.size() % 2) == 0);
2478 int WsIdx = 0;
2479 int WtIdx = ResTy.getVectorNumElements();
2480
2481 for (unsigned i = 0; i < Indices.size(); i += 2) {
2482 if (Indices[i] != -1 && Indices[i] != WsIdx)
2483 return SDValue();
2484 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2485 return SDValue();
2486 WsIdx += 2;
2487 WtIdx += 2;
2488 }
2489
2490 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Op->getOperand(0),
2491 Op->getOperand(1));
2492}
2493
2494// Lower VECTOR_SHUFFLE into ILVOD (if possible).
2495//
2496// ILVOD interleaves the odd elements from each vector.
2497//
2498// It is possible to lower into ILVOD when the mask takes the form:
2499// <1, n+1, 3, n+3, 5, n+5, ...>
2500// where n is the number of elements in the vector.
2501//
2502// When undef's appear in the mask they are treated as if they were whatever
2503// value is necessary in order to fit the above form.
2504static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy,
2505 SmallVector<int, 16> Indices,
2506 SelectionDAG &DAG) {
2507 assert ((Indices.size() % 2) == 0);
2508 int WsIdx = 1;
2509 int WtIdx = ResTy.getVectorNumElements() + 1;
2510
2511 for (unsigned i = 0; i < Indices.size(); i += 2) {
2512 if (Indices[i] != -1 && Indices[i] != WsIdx)
2513 return SDValue();
2514 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2515 return SDValue();
2516 WsIdx += 2;
2517 WtIdx += 2;
2518 }
2519
2520 return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Op->getOperand(0),
2521 Op->getOperand(1));
2522}
2523
2524// Lower VECTOR_SHUFFLE into ILVL (if possible).
2525//
2526// ILVL interleaves consecutive elements from the left half of each vector.
2527//
2528// It is possible to lower into ILVL when the mask takes the form:
2529// <0, n, 1, n+1, 2, n+2, ...>
2530// where n is the number of elements in the vector.
2531//
2532// When undef's appear in the mask they are treated as if they were whatever
2533// value is necessary in order to fit the above form.
2534static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy,
2535 SmallVector<int, 16> Indices,
2536 SelectionDAG &DAG) {
2537 assert ((Indices.size() % 2) == 0);
2538 int WsIdx = 0;
2539 int WtIdx = ResTy.getVectorNumElements();
2540
2541 for (unsigned i = 0; i < Indices.size(); i += 2) {
2542 if (Indices[i] != -1 && Indices[i] != WsIdx)
2543 return SDValue();
2544 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2545 return SDValue();
2546 WsIdx ++;
2547 WtIdx ++;
2548 }
2549
2550 return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Op->getOperand(0),
2551 Op->getOperand(1));
2552}
2553
2554// Lower VECTOR_SHUFFLE into ILVR (if possible).
2555//
2556// ILVR interleaves consecutive elements from the right half of each vector.
2557//
2558// It is possible to lower into ILVR when the mask takes the form:
2559// <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>
2560// where n is the number of elements in the vector and x is half n.
2561//
2562// When undef's appear in the mask they are treated as if they were whatever
2563// value is necessary in order to fit the above form.
2564static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy,
2565 SmallVector<int, 16> Indices,
2566 SelectionDAG &DAG) {
2567 assert ((Indices.size() % 2) == 0);
2568 unsigned NumElts = ResTy.getVectorNumElements();
2569 int WsIdx = NumElts / 2;
2570 int WtIdx = NumElts + NumElts / 2;
2571
2572 for (unsigned i = 0; i < Indices.size(); i += 2) {
2573 if (Indices[i] != -1 && Indices[i] != WsIdx)
2574 return SDValue();
2575 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2576 return SDValue();
2577 WsIdx ++;
2578 WtIdx ++;
2579 }
2580
2581 return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Op->getOperand(0),
2582 Op->getOperand(1));
2583}
2584
2585// Lower VECTOR_SHUFFLE into PCKEV (if possible).
2586//
2587// PCKEV copies the even elements of each vector into the result vector.
2588//
2589// It is possible to lower into PCKEV when the mask takes the form:
2590// <0, 2, 4, ..., n, n+2, n+4, ...>
2591// where n is the number of elements in the vector.
2592//
2593// When undef's appear in the mask they are treated as if they were whatever
2594// value is necessary in order to fit the above form.
2595static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy,
2596 SmallVector<int, 16> Indices,
2597 SelectionDAG &DAG) {
2598 assert ((Indices.size() % 2) == 0);
2599 int Idx = 0;
2600
2601 for (unsigned i = 0; i < Indices.size(); ++i) {
2602 if (Indices[i] != -1 && Indices[i] != Idx)
2603 return SDValue();
2604 Idx += 2;
2605 }
2606
2607 return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Op->getOperand(0),
2608 Op->getOperand(1));
2609}
2610
2611// Lower VECTOR_SHUFFLE into PCKOD (if possible).
2612//
2613// PCKOD copies the odd elements of each vector into the result vector.
2614//
2615// It is possible to lower into PCKOD when the mask takes the form:
2616// <1, 3, 5, ..., n+1, n+3, n+5, ...>
2617// where n is the number of elements in the vector.
2618//
2619// When undef's appear in the mask they are treated as if they were whatever
2620// value is necessary in order to fit the above form.
2621static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy,
2622 SmallVector<int, 16> Indices,
2623 SelectionDAG &DAG) {
2624 assert ((Indices.size() % 2) == 0);
2625 int Idx = 1;
2626
2627 for (unsigned i = 0; i < Indices.size(); ++i) {
2628 if (Indices[i] != -1 && Indices[i] != Idx)
2629 return SDValue();
2630 Idx += 2;
2631 }
2632
2633 return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Op->getOperand(0),
2634 Op->getOperand(1));
2635}
2636
2637// Lower VECTOR_SHUFFLE into VSHF.
2638//
2639// This mostly consists of converting the shuffle indices in Indices into a
2640// BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is
2641// also code to eliminate unused operands of the VECTOR_SHUFFLE. For example,
2642// if the type is v8i16 and all the indices are less than 8 then the second
2643// operand is unused and can be replaced with anything. We choose to replace it
2644// with the used operand since this reduces the number of instructions overall.
2645static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
2646 SmallVector<int, 16> Indices,
2647 SelectionDAG &DAG) {
2648 SmallVector<SDValue, 16> Ops;
2649 SDValue Op0;
2650 SDValue Op1;
2651 EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2652 EVT MaskEltTy = MaskVecTy.getVectorElementType();
2653 bool Using1stVec = false;
2654 bool Using2ndVec = false;
2655 SDLoc DL(Op);
2656 int ResTyNumElts = ResTy.getVectorNumElements();
2657
2658 for (int i = 0; i < ResTyNumElts; ++i) {
2659 // Idx == -1 means UNDEF
2660 int Idx = Indices[i];
2661
2662 if (0 <= Idx && Idx < ResTyNumElts)
2663 Using1stVec = true;
2664 if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
2665 Using2ndVec = true;
2666 }
2667
2668 for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
2669 ++I)
2670 Ops.push_back(DAG.getTargetConstant(*I, MaskEltTy));
2671
2672 SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, Ops);
2673
2674 if (Using1stVec && Using2ndVec) {
2675 Op0 = Op->getOperand(0);
2676 Op1 = Op->getOperand(1);
2677 } else if (Using1stVec)
2678 Op0 = Op1 = Op->getOperand(0);
2679 else if (Using2ndVec)
2680 Op0 = Op1 = Op->getOperand(1);
2681 else
2682 llvm_unreachable("shuffle vector mask references neither vector operand?");
2683
2684 // VECTOR_SHUFFLE concatenates the vectors in an vectorwise fashion.
2685 // <0b00, 0b01> + <0b10, 0b11> -> <0b00, 0b01, 0b10, 0b11>
2686 // VSHF concatenates the vectors in a bitwise fashion:
2687 // <0b00, 0b01> + <0b10, 0b11> ->
2688 // 0b0100 + 0b1110 -> 0b01001110
2689 // <0b10, 0b11, 0b00, 0b01>
2690 // We must therefore swap the operands to get the correct result.
2691 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op1, Op0);
2692}
2693
2694// Lower VECTOR_SHUFFLE into one of a number of instructions depending on the
2695// indices in the shuffle.
2696SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
2697 SelectionDAG &DAG) const {
2698 ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
2699 EVT ResTy = Op->getValueType(0);
2700
2701 if (!ResTy.is128BitVector())
2702 return SDValue();
2703
2704 int ResTyNumElts = ResTy.getVectorNumElements();
2705 SmallVector<int, 16> Indices;
2706
2707 for (int i = 0; i < ResTyNumElts; ++i)
2708 Indices.push_back(Node->getMaskElt(i));
2709
2710 SDValue Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG);
2711 if (Result.getNode())
2712 return Result;
2713 Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG);
2714 if (Result.getNode())
2715 return Result;
2716 Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG);
2717 if (Result.getNode())
2718 return Result;
2719 Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG);
2720 if (Result.getNode())
2721 return Result;
2722 Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG);
2723 if (Result.getNode())
2724 return Result;
2725 Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG);
2726 if (Result.getNode())
2727 return Result;
2728 Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG);
2729 if (Result.getNode())
2730 return Result;
2731 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2732}
2733
2734MachineBasicBlock * MipsSETargetLowering::
2735emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
2736 // $bb:
2737 // bposge32_pseudo $vr0
2738 // =>
2739 // $bb:
2740 // bposge32 $tbb
2741 // $fbb:
2742 // li $vr2, 0
2743 // b $sink
2744 // $tbb:
2745 // li $vr1, 1
2746 // $sink:
2747 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
2748
2749 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2750 const TargetInstrInfo *TII =
2751 getTargetMachine().getSubtargetImpl()->getInstrInfo();
2752 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2753 DebugLoc DL = MI->getDebugLoc();
2754 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2755 MachineFunction::iterator It = std::next(MachineFunction::iterator(BB));
2756 MachineFunction *F = BB->getParent();
2757 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2758 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2759 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
2760 F->insert(It, FBB);
2761 F->insert(It, TBB);
2762 F->insert(It, Sink);
2763
2764 // Transfer the remainder of BB and its successor edges to Sink.
2765 Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
2766 BB->end());
2767 Sink->transferSuccessorsAndUpdatePHIs(BB);
2768
2769 // Add successors.
2770 BB->addSuccessor(FBB);
2771 BB->addSuccessor(TBB);
2772 FBB->addSuccessor(Sink);
2773 TBB->addSuccessor(Sink);
2774
2775 // Insert the real bposge32 instruction to $BB.
2776 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
2777
2778 // Fill $FBB.
2779 unsigned VR2 = RegInfo.createVirtualRegister(RC);
2780 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
2781 .addReg(Mips::ZERO).addImm(0);
2782 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2783
2784 // Fill $TBB.
2785 unsigned VR1 = RegInfo.createVirtualRegister(RC);
2786 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
2787 .addReg(Mips::ZERO).addImm(1);
2788
2789 // Insert phi function to $Sink.
2790 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2791 MI->getOperand(0).getReg())
2792 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
2793
2794 MI->eraseFromParent(); // The pseudo instruction is gone now.
2795 return Sink;
2796}
2797
2798MachineBasicBlock * MipsSETargetLowering::
2799emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
2800 unsigned BranchOp) const{
2801 // $bb:
2802 // vany_nonzero $rd, $ws
2803 // =>
2804 // $bb:
2805 // bnz.b $ws, $tbb
2806 // b $fbb
2807 // $fbb:
2808 // li $rd1, 0
2809 // b $sink
2810 // $tbb:
2811 // li $rd2, 1
2812 // $sink:
2813 // $rd = phi($rd1, $fbb, $rd2, $tbb)
2814
2815 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2816 const TargetInstrInfo *TII =
2817 getTargetMachine().getSubtargetImpl()->getInstrInfo();
2818 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2819 DebugLoc DL = MI->getDebugLoc();
2820 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2821 MachineFunction::iterator It = std::next(MachineFunction::iterator(BB));
2822 MachineFunction *F = BB->getParent();
2823 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2824 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2825 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
2826 F->insert(It, FBB);
2827 F->insert(It, TBB);
2828 F->insert(It, Sink);
2829
2830 // Transfer the remainder of BB and its successor edges to Sink.
2831 Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
2832 BB->end());
2833 Sink->transferSuccessorsAndUpdatePHIs(BB);
2834
2835 // Add successors.
2836 BB->addSuccessor(FBB);
2837 BB->addSuccessor(TBB);
2838 FBB->addSuccessor(Sink);
2839 TBB->addSuccessor(Sink);
2840
2841 // Insert the real bnz.b instruction to $BB.
2842 BuildMI(BB, DL, TII->get(BranchOp))
2843 .addReg(MI->getOperand(1).getReg())
2844 .addMBB(TBB);
2845
2846 // Fill $FBB.
2847 unsigned RD1 = RegInfo.createVirtualRegister(RC);
2848 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
2849 .addReg(Mips::ZERO).addImm(0);
2850 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2851
2852 // Fill $TBB.
2853 unsigned RD2 = RegInfo.createVirtualRegister(RC);
2854 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
2855 .addReg(Mips::ZERO).addImm(1);
2856
2857 // Insert phi function to $Sink.
2858 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2859 MI->getOperand(0).getReg())
2860 .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
2861
2862 MI->eraseFromParent(); // The pseudo instruction is gone now.
2863 return Sink;
2864}
2865
2866// Emit the COPY_FW pseudo instruction.
2867//
2868// copy_fw_pseudo $fd, $ws, n
2869// =>
2870// copy_u_w $rt, $ws, $n
2871// mtc1 $rt, $fd
2872//
2873// When n is zero, the equivalent operation can be performed with (potentially)
2874// zero instructions due to register overlaps. This optimization is never valid
2875// for lane 1 because it would require FR=0 mode which isn't supported by MSA.
2876MachineBasicBlock * MipsSETargetLowering::
2877emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{
2878 const TargetInstrInfo *TII =
2879 getTargetMachine().getSubtargetImpl()->getInstrInfo();
2880 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2881 DebugLoc DL = MI->getDebugLoc();
2882 unsigned Fd = MI->getOperand(0).getReg();
2883 unsigned Ws = MI->getOperand(1).getReg();
2884 unsigned Lane = MI->getOperand(2).getImm();
2885
|