1//===- MipsRegisterInfo.td - Mips Register defs -----------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Declarations that describe the MIPS register file
12//===----------------------------------------------------------------------===//
13
14// We have banks of 32 registers each.
15class MipsReg<string n> : Register<n> {
16 field bits<5> Num;
17 let Namespace = "Mips";
18}
19
20// Mips CPU Registers
21class MipsGPRReg<bits<5> num, string n> : MipsReg<n> {
22 let Num = num;
23}
24
25// Mips 32-bit FPU Registers
26class FPR<bits<5> num, string n> : MipsReg<n> {
27 let Num = num;
28}
29
30// Mips 64-bit (aliased) FPU Registers
31class AFPR<bits<5> num, string n, list<Register> aliases> : MipsReg<n> {
32 let Num = num;
33 let Aliases = aliases;
34}
35
36//===----------------------------------------------------------------------===//
37// Registers
38//===----------------------------------------------------------------------===//
39
40let Namespace = "Mips" in {
41
42 // General Purpose Registers
43 def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<[0]>;
44 def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>;
45 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
46 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
47 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[5]>;
48 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
49 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
50 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
51 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
52 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
53 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>;
54 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>;
55 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>;
56 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>;
57 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>;
58 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>;
59 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>;
60 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>;
61 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>;
62 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>;
63 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>;
64 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>;
65 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>;
66 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>;
67 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>;
68 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>;
69 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>;
70 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>;
71 def GP : MipsGPRReg< 28, "GP">, DwarfRegNum<[28]>;
72 def SP : MipsGPRReg< 29, "SP">, DwarfRegNum<[29]>;
73 def FP : MipsGPRReg< 30, "FP">, DwarfRegNum<[30]>;
74 def RA : MipsGPRReg< 31, "RA">, DwarfRegNum<[31]>;
75
76 /// Mips Single point precision FPU Registers
77 def F0 : FPR< 0, "F0">, DwarfRegNum<[32]>;
78 def F1 : FPR< 1, "F1">, DwarfRegNum<[33]>;
79 def F2 : FPR< 2, "F2">, DwarfRegNum<[34]>;
80 def F3 : FPR< 3, "F3">, DwarfRegNum<[35]>;
81 def F4 : FPR< 4, "F4">, DwarfRegNum<[36]>;
82 def F5 : FPR< 5, "F5">, DwarfRegNum<[37]>;
83 def F6 : FPR< 6, "F6">, DwarfRegNum<[38]>;
84 def F7 : FPR< 7, "F7">, DwarfRegNum<[39]>;
85 def F8 : FPR< 8, "F8">, DwarfRegNum<[40]>;
86 def F9 : FPR< 9, "F9">, DwarfRegNum<[41]>;
87 def F10 : FPR<10, "F10">, DwarfRegNum<[42]>;
88 def F11 : FPR<11, "F11">, DwarfRegNum<[43]>;
89 def F12 : FPR<12, "F12">, DwarfRegNum<[44]>;
90 def F13 : FPR<13, "F13">, DwarfRegNum<[45]>;
91 def F14 : FPR<14, "F14">, DwarfRegNum<[46]>;
92 def F15 : FPR<15, "F15">, DwarfRegNum<[47]>;
93 def F16 : FPR<16, "F16">, DwarfRegNum<[48]>;
94 def F17 : FPR<17, "F17">, DwarfRegNum<[49]>;
95 def F18 : FPR<18, "F18">, DwarfRegNum<[50]>;
96 def F19 : FPR<19, "F19">, DwarfRegNum<[51]>;
97 def F20 : FPR<20, "F20">, DwarfRegNum<[52]>;
98 def F21 : FPR<21, "F21">, DwarfRegNum<[53]>;
99 def F22 : FPR<22, "F22">, DwarfRegNum<[54]>;
100 def F23 : FPR<23, "F23">, DwarfRegNum<[55]>;
101 def F24 : FPR<24, "F24">, DwarfRegNum<[56]>;
102 def F25 : FPR<25, "F25">, DwarfRegNum<[57]>;
103 def F26 : FPR<26, "F26">, DwarfRegNum<[58]>;
104 def F27 : FPR<27, "F27">, DwarfRegNum<[59]>;
105 def F28 : FPR<28, "F28">, DwarfRegNum<[60]>;
106 def F29 : FPR<29, "F29">, DwarfRegNum<[61]>;
107 def F30 : FPR<30, "F30">, DwarfRegNum<[62]>;
108 def F31 : FPR<31, "F31">, DwarfRegNum<[63]>;
109
110 /// Mips Double point precision FPU Registers (aliased
111 /// with the single precision to hold 64 bit values)
112 def D0 : AFPR< 0, "F0", [F0, F1]>, DwarfRegNum<[32]>;
113 def D1 : AFPR< 2, "F2", [F2, F3]>, DwarfRegNum<[34]>;
114 def D2 : AFPR< 4, "F4", [F4, F5]>, DwarfRegNum<[36]>;
115 def D3 : AFPR< 6, "F6", [F6, F7]>, DwarfRegNum<[38]>;
116 def D4 : AFPR< 8, "F8", [F8, F9]>, DwarfRegNum<[40]>;
117 def D5 : AFPR<10, "F10", [F10, F11]>, DwarfRegNum<[42]>;
118 def D6 : AFPR<12, "F12", [F12, F13]>, DwarfRegNum<[44]>;
119 def D7 : AFPR<14, "F14", [F14, F15]>, DwarfRegNum<[46]>;
120 def D8 : AFPR<16, "F16", [F16, F17]>, DwarfRegNum<[48]>;
121 def D9 : AFPR<18, "F18", [F18, F19]>, DwarfRegNum<[50]>;
122 def D10 : AFPR<20, "F20", [F20, F21]>, DwarfRegNum<[52]>;
123 def D11 : AFPR<22, "F22", [F22, F23]>, DwarfRegNum<[54]>;
124 def D12 : AFPR<24, "F24", [F24, F25]>, DwarfRegNum<[56]>;
125 def D13 : AFPR<26, "F26", [F26, F27]>, DwarfRegNum<[58]>;
126 def D14 : AFPR<28, "F28", [F28, F29]>, DwarfRegNum<[60]>;
127 def D15 : AFPR<30, "F30", [F30, F31]>, DwarfRegNum<[62]>;
128
129 // Hi/Lo registers
130 def HI : Register<"hi">, DwarfRegNum<[64]>;
131 def LO : Register<"lo">, DwarfRegNum<[65]>;
132
133 // Status flags register
134 def FCR31 : Register<"31">;
135}
136
137//===----------------------------------------------------------------------===//
138// Register Classes
139//===----------------------------------------------------------------------===//
140
141def CPURegs : RegisterClass<"Mips", [i32], 32,
142 // Return Values and Arguments
143 [V0, V1, A0, A1, A2, A3,
144 // Not preserved across procedure calls
145 T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
146 // Callee save
147 S0, S1, S2, S3, S4, S5, S6, S7,
148 // Reserved
149 ZERO, AT, K0, K1, GP, SP, FP, RA]>
150{
151 let MethodProtos = [{
152 iterator allocation_order_end(const MachineFunction &MF) const;
153 }];
154 let MethodBodies = [{
155 CPURegsClass::iterator
156 CPURegsClass::allocation_order_end(const MachineFunction &MF) const {
157 // The last 8 registers on the list above are reserved
158 return end()-8;
159 }
160 }];
161}
162
163// 64bit fp:
164// * FGR64 - 32 64-bit registers
165// * AFGR64 - 16 32-bit even registers (32-bit FP Mode)
166//
167// 32bit fp:
168// * FGR32 - 16 32-bit even registers
169// * FGR32 - 32 32-bit registers (single float only mode)
170def FGR32 : RegisterClass<"Mips", [f32], 32,
171 // Return Values and Arguments
172 [F0, F1, F2, F3, F12, F13, F14, F15,
173 // Not preserved across procedure calls
174 F4, F5, F6, F7, F8, F9, F10, F11, F16, F17, F18, F19,
175 // Callee save
176 F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
177 // Reserved
178 F31]>
179{
180 let MethodProtos = [{
181 iterator allocation_order_begin(const MachineFunction &MF) const;
182 iterator allocation_order_end(const MachineFunction &MF) const;
183 }];
184 let MethodBodies = [{
185
186 static const unsigned MIPS_FGR32[] = {
187 Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F12, Mips::F13,
188 Mips::F14, Mips::F15, Mips::F4, Mips::F5, Mips::F6, Mips::F7,
189 Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F16, Mips::F17,
190 Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23,
191 Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
192 Mips::F30
193 };
194
195 static const unsigned MIPS_SVR4_FGR32[] = {
196 Mips::F0, Mips::F2, Mips::F12, Mips::F14, Mips::F4,
197 Mips::F6, Mips::F8, Mips::F10, Mips::F16, Mips::F18,
198 Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30,
199 };
200
201 FGR32Class::iterator
202 FGR32Class::allocation_order_begin(const MachineFunction &MF) const {
203 const TargetMachine &TM = MF.getTarget();
204 const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>();
205
206 if (Subtarget.isSingleFloat())
207 return MIPS_FGR32;
208 else
209 return MIPS_SVR4_FGR32;
210 }
211
212 FGR32Class::iterator
213 FGR32Class::allocation_order_end(const MachineFunction &MF) const {
214 const TargetMachine &TM = MF.getTarget();
215 const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>();
216
217 if (Subtarget.isSingleFloat())
218 return MIPS_FGR32 + (sizeof(MIPS_FGR32) / sizeof(unsigned));
219 else
220 return MIPS_SVR4_FGR32 + (sizeof(MIPS_SVR4_FGR32) / sizeof(unsigned));
221 }
222 }];
223}
224
225def AFGR64 : RegisterClass<"Mips", [f64], 64,
226 // Return Values and Arguments
227 [D0, D1, D6, D7,
228 // Not preserved across procedure calls
229 D2, D3, D4, D5, D8, D9,
230 // Callee save
231 D10, D11, D12, D13, D14,
232 // Reserved
233 D15]>
234{
235 let MethodProtos = [{
236 iterator allocation_order_end(const MachineFunction &MF) const;
237 }];
238 let MethodBodies = [{
239 AFGR64Class::iterator
240 AFGR64Class::allocation_order_end(const MachineFunction &MF) const {
241 // The last register on the list above is reserved
242 return end()-1;
243 }
244 }];
245}
246
247// Condition Register for floating point operations
248def CCR : RegisterClass<"Mips", [i32], 32, [FCR31]>;
249
250// Hi/Lo Registers
251def HILO : RegisterClass<"Mips", [i32], 32, [HI, LO]>;
252