1//===- MipsRegisterInfo.td - Mips Register defs -----------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Declarations that describe the MIPS register file
12//===----------------------------------------------------------------------===//
13
14// We have banks of 32 registers each.
15class MipsReg<string n> : Register<n> {
16 field bits<5> Num;
17 let Namespace = "Mips";
18}
19
20// Mips CPU Registers
21class MipsGPRReg<bits<5> num, string n> : MipsReg<n> {
22 let Num = num;
23}
24
25// Mips 32-bit FPU Registers
26class FPR<bits<5> num, string n> : MipsReg<n> {
27 let Num = num;
28}
29
30// Mips 64-bit (aliased) FPU Registers
31class AFPR<bits<5> num, string n, list<Register> aliases> : MipsReg<n> {
32 let Num = num;
33 let Aliases = aliases;
34}
35
36//===----------------------------------------------------------------------===//
37// Registers
38//===----------------------------------------------------------------------===//
39
40let Namespace = "Mips" in {
41

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130 def HI : Register<"hi">, DwarfRegNum<[64]>;
131 def LO : Register<"lo">, DwarfRegNum<[65]>;
132
133 // Status flags register
134 def FCR31 : Register<"31">;
135}
136
137//===----------------------------------------------------------------------===//
138// Register Classes
139//===----------------------------------------------------------------------===//
140
141def CPURegs : RegisterClass<"Mips", [i32], 32,
142 // Return Values and Arguments
143 [V0, V1, A0, A1, A2, A3,
144 // Not preserved across procedure calls
145 T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,

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227 [D0, D1, D6, D7,
228 // Not preserved across procedure calls
229 D2, D3, D4, D5, D8, D9,
230 // Callee save
231 D10, D11, D12, D13, D14,
232 // Reserved
233 D15]>
234{
235 let MethodProtos = [{
236 iterator allocation_order_end(const MachineFunction &MF) const;
237 }];
238 let MethodBodies = [{
239 AFGR64Class::iterator
240 AFGR64Class::allocation_order_end(const MachineFunction &MF) const {
241 // The last register on the list above is reserved
242 return end()-1;
243 }
244 }];
245}
246
247// Condition Register for floating point operations
248def CCR : RegisterClass<"Mips", [i32], 32, [FCR31]>;
249
250// Hi/Lo Registers
251def HILO : RegisterClass<"Mips", [i32], 32, [HI, LO]>;
252