1//===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Mips FPU instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Floating Point Instructions 16// ------------------------ 17// * 64bit fp: 18// - 32 64-bit registers (default mode) 19// - 16 even 32-bit registers (32-bit compatible mode) for 20// single and double access. 21// * 32bit fp: 22// - 16 even 32-bit registers - single and double (aliased) 23// - 32 32-bit registers (within single-only mode) 24//===----------------------------------------------------------------------===// 25 26// Floating Point Compare and Branch 27def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>, 28 SDTCisVT<1, i32>, 29 SDTCisVT<2, OtherVT>]>; 30def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>, 31 SDTCisVT<2, i32>]>; 32def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>, 33 SDTCisSameAs<1, 3>]>; 34def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>; 35def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, 36 SDTCisVT<1, i32>, 37 SDTCisSameAs<1, 2>]>; 38def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 39 SDTCisVT<1, f64>, 40 SDTCisVT<2, i32>]>; 41 42def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>; 43def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>; 44def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>; 45def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond, 46 [SDNPHasChain, SDNPOptInGlue]>; 47def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>; 48def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>; 49def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64", 50 SDT_MipsExtractElementF64>; 51 52// Operand for printing out a condition code. 53let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in 54 def condcode : Operand<i32>; 55 56//===----------------------------------------------------------------------===// 57// Feature predicates. 58//===----------------------------------------------------------------------===// 59 60def IsFP64bit : Predicate<"Subtarget->isFP64bit()">, 61 AssemblerPredicate<"FeatureFP64Bit">; 62def NotFP64bit : Predicate<"!Subtarget->isFP64bit()">, 63 AssemblerPredicate<"!FeatureFP64Bit">; 64def IsSingleFloat : Predicate<"Subtarget->isSingleFloat()">, 65 AssemblerPredicate<"FeatureSingleFloat">; 66def IsNotSingleFloat : Predicate<"!Subtarget->isSingleFloat()">, 67 AssemblerPredicate<"!FeatureSingleFloat">; 68 69//===----------------------------------------------------------------------===// 70// Mips FGR size adjectives. 71// They are mutually exclusive. 72//===----------------------------------------------------------------------===// 73 74class FGR_32 { list<Predicate> FGRPredicates = [NotFP64bit]; } 75class FGR_64 { list<Predicate> FGRPredicates = [IsFP64bit]; } 76 77//===----------------------------------------------------------------------===// 78 79// FP immediate patterns. 80def fpimm0 : PatLeaf<(fpimm), [{ 81 return N->isExactlyValue(+0.0); 82}]>; 83 84def fpimm0neg : PatLeaf<(fpimm), [{ 85 return N->isExactlyValue(-0.0); 86}]>; 87 88//===----------------------------------------------------------------------===// 89// Instruction Class Templates 90// 91// A set of multiclasses is used to address the register usage. 92// 93// S32 - single precision in 16 32bit even fp registers 94// single precision in 32 32bit fp registers in SingleOnly mode 95// S64 - single precision in 32 64bit fp registers (In64BitMode) 96// D32 - double precision in 16 32bit even fp registers 97// D64 - double precision in 32 64bit fp registers (In64BitMode) 98// 99// Only S32 and D32 are supported right now. 100//===----------------------------------------------------------------------===// 101 102class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm, 103 SDPatternOperator OpNode= null_frag> : 104 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft), 105 !strconcat(opstr, "\t$fd, $fs, $ft"), 106 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr> { 107 let isCommutable = IsComm; 108} 109 110multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm, 111 SDPatternOperator OpNode = null_frag> { 112 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, 113 AdditionalRequires<[NotFP64bit]>; 114 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, 115 IsComm, OpNode>, 116 AdditionalRequires<[IsFP64bit]> { 117 string DecoderNamespace = "Mips64"; 118 } 119} 120 121class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 122 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 123 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"), 124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, 125 NeverHasSideEffects; 126 127multiclass ABSS_M<string opstr, InstrItinClass Itin, 128 SDPatternOperator OpNode= null_frag> { 129 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>, 130 AdditionalRequires<[NotFP64bit]>; 131 def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, 132 AdditionalRequires<[IsFP64bit]> { 133 string DecoderNamespace = "Mips64"; 134 } 135} 136 137multiclass ROUND_M<string opstr, InstrItinClass Itin> { 138 def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>, 139 AdditionalRequires<[NotFP64bit]>; 140 def _D64 : ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>, 141 AdditionalRequires<[IsFP64bit]> { 142 let DecoderNamespace = "Mips64"; 143 } 144} 145 146class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 147 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 148 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"), 149 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>; 150 151class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 152 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 153 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"), 154 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>; 155 156class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 157 InstrItinClass Itin> : 158 InstSE<(outs DstRC:$fs), (ins DstRC:$fs_in, SrcRC:$rt), 159 !strconcat(opstr, "\t$rt, $fs"), [], Itin, FrmFR, opstr> { 160 // $fs_in is part of a white lie to work around a widespread bug in the FPU 161 // implementation. See expandBuildPairF64 for details. 162 let Constraints = "$fs = $fs_in"; 163} 164 165class LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 166 SDPatternOperator OpNode= null_frag> : 167 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 168 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> { 169 let DecoderMethod = "DecodeFMem"; 170 let mayLoad = 1; 171} 172 173class SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 174 SDPatternOperator OpNode= null_frag> : 175 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 176 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> { 177 let DecoderMethod = "DecodeFMem"; 178 let mayStore = 1; 179} 180 181class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 182 SDPatternOperator OpNode = null_frag> : 183 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 184 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 185 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, 186 FrmFR, opstr>; 187 188class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 189 SDPatternOperator OpNode = null_frag> : 190 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 191 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 192 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))], 193 Itin, FrmFR, opstr>; 194 195class LWXC1_FT<string opstr, RegisterOperand DRC, 196 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 197 InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index), 198 !strconcat(opstr, "\t$fd, ${index}(${base})"), 199 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin, 200 FrmFI, opstr> { 201 let AddedComplexity = 20; 202} 203 204class SWXC1_FT<string opstr, RegisterOperand DRC, 205 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 206 InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index), 207 !strconcat(opstr, "\t$fs, ${index}(${base})"), 208 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin, 209 FrmFI, opstr> { 210 let AddedComplexity = 20; 211} 212 213class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin, 214 SDPatternOperator Op = null_frag, bit DelaySlot = 1> : 215 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset), 216 !strconcat(opstr, "\t$fcc, $offset"), 217 [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin, 218 FrmFI, opstr> { 219 let isBranch = 1; 220 let isTerminator = 1; 221 let hasDelaySlot = DelaySlot; 222 let Defs = [AT]; 223} 224 225class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin, 226 SDPatternOperator OpNode = null_frag> : 227 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond), 228 !strconcat("c.$cond.", typestr, "\t$fs, $ft"), 229 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR, 230 !strconcat("c.$cond.", typestr)> { 231 let Defs = [FCC0]; 232 let isCodeGenOnly = 1; 233} 234 235class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC, 236 InstrItinClass itin> : 237 InstSE<(outs), (ins RC:$fs, RC:$ft), 238 !strconcat("c.", CondStr, ".", Typestr, "\t$fs, $ft"), [], itin, 239 FrmFR>; 240 241multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt, 242 InstrItinClass itin> { 243 def C_F_#NAME : C_COND_FT<"f", TypeStr, RC, itin>, C_COND_FM<fmt, 0>; 244 def C_UN_#NAME : C_COND_FT<"un", TypeStr, RC, itin>, C_COND_FM<fmt, 1>; 245 def C_EQ_#NAME : C_COND_FT<"eq", TypeStr, RC, itin>, C_COND_FM<fmt, 2>; 246 def C_UEQ_#NAME : C_COND_FT<"ueq", TypeStr, RC, itin>, C_COND_FM<fmt, 3>; 247 def C_OLT_#NAME : C_COND_FT<"olt", TypeStr, RC, itin>, C_COND_FM<fmt, 4>; 248 def C_ULT_#NAME : C_COND_FT<"ult", TypeStr, RC, itin>, C_COND_FM<fmt, 5>; 249 def C_OLE_#NAME : C_COND_FT<"ole", TypeStr, RC, itin>, C_COND_FM<fmt, 6>; 250 def C_ULE_#NAME : C_COND_FT<"ule", TypeStr, RC, itin>, C_COND_FM<fmt, 7>; 251 def C_SF_#NAME : C_COND_FT<"sf", TypeStr, RC, itin>, C_COND_FM<fmt, 8>; 252 def C_NGLE_#NAME : C_COND_FT<"ngle", TypeStr, RC, itin>, C_COND_FM<fmt, 9>; 253 def C_SEQ_#NAME : C_COND_FT<"seq", TypeStr, RC, itin>, C_COND_FM<fmt, 10>; 254 def C_NGL_#NAME : C_COND_FT<"ngl", TypeStr, RC, itin>, C_COND_FM<fmt, 11>; 255 def C_LT_#NAME : C_COND_FT<"lt", TypeStr, RC, itin>, C_COND_FM<fmt, 12>; 256 def C_NGE_#NAME : C_COND_FT<"nge", TypeStr, RC, itin>, C_COND_FM<fmt, 13>; 257 def C_LE_#NAME : C_COND_FT<"le", TypeStr, RC, itin>, C_COND_FM<fmt, 14>; 258 def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC, itin>, C_COND_FM<fmt, 15>; 259} 260 261defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6; 262defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, 263 AdditionalRequires<[NotFP64bit]>; 264let DecoderNamespace = "Mips64" in 265defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, 266 AdditionalRequires<[IsFP64bit]>; 267 268//===----------------------------------------------------------------------===// 269// Floating Point Instructions 270//===----------------------------------------------------------------------===// 271def ROUND_W_S : MMRel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>, 272 ABSS_FM<0xc, 16>, ISA_MIPS2; 273def TRUNC_W_S : MMRel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>, 274 ABSS_FM<0xd, 16>, ISA_MIPS2; 275def CEIL_W_S : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, 276 ABSS_FM<0xe, 16>, ISA_MIPS2; 277def FLOOR_W_S : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>, 278 ABSS_FM<0xf, 16>, ISA_MIPS2; 279def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, 280 ABSS_FM<0x24, 16>; 281 282defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2; 283defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2; 284defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2; 285defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2; 286defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>; 287 288let DecoderNamespace = "Mips64" in { 289 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>, 290 ABSS_FM<0x8, 16>, FGR_64; 291 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>, 292 ABSS_FM<0x8, 17>, FGR_64; 293 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>, 294 ABSS_FM<0x9, 16>, FGR_64; 295 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>, 296 ABSS_FM<0x9, 17>, FGR_64; 297 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, II_CEIL>, 298 ABSS_FM<0xa, 16>, FGR_64; 299 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, II_CEIL>, 300 ABSS_FM<0xa, 17>, FGR_64; 301 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>, 302 ABSS_FM<0xb, 16>, FGR_64; 303 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>, 304 ABSS_FM<0xb, 17>, FGR_64; 305} 306 307def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>, 308 ABSS_FM<0x20, 20>; 309def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, 310 ABSS_FM<0x25, 16>, INSN_MIPS3_32R2; 311def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, 312 ABSS_FM<0x25, 17>, INSN_MIPS3_32R2; 313 314def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, 315 ABSS_FM<0x20, 17>, FGR_32; 316def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, 317 ABSS_FM<0x21, 20>, FGR_32; 318def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, 319 ABSS_FM<0x21, 16>, FGR_32; 320 321let DecoderNamespace = "Mips64" in { 322 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>, 323 ABSS_FM<0x20, 17>, FGR_64; 324 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>, 325 ABSS_FM<0x20, 21>, FGR_64; 326 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>, 327 ABSS_FM<0x21, 20>, FGR_64; 328 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>, 329 ABSS_FM<0x21, 16>, FGR_64; 330 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>, 331 ABSS_FM<0x21, 21>, FGR_64; 332} 333 334let isPseudo = 1, isCodeGenOnly = 1 in { 335 def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>; 336 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>; 337 def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>; 338 def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>; 339 def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>; 340} 341 342def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>, 343 ABSS_FM<0x5, 16>; 344def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, 345 ABSS_FM<0x7, 16>; 346defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>; 347defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>; 348 349def FSQRT_S : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, fsqrt>, 350 ABSS_FM<0x4, 16>, ISA_MIPS2; 351defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2; 352 353// The odd-numbered registers are only referenced when doing loads, 354// stores, and moves between floating-point and integer registers. 355// When defining instructions, we reference all 32-bit registers, 356// regardless of register aliasing. 357 358/// Move Control Registers From/To CPU Registers 359def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>; 360def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>; 361def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, 362 bitconvert>, MFC1_FM<0>; 363def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, 364 bitconvert>, MFC1_FM<4>; 365def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, 366 MFC1_FM<3>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>; 367def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>, 368 MFC1_FM<3>, ISA_MIPS32R2, AdditionalRequires<[IsFP64bit]> { 369 let DecoderNamespace = "Mips64"; 370} 371def MTHC1_D32 : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, 372 MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>; 373def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>, 374 MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[IsFP64bit]> { 375 let DecoderNamespace = "Mips64"; 376} 377def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1, 378 bitconvert>, MFC1_FM<1>, ISA_MIPS3; 379def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1, 380 bitconvert>, MFC1_FM<5>, ISA_MIPS3; 381 382def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, 383 ABSS_FM<0x6, 16>; 384def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>, 385 ABSS_FM<0x6, 17>, AdditionalRequires<[NotFP64bit]>; 386def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>, 387 ABSS_FM<0x6, 17>, AdditionalRequires<[IsFP64bit]> { 388 let DecoderNamespace = "Mips64"; 389} 390 391/// Floating Point Memory Instructions 392def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM<0x31>; 393def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM<0x39>; 394 395let DecoderNamespace = "Mips64" in { 396 def LDC164 : LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>, LW_FM<0x35>, ISA_MIPS2, 397 FGR_64; 398 def SDC164 : SW_FT<"sdc1", FGR64Opnd, II_SDC1, store>, LW_FM<0x3d>, ISA_MIPS2, 399 FGR_64; 400} 401 402def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>, 403 ISA_MIPS2, FGR_32; 404def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>, 405 ISA_MIPS2, FGR_32; 406 407// Indexed loads and stores. 408// Base register + offset register addressing mode (indicated by "x" in the 409// instruction mnemonic) is disallowed under NaCl. 410let AdditionalPredicates = [IsNotNaCl] in { 411 def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>, 412 INSN_MIPS4_32R2_NOT_32R6_64R6; 413 def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>, 414 INSN_MIPS4_32R2_NOT_32R6_64R6; 415} 416 417let AdditionalPredicates = [NotInMicroMips, IsNotNaCl] in { 418 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>, 419 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 420 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>, 421 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 422} 423 424let DecoderNamespace="Mips64" in { 425 def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>, 426 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 427 def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>, 428 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 429} 430 431// Load/store doubleword indexed unaligned. 432let AdditionalPredicates = [IsNotNaCl] in { 433 def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>, 434 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32; 435 def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>, 436 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32; 437} 438 439let DecoderNamespace="Mips64" in { 440 def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>, 441 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64; 442 def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>, 443 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64; 444} 445 446/// Floating-point Aritmetic 447def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, 448 ADDS_FM<0x00, 16>; 449defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>; 450def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>, 451 ADDS_FM<0x03, 16>; 452defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>; 453def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>, 454 ADDS_FM<0x02, 16>; 455defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>; 456def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, 457 ADDS_FM<0x01, 16>; 458defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>; 459 460def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
| 1//===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Mips FPU instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Floating Point Instructions 16// ------------------------ 17// * 64bit fp: 18// - 32 64-bit registers (default mode) 19// - 16 even 32-bit registers (32-bit compatible mode) for 20// single and double access. 21// * 32bit fp: 22// - 16 even 32-bit registers - single and double (aliased) 23// - 32 32-bit registers (within single-only mode) 24//===----------------------------------------------------------------------===// 25 26// Floating Point Compare and Branch 27def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>, 28 SDTCisVT<1, i32>, 29 SDTCisVT<2, OtherVT>]>; 30def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>, 31 SDTCisVT<2, i32>]>; 32def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>, 33 SDTCisSameAs<1, 3>]>; 34def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>; 35def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, 36 SDTCisVT<1, i32>, 37 SDTCisSameAs<1, 2>]>; 38def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 39 SDTCisVT<1, f64>, 40 SDTCisVT<2, i32>]>; 41 42def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>; 43def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>; 44def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>; 45def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond, 46 [SDNPHasChain, SDNPOptInGlue]>; 47def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>; 48def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>; 49def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64", 50 SDT_MipsExtractElementF64>; 51 52// Operand for printing out a condition code. 53let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in 54 def condcode : Operand<i32>; 55 56//===----------------------------------------------------------------------===// 57// Feature predicates. 58//===----------------------------------------------------------------------===// 59 60def IsFP64bit : Predicate<"Subtarget->isFP64bit()">, 61 AssemblerPredicate<"FeatureFP64Bit">; 62def NotFP64bit : Predicate<"!Subtarget->isFP64bit()">, 63 AssemblerPredicate<"!FeatureFP64Bit">; 64def IsSingleFloat : Predicate<"Subtarget->isSingleFloat()">, 65 AssemblerPredicate<"FeatureSingleFloat">; 66def IsNotSingleFloat : Predicate<"!Subtarget->isSingleFloat()">, 67 AssemblerPredicate<"!FeatureSingleFloat">; 68 69//===----------------------------------------------------------------------===// 70// Mips FGR size adjectives. 71// They are mutually exclusive. 72//===----------------------------------------------------------------------===// 73 74class FGR_32 { list<Predicate> FGRPredicates = [NotFP64bit]; } 75class FGR_64 { list<Predicate> FGRPredicates = [IsFP64bit]; } 76 77//===----------------------------------------------------------------------===// 78 79// FP immediate patterns. 80def fpimm0 : PatLeaf<(fpimm), [{ 81 return N->isExactlyValue(+0.0); 82}]>; 83 84def fpimm0neg : PatLeaf<(fpimm), [{ 85 return N->isExactlyValue(-0.0); 86}]>; 87 88//===----------------------------------------------------------------------===// 89// Instruction Class Templates 90// 91// A set of multiclasses is used to address the register usage. 92// 93// S32 - single precision in 16 32bit even fp registers 94// single precision in 32 32bit fp registers in SingleOnly mode 95// S64 - single precision in 32 64bit fp registers (In64BitMode) 96// D32 - double precision in 16 32bit even fp registers 97// D64 - double precision in 32 64bit fp registers (In64BitMode) 98// 99// Only S32 and D32 are supported right now. 100//===----------------------------------------------------------------------===// 101 102class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm, 103 SDPatternOperator OpNode= null_frag> : 104 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft), 105 !strconcat(opstr, "\t$fd, $fs, $ft"), 106 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr> { 107 let isCommutable = IsComm; 108} 109 110multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm, 111 SDPatternOperator OpNode = null_frag> { 112 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, 113 AdditionalRequires<[NotFP64bit]>; 114 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, 115 IsComm, OpNode>, 116 AdditionalRequires<[IsFP64bit]> { 117 string DecoderNamespace = "Mips64"; 118 } 119} 120 121class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 122 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 123 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"), 124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, 125 NeverHasSideEffects; 126 127multiclass ABSS_M<string opstr, InstrItinClass Itin, 128 SDPatternOperator OpNode= null_frag> { 129 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>, 130 AdditionalRequires<[NotFP64bit]>; 131 def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, 132 AdditionalRequires<[IsFP64bit]> { 133 string DecoderNamespace = "Mips64"; 134 } 135} 136 137multiclass ROUND_M<string opstr, InstrItinClass Itin> { 138 def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>, 139 AdditionalRequires<[NotFP64bit]>; 140 def _D64 : ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>, 141 AdditionalRequires<[IsFP64bit]> { 142 let DecoderNamespace = "Mips64"; 143 } 144} 145 146class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 147 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 148 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"), 149 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>; 150 151class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 152 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 153 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"), 154 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>; 155 156class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 157 InstrItinClass Itin> : 158 InstSE<(outs DstRC:$fs), (ins DstRC:$fs_in, SrcRC:$rt), 159 !strconcat(opstr, "\t$rt, $fs"), [], Itin, FrmFR, opstr> { 160 // $fs_in is part of a white lie to work around a widespread bug in the FPU 161 // implementation. See expandBuildPairF64 for details. 162 let Constraints = "$fs = $fs_in"; 163} 164 165class LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 166 SDPatternOperator OpNode= null_frag> : 167 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 168 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> { 169 let DecoderMethod = "DecodeFMem"; 170 let mayLoad = 1; 171} 172 173class SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 174 SDPatternOperator OpNode= null_frag> : 175 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 176 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> { 177 let DecoderMethod = "DecodeFMem"; 178 let mayStore = 1; 179} 180 181class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 182 SDPatternOperator OpNode = null_frag> : 183 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 184 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 185 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, 186 FrmFR, opstr>; 187 188class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 189 SDPatternOperator OpNode = null_frag> : 190 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 191 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 192 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))], 193 Itin, FrmFR, opstr>; 194 195class LWXC1_FT<string opstr, RegisterOperand DRC, 196 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 197 InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index), 198 !strconcat(opstr, "\t$fd, ${index}(${base})"), 199 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin, 200 FrmFI, opstr> { 201 let AddedComplexity = 20; 202} 203 204class SWXC1_FT<string opstr, RegisterOperand DRC, 205 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 206 InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index), 207 !strconcat(opstr, "\t$fs, ${index}(${base})"), 208 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin, 209 FrmFI, opstr> { 210 let AddedComplexity = 20; 211} 212 213class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin, 214 SDPatternOperator Op = null_frag, bit DelaySlot = 1> : 215 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset), 216 !strconcat(opstr, "\t$fcc, $offset"), 217 [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin, 218 FrmFI, opstr> { 219 let isBranch = 1; 220 let isTerminator = 1; 221 let hasDelaySlot = DelaySlot; 222 let Defs = [AT]; 223} 224 225class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin, 226 SDPatternOperator OpNode = null_frag> : 227 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond), 228 !strconcat("c.$cond.", typestr, "\t$fs, $ft"), 229 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR, 230 !strconcat("c.$cond.", typestr)> { 231 let Defs = [FCC0]; 232 let isCodeGenOnly = 1; 233} 234 235class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC, 236 InstrItinClass itin> : 237 InstSE<(outs), (ins RC:$fs, RC:$ft), 238 !strconcat("c.", CondStr, ".", Typestr, "\t$fs, $ft"), [], itin, 239 FrmFR>; 240 241multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt, 242 InstrItinClass itin> { 243 def C_F_#NAME : C_COND_FT<"f", TypeStr, RC, itin>, C_COND_FM<fmt, 0>; 244 def C_UN_#NAME : C_COND_FT<"un", TypeStr, RC, itin>, C_COND_FM<fmt, 1>; 245 def C_EQ_#NAME : C_COND_FT<"eq", TypeStr, RC, itin>, C_COND_FM<fmt, 2>; 246 def C_UEQ_#NAME : C_COND_FT<"ueq", TypeStr, RC, itin>, C_COND_FM<fmt, 3>; 247 def C_OLT_#NAME : C_COND_FT<"olt", TypeStr, RC, itin>, C_COND_FM<fmt, 4>; 248 def C_ULT_#NAME : C_COND_FT<"ult", TypeStr, RC, itin>, C_COND_FM<fmt, 5>; 249 def C_OLE_#NAME : C_COND_FT<"ole", TypeStr, RC, itin>, C_COND_FM<fmt, 6>; 250 def C_ULE_#NAME : C_COND_FT<"ule", TypeStr, RC, itin>, C_COND_FM<fmt, 7>; 251 def C_SF_#NAME : C_COND_FT<"sf", TypeStr, RC, itin>, C_COND_FM<fmt, 8>; 252 def C_NGLE_#NAME : C_COND_FT<"ngle", TypeStr, RC, itin>, C_COND_FM<fmt, 9>; 253 def C_SEQ_#NAME : C_COND_FT<"seq", TypeStr, RC, itin>, C_COND_FM<fmt, 10>; 254 def C_NGL_#NAME : C_COND_FT<"ngl", TypeStr, RC, itin>, C_COND_FM<fmt, 11>; 255 def C_LT_#NAME : C_COND_FT<"lt", TypeStr, RC, itin>, C_COND_FM<fmt, 12>; 256 def C_NGE_#NAME : C_COND_FT<"nge", TypeStr, RC, itin>, C_COND_FM<fmt, 13>; 257 def C_LE_#NAME : C_COND_FT<"le", TypeStr, RC, itin>, C_COND_FM<fmt, 14>; 258 def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC, itin>, C_COND_FM<fmt, 15>; 259} 260 261defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6; 262defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, 263 AdditionalRequires<[NotFP64bit]>; 264let DecoderNamespace = "Mips64" in 265defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, 266 AdditionalRequires<[IsFP64bit]>; 267 268//===----------------------------------------------------------------------===// 269// Floating Point Instructions 270//===----------------------------------------------------------------------===// 271def ROUND_W_S : MMRel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>, 272 ABSS_FM<0xc, 16>, ISA_MIPS2; 273def TRUNC_W_S : MMRel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>, 274 ABSS_FM<0xd, 16>, ISA_MIPS2; 275def CEIL_W_S : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, 276 ABSS_FM<0xe, 16>, ISA_MIPS2; 277def FLOOR_W_S : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>, 278 ABSS_FM<0xf, 16>, ISA_MIPS2; 279def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, 280 ABSS_FM<0x24, 16>; 281 282defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2; 283defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2; 284defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2; 285defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2; 286defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>; 287 288let DecoderNamespace = "Mips64" in { 289 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>, 290 ABSS_FM<0x8, 16>, FGR_64; 291 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>, 292 ABSS_FM<0x8, 17>, FGR_64; 293 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>, 294 ABSS_FM<0x9, 16>, FGR_64; 295 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>, 296 ABSS_FM<0x9, 17>, FGR_64; 297 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, II_CEIL>, 298 ABSS_FM<0xa, 16>, FGR_64; 299 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, II_CEIL>, 300 ABSS_FM<0xa, 17>, FGR_64; 301 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>, 302 ABSS_FM<0xb, 16>, FGR_64; 303 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>, 304 ABSS_FM<0xb, 17>, FGR_64; 305} 306 307def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>, 308 ABSS_FM<0x20, 20>; 309def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, 310 ABSS_FM<0x25, 16>, INSN_MIPS3_32R2; 311def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, 312 ABSS_FM<0x25, 17>, INSN_MIPS3_32R2; 313 314def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, 315 ABSS_FM<0x20, 17>, FGR_32; 316def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, 317 ABSS_FM<0x21, 20>, FGR_32; 318def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, 319 ABSS_FM<0x21, 16>, FGR_32; 320 321let DecoderNamespace = "Mips64" in { 322 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>, 323 ABSS_FM<0x20, 17>, FGR_64; 324 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>, 325 ABSS_FM<0x20, 21>, FGR_64; 326 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>, 327 ABSS_FM<0x21, 20>, FGR_64; 328 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>, 329 ABSS_FM<0x21, 16>, FGR_64; 330 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>, 331 ABSS_FM<0x21, 21>, FGR_64; 332} 333 334let isPseudo = 1, isCodeGenOnly = 1 in { 335 def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>; 336 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>; 337 def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>; 338 def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>; 339 def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>; 340} 341 342def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>, 343 ABSS_FM<0x5, 16>; 344def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, 345 ABSS_FM<0x7, 16>; 346defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>; 347defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>; 348 349def FSQRT_S : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, fsqrt>, 350 ABSS_FM<0x4, 16>, ISA_MIPS2; 351defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2; 352 353// The odd-numbered registers are only referenced when doing loads, 354// stores, and moves between floating-point and integer registers. 355// When defining instructions, we reference all 32-bit registers, 356// regardless of register aliasing. 357 358/// Move Control Registers From/To CPU Registers 359def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>; 360def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>; 361def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, 362 bitconvert>, MFC1_FM<0>; 363def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, 364 bitconvert>, MFC1_FM<4>; 365def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, 366 MFC1_FM<3>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>; 367def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>, 368 MFC1_FM<3>, ISA_MIPS32R2, AdditionalRequires<[IsFP64bit]> { 369 let DecoderNamespace = "Mips64"; 370} 371def MTHC1_D32 : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, 372 MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>; 373def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>, 374 MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[IsFP64bit]> { 375 let DecoderNamespace = "Mips64"; 376} 377def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1, 378 bitconvert>, MFC1_FM<1>, ISA_MIPS3; 379def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1, 380 bitconvert>, MFC1_FM<5>, ISA_MIPS3; 381 382def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, 383 ABSS_FM<0x6, 16>; 384def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>, 385 ABSS_FM<0x6, 17>, AdditionalRequires<[NotFP64bit]>; 386def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>, 387 ABSS_FM<0x6, 17>, AdditionalRequires<[IsFP64bit]> { 388 let DecoderNamespace = "Mips64"; 389} 390 391/// Floating Point Memory Instructions 392def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM<0x31>; 393def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM<0x39>; 394 395let DecoderNamespace = "Mips64" in { 396 def LDC164 : LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>, LW_FM<0x35>, ISA_MIPS2, 397 FGR_64; 398 def SDC164 : SW_FT<"sdc1", FGR64Opnd, II_SDC1, store>, LW_FM<0x3d>, ISA_MIPS2, 399 FGR_64; 400} 401 402def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>, 403 ISA_MIPS2, FGR_32; 404def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>, 405 ISA_MIPS2, FGR_32; 406 407// Indexed loads and stores. 408// Base register + offset register addressing mode (indicated by "x" in the 409// instruction mnemonic) is disallowed under NaCl. 410let AdditionalPredicates = [IsNotNaCl] in { 411 def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>, 412 INSN_MIPS4_32R2_NOT_32R6_64R6; 413 def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>, 414 INSN_MIPS4_32R2_NOT_32R6_64R6; 415} 416 417let AdditionalPredicates = [NotInMicroMips, IsNotNaCl] in { 418 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>, 419 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 420 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>, 421 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 422} 423 424let DecoderNamespace="Mips64" in { 425 def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>, 426 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 427 def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>, 428 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 429} 430 431// Load/store doubleword indexed unaligned. 432let AdditionalPredicates = [IsNotNaCl] in { 433 def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>, 434 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32; 435 def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>, 436 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32; 437} 438 439let DecoderNamespace="Mips64" in { 440 def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>, 441 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64; 442 def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>, 443 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64; 444} 445 446/// Floating-point Aritmetic 447def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, 448 ADDS_FM<0x00, 16>; 449defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>; 450def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>, 451 ADDS_FM<0x03, 16>; 452defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>; 453def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>, 454 ADDS_FM<0x02, 16>; 455defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>; 456def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, 457 ADDS_FM<0x01, 16>; 458defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>; 459 460def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
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