621a622,648
> static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG,
> TargetLowering::DAGCombinerInfo &DCI,
> const MipsSubtarget &Subtarget) {
> if (DCI.isBeforeLegalizeOps())
> return SDValue();
>
> SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2);
>
> ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse);
> if (!FalseC || FalseC->getZExtValue())
> return SDValue();
>
> // Since RHS (False) is 0, we swap the order of the True/False operands
> // (obviously also inverting the condition) so that we can
> // take advantage of conditional moves using the $0 register.
> // Example:
> // return (a != 0) ? x : 0;
> // load $reg, x
> // movz $reg, $0, a
> unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F :
> MipsISD::CMovFP_T;
>
> SDValue FCC = N->getOperand(1), Glue = N->getOperand(3);
> return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(),
> ValueIfFalse, FCC, ValueIfTrue, Glue);
> }
>
754a782,784
> case MipsISD::CMovFP_F:
> case MipsISD::CMovFP_T:
> return performCMovFPCombine(N, DAG, DCI, Subtarget);
2042c2072
< DAG.getConstant(0x20, MVT::i32));
---
> DAG.getConstant(VT.getSizeInBits(), MVT::i32));
2081,2082c2111,2113
< DAG.getConstant(0x20, MVT::i32));
< SDValue Shift31 = DAG.getNode(ISD::SRA, DL, VT, Hi, DAG.getConstant(31, VT));
---
> DAG.getConstant(VT.getSizeInBits(), MVT::i32));
> SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
> DAG.getConstant(VT.getSizeInBits() - 1, VT));
2085c2116
< IsSRA ? Shift31 : DAG.getConstant(0, VT), ShiftRightHi);
---
> IsSRA ? Ext : DAG.getConstant(0, VT), ShiftRightHi);
2905,2906c2936,2939
< std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx);
< CurArgIdx = Ins[i].OrigArgIndex;
---
> if (Ins[i].isOrigArg()) {
> std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx);
> CurArgIdx = Ins[i].getOrigArgIndex();
> }
2911a2945
> assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit");
3031a3066,3074
> bool
> MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
> if (Subtarget.hasMips3() && Subtarget.abiUsesSoftFloat()) {
> if (Type == MVT::i32)
> return true;
> }
> return IsSigned;
> }
>
> static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG,
> TargetLowering::DAGCombinerInfo &DCI,
> const MipsSubtarget &Subtarget) {
> if (DCI.isBeforeLegalizeOps())
> return SDValue();
>
> SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2);
>
> ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse);
> if (!FalseC || FalseC->getZExtValue())
> return SDValue();
>
> // Since RHS (False) is 0, we swap the order of the True/False operands
> // (obviously also inverting the condition) so that we can
> // take advantage of conditional moves using the $0 register.
> // Example:
> // return (a != 0) ? x : 0;
> // load $reg, x
> // movz $reg, $0, a
> unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F :
> MipsISD::CMovFP_T;
>
> SDValue FCC = N->getOperand(1), Glue = N->getOperand(3);
> return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(),
> ValueIfFalse, FCC, ValueIfTrue, Glue);
> }
>
754a782,784
> case MipsISD::CMovFP_F:
> case MipsISD::CMovFP_T:
> return performCMovFPCombine(N, DAG, DCI, Subtarget);
2042c2072
< DAG.getConstant(0x20, MVT::i32));
---
> DAG.getConstant(VT.getSizeInBits(), MVT::i32));
2081,2082c2111,2113
< DAG.getConstant(0x20, MVT::i32));
< SDValue Shift31 = DAG.getNode(ISD::SRA, DL, VT, Hi, DAG.getConstant(31, VT));
---
> DAG.getConstant(VT.getSizeInBits(), MVT::i32));
> SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
> DAG.getConstant(VT.getSizeInBits() - 1, VT));
2085c2116
< IsSRA ? Shift31 : DAG.getConstant(0, VT), ShiftRightHi);
---
> IsSRA ? Ext : DAG.getConstant(0, VT), ShiftRightHi);
2905,2906c2936,2939
< std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx);
< CurArgIdx = Ins[i].OrigArgIndex;
---
> if (Ins[i].isOrigArg()) {
> std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx);
> CurArgIdx = Ins[i].getOrigArgIndex();
> }
2911a2945
> assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit");
3031a3066,3074
> bool
> MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
> if (Subtarget.hasMips3() && Subtarget.abiUsesSoftFloat()) {
> if (Type == MVT::i32)
> return true;
> }
> return IsSigned;
> }
>