1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

--- 605 unchanged lines hidden (view full) ---

614 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
615 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
616 }
617
618 // Couldn't optimize.
619 return SDValue();
620}
621
622static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
623 TargetLowering::DAGCombinerInfo &DCI,
624 const MipsSubtarget &Subtarget) {
625 // Pattern match EXT.
626 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
627 // => ext $dst, $src, size, pos
628 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
629 return SDValue();

--- 117 unchanged lines hidden (view full) ---

747
748 switch (Opc) {
749 default: break;
750 case ISD::SDIVREM:
751 case ISD::UDIVREM:
752 return performDivRemCombine(N, DAG, DCI, Subtarget);
753 case ISD::SELECT:
754 return performSELECTCombine(N, DAG, DCI, Subtarget);
755 case ISD::AND:
756 return performANDCombine(N, DAG, DCI, Subtarget);
757 case ISD::OR:
758 return performORCombine(N, DAG, DCI, Subtarget);
759 case ISD::ADD:
760 return performADDCombine(N, DAG, DCI, Subtarget);
761 }
762

--- 1271 unchanged lines hidden (view full) ---

2034 DAG.getConstant(-1, MVT::i32));
2035 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2036 DAG.getConstant(1, VT));
2037 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
2038 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2039 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2040 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
2041 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2042 DAG.getConstant(0x20, MVT::i32));
2043 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2044 DAG.getConstant(0, VT), ShiftLeftLo);
2045 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
2046
2047 SDValue Ops[2] = {Lo, Hi};
2048 return DAG.getMergeValues(Ops, DL);
2049}
2050

--- 22 unchanged lines hidden (view full) ---

2073 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
2074 DAG.getConstant(1, VT));
2075 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
2076 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2077 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2078 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
2079 DL, VT, Hi, Shamt);
2080 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2081 DAG.getConstant(0x20, MVT::i32));
2082 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, VT, Hi, DAG.getConstant(31, VT));
2083 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
2084 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2085 IsSRA ? Shift31 : DAG.getConstant(0, VT), ShiftRightHi);
2086
2087 SDValue Ops[2] = {Lo, Hi};
2088 return DAG.getMergeValues(Ops, DL);
2089}
2090
2091static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2092 SDValue Chain, SDValue Src, unsigned Offset) {
2093 SDValue Ptr = LD->getBasePtr();

--- 803 unchanged lines hidden (view full) ---

2897 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
2898 CCInfo.getInRegsParamsCount() > 0);
2899
2900 unsigned CurArgIdx = 0;
2901 CCInfo.rewindByValRegsInfo();
2902
2903 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2904 CCValAssign &VA = ArgLocs[i];
2905 std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx);
2906 CurArgIdx = Ins[i].OrigArgIndex;
2907 EVT ValVT = VA.getValVT();
2908 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2909 bool IsRegLoc = VA.isRegLoc();
2910
2911 if (Flags.isByVal()) {
2912 unsigned FirstByValReg, LastByValReg;
2913 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
2914 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
2915
2916 assert(Flags.getByValSize() &&
2917 "ByVal args of size 0 should have been ignored by front-end.");
2918 assert(ByValIdx < CCInfo.getInRegsParamsCount());
2919 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,

--- 104 unchanged lines hidden (view full) ---

3024 MachineFunction &MF, bool IsVarArg,
3025 const SmallVectorImpl<ISD::OutputArg> &Outs,
3026 LLVMContext &Context) const {
3027 SmallVector<CCValAssign, 16> RVLocs;
3028 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3029 return CCInfo.CheckReturn(Outs, RetCC_Mips);
3030}
3031
3032SDValue
3033MipsTargetLowering::LowerReturn(SDValue Chain,
3034 CallingConv::ID CallConv, bool IsVarArg,
3035 const SmallVectorImpl<ISD::OutputArg> &Outs,
3036 const SmallVectorImpl<SDValue> &OutVals,
3037 SDLoc DL, SelectionDAG &DAG) const {
3038 // CCValAssign - represent the assignment of
3039 // the return value to a location

--- 826 unchanged lines hidden ---