1//===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// This describes the calling conventions for Mips architecture.
10//===----------------------------------------------------------------------===//
11
12/// CCIfSubtarget - Match if the current subtarget has a feature F.
13class CCIfSubtarget<string F, CCAction A, string Invert = "">
14 : CCIf<!strconcat(Invert,
15 "static_cast<const MipsSubtarget&>"
16 "(State.getMachineFunction().getSubtarget()).",
17 F),
18 A>;
19
20// The inverse of CCIfSubtarget
21class CCIfSubtargetNot<string F, CCAction A> : CCIfSubtarget<F, A, "!">;
22
23/// Match if the original argument (before lowering) was a float.
24/// For example, this is true for i32's that were lowered from soft-float.
25class CCIfOrigArgWasNotFloat<CCAction A>
26 : CCIf<"!static_cast<MipsCCState *>(&State)->WasOriginalArgFloat(ValNo)",
27 A>;
28
29/// Match if the original argument (before lowering) was a 128-bit float (i.e.
30/// long double).
31class CCIfOrigArgWasF128<CCAction A>
32 : CCIf<"static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)", A>;
33
34/// Match if this specific argument is a vararg.
35/// This is slightly different fro CCIfIsVarArg which matches if any argument is
36/// a vararg.
37class CCIfArgIsVarArg<CCAction A>
38 : CCIf<"!static_cast<MipsCCState *>(&State)->IsCallOperandFixed(ValNo)", A>;
39
40
41/// Match if the special calling conv is the specified value.
42class CCIfSpecialCallingConv<string CC, CCAction A>
43 : CCIf<"static_cast<MipsCCState *>(&State)->getSpecialCallingConv() == "
44 "MipsCCState::" # CC, A>;
45
46// For soft-float, f128 values are returned in A0_64 rather than V1_64.
47def RetCC_F128SoftFloat : CallingConv<[
48 CCAssignToReg<[V0_64, A0_64]>
49]>;
50
51// For hard-float, f128 values are returned as a pair of f64's rather than a
52// pair of i64's.
53def RetCC_F128HardFloat : CallingConv<[
54 CCBitConvertToType<f64>,
55
56 // Contrary to the ABI documentation, a struct containing a long double is
57 // returned in $f0, and $f1 instead of the usual $f0, and $f2. This is to
58 // match the de facto ABI as implemented by GCC.
59 CCIfInReg<CCAssignToReg<[D0_64, D1_64]>>,
60
61 CCAssignToReg<[D0_64, D2_64]>
62]>;
63
64// Handle F128 specially since we can't identify the original type during the
65// tablegen-erated code.
66def RetCC_F128 : CallingConv<[
67 CCIfSubtarget<"abiUsesSoftFloat()",
68 CCIfType<[i64], CCDelegateTo<RetCC_F128SoftFloat>>>,
69 CCIfSubtargetNot<"abiUsesSoftFloat()",
70 CCIfType<[i64], CCDelegateTo<RetCC_F128HardFloat>>>
71]>;
72
73//===----------------------------------------------------------------------===//
74// Mips O32 Calling Convention
75//===----------------------------------------------------------------------===//
76
77def CC_MipsO32 : CallingConv<[
78 // Promote i8/i16 arguments to i32.
79 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
80
81 // Integer values get stored in stack slots that are 4 bytes in
82 // size and 4-byte aligned.
83 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
84
85 // Integer values get stored in stack slots that are 8 bytes in
86 // size and 8-byte aligned.
87 CCIfType<[f64], CCAssignToStack<8, 8>>
88]>;
89
90// Only the return rules are defined here for O32. The rules for argument
91// passing are defined in MipsISelLowering.cpp.
92def RetCC_MipsO32 : CallingConv<[
93 // i32 are returned in registers V0, V1, A0, A1
94 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>,
95
96 // f32 are returned in registers F0, F2
97 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
98
99 // f64 arguments are returned in D0_64 and D2_64 in FP64bit mode or
100 // in D0 and D1 in FP32bit mode.
101 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D2_64]>>>,
102 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()", CCAssignToReg<[D0, D1]>>>
103]>;
104
105def CC_MipsO32_FP32 : CustomCallingConv;
106def CC_MipsO32_FP64 : CustomCallingConv;
107
108def CC_MipsO32_FP : CallingConv<[
109 CCIfSubtargetNot<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP32>>,
110 CCIfSubtarget<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP64>>
111]>;
112
113//===----------------------------------------------------------------------===//
114// Mips N32/64 Calling Convention
115//===----------------------------------------------------------------------===//
116
117def CC_MipsN_SoftFloat : CallingConv<[
118 CCAssignToRegWithShadow<[A0, A1, A2, A3,
119 T0, T1, T2, T3],
120 [D12_64, D13_64, D14_64, D15_64,
121 D16_64, D17_64, D18_64, D19_64]>,
122 CCAssignToStack<4, 8>
123]>;
124
125def CC_MipsN : CallingConv<[
| 1//===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// This describes the calling conventions for Mips architecture.
10//===----------------------------------------------------------------------===//
11
12/// CCIfSubtarget - Match if the current subtarget has a feature F.
13class CCIfSubtarget<string F, CCAction A, string Invert = "">
14 : CCIf<!strconcat(Invert,
15 "static_cast<const MipsSubtarget&>"
16 "(State.getMachineFunction().getSubtarget()).",
17 F),
18 A>;
19
20// The inverse of CCIfSubtarget
21class CCIfSubtargetNot<string F, CCAction A> : CCIfSubtarget<F, A, "!">;
22
23/// Match if the original argument (before lowering) was a float.
24/// For example, this is true for i32's that were lowered from soft-float.
25class CCIfOrigArgWasNotFloat<CCAction A>
26 : CCIf<"!static_cast<MipsCCState *>(&State)->WasOriginalArgFloat(ValNo)",
27 A>;
28
29/// Match if the original argument (before lowering) was a 128-bit float (i.e.
30/// long double).
31class CCIfOrigArgWasF128<CCAction A>
32 : CCIf<"static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)", A>;
33
34/// Match if this specific argument is a vararg.
35/// This is slightly different fro CCIfIsVarArg which matches if any argument is
36/// a vararg.
37class CCIfArgIsVarArg<CCAction A>
38 : CCIf<"!static_cast<MipsCCState *>(&State)->IsCallOperandFixed(ValNo)", A>;
39
40
41/// Match if the special calling conv is the specified value.
42class CCIfSpecialCallingConv<string CC, CCAction A>
43 : CCIf<"static_cast<MipsCCState *>(&State)->getSpecialCallingConv() == "
44 "MipsCCState::" # CC, A>;
45
46// For soft-float, f128 values are returned in A0_64 rather than V1_64.
47def RetCC_F128SoftFloat : CallingConv<[
48 CCAssignToReg<[V0_64, A0_64]>
49]>;
50
51// For hard-float, f128 values are returned as a pair of f64's rather than a
52// pair of i64's.
53def RetCC_F128HardFloat : CallingConv<[
54 CCBitConvertToType<f64>,
55
56 // Contrary to the ABI documentation, a struct containing a long double is
57 // returned in $f0, and $f1 instead of the usual $f0, and $f2. This is to
58 // match the de facto ABI as implemented by GCC.
59 CCIfInReg<CCAssignToReg<[D0_64, D1_64]>>,
60
61 CCAssignToReg<[D0_64, D2_64]>
62]>;
63
64// Handle F128 specially since we can't identify the original type during the
65// tablegen-erated code.
66def RetCC_F128 : CallingConv<[
67 CCIfSubtarget<"abiUsesSoftFloat()",
68 CCIfType<[i64], CCDelegateTo<RetCC_F128SoftFloat>>>,
69 CCIfSubtargetNot<"abiUsesSoftFloat()",
70 CCIfType<[i64], CCDelegateTo<RetCC_F128HardFloat>>>
71]>;
72
73//===----------------------------------------------------------------------===//
74// Mips O32 Calling Convention
75//===----------------------------------------------------------------------===//
76
77def CC_MipsO32 : CallingConv<[
78 // Promote i8/i16 arguments to i32.
79 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
80
81 // Integer values get stored in stack slots that are 4 bytes in
82 // size and 4-byte aligned.
83 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
84
85 // Integer values get stored in stack slots that are 8 bytes in
86 // size and 8-byte aligned.
87 CCIfType<[f64], CCAssignToStack<8, 8>>
88]>;
89
90// Only the return rules are defined here for O32. The rules for argument
91// passing are defined in MipsISelLowering.cpp.
92def RetCC_MipsO32 : CallingConv<[
93 // i32 are returned in registers V0, V1, A0, A1
94 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>,
95
96 // f32 are returned in registers F0, F2
97 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
98
99 // f64 arguments are returned in D0_64 and D2_64 in FP64bit mode or
100 // in D0 and D1 in FP32bit mode.
101 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D2_64]>>>,
102 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()", CCAssignToReg<[D0, D1]>>>
103]>;
104
105def CC_MipsO32_FP32 : CustomCallingConv;
106def CC_MipsO32_FP64 : CustomCallingConv;
107
108def CC_MipsO32_FP : CallingConv<[
109 CCIfSubtargetNot<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP32>>,
110 CCIfSubtarget<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP64>>
111]>;
112
113//===----------------------------------------------------------------------===//
114// Mips N32/64 Calling Convention
115//===----------------------------------------------------------------------===//
116
117def CC_MipsN_SoftFloat : CallingConv<[
118 CCAssignToRegWithShadow<[A0, A1, A2, A3,
119 T0, T1, T2, T3],
120 [D12_64, D13_64, D14_64, D15_64,
121 D16_64, D17_64, D18_64, D19_64]>,
122 CCAssignToStack<4, 8>
123]>;
124
125def CC_MipsN : CallingConv<[
|
162 // All integers are promoted to 64-bit.
163 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
164
165 CCIfType<[f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
166
167 CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64,
168 T0_64, T1_64, T2_64, T3_64]>>,
169
170 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
171 CCIfType<[f32], CCAssignToStack<4, 8>>,
172 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
173]>;
174
175def RetCC_MipsN : CallingConv<[
176 // f128 needs to be handled similarly to f32 and f64. However, f128 is not
177 // legal and is lowered to i128 which is further lowered to a pair of i64's.
178 // This presents us with a problem for the calling convention since hard-float
179 // still needs to pass them in FPU registers, and soft-float needs to use $v0,
180 // and $a0 instead of the usual $v0, and $v1. We therefore resort to a
181 // pre-analyze (see PreAnalyzeReturnForF128()) step to pass information on
182 // whether the result was originally an f128 into the tablegen-erated code.
183 //
184 // f128 should only occur for the N64 ABI where long double is 128-bit. On
185 // N32, long double is equivalent to double.
186 CCIfType<[i64], CCIfOrigArgWasF128<CCDelegateTo<RetCC_F128>>>,
187
188 // Aggregate returns are positioned at the lowest address in the slot for
189 // both little and big-endian targets. When passing in registers, this
190 // requires that big-endian targets shift the value into the upper bits.
191 CCIfSubtarget<"isLittle()",
192 CCIfType<[i8, i16, i32, i64], CCIfInReg<CCPromoteToType<i64>>>>,
193 CCIfSubtargetNot<"isLittle()",
194 CCIfType<[i8, i16, i32, i64],
195 CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>,
196
197 // i64 are returned in registers V0_64, V1_64
198 CCIfType<[i64], CCAssignToReg<[V0_64, V1_64]>>,
199
200 // f32 are returned in registers F0, F2
201 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
202
203 // f64 are returned in registers D0, D2
204 CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>>
205]>;
206
207//===----------------------------------------------------------------------===//
208// Mips EABI Calling Convention
209//===----------------------------------------------------------------------===//
210
211def CC_MipsEABI : CallingConv<[
212 // Promote i8/i16 arguments to i32.
213 CCIfType<[i8, i16], CCPromoteToType<i32>>,
214
215 // Integer arguments are passed in integer registers.
216 CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
217
218 // Single fp arguments are passed in pairs within 32-bit mode
219 CCIfType<[f32], CCIfSubtarget<"isSingleFloat()",
220 CCAssignToReg<[F12, F13, F14, F15, F16, F17, F18, F19]>>>,
221
222 CCIfType<[f32], CCIfSubtargetNot<"isSingleFloat()",
223 CCAssignToReg<[F12, F14, F16, F18]>>>,
224
225 // The first 4 double fp arguments are passed in single fp registers.
226 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()",
227 CCAssignToReg<[D6, D7, D8, D9]>>>,
228
229 // Integer values get stored in stack slots that are 4 bytes in
230 // size and 4-byte aligned.
231 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
232
233 // Integer values get stored in stack slots that are 8 bytes in
234 // size and 8-byte aligned.
235 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToStack<8, 8>>>
236]>;
237
238def RetCC_MipsEABI : CallingConv<[
239 // i32 are returned in registers V0, V1
240 CCIfType<[i32], CCAssignToReg<[V0, V1]>>,
241
242 // f32 are returned in registers F0, F1
243 CCIfType<[f32], CCAssignToReg<[F0, F1]>>,
244
245 // f64 are returned in register D0
246 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToReg<[D0]>>>
247]>;
248
249//===----------------------------------------------------------------------===//
250// Mips FastCC Calling Convention
251//===----------------------------------------------------------------------===//
252def CC_MipsO32_FastCC : CallingConv<[
253 // f64 arguments are passed in double-precision floating pointer registers.
254 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()",
255 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6,
256 D7, D8, D9]>>>,
257 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"useOddSPReg()",
258 CCAssignToReg<[D0_64, D1_64, D2_64, D3_64,
259 D4_64, D5_64, D6_64, D7_64,
260 D8_64, D9_64, D10_64, D11_64,
261 D12_64, D13_64, D14_64, D15_64,
262 D16_64, D17_64, D18_64,
263 D19_64]>>>>,
264 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"noOddSPReg()",
265 CCAssignToReg<[D0_64, D2_64, D4_64, D6_64,
266 D8_64, D10_64, D12_64, D14_64,
267 D16_64, D18_64]>>>>,
268
269 // Stack parameter slots for f64 are 64-bit doublewords and 8-byte aligned.
270 CCIfType<[f64], CCAssignToStack<8, 8>>
271]>;
272
273def CC_MipsN_FastCC : CallingConv<[
274 // Integer arguments are passed in integer registers.
275 CCIfType<[i64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, T0_64, T1_64,
276 T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
277 T8_64, V1_64]>>,
278
279 // f64 arguments are passed in double-precision floating pointer registers.
280 CCIfType<[f64], CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, D4_64, D5_64,
281 D6_64, D7_64, D8_64, D9_64, D10_64, D11_64,
282 D12_64, D13_64, D14_64, D15_64, D16_64, D17_64,
283 D18_64, D19_64]>>,
284
285 // Stack parameter slots for i64 and f64 are 64-bit doublewords and
286 // 8-byte aligned.
287 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
288]>;
289
290def CC_Mips_FastCC : CallingConv<[
291 // Handles byval parameters.
292 CCIfByVal<CCPassByVal<4, 4>>,
293
294 // Promote i8/i16 arguments to i32.
295 CCIfType<[i8, i16], CCPromoteToType<i32>>,
296
297 // Integer arguments are passed in integer registers. All scratch registers,
298 // except for AT, V0 and T9, are available to be used as argument registers.
299 CCIfType<[i32], CCIfSubtargetNot<"isTargetNaCl()",
300 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, V1]>>>,
301
302 // In NaCl, T6, T7 and T8 are reserved and not available as argument
303 // registers for fastcc. T6 contains the mask for sandboxing control flow
304 // (indirect jumps and calls). T7 contains the mask for sandboxing memory
305 // accesses (loads and stores). T8 contains the thread pointer.
306 CCIfType<[i32], CCIfSubtarget<"isTargetNaCl()",
307 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, V1]>>>,
308
309 // f32 arguments are passed in single-precision floating pointer registers.
310 CCIfType<[f32], CCIfSubtarget<"useOddSPReg()",
311 CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13,
312 F14, F15, F16, F17, F18, F19]>>>,
313
314 // Don't use odd numbered single-precision registers for -mno-odd-spreg.
315 CCIfType<[f32], CCIfSubtarget<"noOddSPReg()",
316 CCAssignToReg<[F0, F2, F4, F6, F8, F10, F12, F14, F16, F18]>>>,
317
318 // Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned.
319 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
320
321 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>,
322 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FastCC>>,
323 CCDelegateTo<CC_MipsN_FastCC>
324]>;
325
326//===----------------------------------------------------------------------===//
327// Mips Calling Convention Dispatch
328//===----------------------------------------------------------------------===//
329
330def RetCC_Mips : CallingConv<[
331 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<RetCC_MipsEABI>>,
332 CCIfSubtarget<"isABI_N32()", CCDelegateTo<RetCC_MipsN>>,
333 CCIfSubtarget<"isABI_N64()", CCDelegateTo<RetCC_MipsN>>,
334 CCDelegateTo<RetCC_MipsO32>
335]>;
336
337def CC_Mips_ByVal : CallingConv<[
338 CCIfSubtarget<"isABI_O32()", CCIfByVal<CCPassByVal<4, 4>>>,
339 CCIfByVal<CCPassByVal<8, 8>>
340]>;
341
342def CC_Mips16RetHelper : CallingConv<[
343 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>,
344
345 // Integer arguments are passed in integer registers.
346 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>
347]>;
348
349def CC_Mips_FixedArg : CallingConv<[
350 // Mips16 needs special handling on some functions.
351 CCIf<"State.getCallingConv() != CallingConv::Fast",
352 CCIfSpecialCallingConv<"Mips16RetHelperConv",
353 CCDelegateTo<CC_Mips16RetHelper>>>,
354
355 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>,
356
357 // f128 needs to be handled similarly to f32 and f64 on hard-float. However,
358 // f128 is not legal and is lowered to i128 which is further lowered to a pair
359 // of i64's.
360 // This presents us with a problem for the calling convention since hard-float
361 // still needs to pass them in FPU registers. We therefore resort to a
362 // pre-analyze (see PreAnalyzeFormalArgsForF128()) step to pass information on
363 // whether the argument was originally an f128 into the tablegen-erated code.
364 //
365 // f128 should only occur for the N64 ABI where long double is 128-bit. On
366 // N32, long double is equivalent to double.
367 CCIfType<[i64],
368 CCIfSubtargetNot<"abiUsesSoftFloat()",
369 CCIfOrigArgWasF128<CCBitConvertToType<f64>>>>,
370
371 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_Mips_FastCC>>,
372
373 // FIXME: There wasn't an EABI case in the original code and it seems unlikely
374 // that it's the same as CC_MipsN
375 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>,
376 CCDelegateTo<CC_MipsN>
377]>;
378
379def CC_Mips_VarArg : CallingConv<[
380 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>,
381
382 // FIXME: There wasn't an EABI case in the original code and it seems unlikely
383 // that it's the same as CC_MipsN_VarArg
384 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>,
385 CCDelegateTo<CC_MipsN_VarArg>
386]>;
387
388def CC_Mips : CallingConv<[
389 CCIfVarArg<CCIfArgIsVarArg<CCDelegateTo<CC_Mips_VarArg>>>,
390 CCDelegateTo<CC_Mips_FixedArg>
391]>;
392
393//===----------------------------------------------------------------------===//
394// Callee-saved register lists.
395//===----------------------------------------------------------------------===//
396
397def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP,
398 (sequence "S%u", 7, 0))>;
399
400def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
401 (sequence "S%u", 7, 0))> {
402 let OtherPreserved = (add (decimate (sequence "F%u", 30, 20), 2));
403}
404
405def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
406 (sequence "S%u", 7, 0))>;
407
408def CSR_O32_FP64 :
409 CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP,
410 (sequence "S%u", 7, 0))>;
411
412def CSR_N32 : CalleeSavedRegs<(add D20_64, D22_64, D24_64, D26_64, D28_64,
413 D30_64, RA_64, FP_64, GP_64,
414 (sequence "S%u_64", 7, 0))>;
415
416def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64,
417 GP_64, (sequence "S%u_64", 7, 0))>;
418
419def CSR_Mips16RetHelper :
420 CalleeSavedRegs<(add V0, V1, FP,
421 (sequence "A%u", 3, 0), (sequence "S%u", 7, 0),
422 (sequence "D%u", 15, 10))>;
| 166 // All integers are promoted to 64-bit.
167 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
168
169 CCIfType<[f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
170
171 CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64,
172 T0_64, T1_64, T2_64, T3_64]>>,
173
174 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
175 CCIfType<[f32], CCAssignToStack<4, 8>>,
176 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
177]>;
178
179def RetCC_MipsN : CallingConv<[
180 // f128 needs to be handled similarly to f32 and f64. However, f128 is not
181 // legal and is lowered to i128 which is further lowered to a pair of i64's.
182 // This presents us with a problem for the calling convention since hard-float
183 // still needs to pass them in FPU registers, and soft-float needs to use $v0,
184 // and $a0 instead of the usual $v0, and $v1. We therefore resort to a
185 // pre-analyze (see PreAnalyzeReturnForF128()) step to pass information on
186 // whether the result was originally an f128 into the tablegen-erated code.
187 //
188 // f128 should only occur for the N64 ABI where long double is 128-bit. On
189 // N32, long double is equivalent to double.
190 CCIfType<[i64], CCIfOrigArgWasF128<CCDelegateTo<RetCC_F128>>>,
191
192 // Aggregate returns are positioned at the lowest address in the slot for
193 // both little and big-endian targets. When passing in registers, this
194 // requires that big-endian targets shift the value into the upper bits.
195 CCIfSubtarget<"isLittle()",
196 CCIfType<[i8, i16, i32, i64], CCIfInReg<CCPromoteToType<i64>>>>,
197 CCIfSubtargetNot<"isLittle()",
198 CCIfType<[i8, i16, i32, i64],
199 CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>,
200
201 // i64 are returned in registers V0_64, V1_64
202 CCIfType<[i64], CCAssignToReg<[V0_64, V1_64]>>,
203
204 // f32 are returned in registers F0, F2
205 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
206
207 // f64 are returned in registers D0, D2
208 CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>>
209]>;
210
211//===----------------------------------------------------------------------===//
212// Mips EABI Calling Convention
213//===----------------------------------------------------------------------===//
214
215def CC_MipsEABI : CallingConv<[
216 // Promote i8/i16 arguments to i32.
217 CCIfType<[i8, i16], CCPromoteToType<i32>>,
218
219 // Integer arguments are passed in integer registers.
220 CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
221
222 // Single fp arguments are passed in pairs within 32-bit mode
223 CCIfType<[f32], CCIfSubtarget<"isSingleFloat()",
224 CCAssignToReg<[F12, F13, F14, F15, F16, F17, F18, F19]>>>,
225
226 CCIfType<[f32], CCIfSubtargetNot<"isSingleFloat()",
227 CCAssignToReg<[F12, F14, F16, F18]>>>,
228
229 // The first 4 double fp arguments are passed in single fp registers.
230 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()",
231 CCAssignToReg<[D6, D7, D8, D9]>>>,
232
233 // Integer values get stored in stack slots that are 4 bytes in
234 // size and 4-byte aligned.
235 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
236
237 // Integer values get stored in stack slots that are 8 bytes in
238 // size and 8-byte aligned.
239 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToStack<8, 8>>>
240]>;
241
242def RetCC_MipsEABI : CallingConv<[
243 // i32 are returned in registers V0, V1
244 CCIfType<[i32], CCAssignToReg<[V0, V1]>>,
245
246 // f32 are returned in registers F0, F1
247 CCIfType<[f32], CCAssignToReg<[F0, F1]>>,
248
249 // f64 are returned in register D0
250 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToReg<[D0]>>>
251]>;
252
253//===----------------------------------------------------------------------===//
254// Mips FastCC Calling Convention
255//===----------------------------------------------------------------------===//
256def CC_MipsO32_FastCC : CallingConv<[
257 // f64 arguments are passed in double-precision floating pointer registers.
258 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()",
259 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6,
260 D7, D8, D9]>>>,
261 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"useOddSPReg()",
262 CCAssignToReg<[D0_64, D1_64, D2_64, D3_64,
263 D4_64, D5_64, D6_64, D7_64,
264 D8_64, D9_64, D10_64, D11_64,
265 D12_64, D13_64, D14_64, D15_64,
266 D16_64, D17_64, D18_64,
267 D19_64]>>>>,
268 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"noOddSPReg()",
269 CCAssignToReg<[D0_64, D2_64, D4_64, D6_64,
270 D8_64, D10_64, D12_64, D14_64,
271 D16_64, D18_64]>>>>,
272
273 // Stack parameter slots for f64 are 64-bit doublewords and 8-byte aligned.
274 CCIfType<[f64], CCAssignToStack<8, 8>>
275]>;
276
277def CC_MipsN_FastCC : CallingConv<[
278 // Integer arguments are passed in integer registers.
279 CCIfType<[i64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, T0_64, T1_64,
280 T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
281 T8_64, V1_64]>>,
282
283 // f64 arguments are passed in double-precision floating pointer registers.
284 CCIfType<[f64], CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, D4_64, D5_64,
285 D6_64, D7_64, D8_64, D9_64, D10_64, D11_64,
286 D12_64, D13_64, D14_64, D15_64, D16_64, D17_64,
287 D18_64, D19_64]>>,
288
289 // Stack parameter slots for i64 and f64 are 64-bit doublewords and
290 // 8-byte aligned.
291 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
292]>;
293
294def CC_Mips_FastCC : CallingConv<[
295 // Handles byval parameters.
296 CCIfByVal<CCPassByVal<4, 4>>,
297
298 // Promote i8/i16 arguments to i32.
299 CCIfType<[i8, i16], CCPromoteToType<i32>>,
300
301 // Integer arguments are passed in integer registers. All scratch registers,
302 // except for AT, V0 and T9, are available to be used as argument registers.
303 CCIfType<[i32], CCIfSubtargetNot<"isTargetNaCl()",
304 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, V1]>>>,
305
306 // In NaCl, T6, T7 and T8 are reserved and not available as argument
307 // registers for fastcc. T6 contains the mask for sandboxing control flow
308 // (indirect jumps and calls). T7 contains the mask for sandboxing memory
309 // accesses (loads and stores). T8 contains the thread pointer.
310 CCIfType<[i32], CCIfSubtarget<"isTargetNaCl()",
311 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, V1]>>>,
312
313 // f32 arguments are passed in single-precision floating pointer registers.
314 CCIfType<[f32], CCIfSubtarget<"useOddSPReg()",
315 CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13,
316 F14, F15, F16, F17, F18, F19]>>>,
317
318 // Don't use odd numbered single-precision registers for -mno-odd-spreg.
319 CCIfType<[f32], CCIfSubtarget<"noOddSPReg()",
320 CCAssignToReg<[F0, F2, F4, F6, F8, F10, F12, F14, F16, F18]>>>,
321
322 // Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned.
323 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
324
325 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>,
326 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FastCC>>,
327 CCDelegateTo<CC_MipsN_FastCC>
328]>;
329
330//===----------------------------------------------------------------------===//
331// Mips Calling Convention Dispatch
332//===----------------------------------------------------------------------===//
333
334def RetCC_Mips : CallingConv<[
335 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<RetCC_MipsEABI>>,
336 CCIfSubtarget<"isABI_N32()", CCDelegateTo<RetCC_MipsN>>,
337 CCIfSubtarget<"isABI_N64()", CCDelegateTo<RetCC_MipsN>>,
338 CCDelegateTo<RetCC_MipsO32>
339]>;
340
341def CC_Mips_ByVal : CallingConv<[
342 CCIfSubtarget<"isABI_O32()", CCIfByVal<CCPassByVal<4, 4>>>,
343 CCIfByVal<CCPassByVal<8, 8>>
344]>;
345
346def CC_Mips16RetHelper : CallingConv<[
347 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>,
348
349 // Integer arguments are passed in integer registers.
350 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>
351]>;
352
353def CC_Mips_FixedArg : CallingConv<[
354 // Mips16 needs special handling on some functions.
355 CCIf<"State.getCallingConv() != CallingConv::Fast",
356 CCIfSpecialCallingConv<"Mips16RetHelperConv",
357 CCDelegateTo<CC_Mips16RetHelper>>>,
358
359 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>,
360
361 // f128 needs to be handled similarly to f32 and f64 on hard-float. However,
362 // f128 is not legal and is lowered to i128 which is further lowered to a pair
363 // of i64's.
364 // This presents us with a problem for the calling convention since hard-float
365 // still needs to pass them in FPU registers. We therefore resort to a
366 // pre-analyze (see PreAnalyzeFormalArgsForF128()) step to pass information on
367 // whether the argument was originally an f128 into the tablegen-erated code.
368 //
369 // f128 should only occur for the N64 ABI where long double is 128-bit. On
370 // N32, long double is equivalent to double.
371 CCIfType<[i64],
372 CCIfSubtargetNot<"abiUsesSoftFloat()",
373 CCIfOrigArgWasF128<CCBitConvertToType<f64>>>>,
374
375 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_Mips_FastCC>>,
376
377 // FIXME: There wasn't an EABI case in the original code and it seems unlikely
378 // that it's the same as CC_MipsN
379 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>,
380 CCDelegateTo<CC_MipsN>
381]>;
382
383def CC_Mips_VarArg : CallingConv<[
384 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>,
385
386 // FIXME: There wasn't an EABI case in the original code and it seems unlikely
387 // that it's the same as CC_MipsN_VarArg
388 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>,
389 CCDelegateTo<CC_MipsN_VarArg>
390]>;
391
392def CC_Mips : CallingConv<[
393 CCIfVarArg<CCIfArgIsVarArg<CCDelegateTo<CC_Mips_VarArg>>>,
394 CCDelegateTo<CC_Mips_FixedArg>
395]>;
396
397//===----------------------------------------------------------------------===//
398// Callee-saved register lists.
399//===----------------------------------------------------------------------===//
400
401def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP,
402 (sequence "S%u", 7, 0))>;
403
404def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
405 (sequence "S%u", 7, 0))> {
406 let OtherPreserved = (add (decimate (sequence "F%u", 30, 20), 2));
407}
408
409def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
410 (sequence "S%u", 7, 0))>;
411
412def CSR_O32_FP64 :
413 CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP,
414 (sequence "S%u", 7, 0))>;
415
416def CSR_N32 : CalleeSavedRegs<(add D20_64, D22_64, D24_64, D26_64, D28_64,
417 D30_64, RA_64, FP_64, GP_64,
418 (sequence "S%u_64", 7, 0))>;
419
420def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64,
421 GP_64, (sequence "S%u_64", 7, 0))>;
422
423def CSR_Mips16RetHelper :
424 CalleeSavedRegs<(add V0, V1, FP,
425 (sequence "A%u", 3, 0), (sequence "S%u", 7, 0),
426 (sequence "D%u", 15, 10))>;
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