1//===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsTargetLowering specialized for mips16.
11//
12//===----------------------------------------------------------------------===//
13#include "Mips16ISelLowering.h"
14#include "MCTargetDesc/MipsBaseInfo.h"
15#include "MipsRegisterInfo.h"
16#include "MipsTargetMachine.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/Support/CommandLine.h"
20#include "llvm/Target/TargetInstrInfo.h"
21#include <string>
22
23using namespace llvm;
24
25#define DEBUG_TYPE "mips-lower"
26
27static cl::opt<bool> DontExpandCondPseudos16(
28 "mips16-dont-expand-cond-pseudo",
29 cl::init(false),
30 cl::desc("Dont expand conditional move related "
31 "pseudos for Mips 16"),
32 cl::Hidden);
33
34namespace {
35struct Mips16Libcall {
36 RTLIB::Libcall Libcall;
37 const char *Name;
38
39 bool operator<(const Mips16Libcall &RHS) const {
40 return std::strcmp(Name, RHS.Name) < 0;
41 }
42};
43
44struct Mips16IntrinsicHelperType{
45 const char* Name;
46 const char* Helper;
47
48 bool operator<(const Mips16IntrinsicHelperType &RHS) const {
49 return std::strcmp(Name, RHS.Name) < 0;
50 }
51 bool operator==(const Mips16IntrinsicHelperType &RHS) const {
52 return std::strcmp(Name, RHS.Name) == 0;
53 }
54};
55}
56
57// Libcalls for which no helper is generated. Sorted by name for binary search.
58static const Mips16Libcall HardFloatLibCalls[] = {
59 { RTLIB::ADD_F64, "__mips16_adddf3" },
60 { RTLIB::ADD_F32, "__mips16_addsf3" },
61 { RTLIB::DIV_F64, "__mips16_divdf3" },
62 { RTLIB::DIV_F32, "__mips16_divsf3" },
63 { RTLIB::OEQ_F64, "__mips16_eqdf2" },
64 { RTLIB::OEQ_F32, "__mips16_eqsf2" },
65 { RTLIB::FPEXT_F32_F64, "__mips16_extendsfdf2" },
66 { RTLIB::FPTOSINT_F64_I32, "__mips16_fix_truncdfsi" },
67 { RTLIB::FPTOSINT_F32_I32, "__mips16_fix_truncsfsi" },
68 { RTLIB::SINTTOFP_I32_F64, "__mips16_floatsidf" },
69 { RTLIB::SINTTOFP_I32_F32, "__mips16_floatsisf" },
70 { RTLIB::UINTTOFP_I32_F64, "__mips16_floatunsidf" },
71 { RTLIB::UINTTOFP_I32_F32, "__mips16_floatunsisf" },
72 { RTLIB::OGE_F64, "__mips16_gedf2" },
73 { RTLIB::OGE_F32, "__mips16_gesf2" },
74 { RTLIB::OGT_F64, "__mips16_gtdf2" },
75 { RTLIB::OGT_F32, "__mips16_gtsf2" },
76 { RTLIB::OLE_F64, "__mips16_ledf2" },
77 { RTLIB::OLE_F32, "__mips16_lesf2" },
78 { RTLIB::OLT_F64, "__mips16_ltdf2" },
79 { RTLIB::OLT_F32, "__mips16_ltsf2" },
80 { RTLIB::MUL_F64, "__mips16_muldf3" },
81 { RTLIB::MUL_F32, "__mips16_mulsf3" },
82 { RTLIB::UNE_F64, "__mips16_nedf2" },
83 { RTLIB::UNE_F32, "__mips16_nesf2" },
84 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_dc" }, // No associated libcall.
85 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_df" }, // No associated libcall.
86 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sc" }, // No associated libcall.
87 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sf" }, // No associated libcall.
88 { RTLIB::SUB_F64, "__mips16_subdf3" },
89 { RTLIB::SUB_F32, "__mips16_subsf3" },
90 { RTLIB::FPROUND_F64_F32, "__mips16_truncdfsf2" },
91 { RTLIB::UO_F64, "__mips16_unorddf2" },
92 { RTLIB::UO_F32, "__mips16_unordsf2" }
93};
94
95static const Mips16IntrinsicHelperType Mips16IntrinsicHelper[] = {
96 {"__fixunsdfsi", "__mips16_call_stub_2" },
97 {"ceil", "__mips16_call_stub_df_2"},
98 {"ceilf", "__mips16_call_stub_sf_1"},
99 {"copysign", "__mips16_call_stub_df_10"},
100 {"copysignf", "__mips16_call_stub_sf_5"},
101 {"cos", "__mips16_call_stub_df_2"},
102 {"cosf", "__mips16_call_stub_sf_1"},
103 {"exp2", "__mips16_call_stub_df_2"},
104 {"exp2f", "__mips16_call_stub_sf_1"},
105 {"floor", "__mips16_call_stub_df_2"},
106 {"floorf", "__mips16_call_stub_sf_1"},
107 {"log2", "__mips16_call_stub_df_2"},
108 {"log2f", "__mips16_call_stub_sf_1"},
109 {"nearbyint", "__mips16_call_stub_df_2"},
110 {"nearbyintf", "__mips16_call_stub_sf_1"},
111 {"rint", "__mips16_call_stub_df_2"},
112 {"rintf", "__mips16_call_stub_sf_1"},
113 {"sin", "__mips16_call_stub_df_2"},
114 {"sinf", "__mips16_call_stub_sf_1"},
115 {"sqrt", "__mips16_call_stub_df_2"},
116 {"sqrtf", "__mips16_call_stub_sf_1"},
117 {"trunc", "__mips16_call_stub_df_2"},
118 {"truncf", "__mips16_call_stub_sf_1"},
119};
120
121Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM,
122 const MipsSubtarget &STI)
123 : MipsTargetLowering(TM, STI) {
124
125 // Set up the register classes
126 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
127
128 if (!TM.Options.UseSoftFloat)
129 setMips16HardFloatLibCalls();
130
131 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
132 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
133 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
134 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
135 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
136 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
137 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
138 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
139 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
140 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
141 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
142 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
143 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
144
145 setOperationAction(ISD::ROTR, MVT::i32, Expand);
146 setOperationAction(ISD::ROTR, MVT::i64, Expand);
147 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
148 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
149
150 computeRegisterProperties();
151}
152
153const MipsTargetLowering *
154llvm::createMips16TargetLowering(MipsTargetMachine &TM,
155 const MipsSubtarget &STI) {
156 return new Mips16TargetLowering(TM, STI);
157}
158
159bool
160Mips16TargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
161 unsigned,
162 bool *Fast) const {
163 return false;
164}
165
166MachineBasicBlock *
167Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
168 MachineBasicBlock *BB) const {
169 switch (MI->getOpcode()) {
170 default:
171 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
172 case Mips::SelBeqZ:
173 return emitSel16(Mips::BeqzRxImm16, MI, BB);
174 case Mips::SelBneZ:
175 return emitSel16(Mips::BnezRxImm16, MI, BB);
176 case Mips::SelTBteqZCmpi:
177 return emitSeliT16(Mips::Bteqz16, Mips::CmpiRxImmX16, MI, BB);
178 case Mips::SelTBteqZSlti:
179 return emitSeliT16(Mips::Bteqz16, Mips::SltiRxImmX16, MI, BB);
180 case Mips::SelTBteqZSltiu:
181 return emitSeliT16(Mips::Bteqz16, Mips::SltiuRxImmX16, MI, BB);
182 case Mips::SelTBtneZCmpi:
183 return emitSeliT16(Mips::Btnez16, Mips::CmpiRxImmX16, MI, BB);
184 case Mips::SelTBtneZSlti:
185 return emitSeliT16(Mips::Btnez16, Mips::SltiRxImmX16, MI, BB);
186 case Mips::SelTBtneZSltiu:
187 return emitSeliT16(Mips::Btnez16, Mips::SltiuRxImmX16, MI, BB);
188 case Mips::SelTBteqZCmp:
189 return emitSelT16(Mips::Bteqz16, Mips::CmpRxRy16, MI, BB);
190 case Mips::SelTBteqZSlt:
191 return emitSelT16(Mips::Bteqz16, Mips::SltRxRy16, MI, BB);
192 case Mips::SelTBteqZSltu:
193 return emitSelT16(Mips::Bteqz16, Mips::SltuRxRy16, MI, BB);
194 case Mips::SelTBtneZCmp:
195 return emitSelT16(Mips::Btnez16, Mips::CmpRxRy16, MI, BB);
196 case Mips::SelTBtneZSlt:
197 return emitSelT16(Mips::Btnez16, Mips::SltRxRy16, MI, BB);
198 case Mips::SelTBtneZSltu:
199 return emitSelT16(Mips::Btnez16, Mips::SltuRxRy16, MI, BB);
200 case Mips::BteqzT8CmpX16:
201 return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::CmpRxRy16, MI, BB);
202 case Mips::BteqzT8SltX16:
203 return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::SltRxRy16, MI, BB);
204 case Mips::BteqzT8SltuX16:
205 // TBD: figure out a way to get this or remove the instruction
206 // altogether.
207 return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::SltuRxRy16, MI, BB);
208 case Mips::BtnezT8CmpX16:
209 return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::CmpRxRy16, MI, BB);
210 case Mips::BtnezT8SltX16:
211 return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::SltRxRy16, MI, BB);
212 case Mips::BtnezT8SltuX16:
213 // TBD: figure out a way to get this or remove the instruction
214 // altogether.
215 return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::SltuRxRy16, MI, BB);
216 case Mips::BteqzT8CmpiX16: return emitFEXT_T8I8I16_ins(
217 Mips::Bteqz16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB);
218 case Mips::BteqzT8SltiX16: return emitFEXT_T8I8I16_ins(
219 Mips::Bteqz16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB);
220 case Mips::BteqzT8SltiuX16: return emitFEXT_T8I8I16_ins(
221 Mips::Bteqz16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB);
222 case Mips::BtnezT8CmpiX16: return emitFEXT_T8I8I16_ins(
223 Mips::Btnez16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB);
224 case Mips::BtnezT8SltiX16: return emitFEXT_T8I8I16_ins(
225 Mips::Btnez16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB);
226 case Mips::BtnezT8SltiuX16: return emitFEXT_T8I8I16_ins(
227 Mips::Btnez16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB);
228 break;
229 case Mips::SltCCRxRy16:
230 return emitFEXT_CCRX16_ins(Mips::SltRxRy16, MI, BB);
231 break;
232 case Mips::SltiCCRxImmX16:
233 return emitFEXT_CCRXI16_ins
234 (Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
235 case Mips::SltiuCCRxImmX16:
236 return emitFEXT_CCRXI16_ins
237 (Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
238 case Mips::SltuCCRxRy16:
239 return emitFEXT_CCRX16_ins
240 (Mips::SltuRxRy16, MI, BB);
241 }
242}
243
244bool Mips16TargetLowering::
245isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
246 unsigned NextStackOffset,
247 const MipsFunctionInfo& FI) const {
248 // No tail call optimization for mips16.
249 return false;
250}
251
252void Mips16TargetLowering::setMips16HardFloatLibCalls() {
253 for (unsigned I = 0; I != array_lengthof(HardFloatLibCalls); ++I) {
254 assert((I == 0 || HardFloatLibCalls[I - 1] < HardFloatLibCalls[I]) &&
255 "Array not sorted!");
256 if (HardFloatLibCalls[I].Libcall != RTLIB::UNKNOWN_LIBCALL)
257 setLibcallName(HardFloatLibCalls[I].Libcall, HardFloatLibCalls[I].Name);
258 }
259
260 setLibcallName(RTLIB::O_F64, "__mips16_unorddf2");
261 setLibcallName(RTLIB::O_F32, "__mips16_unordsf2");
262}
263
264//
265// The Mips16 hard float is a crazy quilt inherited from gcc. I have a much
266// cleaner way to do all of this but it will have to wait until the traditional
267// gcc mechanism is completed.
268//
269// For Pic, in order for Mips16 code to call Mips32 code which according the abi
270// have either arguments or returned values placed in floating point registers,
271// we use a set of helper functions. (This includes functions which return type
272// complex which on Mips are returned in a pair of floating point registers).
273//
274// This is an encoding that we inherited from gcc.
275// In Mips traditional O32, N32 ABI, floating point numbers are passed in
276// floating point argument registers 1,2 only when the first and optionally
277// the second arguments are float (sf) or double (df).
278// For Mips16 we are only concerned with the situations where floating point
279// arguments are being passed in floating point registers by the ABI, because
280// Mips16 mode code cannot execute floating point instructions to load those
281// values and hence helper functions are needed.
282// The possibilities are (), (sf), (sf, sf), (sf, df), (df), (df, sf), (df, df)
283// the helper function suffixs for these are:
284// 0, 1, 5, 9, 2, 6, 10
285// this suffix can then be calculated as follows:
286// for a given argument Arg:
287// Arg1x, Arg2x = 1 : Arg is sf
288// 2 : Arg is df
289// 0: Arg is neither sf or df
290// So this stub is the string for number Arg1x + Arg2x*4.
291// However not all numbers between 0 and 10 are possible, we check anyway and
292// assert if the impossible exists.
293//
294
295unsigned int Mips16TargetLowering::getMips16HelperFunctionStubNumber
296 (ArgListTy &Args) const {
297 unsigned int resultNum = 0;
298 if (Args.size() >= 1) {
299 Type *t = Args[0].Ty;
300 if (t->isFloatTy()) {
301 resultNum = 1;
302 }
303 else if (t->isDoubleTy()) {
304 resultNum = 2;
305 }
306 }
307 if (resultNum) {
308 if (Args.size() >=2) {
309 Type *t = Args[1].Ty;
310 if (t->isFloatTy()) {
311 resultNum += 4;
312 }
313 else if (t->isDoubleTy()) {
314 resultNum += 8;
315 }
316 }
317 }
318 return resultNum;
319}
320
321//
322// prefixs are attached to stub numbers depending on the return type .
323// return type: float sf_
324// double df_
325// single complex sc_
326// double complext dc_
327// others NO PREFIX
328//
329//
330// The full name of a helper function is__mips16_call_stub +
331// return type dependent prefix + stub number
332//
333//
334// This is something that probably should be in a different source file and
335// perhaps done differently but my main purpose is to not waste runtime
336// on something that we can enumerate in the source. Another possibility is
337// to have a python script to generate these mapping tables. This will do
338// for now. There are a whole series of helper function mapping arrays, one
339// for each return type class as outlined above. There there are 11 possible
340// entries. Ones with 0 are ones which should never be selected
341//
342// All the arrays are similar except for ones which return neither
343// sf, df, sc, dc, in which only care about ones which have sf or df as a
344// first parameter.
345//
346#define P_ "__mips16_call_stub_"
347#define MAX_STUB_NUMBER 10
348#define T1 P "1", P "2", 0, 0, P "5", P "6", 0, 0, P "9", P "10"
349#define T P "0" , T1
350#define P P_
351static char const * vMips16Helper[MAX_STUB_NUMBER+1] =
352 {nullptr, T1 };
353#undef P
354#define P P_ "sf_"
355static char const * sfMips16Helper[MAX_STUB_NUMBER+1] =
356 { T };
357#undef P
358#define P P_ "df_"
359static char const * dfMips16Helper[MAX_STUB_NUMBER+1] =
360 { T };
361#undef P
362#define P P_ "sc_"
363static char const * scMips16Helper[MAX_STUB_NUMBER+1] =
364 { T };
365#undef P
366#define P P_ "dc_"
367static char const * dcMips16Helper[MAX_STUB_NUMBER+1] =
368 { T };
369#undef P
370#undef P_
371
372
373const char* Mips16TargetLowering::
374 getMips16HelperFunction
375 (Type* RetTy, ArgListTy &Args, bool &needHelper) const {
376 const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args);
377#ifndef NDEBUG
378 const unsigned int maxStubNum = 10;
379 assert(stubNum <= maxStubNum);
380 const bool validStubNum[maxStubNum+1] =
381 {true, true, true, false, false, true, true, false, false, true, true};
382 assert(validStubNum[stubNum]);
383#endif
384 const char *result;
385 if (RetTy->isFloatTy()) {
386 result = sfMips16Helper[stubNum];
387 }
388 else if (RetTy ->isDoubleTy()) {
389 result = dfMips16Helper[stubNum];
390 }
391 else if (RetTy->isStructTy()) {
392 // check if it's complex
393 if (RetTy->getNumContainedTypes() == 2) {
394 if ((RetTy->getContainedType(0)->isFloatTy()) &&
395 (RetTy->getContainedType(1)->isFloatTy())) {
396 result = scMips16Helper[stubNum];
397 }
398 else if ((RetTy->getContainedType(0)->isDoubleTy()) &&
399 (RetTy->getContainedType(1)->isDoubleTy())) {
400 result = dcMips16Helper[stubNum];
401 }
402 else {
403 llvm_unreachable("Uncovered condition");
404 }
405 }
406 else {
407 llvm_unreachable("Uncovered condition");
408 }
409 }
410 else {
411 if (stubNum == 0) {
412 needHelper = false;
413 return "";
414 }
415 result = vMips16Helper[stubNum];
416 }
417 needHelper = true;
418 return result;
419}
420
421void Mips16TargetLowering::
422getOpndList(SmallVectorImpl<SDValue> &Ops,
423 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
424 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
425 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
426 SelectionDAG &DAG = CLI.DAG;
427 MachineFunction &MF = DAG.getMachineFunction();
428 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
429 const char* Mips16HelperFunction = nullptr;
430 bool NeedMips16Helper = false;
431
432 if (Subtarget.inMips16HardFloat()) {
433 //
434 // currently we don't have symbols tagged with the mips16 or mips32
435 // qualifier so we will assume that we don't know what kind it is.
436 // and generate the helper
437 //
438 bool LookupHelper = true;
439 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(CLI.Callee)) {
440 Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL, S->getSymbol() };
441
442 if (std::binary_search(std::begin(HardFloatLibCalls),
443 std::end(HardFloatLibCalls), Find))
444 LookupHelper = false;
445 else {
446 const char *Symbol = S->getSymbol();
447 Mips16IntrinsicHelperType IntrinsicFind = { Symbol, "" };
448 const Mips16HardFloatInfo::FuncSignature *Signature =
449 Mips16HardFloatInfo::findFuncSignature(Symbol);
450 if (!IsPICCall && (Signature && (FuncInfo->StubsNeeded.find(Symbol) ==
451 FuncInfo->StubsNeeded.end()))) {
452 FuncInfo->StubsNeeded[Symbol] = Signature;
453 //
454 // S2 is normally saved if the stub is for a function which
455 // returns a float or double value and is not otherwise. This is
456 // because more work is required after the function the stub
457 // is calling completes, and so the stub cannot directly return
458 // and the stub has no stack space to store the return address so
459 // S2 is used for that purpose.
460 // In order to take advantage of not saving S2, we need to also
461 // optimize the call in the stub and this requires some further
462 // functionality in MipsAsmPrinter which we don't have yet.
463 // So for now we always save S2. The optimization will be done
464 // in a follow-on patch.
465 //
466 if (1 || (Signature->RetSig != Mips16HardFloatInfo::NoFPRet))
467 FuncInfo->setSaveS2();
468 }
469 // one more look at list of intrinsics
470 const Mips16IntrinsicHelperType *Helper =
471 std::lower_bound(std::begin(Mips16IntrinsicHelper),
472 std::end(Mips16IntrinsicHelper), IntrinsicFind);
473 if (Helper != std::end(Mips16IntrinsicHelper) &&
474 *Helper == IntrinsicFind) {
475 Mips16HelperFunction = Helper->Helper;
476 NeedMips16Helper = true;
477 LookupHelper = false;
478 }
479
480 }
481 } else if (GlobalAddressSDNode *G =
482 dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
483 Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL,
484 G->getGlobal()->getName().data() };
485
486 if (std::binary_search(std::begin(HardFloatLibCalls),
487 std::end(HardFloatLibCalls), Find))
488 LookupHelper = false;
489 }
490 if (LookupHelper)
491 Mips16HelperFunction =
492 getMips16HelperFunction(CLI.RetTy, CLI.getArgs(), NeedMips16Helper);
493 }
494
495 SDValue JumpTarget = Callee;
496
497 // T9 should contain the address of the callee function if
498 // -reloction-model=pic or it is an indirect call.
499 if (IsPICCall || !GlobalOrExternal) {
500 unsigned V0Reg = Mips::V0;
501 if (NeedMips16Helper) {
502 RegsToPass.push_front(std::make_pair(V0Reg, Callee));
503 JumpTarget = DAG.getExternalSymbol(Mips16HelperFunction, getPointerTy());
504 ExternalSymbolSDNode *S = cast<ExternalSymbolSDNode>(JumpTarget);
505 JumpTarget = getAddrGlobal(S, JumpTarget.getValueType(), DAG,
506 MipsII::MO_GOT, Chain,
507 FuncInfo->callPtrInfo(S->getSymbol()));
508 } else
509 RegsToPass.push_front(std::make_pair((unsigned)Mips::T9, Callee));
510 }
511
512 Ops.push_back(JumpTarget);
513
514 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
515 InternalLinkage, CLI, Callee, Chain);
516}
517
518MachineBasicBlock *Mips16TargetLowering::
519emitSel16(unsigned Opc, MachineInstr *MI, MachineBasicBlock *BB) const {
520 if (DontExpandCondPseudos16)
521 return BB;
522 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
523 DebugLoc DL = MI->getDebugLoc();
524 // To "insert" a SELECT_CC instruction, we actually have to insert the
525 // diamond control-flow pattern. The incoming instruction knows the
526 // destination vreg to set, the condition code register to branch on, the
527 // true/false values to select between, and a branch opcode to use.
528 const BasicBlock *LLVM_BB = BB->getBasicBlock();
529 MachineFunction::iterator It = BB;
530 ++It;
531
532 // thisMBB:
533 // ...
534 // TrueVal = ...
535 // setcc r1, r2, r3
536 // bNE r1, r0, copy1MBB
537 // fallthrough --> copy0MBB
538 MachineBasicBlock *thisMBB = BB;
539 MachineFunction *F = BB->getParent();
540 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
541 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
542 F->insert(It, copy0MBB);
543 F->insert(It, sinkMBB);
544
545 // Transfer the remainder of BB and its successor edges to sinkMBB.
546 sinkMBB->splice(sinkMBB->begin(), BB,
547 std::next(MachineBasicBlock::iterator(MI)), BB->end());
548 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
549
550 // Next, add the true and fallthrough blocks as its successors.
551 BB->addSuccessor(copy0MBB);
552 BB->addSuccessor(sinkMBB);
553
554 BuildMI(BB, DL, TII->get(Opc)).addReg(MI->getOperand(3).getReg())
555 .addMBB(sinkMBB);
556
557 // copy0MBB:
558 // %FalseValue = ...
559 // # fallthrough to sinkMBB
560 BB = copy0MBB;
561
562 // Update machine-CFG edges
563 BB->addSuccessor(sinkMBB);
564
565 // sinkMBB:
566 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
567 // ...
568 BB = sinkMBB;
569
570 BuildMI(*BB, BB->begin(), DL,
571 TII->get(Mips::PHI), MI->getOperand(0).getReg())
572 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
573 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
574
575 MI->eraseFromParent(); // The pseudo instruction is gone now.
576 return BB;
577}
578
579MachineBasicBlock *Mips16TargetLowering::emitSelT16
580 (unsigned Opc1, unsigned Opc2,
581 MachineInstr *MI, MachineBasicBlock *BB) const {
582 if (DontExpandCondPseudos16)
583 return BB;
584 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
585 DebugLoc DL = MI->getDebugLoc();
586 // To "insert" a SELECT_CC instruction, we actually have to insert the
587 // diamond control-flow pattern. The incoming instruction knows the
588 // destination vreg to set, the condition code register to branch on, the
589 // true/false values to select between, and a branch opcode to use.
590 const BasicBlock *LLVM_BB = BB->getBasicBlock();
591 MachineFunction::iterator It = BB;
592 ++It;
593
594 // thisMBB:
595 // ...
596 // TrueVal = ...
597 // setcc r1, r2, r3
598 // bNE r1, r0, copy1MBB
599 // fallthrough --> copy0MBB
600 MachineBasicBlock *thisMBB = BB;
601 MachineFunction *F = BB->getParent();
602 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
603 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
604 F->insert(It, copy0MBB);
605 F->insert(It, sinkMBB);
606
607 // Transfer the remainder of BB and its successor edges to sinkMBB.
608 sinkMBB->splice(sinkMBB->begin(), BB,
609 std::next(MachineBasicBlock::iterator(MI)), BB->end());
610 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
611
612 // Next, add the true and fallthrough blocks as its successors.
613 BB->addSuccessor(copy0MBB);
614 BB->addSuccessor(sinkMBB);
615
616 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
617 .addReg(MI->getOperand(4).getReg());
618 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
619
620 // copy0MBB:
621 // %FalseValue = ...
622 // # fallthrough to sinkMBB
623 BB = copy0MBB;
624
625 // Update machine-CFG edges
626 BB->addSuccessor(sinkMBB);
627
628 // sinkMBB:
629 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
630 // ...
631 BB = sinkMBB;
632
633 BuildMI(*BB, BB->begin(), DL,
634 TII->get(Mips::PHI), MI->getOperand(0).getReg())
635 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
636 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
637
638 MI->eraseFromParent(); // The pseudo instruction is gone now.
639 return BB;
640
641}
642
643MachineBasicBlock *Mips16TargetLowering::emitSeliT16
644 (unsigned Opc1, unsigned Opc2,
645 MachineInstr *MI, MachineBasicBlock *BB) const {
646 if (DontExpandCondPseudos16)
647 return BB;
648 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
649 DebugLoc DL = MI->getDebugLoc();
650 // To "insert" a SELECT_CC instruction, we actually have to insert the
651 // diamond control-flow pattern. The incoming instruction knows the
652 // destination vreg to set, the condition code register to branch on, the
653 // true/false values to select between, and a branch opcode to use.
654 const BasicBlock *LLVM_BB = BB->getBasicBlock();
655 MachineFunction::iterator It = BB;
656 ++It;
657
658 // thisMBB:
659 // ...
660 // TrueVal = ...
661 // setcc r1, r2, r3
662 // bNE r1, r0, copy1MBB
663 // fallthrough --> copy0MBB
664 MachineBasicBlock *thisMBB = BB;
665 MachineFunction *F = BB->getParent();
666 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
667 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
668 F->insert(It, copy0MBB);
669 F->insert(It, sinkMBB);
670
671 // Transfer the remainder of BB and its successor edges to sinkMBB.
672 sinkMBB->splice(sinkMBB->begin(), BB,
673 std::next(MachineBasicBlock::iterator(MI)), BB->end());
674 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
675
676 // Next, add the true and fallthrough blocks as its successors.
677 BB->addSuccessor(copy0MBB);
678 BB->addSuccessor(sinkMBB);
679
680 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
681 .addImm(MI->getOperand(4).getImm());
682 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
683
684 // copy0MBB:
685 // %FalseValue = ...
686 // # fallthrough to sinkMBB
687 BB = copy0MBB;
688
689 // Update machine-CFG edges
690 BB->addSuccessor(sinkMBB);
691
692 // sinkMBB:
693 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
694 // ...
695 BB = sinkMBB;
696
697 BuildMI(*BB, BB->begin(), DL,
698 TII->get(Mips::PHI), MI->getOperand(0).getReg())
699 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
700 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
701
702 MI->eraseFromParent(); // The pseudo instruction is gone now.
703 return BB;
704
705}
706
707MachineBasicBlock
708 *Mips16TargetLowering::emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
709 MachineInstr *MI,
710 MachineBasicBlock *BB) const {
711 if (DontExpandCondPseudos16)
712 return BB;
713 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
714 unsigned regX = MI->getOperand(0).getReg();
715 unsigned regY = MI->getOperand(1).getReg();
716 MachineBasicBlock *target = MI->getOperand(2).getMBB();
717 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX)
718 .addReg(regY);
719 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
720 MI->eraseFromParent(); // The pseudo instruction is gone now.
721 return BB;
722}
723
724MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins(
725 unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, bool ImmSigned,
726 MachineInstr *MI, MachineBasicBlock *BB) const {
727 if (DontExpandCondPseudos16)
728 return BB;
729 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
730 unsigned regX = MI->getOperand(0).getReg();
731 int64_t imm = MI->getOperand(1).getImm();
732 MachineBasicBlock *target = MI->getOperand(2).getMBB();
733 unsigned CmpOpc;
734 if (isUInt<8>(imm))
735 CmpOpc = CmpiOpc;
736 else if ((!ImmSigned && isUInt<16>(imm)) ||
737 (ImmSigned && isInt<16>(imm)))
738 CmpOpc = CmpiXOpc;
739 else
740 llvm_unreachable("immediate field not usable");
741 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX)
742 .addImm(imm);
743 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
744 MI->eraseFromParent(); // The pseudo instruction is gone now.
745 return BB;
746}
747
748static unsigned Mips16WhichOp8uOr16simm
749 (unsigned shortOp, unsigned longOp, int64_t Imm) {
750 if (isUInt<8>(Imm))
751 return shortOp;
752 else if (isInt<16>(Imm))
753 return longOp;
754 else
755 llvm_unreachable("immediate field not usable");
756}
757
758MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRX16_ins(
759 unsigned SltOpc,
760 MachineInstr *MI, MachineBasicBlock *BB) const {
761 if (DontExpandCondPseudos16)
762 return BB;
763 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
764 unsigned CC = MI->getOperand(0).getReg();
765 unsigned regX = MI->getOperand(1).getReg();
766 unsigned regY = MI->getOperand(2).getReg();
767 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(SltOpc)).addReg(regX).addReg(
768 regY);
769 BuildMI(*BB, MI, MI->getDebugLoc(),
770 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8);
771 MI->eraseFromParent(); // The pseudo instruction is gone now.
772 return BB;
773}
774
775MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRXI16_ins(
776 unsigned SltiOpc, unsigned SltiXOpc,
777 MachineInstr *MI, MachineBasicBlock *BB )const {
778 if (DontExpandCondPseudos16)
779 return BB;
780 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
781 unsigned CC = MI->getOperand(0).getReg();
782 unsigned regX = MI->getOperand(1).getReg();
783 int64_t Imm = MI->getOperand(2).getImm();
784 unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm);
785 BuildMI(*BB, MI, MI->getDebugLoc(),
786 TII->get(SltOpc)).addReg(regX).addImm(Imm);
787 BuildMI(*BB, MI, MI->getDebugLoc(),
788 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8);
789 MI->eraseFromParent(); // The pseudo instruction is gone now.
790 return BB;
791
792}