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Mips.td (277320) Mips.td (283526)
1//===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// This is the top level entry point for the Mips target.
10//===----------------------------------------------------------------------===//
11
12//===----------------------------------------------------------------------===//
13// Target-independent interfaces
14//===----------------------------------------------------------------------===//
15
16include "llvm/Target/Target.td"
17
18// The overall idea of the PredicateControl class is to chop the Predicates list
19// into subsets that are usually overridden independently. This allows
20// subclasses to partially override the predicates of their superclasses without
21// having to re-add all the existing predicates.
22class PredicateControl {
23 // Predicates for the encoding scheme in use such as HasStdEnc
24 list<Predicate> EncodingPredicates = [];
25 // Predicates for the GPR size such as IsGP64bit
26 list<Predicate> GPRPredicates = [];
27 // Predicates for the FGR size and layout such as IsFP64bit
28 list<Predicate> FGRPredicates = [];
29 // Predicates for the instruction group membership such as ISA's and ASE's
30 list<Predicate> InsnPredicates = [];
31 // Predicates for anything else
32 list<Predicate> AdditionalPredicates = [];
33 list<Predicate> Predicates = !listconcat(EncodingPredicates,
34 GPRPredicates,
35 FGRPredicates,
36 InsnPredicates,
37 AdditionalPredicates);
38}
39
40// Like Requires<> but for the AdditionalPredicates list
41class AdditionalRequires<list<Predicate> preds> {
42 list<Predicate> AdditionalPredicates = preds;
43}
44
45//===----------------------------------------------------------------------===//
46// Register File, Calling Conv, Instruction Descriptions
47//===----------------------------------------------------------------------===//
48
49include "MipsRegisterInfo.td"
50include "MipsSchedule.td"
51include "MipsInstrInfo.td"
52include "MipsCallingConv.td"
53
54def MipsInstrInfo : InstrInfo;
55
56//===----------------------------------------------------------------------===//
57// Mips Subtarget features //
58//===----------------------------------------------------------------------===//
59
60def FeatureNoABICalls : SubtargetFeature<"noabicalls", "NoABICalls", "true",
1//===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// This is the top level entry point for the Mips target.
10//===----------------------------------------------------------------------===//
11
12//===----------------------------------------------------------------------===//
13// Target-independent interfaces
14//===----------------------------------------------------------------------===//
15
16include "llvm/Target/Target.td"
17
18// The overall idea of the PredicateControl class is to chop the Predicates list
19// into subsets that are usually overridden independently. This allows
20// subclasses to partially override the predicates of their superclasses without
21// having to re-add all the existing predicates.
22class PredicateControl {
23 // Predicates for the encoding scheme in use such as HasStdEnc
24 list<Predicate> EncodingPredicates = [];
25 // Predicates for the GPR size such as IsGP64bit
26 list<Predicate> GPRPredicates = [];
27 // Predicates for the FGR size and layout such as IsFP64bit
28 list<Predicate> FGRPredicates = [];
29 // Predicates for the instruction group membership such as ISA's and ASE's
30 list<Predicate> InsnPredicates = [];
31 // Predicates for anything else
32 list<Predicate> AdditionalPredicates = [];
33 list<Predicate> Predicates = !listconcat(EncodingPredicates,
34 GPRPredicates,
35 FGRPredicates,
36 InsnPredicates,
37 AdditionalPredicates);
38}
39
40// Like Requires<> but for the AdditionalPredicates list
41class AdditionalRequires<list<Predicate> preds> {
42 list<Predicate> AdditionalPredicates = preds;
43}
44
45//===----------------------------------------------------------------------===//
46// Register File, Calling Conv, Instruction Descriptions
47//===----------------------------------------------------------------------===//
48
49include "MipsRegisterInfo.td"
50include "MipsSchedule.td"
51include "MipsInstrInfo.td"
52include "MipsCallingConv.td"
53
54def MipsInstrInfo : InstrInfo;
55
56//===----------------------------------------------------------------------===//
57// Mips Subtarget features //
58//===----------------------------------------------------------------------===//
59
60def FeatureNoABICalls : SubtargetFeature<"noabicalls", "NoABICalls", "true",
61 "Disable SVR4-style position-independent code.">;
61 "Disable SVR4-style position-independent code">;
62def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
62def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
63 "General Purpose Registers are 64-bit wide.">;
63 "General Purpose Registers are 64-bit wide">;
64def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
64def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
65 "Support 64-bit FP registers.">;
65 "Support 64-bit FP registers">;
66def FeatureFPXX : SubtargetFeature<"fpxx", "IsFPXX", "true",
66def FeatureFPXX : SubtargetFeature<"fpxx", "IsFPXX", "true",
67 "Support for FPXX.">;
67 "Support for FPXX">;
68def FeatureNaN2008 : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
68def FeatureNaN2008 : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
69 "IEEE 754-2008 NaN encoding.">;
69 "IEEE 754-2008 NaN encoding">;
70def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
71 "true", "Only supports single precision float">;
72def FeatureO32 : SubtargetFeature<"o32", "ABI", "MipsABIInfo::O32()",
73 "Enable o32 ABI">;
74def FeatureN32 : SubtargetFeature<"n32", "ABI", "MipsABIInfo::N32()",
75 "Enable n32 ABI">;
76def FeatureN64 : SubtargetFeature<"n64", "ABI", "MipsABIInfo::N64()",
77 "Enable n64 ABI">;
78def FeatureEABI : SubtargetFeature<"eabi", "ABI", "MipsABIInfo::EABI()",
79 "Enable eabi ABI">;
80def FeatureNoOddSPReg : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false",
81 "Disable odd numbered single-precision "
82 "registers">;
83def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
70def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
71 "true", "Only supports single precision float">;
72def FeatureO32 : SubtargetFeature<"o32", "ABI", "MipsABIInfo::O32()",
73 "Enable o32 ABI">;
74def FeatureN32 : SubtargetFeature<"n32", "ABI", "MipsABIInfo::N32()",
75 "Enable n32 ABI">;
76def FeatureN64 : SubtargetFeature<"n64", "ABI", "MipsABIInfo::N64()",
77 "Enable n64 ABI">;
78def FeatureEABI : SubtargetFeature<"eabi", "ABI", "MipsABIInfo::EABI()",
79 "Enable eabi ABI">;
80def FeatureNoOddSPReg : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false",
81 "Disable odd numbered single-precision "
82 "registers">;
83def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
84 "true", "Enable vector FPU instructions.">;
84 "true", "Enable vector FPU instructions">;
85def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
86 "Mips I ISA Support [highly experimental]">;
87def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
88 "Mips II ISA Support [highly experimental]",
89 [FeatureMips1]>;
90def FeatureMips3_32 : SubtargetFeature<"mips3_32", "HasMips3_32", "true",
91 "Subset of MIPS-III that is also in MIPS32 "
92 "[highly experimental]">;
93def FeatureMips3_32r2 : SubtargetFeature<"mips3_32r2", "HasMips3_32r2", "true",
94 "Subset of MIPS-III that is also in MIPS32r2 "
95 "[highly experimental]">;
96def FeatureMips3 : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
97 "MIPS III ISA Support [highly experimental]",
98 [FeatureMips2, FeatureMips3_32,
99 FeatureMips3_32r2, FeatureGP64Bit,
100 FeatureFP64Bit]>;
101def FeatureMips4_32 : SubtargetFeature<"mips4_32", "HasMips4_32", "true",
102 "Subset of MIPS-IV that is also in MIPS32 "
103 "[highly experimental]">;
104def FeatureMips4_32r2 : SubtargetFeature<"mips4_32r2", "HasMips4_32r2", "true",
105 "Subset of MIPS-IV that is also in MIPS32r2 "
106 "[highly experimental]">;
107def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion",
108 "Mips4", "MIPS IV ISA Support",
109 [FeatureMips3, FeatureMips4_32,
110 FeatureMips4_32r2]>;
111def FeatureMips5_32r2 : SubtargetFeature<"mips5_32r2", "HasMips5_32r2", "true",
112 "Subset of MIPS-V that is also in MIPS32r2 "
113 "[highly experimental]">;
114def FeatureMips5 : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
115 "MIPS V ISA Support [highly experimental]",
116 [FeatureMips4, FeatureMips5_32r2]>;
117def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
118 "Mips32 ISA Support",
119 [FeatureMips2, FeatureMips3_32,
120 FeatureMips4_32]>;
121def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
122 "Mips32r2", "Mips32r2 ISA Support",
123 [FeatureMips3_32r2, FeatureMips4_32r2,
124 FeatureMips5_32r2, FeatureMips32]>;
125def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion",
126 "Mips32r6",
127 "Mips32r6 ISA Support [experimental]",
128 [FeatureMips32r2, FeatureFP64Bit,
129 FeatureNaN2008]>;
130def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion",
131 "Mips64", "Mips64 ISA Support",
132 [FeatureMips5, FeatureMips32]>;
133def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion",
134 "Mips64r2", "Mips64r2 ISA Support",
135 [FeatureMips64, FeatureMips32r2]>;
136def FeatureMips64r6 : SubtargetFeature<"mips64r6", "MipsArchVersion",
137 "Mips64r6",
138 "Mips64r6 ISA Support [experimental]",
139 [FeatureMips32r6, FeatureMips64r2,
140 FeatureNaN2008]>;
141
142def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true",
143 "Mips16 mode">;
144
145def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
146def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
147 "Mips DSP-R2 ASE", [FeatureDSP]>;
148
149def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
150
151def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
152 "microMips mode">;
153
154def FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips",
155 "true", "Octeon cnMIPS Support",
156 [FeatureMips64r2]>;
157
158//===----------------------------------------------------------------------===//
159// Mips processors supported.
160//===----------------------------------------------------------------------===//
161
162class Proc<string Name, list<SubtargetFeature> Features>
163 : Processor<Name, MipsGenericItineraries, Features>;
164
165def : Proc<"mips1", [FeatureMips1, FeatureO32]>;
166def : Proc<"mips2", [FeatureMips2, FeatureO32]>;
167def : Proc<"mips32", [FeatureMips32, FeatureO32]>;
168def : Proc<"mips32r2", [FeatureMips32r2, FeatureO32]>;
169def : Proc<"mips32r6", [FeatureMips32r6, FeatureO32]>;
170
171def : Proc<"mips3", [FeatureMips3, FeatureN64]>;
172def : Proc<"mips4", [FeatureMips4, FeatureN64]>;
173def : Proc<"mips5", [FeatureMips5, FeatureN64]>;
174def : Proc<"mips64", [FeatureMips64, FeatureN64]>;
175def : Proc<"mips64r2", [FeatureMips64r2, FeatureN64]>;
176def : Proc<"mips64r6", [FeatureMips64r6, FeatureN64]>;
177def : Proc<"mips16", [FeatureMips16, FeatureO32]>;
178def : Proc<"octeon", [FeatureMips64r2, FeatureN64, FeatureCnMips]>;
179
180def MipsAsmParser : AsmParser {
181 let ShouldEmitMatchRegisterName = 0;
182 let MnemonicContainsDot = 1;
183}
184
185def MipsAsmParserVariant : AsmParserVariant {
186 int Variant = 0;
187
188 // Recognize hard coded registers.
189 string RegisterPrefix = "$";
190}
191
192def Mips : Target {
193 let InstructionSet = MipsInstrInfo;
194 let AssemblyParsers = [MipsAsmParser];
195 let AssemblyParserVariants = [MipsAsmParserVariant];
196}
85def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
86 "Mips I ISA Support [highly experimental]">;
87def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
88 "Mips II ISA Support [highly experimental]",
89 [FeatureMips1]>;
90def FeatureMips3_32 : SubtargetFeature<"mips3_32", "HasMips3_32", "true",
91 "Subset of MIPS-III that is also in MIPS32 "
92 "[highly experimental]">;
93def FeatureMips3_32r2 : SubtargetFeature<"mips3_32r2", "HasMips3_32r2", "true",
94 "Subset of MIPS-III that is also in MIPS32r2 "
95 "[highly experimental]">;
96def FeatureMips3 : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
97 "MIPS III ISA Support [highly experimental]",
98 [FeatureMips2, FeatureMips3_32,
99 FeatureMips3_32r2, FeatureGP64Bit,
100 FeatureFP64Bit]>;
101def FeatureMips4_32 : SubtargetFeature<"mips4_32", "HasMips4_32", "true",
102 "Subset of MIPS-IV that is also in MIPS32 "
103 "[highly experimental]">;
104def FeatureMips4_32r2 : SubtargetFeature<"mips4_32r2", "HasMips4_32r2", "true",
105 "Subset of MIPS-IV that is also in MIPS32r2 "
106 "[highly experimental]">;
107def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion",
108 "Mips4", "MIPS IV ISA Support",
109 [FeatureMips3, FeatureMips4_32,
110 FeatureMips4_32r2]>;
111def FeatureMips5_32r2 : SubtargetFeature<"mips5_32r2", "HasMips5_32r2", "true",
112 "Subset of MIPS-V that is also in MIPS32r2 "
113 "[highly experimental]">;
114def FeatureMips5 : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
115 "MIPS V ISA Support [highly experimental]",
116 [FeatureMips4, FeatureMips5_32r2]>;
117def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
118 "Mips32 ISA Support",
119 [FeatureMips2, FeatureMips3_32,
120 FeatureMips4_32]>;
121def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
122 "Mips32r2", "Mips32r2 ISA Support",
123 [FeatureMips3_32r2, FeatureMips4_32r2,
124 FeatureMips5_32r2, FeatureMips32]>;
125def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion",
126 "Mips32r6",
127 "Mips32r6 ISA Support [experimental]",
128 [FeatureMips32r2, FeatureFP64Bit,
129 FeatureNaN2008]>;
130def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion",
131 "Mips64", "Mips64 ISA Support",
132 [FeatureMips5, FeatureMips32]>;
133def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion",
134 "Mips64r2", "Mips64r2 ISA Support",
135 [FeatureMips64, FeatureMips32r2]>;
136def FeatureMips64r6 : SubtargetFeature<"mips64r6", "MipsArchVersion",
137 "Mips64r6",
138 "Mips64r6 ISA Support [experimental]",
139 [FeatureMips32r6, FeatureMips64r2,
140 FeatureNaN2008]>;
141
142def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true",
143 "Mips16 mode">;
144
145def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
146def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
147 "Mips DSP-R2 ASE", [FeatureDSP]>;
148
149def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
150
151def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
152 "microMips mode">;
153
154def FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips",
155 "true", "Octeon cnMIPS Support",
156 [FeatureMips64r2]>;
157
158//===----------------------------------------------------------------------===//
159// Mips processors supported.
160//===----------------------------------------------------------------------===//
161
162class Proc<string Name, list<SubtargetFeature> Features>
163 : Processor<Name, MipsGenericItineraries, Features>;
164
165def : Proc<"mips1", [FeatureMips1, FeatureO32]>;
166def : Proc<"mips2", [FeatureMips2, FeatureO32]>;
167def : Proc<"mips32", [FeatureMips32, FeatureO32]>;
168def : Proc<"mips32r2", [FeatureMips32r2, FeatureO32]>;
169def : Proc<"mips32r6", [FeatureMips32r6, FeatureO32]>;
170
171def : Proc<"mips3", [FeatureMips3, FeatureN64]>;
172def : Proc<"mips4", [FeatureMips4, FeatureN64]>;
173def : Proc<"mips5", [FeatureMips5, FeatureN64]>;
174def : Proc<"mips64", [FeatureMips64, FeatureN64]>;
175def : Proc<"mips64r2", [FeatureMips64r2, FeatureN64]>;
176def : Proc<"mips64r6", [FeatureMips64r6, FeatureN64]>;
177def : Proc<"mips16", [FeatureMips16, FeatureO32]>;
178def : Proc<"octeon", [FeatureMips64r2, FeatureN64, FeatureCnMips]>;
179
180def MipsAsmParser : AsmParser {
181 let ShouldEmitMatchRegisterName = 0;
182 let MnemonicContainsDot = 1;
183}
184
185def MipsAsmParserVariant : AsmParserVariant {
186 int Variant = 0;
187
188 // Recognize hard coded registers.
189 string RegisterPrefix = "$";
190}
191
192def Mips : Target {
193 let InstructionSet = MipsInstrInfo;
194 let AssemblyParsers = [MipsAsmParser];
195 let AssemblyParserVariants = [MipsAsmParserVariant];
196}