| MipsMCTargetDesc.h (239462) | MipsMCTargetDesc.h (241430) |
|---|---|
| 1//===-- MipsMCTargetDesc.h - Mips Target Descriptions -----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 28 unchanged lines hidden (view full) --- 37 const MCRegisterInfo &MRI, 38 const MCSubtargetInfo &STI, 39 MCContext &Ctx); 40MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, 41 const MCRegisterInfo &MRI, 42 const MCSubtargetInfo &STI, 43 MCContext &Ctx); 44 | 1//===-- MipsMCTargetDesc.h - Mips Target Descriptions -----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 28 unchanged lines hidden (view full) --- 37 const MCRegisterInfo &MRI, 38 const MCSubtargetInfo &STI, 39 MCContext &Ctx); 40MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, 41 const MCRegisterInfo &MRI, 42 const MCSubtargetInfo &STI, 43 MCContext &Ctx); 44 |
| 45MCAsmBackend *createMipsAsmBackendEB32(const Target &T, StringRef TT); 46MCAsmBackend *createMipsAsmBackendEL32(const Target &T, StringRef TT); 47MCAsmBackend *createMipsAsmBackendEB64(const Target &T, StringRef TT); 48MCAsmBackend *createMipsAsmBackendEL64(const Target &T, StringRef TT); | 45MCAsmBackend *createMipsAsmBackendEB32(const Target &T, StringRef TT, 46 StringRef CPU); 47MCAsmBackend *createMipsAsmBackendEL32(const Target &T, StringRef TT, 48 StringRef CPU); 49MCAsmBackend *createMipsAsmBackendEB64(const Target &T, StringRef TT, 50 StringRef CPU); 51MCAsmBackend *createMipsAsmBackendEL64(const Target &T, StringRef TT, 52 StringRef CPU); |
| 49 50MCObjectWriter *createMipsELFObjectWriter(raw_ostream &OS, 51 uint8_t OSABI, 52 bool IsLittleEndian, 53 bool Is64Bit); 54} // End llvm namespace 55 56// Defines symbolic names for Mips registers. This defines a mapping from --- 12 unchanged lines hidden --- | 53 54MCObjectWriter *createMipsELFObjectWriter(raw_ostream &OS, 55 uint8_t OSABI, 56 bool IsLittleEndian, 57 bool Is64Bit); 58} // End llvm namespace 59 60// Defines symbolic names for Mips registers. This defines a mapping from --- 12 unchanged lines hidden --- |