Cross Reference: /freebsd-11.0-release/contrib/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp

1//===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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245 uint64_t Address,
246 const void *Decoder);
247
248static DecodeStatus DecodeMem(MCInst &Inst,
249 unsigned Insn,
250 uint64_t Address,
251 const void *Decoder);
252

253static DecodeStatus DecodeCacheOp(MCInst &Inst,
254 unsigned Insn,
255 uint64_t Address,
256 const void *Decoder);
257

253static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
254 uint64_t Address, const void *Decoder);
255
256static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
257 unsigned Insn,
258 uint64_t Address,
259 const void *Decoder);
260
261static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
262 unsigned Insn,
263 uint64_t Address,
264 const void *Decoder);
265
266static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
267 uint64_t Address,
268 const void *Decoder);
269

258static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
259 uint64_t Address, const void *Decoder);
260
261static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
262 unsigned Insn,
263 uint64_t Address,
264 const void *Decoder);
265
266static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
267 unsigned Insn,
268 uint64_t Address,
269 const void *Decoder);
270
271static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
272 uint64_t Address,
273 const void *Decoder);
274

275static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
276 uint64_t Address,
277 const void *Decoder);
278
279static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
280 uint64_t Address,
281 const void *Decoder);
282

270static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
271 unsigned Insn,
272 uint64_t Address,
273 const void *Decoder);
274
275static DecodeStatus DecodeSimm16(MCInst &Inst,
276 unsigned Insn,
277 uint64_t Address,

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446 // We have:
447 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
448 // BOVC if rs >= rt
449 // BEQZALC if rs == 0 && rt != 0
450 // BEQC if rs < rt && rs != 0
451
452 InsnType Rs = fieldFromInstruction(insn, 21, 5);
453 InsnType Rt = fieldFromInstruction(insn, 16, 5);

283static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
284 unsigned Insn,
285 uint64_t Address,
286 const void *Decoder);
287
288static DecodeStatus DecodeSimm16(MCInst &Inst,
289 unsigned Insn,
290 uint64_t Address,

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459 // We have:
460 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
461 // BOVC if rs >= rt
462 // BEQZALC if rs == 0 && rt != 0
463 // BEQC if rs < rt && rs != 0
464
465 InsnType Rs = fieldFromInstruction(insn, 21, 5);
466 InsnType Rt = fieldFromInstruction(insn, 16, 5);

454 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;

467 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;

455 bool HasRs = false;
456
457 if (Rs >= Rt) {
458 MI.setOpcode(Mips::BOVC);
459 HasRs = true;
460 } else if (Rs != 0 && Rs < Rt) {
461 MI.setOpcode(Mips::BEQC);
462 HasRs = true;

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485 // We have:
486 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
487 // BNVC if rs >= rt
488 // BNEZALC if rs == 0 && rt != 0
489 // BNEC if rs < rt && rs != 0
490
491 InsnType Rs = fieldFromInstruction(insn, 21, 5);
492 InsnType Rt = fieldFromInstruction(insn, 16, 5);

468 bool HasRs = false;
469
470 if (Rs >= Rt) {
471 MI.setOpcode(Mips::BOVC);
472 HasRs = true;
473 } else if (Rs != 0 && Rs < Rt) {
474 MI.setOpcode(Mips::BEQC);
475 HasRs = true;

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498 // We have:
499 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
500 // BNVC if rs >= rt
501 // BNEZALC if rs == 0 && rt != 0
502 // BNEC if rs < rt && rs != 0
503
504 InsnType Rs = fieldFromInstruction(insn, 21, 5);
505 InsnType Rt = fieldFromInstruction(insn, 16, 5);

493 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;

506 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;

494 bool HasRs = false;
495
496 if (Rs >= Rt) {
497 MI.setOpcode(Mips::BNVC);
498 HasRs = true;
499 } else if (Rs != 0 && Rs < Rt) {
500 MI.setOpcode(Mips::BNEC);
501 HasRs = true;

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525 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
526 // Invalid if rs == 0
527 // BLEZC if rs == 0 && rt != 0
528 // BGEZC if rs == rt && rt != 0
529 // BGEC if rs != rt && rs != 0 && rt != 0
530
531 InsnType Rs = fieldFromInstruction(insn, 21, 5);
532 InsnType Rt = fieldFromInstruction(insn, 16, 5);

507 bool HasRs = false;
508
509 if (Rs >= Rt) {
510 MI.setOpcode(Mips::BNVC);
511 HasRs = true;
512 } else if (Rs != 0 && Rs < Rt) {
513 MI.setOpcode(Mips::BNEC);
514 HasRs = true;

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538 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
539 // Invalid if rs == 0
540 // BLEZC if rs == 0 && rt != 0
541 // BGEZC if rs == rt && rt != 0
542 // BGEC if rs != rt && rs != 0 && rt != 0
543
544 InsnType Rs = fieldFromInstruction(insn, 21, 5);
545 InsnType Rt = fieldFromInstruction(insn, 16, 5);

533 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;

546 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;

534 bool HasRs = false;
535
536 if (Rt == 0)
537 return MCDisassembler::Fail;
538 else if (Rs == 0)
539 MI.setOpcode(Mips::BLEZC);
540 else if (Rs == Rt)
541 MI.setOpcode(Mips::BGEZC);

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570 // BGTZC if rs == 0 && rt != 0
571 // BLTZC if rs == rt && rt != 0
572 // BLTC if rs != rt && rs != 0 && rt != 0
573
574 bool HasRs = false;
575
576 InsnType Rs = fieldFromInstruction(insn, 21, 5);
577 InsnType Rt = fieldFromInstruction(insn, 16, 5);

547 bool HasRs = false;
548
549 if (Rt == 0)
550 return MCDisassembler::Fail;
551 else if (Rs == 0)
552 MI.setOpcode(Mips::BLEZC);
553 else if (Rs == Rt)
554 MI.setOpcode(Mips::BGEZC);

--- 28 unchanged lines hidden (view full) ---

583 // BGTZC if rs == 0 && rt != 0
584 // BLTZC if rs == rt && rt != 0
585 // BLTC if rs != rt && rs != 0 && rt != 0
586
587 bool HasRs = false;
588
589 InsnType Rs = fieldFromInstruction(insn, 21, 5);
590 InsnType Rt = fieldFromInstruction(insn, 16, 5);

578 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;

591 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;

579
580 if (Rt == 0)
581 return MCDisassembler::Fail;
582 else if (Rs == 0)
583 MI.setOpcode(Mips::BGTZC);
584 else if (Rs == Rt)
585 MI.setOpcode(Mips::BLTZC);
586 else {

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612 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
613 // BGTZ if rt == 0
614 // BGTZALC if rs == 0 && rt != 0
615 // BLTZALC if rs != 0 && rs == rt
616 // BLTUC if rs != 0 && rs != rt
617
618 InsnType Rs = fieldFromInstruction(insn, 21, 5);
619 InsnType Rt = fieldFromInstruction(insn, 16, 5);

592
593 if (Rt == 0)
594 return MCDisassembler::Fail;
595 else if (Rs == 0)
596 MI.setOpcode(Mips::BGTZC);
597 else if (Rs == Rt)
598 MI.setOpcode(Mips::BLTZC);
599 else {

--- 25 unchanged lines hidden (view full) ---

625 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
626 // BGTZ if rt == 0
627 // BGTZALC if rs == 0 && rt != 0
628 // BLTZALC if rs != 0 && rs == rt
629 // BLTUC if rs != 0 && rs != rt
630
631 InsnType Rs = fieldFromInstruction(insn, 21, 5);
632 InsnType Rt = fieldFromInstruction(insn, 16, 5);

620 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;

633 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;

621 bool HasRs = false;
622 bool HasRt = false;
623
624 if (Rt == 0) {
625 MI.setOpcode(Mips::BGTZ);
626 HasRs = true;
627 } else if (Rs == 0) {
628 MI.setOpcode(Mips::BGTZALC);

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661 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
662 // Invalid if rs == 0
663 // BLEZALC if rs == 0 && rt != 0
664 // BGEZALC if rs == rt && rt != 0
665 // BGEUC if rs != rt && rs != 0 && rt != 0
666
667 InsnType Rs = fieldFromInstruction(insn, 21, 5);
668 InsnType Rt = fieldFromInstruction(insn, 16, 5);

634 bool HasRs = false;
635 bool HasRt = false;
636
637 if (Rt == 0) {
638 MI.setOpcode(Mips::BGTZ);
639 HasRs = true;
640 } else if (Rs == 0) {
641 MI.setOpcode(Mips::BGTZALC);

--- 32 unchanged lines hidden (view full) ---

674 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
675 // Invalid if rs == 0
676 // BLEZALC if rs == 0 && rt != 0
677 // BGEZALC if rs == rt && rt != 0
678 // BGEUC if rs != rt && rs != 0 && rt != 0
679
680 InsnType Rs = fieldFromInstruction(insn, 21, 5);
681 InsnType Rt = fieldFromInstruction(insn, 16, 5);

669 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;

682 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;

670 bool HasRs = false;
671
672 if (Rt == 0)
673 return MCDisassembler::Fail;
674 else if (Rs == 0)
675 MI.setOpcode(Mips::BLEZALC);
676 else if (Rs == Rt)
677 MI.setOpcode(Mips::BGEZALC);

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959
960 Inst.addOperand(MCOperand::CreateReg(Reg));
961 Inst.addOperand(MCOperand::CreateReg(Base));
962 Inst.addOperand(MCOperand::CreateImm(Offset));
963
964 return MCDisassembler::Success;
965}
966

683 bool HasRs = false;
684
685 if (Rt == 0)
686 return MCDisassembler::Fail;
687 else if (Rs == 0)
688 MI.setOpcode(Mips::BLEZALC);
689 else if (Rs == Rt)
690 MI.setOpcode(Mips::BGEZALC);

--- 281 unchanged lines hidden (view full) ---

972
973 Inst.addOperand(MCOperand::CreateReg(Reg));
974 Inst.addOperand(MCOperand::CreateReg(Base));
975 Inst.addOperand(MCOperand::CreateImm(Offset));
976
977 return MCDisassembler::Success;
978}
979

980static DecodeStatus DecodeCacheOp(MCInst &Inst,
981 unsigned Insn,
982 uint64_t Address,
983 const void *Decoder) {
984 int Offset = SignExtend32<16>(Insn & 0xffff);
985 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
986 unsigned Base = fieldFromInstruction(Insn, 21, 5);
987
988 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
989
990 Inst.addOperand(MCOperand::CreateReg(Base));
991 Inst.addOperand(MCOperand::CreateImm(Offset));
992 Inst.addOperand(MCOperand::CreateImm(Hint));
993
994 return MCDisassembler::Success;
995}
996

967static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
968 uint64_t Address, const void *Decoder) {
969 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
970 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
971 unsigned Base = fieldFromInstruction(Insn, 11, 5);
972
973 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
974 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);

--- 15 unchanged lines hidden (view full) ---

990 return MCDisassembler::Fail;
991 break;
992 case Mips::LD_B:
993 case Mips::ST_B:
994 Inst.addOperand(MCOperand::CreateImm(Offset));
995 break;
996 case Mips::LD_H:
997 case Mips::ST_H:

997static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
998 uint64_t Address, const void *Decoder) {
999 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1000 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1001 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1002
1003 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1004 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);

--- 15 unchanged lines hidden (view full) ---

1020 return MCDisassembler::Fail;
1021 break;
1022 case Mips::LD_B:
1023 case Mips::ST_B:
1024 Inst.addOperand(MCOperand::CreateImm(Offset));
1025 break;
1026 case Mips::LD_H:
1027 case Mips::ST_H:

998 Inst.addOperand(MCOperand::CreateImm(Offset << 1));

1028 Inst.addOperand(MCOperand::CreateImm(Offset * 2));

999 break;
1000 case Mips::LD_W:
1001 case Mips::ST_W:

1029 break;
1030 case Mips::LD_W:
1031 case Mips::ST_W:

1002 Inst.addOperand(MCOperand::CreateImm(Offset << 2));

1032 Inst.addOperand(MCOperand::CreateImm(Offset * 4));

1003 break;
1004 case Mips::LD_D:
1005 case Mips::ST_D:

1033 break;
1034 case Mips::LD_D:
1035 case Mips::ST_D:

1006 Inst.addOperand(MCOperand::CreateImm(Offset << 3));

1036 Inst.addOperand(MCOperand::CreateImm(Offset * 8));

1007 break;
1008 }
1009
1010 return MCDisassembler::Success;
1011}
1012
1013static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1014 unsigned Insn,

--- 47 unchanged lines hidden (view full) ---

1062
1063 Inst.addOperand(MCOperand::CreateReg(Reg));
1064 Inst.addOperand(MCOperand::CreateReg(Base));
1065 Inst.addOperand(MCOperand::CreateImm(Offset));
1066
1067 return MCDisassembler::Success;
1068}
1069

1037 break;
1038 }
1039
1040 return MCDisassembler::Success;
1041}
1042
1043static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1044 unsigned Insn,

--- 47 unchanged lines hidden (view full) ---

1092
1093 Inst.addOperand(MCOperand::CreateReg(Reg));
1094 Inst.addOperand(MCOperand::CreateReg(Base));
1095 Inst.addOperand(MCOperand::CreateImm(Offset));
1096
1097 return MCDisassembler::Success;
1098}
1099

1100static DecodeStatus DecodeFMem2(MCInst &Inst,
1101 unsigned Insn,
1102 uint64_t Address,
1103 const void *Decoder) {
1104 int Offset = SignExtend32<16>(Insn & 0xffff);
1105 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1106 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1107
1108 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1109 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1110
1111 Inst.addOperand(MCOperand::CreateReg(Reg));
1112 Inst.addOperand(MCOperand::CreateReg(Base));
1113 Inst.addOperand(MCOperand::CreateImm(Offset));
1114
1115 return MCDisassembler::Success;
1116}
1117
1118static DecodeStatus DecodeFMem3(MCInst &Inst,
1119 unsigned Insn,
1120 uint64_t Address,
1121 const void *Decoder) {
1122 int Offset = SignExtend32<16>(Insn & 0xffff);
1123 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1124 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1125
1126 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1127 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1128
1129 Inst.addOperand(MCOperand::CreateReg(Reg));
1130 Inst.addOperand(MCOperand::CreateReg(Base));
1131 Inst.addOperand(MCOperand::CreateImm(Offset));
1132
1133 return MCDisassembler::Success;
1134}
1135

1070static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1071 unsigned Insn,
1072 uint64_t Address,
1073 const void *Decoder) {
1074 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1075 unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1076 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1077

--- 142 unchanged lines hidden (view full) ---

1220 Inst.addOperand(MCOperand::CreateReg(Reg));
1221 return MCDisassembler::Success;
1222}
1223
1224static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1225 unsigned Offset,
1226 uint64_t Address,
1227 const void *Decoder) {

1136static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1137 unsigned Insn,
1138 uint64_t Address,
1139 const void *Decoder) {
1140 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1141 unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1142 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1143

--- 142 unchanged lines hidden (view full) ---

1286 Inst.addOperand(MCOperand::CreateReg(Reg));
1287 return MCDisassembler::Success;
1288}
1289
1290static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1291 unsigned Offset,
1292 uint64_t Address,
1293 const void *Decoder) {

1228 int32_t BranchOffset = (SignExtend32<16>(Offset) << 2) + 4;

1294 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;

1229 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1230 return MCDisassembler::Success;
1231}
1232
1233static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1234 unsigned Insn,
1235 uint64_t Address,
1236 const void *Decoder) {
1237
1238 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1239 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1240 return MCDisassembler::Success;
1241}
1242
1243static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1244 unsigned Offset,
1245 uint64_t Address,
1246 const void *Decoder) {

1295 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1296 return MCDisassembler::Success;
1297}
1298
1299static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1300 unsigned Insn,
1301 uint64_t Address,
1302 const void *Decoder) {
1303
1304 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1305 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1306 return MCDisassembler::Success;
1307}
1308
1309static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1310 unsigned Offset,
1311 uint64_t Address,
1312 const void *Decoder) {

1247 int32_t BranchOffset = SignExtend32<21>(Offset) << 2;

1313 int32_t BranchOffset = SignExtend32<21>(Offset) * 4;

1248
1249 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1250 return MCDisassembler::Success;
1251}
1252
1253static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1254 unsigned Offset,
1255 uint64_t Address,
1256 const void *Decoder) {

1314
1315 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1316 return MCDisassembler::Success;
1317}
1318
1319static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1320 unsigned Offset,
1321 uint64_t Address,
1322 const void *Decoder) {

1257 int32_t BranchOffset = SignExtend32<26>(Offset) << 2;

1323 int32_t BranchOffset = SignExtend32<26>(Offset) * 4;

1258
1259 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1260 return MCDisassembler::Success;
1261}
1262
1263static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1264 unsigned Offset,
1265 uint64_t Address,
1266 const void *Decoder) {

1324
1325 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1326 return MCDisassembler::Success;
1327}
1328
1329static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1330 unsigned Offset,
1331 uint64_t Address,
1332 const void *Decoder) {

1267 int32_t BranchOffset = SignExtend32<16>(Offset) << 1;

1333 int32_t BranchOffset = SignExtend32<16>(Offset) * 2;

1268 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1269 return MCDisassembler::Success;
1270}
1271
1272static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1273 unsigned Insn,
1274 uint64_t Address,
1275 const void *Decoder) {

--- 36 unchanged lines hidden (view full) ---

1312 const void *Decoder) {
1313 int Size = (int) Insn + 1;
1314 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1315 return MCDisassembler::Success;
1316}
1317
1318static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1319 uint64_t Address, const void *Decoder) {

1334 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1335 return MCDisassembler::Success;
1336}
1337
1338static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1339 unsigned Insn,
1340 uint64_t Address,
1341 const void *Decoder) {

--- 36 unchanged lines hidden (view full) ---

1378 const void *Decoder) {
1379 int Size = (int) Insn + 1;
1380 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1381 return MCDisassembler::Success;
1382}
1383
1384static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1385 uint64_t Address, const void *Decoder) {

1320 Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) << 2));

1386 Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4));

1321 return MCDisassembler::Success;
1322}
1323
1324static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1325 uint64_t Address, const void *Decoder) {

1387 return MCDisassembler::Success;
1388}
1389
1390static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1391 uint64_t Address, const void *Decoder) {

1326 Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) << 3));

1392 Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8));