252a253,257
> static DecodeStatus DecodeCacheOp(MCInst &Inst,
> unsigned Insn,
> uint64_t Address,
> const void *Decoder);
>
269a275,282
> static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
> uint64_t Address,
> const void *Decoder);
>
> static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
> uint64_t Address,
> const void *Decoder);
>
454c467
< InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
---
> InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
493c506
< InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
---
> InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
533c546
< InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
---
> InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
578c591
< InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
---
> InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
620c633
< InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
---
> InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
669c682
< InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
---
> InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
966a980,996
> static DecodeStatus DecodeCacheOp(MCInst &Inst,
> unsigned Insn,
> uint64_t Address,
> const void *Decoder) {
> int Offset = SignExtend32<16>(Insn & 0xffff);
> unsigned Hint = fieldFromInstruction(Insn, 16, 5);
> unsigned Base = fieldFromInstruction(Insn, 21, 5);
>
> Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
>
> Inst.addOperand(MCOperand::CreateReg(Base));
> Inst.addOperand(MCOperand::CreateImm(Offset));
> Inst.addOperand(MCOperand::CreateImm(Hint));
>
> return MCDisassembler::Success;
> }
>
998c1028
< Inst.addOperand(MCOperand::CreateImm(Offset << 1));
---
> Inst.addOperand(MCOperand::CreateImm(Offset * 2));
1002c1032
< Inst.addOperand(MCOperand::CreateImm(Offset << 2));
---
> Inst.addOperand(MCOperand::CreateImm(Offset * 4));
1006c1036
< Inst.addOperand(MCOperand::CreateImm(Offset << 3));
---
> Inst.addOperand(MCOperand::CreateImm(Offset * 8));
1069a1100,1135
> static DecodeStatus DecodeFMem2(MCInst &Inst,
> unsigned Insn,
> uint64_t Address,
> const void *Decoder) {
> int Offset = SignExtend32<16>(Insn & 0xffff);
> unsigned Reg = fieldFromInstruction(Insn, 16, 5);
> unsigned Base = fieldFromInstruction(Insn, 21, 5);
>
> Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
> Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
>
> Inst.addOperand(MCOperand::CreateReg(Reg));
> Inst.addOperand(MCOperand::CreateReg(Base));
> Inst.addOperand(MCOperand::CreateImm(Offset));
>
> return MCDisassembler::Success;
> }
>
> static DecodeStatus DecodeFMem3(MCInst &Inst,
> unsigned Insn,
> uint64_t Address,
> const void *Decoder) {
> int Offset = SignExtend32<16>(Insn & 0xffff);
> unsigned Reg = fieldFromInstruction(Insn, 16, 5);
> unsigned Base = fieldFromInstruction(Insn, 21, 5);
>
> Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
> Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
>
> Inst.addOperand(MCOperand::CreateReg(Reg));
> Inst.addOperand(MCOperand::CreateReg(Base));
> Inst.addOperand(MCOperand::CreateImm(Offset));
>
> return MCDisassembler::Success;
> }
>
1228c1294
< int32_t BranchOffset = (SignExtend32<16>(Offset) << 2) + 4;
---
> int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1247c1313
< int32_t BranchOffset = SignExtend32<21>(Offset) << 2;
---
> int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1257c1323
< int32_t BranchOffset = SignExtend32<26>(Offset) << 2;
---
> int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1267c1333
< int32_t BranchOffset = SignExtend32<16>(Offset) << 1;
---
> int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1320c1386
< Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) << 2));
---
> Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4));
1326c1392
< Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) << 3));
---
> Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8));