1//===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file is part of the Mips Disassembler.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Mips.h"
15#include "MipsRegisterInfo.h"
16#include "MipsSubtarget.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCDisassembler.h"
19#include "llvm/MC/MCFixedLenDisassembler.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCSubtargetInfo.h"
22#include "llvm/Support/MathExtras.h"
23#include "llvm/Support/MemoryObject.h"
24#include "llvm/Support/TargetRegistry.h"
25
26using namespace llvm;
27
28#define DEBUG_TYPE "mips-disassembler"
29
30typedef MCDisassembler::DecodeStatus DecodeStatus;
31
32namespace {
33
34/// MipsDisassemblerBase - a disasembler class for Mips.
35class MipsDisassemblerBase : public MCDisassembler {
36public:
37 /// Constructor - Initializes the disassembler.
38 ///
39 MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
40 bool bigEndian) :
41 MCDisassembler(STI, Ctx),
42 IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
43
44 virtual ~MipsDisassemblerBase() {}
45
46 bool isN64() const { return IsN64; }
47
48private:
49 bool IsN64;
50protected:
51 bool isBigEndian;
52};
53
54/// MipsDisassembler - a disasembler class for Mips32.
55class MipsDisassembler : public MipsDisassemblerBase {
56 bool IsMicroMips;
57public:
58 /// Constructor - Initializes the disassembler.
59 ///
60 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian)
61 : MipsDisassemblerBase(STI, Ctx, bigEndian) {
62 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
63 }
64
65 bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
66 bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
67 bool hasMips32r6() const {
68 return STI.getFeatureBits() & Mips::FeatureMips32r6;
69 }
70
71 bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
72
73 bool hasCOP3() const {
74 // Only present in MIPS-I and MIPS-II
75 return !hasMips32() && !hasMips3();
76 }
77
78 /// getInstruction - See MCDisassembler.
79 DecodeStatus getInstruction(MCInst &instr,
80 uint64_t &size,
81 const MemoryObject &region,
82 uint64_t address,
83 raw_ostream &vStream,
84 raw_ostream &cStream) const override;
85};
86
87
88/// Mips64Disassembler - a disasembler class for Mips64.
89class Mips64Disassembler : public MipsDisassemblerBase {
90public:
91 /// Constructor - Initializes the disassembler.
92 ///
93 Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
94 bool bigEndian) :
95 MipsDisassemblerBase(STI, Ctx, bigEndian) {}
96
97 /// getInstruction - See MCDisassembler.
98 DecodeStatus getInstruction(MCInst &instr,
99 uint64_t &size,
100 const MemoryObject &region,
101 uint64_t address,
102 raw_ostream &vStream,
103 raw_ostream &cStream) const override;
104};
105
106} // end anonymous namespace
107
108// Forward declare these because the autogenerated code will reference them.
109// Definitions are further down.
110static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
111 unsigned RegNo,
112 uint64_t Address,
113 const void *Decoder);
114
115static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
116 unsigned RegNo,
117 uint64_t Address,
118 const void *Decoder);
119
120static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
121 unsigned RegNo,
122 uint64_t Address,
123 const void *Decoder);
124
125static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
126 unsigned Insn,
127 uint64_t Address,
128 const void *Decoder);
129
130static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
131 unsigned RegNo,
132 uint64_t Address,
133 const void *Decoder);
134
135static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
136 unsigned RegNo,
137 uint64_t Address,
138 const void *Decoder);
139
140static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
141 unsigned RegNo,
142 uint64_t Address,
143 const void *Decoder);
144
145static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
146 unsigned RegNo,
147 uint64_t Address,
148 const void *Decoder);
149
150static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
151 unsigned RegNo,
152 uint64_t Address,
153 const void *Decoder);
154
155static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
156 uint64_t Address,
157 const void *Decoder);
158
159static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
160 unsigned Insn,
161 uint64_t Address,
162 const void *Decoder);
163
164static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
165 unsigned RegNo,
166 uint64_t Address,
167 const void *Decoder);
168
169static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
170 unsigned RegNo,
171 uint64_t Address,
172 const void *Decoder);
173
174static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
175 unsigned RegNo,
176 uint64_t Address,
177 const void *Decoder);
178
179static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
180 unsigned RegNo,
181 uint64_t Address,
182 const void *Decoder);
183
184static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
185 unsigned RegNo,
186 uint64_t Address,
187 const void *Decoder);
188
189static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
190 unsigned RegNo,
191 uint64_t Address,
192 const void *Decoder);
193
194static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
195 unsigned RegNo,
196 uint64_t Address,
197 const void *Decoder);
198
199static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
200 unsigned RegNo,
201 uint64_t Address,
202 const void *Decoder);
203
204static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
205 unsigned RegNo,
206 uint64_t Address,
207 const void *Decoder);
208
209static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
210 unsigned RegNo,
211 uint64_t Address,
212 const void *Decoder);
213
214static DecodeStatus DecodeBranchTarget(MCInst &Inst,
215 unsigned Offset,
216 uint64_t Address,
217 const void *Decoder);
218
219static DecodeStatus DecodeJumpTarget(MCInst &Inst,
220 unsigned Insn,
221 uint64_t Address,
222 const void *Decoder);
223
224static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
225 unsigned Offset,
226 uint64_t Address,
227 const void *Decoder);
228
229static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
230 unsigned Offset,
231 uint64_t Address,
232 const void *Decoder);
233
234// DecodeBranchTargetMM - Decode microMIPS branch offset, which is
235// shifted left by 1 bit.
236static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
237 unsigned Offset,
238 uint64_t Address,
239 const void *Decoder);
240
241// DecodeJumpTargetMM - Decode microMIPS jump target, which is
242// shifted left by 1 bit.
243static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
244 unsigned Insn,
245 uint64_t Address,
246 const void *Decoder);
247
248static DecodeStatus DecodeMem(MCInst &Inst,
249 unsigned Insn,
250 uint64_t Address,
251 const void *Decoder);
252
253static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
254 uint64_t Address, const void *Decoder);
255
256static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
257 unsigned Insn,
258 uint64_t Address,
259 const void *Decoder);
260
261static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
262 unsigned Insn,
263 uint64_t Address,
264 const void *Decoder);
265
266static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
267 uint64_t Address,
268 const void *Decoder);
269
270static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
271 unsigned Insn,
272 uint64_t Address,
273 const void *Decoder);
274
275static DecodeStatus DecodeSimm16(MCInst &Inst,
276 unsigned Insn,
277 uint64_t Address,
278 const void *Decoder);
279
280// Decode the immediate field of an LSA instruction which
281// is off by one.
282static DecodeStatus DecodeLSAImm(MCInst &Inst,
283 unsigned Insn,
284 uint64_t Address,
285 const void *Decoder);
286
287static DecodeStatus DecodeInsSize(MCInst &Inst,
288 unsigned Insn,
289 uint64_t Address,
290 const void *Decoder);
291
292static DecodeStatus DecodeExtSize(MCInst &Inst,
293 unsigned Insn,
294 uint64_t Address,
295 const void *Decoder);
296
297static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
298 uint64_t Address, const void *Decoder);
299
300static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
301 uint64_t Address, const void *Decoder);
302
303/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
304/// handle.
305template <typename InsnType>
306static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
307 const void *Decoder);
308
309template <typename InsnType>
310static DecodeStatus
311DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
312 const void *Decoder);
313
314template <typename InsnType>
315static DecodeStatus
316DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
317 const void *Decoder);
318
319template <typename InsnType>
320static DecodeStatus
321DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
322 const void *Decoder);
323
324template <typename InsnType>
325static DecodeStatus
326DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
327 const void *Decoder);
328
329template <typename InsnType>
330static DecodeStatus
331DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
332 const void *Decoder);
333
334template <typename InsnType>
335static DecodeStatus
336DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
337 const void *Decoder);
338
339namespace llvm {
340extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
341 TheMips64elTarget;
342}
343
344static MCDisassembler *createMipsDisassembler(
345 const Target &T,
346 const MCSubtargetInfo &STI,
347 MCContext &Ctx) {
348 return new MipsDisassembler(STI, Ctx, true);
349}
350
351static MCDisassembler *createMipselDisassembler(
352 const Target &T,
353 const MCSubtargetInfo &STI,
354 MCContext &Ctx) {
355 return new MipsDisassembler(STI, Ctx, false);
356}
357
358static MCDisassembler *createMips64Disassembler(
359 const Target &T,
360 const MCSubtargetInfo &STI,
361 MCContext &Ctx) {
362 return new Mips64Disassembler(STI, Ctx, true);
363}
364
365static MCDisassembler *createMips64elDisassembler(
366 const Target &T,
367 const MCSubtargetInfo &STI,
368 MCContext &Ctx) {
369 return new Mips64Disassembler(STI, Ctx, false);
370}
371
372extern "C" void LLVMInitializeMipsDisassembler() {
373 // Register the disassembler.
374 TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
375 createMipsDisassembler);
376 TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
377 createMipselDisassembler);
378 TargetRegistry::RegisterMCDisassembler(TheMips64Target,
379 createMips64Disassembler);
380 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
381 createMips64elDisassembler);
382}
383
384#include "MipsGenDisassemblerTables.inc"
385
386static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
387 const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
388 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
389 return *(RegInfo->getRegClass(RC).begin() + RegNo);
390}
391
392template <typename InsnType>
393static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
394 const void *Decoder) {
395 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
396 // The size of the n field depends on the element size
397 // The register class also depends on this.
398 InsnType tmp = fieldFromInstruction(insn, 17, 5);
399 unsigned NSize = 0;
400 DecodeFN RegDecoder = nullptr;
401 if ((tmp & 0x18) == 0x00) { // INSVE_B
402 NSize = 4;
403 RegDecoder = DecodeMSA128BRegisterClass;
404 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
405 NSize = 3;
406 RegDecoder = DecodeMSA128HRegisterClass;
407 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
408 NSize = 2;
409 RegDecoder = DecodeMSA128WRegisterClass;
410 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
411 NSize = 1;
412 RegDecoder = DecodeMSA128DRegisterClass;
413 } else
414 llvm_unreachable("Invalid encoding");
415
416 assert(NSize != 0 && RegDecoder != nullptr);
417
418 // $wd
419 tmp = fieldFromInstruction(insn, 6, 5);
420 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
421 return MCDisassembler::Fail;
422 // $wd_in
423 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
424 return MCDisassembler::Fail;
425 // $n
426 tmp = fieldFromInstruction(insn, 16, NSize);
427 MI.addOperand(MCOperand::CreateImm(tmp));
428 // $ws
429 tmp = fieldFromInstruction(insn, 11, 5);
430 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
431 return MCDisassembler::Fail;
432 // $n2
433 MI.addOperand(MCOperand::CreateImm(0));
434
435 return MCDisassembler::Success;
436}
437
438template <typename InsnType>
439static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
440 uint64_t Address,
441 const void *Decoder) {
442 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
443 // (otherwise we would have matched the ADDI instruction from the earlier
444 // ISA's instead).
445 //
446 // We have:
447 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
448 // BOVC if rs >= rt
449 // BEQZALC if rs == 0 && rt != 0
450 // BEQC if rs < rt && rs != 0
451
452 InsnType Rs = fieldFromInstruction(insn, 21, 5);
453 InsnType Rt = fieldFromInstruction(insn, 16, 5);
454 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
455 bool HasRs = false;
456
457 if (Rs >= Rt) {
458 MI.setOpcode(Mips::BOVC);
459 HasRs = true;
460 } else if (Rs != 0 && Rs < Rt) {
461 MI.setOpcode(Mips::BEQC);
462 HasRs = true;
463 } else
464 MI.setOpcode(Mips::BEQZALC);
465
466 if (HasRs)
467 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
468 Rs)));
469
470 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
471 Rt)));
472 MI.addOperand(MCOperand::CreateImm(Imm));
473
474 return MCDisassembler::Success;
475}
476
477template <typename InsnType>
478static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
479 uint64_t Address,
480 const void *Decoder) {
481 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
482 // (otherwise we would have matched the ADDI instruction from the earlier
483 // ISA's instead).
484 //
485 // We have:
486 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
487 // BNVC if rs >= rt
488 // BNEZALC if rs == 0 && rt != 0
489 // BNEC if rs < rt && rs != 0
490
491 InsnType Rs = fieldFromInstruction(insn, 21, 5);
492 InsnType Rt = fieldFromInstruction(insn, 16, 5);
493 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
494 bool HasRs = false;
495
496 if (Rs >= Rt) {
497 MI.setOpcode(Mips::BNVC);
498 HasRs = true;
499 } else if (Rs != 0 && Rs < Rt) {
500 MI.setOpcode(Mips::BNEC);
501 HasRs = true;
502 } else
503 MI.setOpcode(Mips::BNEZALC);
504
505 if (HasRs)
506 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
507 Rs)));
508
509 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
510 Rt)));
511 MI.addOperand(MCOperand::CreateImm(Imm));
512
513 return MCDisassembler::Success;
514}
515
516template <typename InsnType>
517static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
518 uint64_t Address,
519 const void *Decoder) {
520 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
521 // (otherwise we would have matched the BLEZL instruction from the earlier
522 // ISA's instead).
523 //
524 // We have:
525 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
526 // Invalid if rs == 0
527 // BLEZC if rs == 0 && rt != 0
528 // BGEZC if rs == rt && rt != 0
529 // BGEC if rs != rt && rs != 0 && rt != 0
530
531 InsnType Rs = fieldFromInstruction(insn, 21, 5);
532 InsnType Rt = fieldFromInstruction(insn, 16, 5);
533 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
534 bool HasRs = false;
535
536 if (Rt == 0)
537 return MCDisassembler::Fail;
538 else if (Rs == 0)
539 MI.setOpcode(Mips::BLEZC);
540 else if (Rs == Rt)
541 MI.setOpcode(Mips::BGEZC);
542 else {
543 HasRs = true;
544 MI.setOpcode(Mips::BGEC);
545 }
546
547 if (HasRs)
548 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
549 Rs)));
550
551 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
552 Rt)));
553
554 MI.addOperand(MCOperand::CreateImm(Imm));
555
556 return MCDisassembler::Success;
557}
558
559template <typename InsnType>
560static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
561 uint64_t Address,
562 const void *Decoder) {
563 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
564 // (otherwise we would have matched the BGTZL instruction from the earlier
565 // ISA's instead).
566 //
567 // We have:
568 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
569 // Invalid if rs == 0
570 // BGTZC if rs == 0 && rt != 0
571 // BLTZC if rs == rt && rt != 0
572 // BLTC if rs != rt && rs != 0 && rt != 0
573
574 bool HasRs = false;
575
576 InsnType Rs = fieldFromInstruction(insn, 21, 5);
577 InsnType Rt = fieldFromInstruction(insn, 16, 5);
578 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
579
580 if (Rt == 0)
581 return MCDisassembler::Fail;
582 else if (Rs == 0)
583 MI.setOpcode(Mips::BGTZC);
584 else if (Rs == Rt)
585 MI.setOpcode(Mips::BLTZC);
586 else {
587 MI.setOpcode(Mips::BLTC);
588 HasRs = true;
589 }
590
591 if (HasRs)
592 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
593 Rs)));
594
595 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
596 Rt)));
597
598 MI.addOperand(MCOperand::CreateImm(Imm));
599
600 return MCDisassembler::Success;
601}
602
603template <typename InsnType>
604static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
605 uint64_t Address,
606 const void *Decoder) {
607 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
608 // (otherwise we would have matched the BGTZ instruction from the earlier
609 // ISA's instead).
610 //
611 // We have:
612 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
613 // BGTZ if rt == 0
614 // BGTZALC if rs == 0 && rt != 0
615 // BLTZALC if rs != 0 && rs == rt
616 // BLTUC if rs != 0 && rs != rt
617
618 InsnType Rs = fieldFromInstruction(insn, 21, 5);
619 InsnType Rt = fieldFromInstruction(insn, 16, 5);
620 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
621 bool HasRs = false;
622 bool HasRt = false;
623
624 if (Rt == 0) {
625 MI.setOpcode(Mips::BGTZ);
626 HasRs = true;
627 } else if (Rs == 0) {
628 MI.setOpcode(Mips::BGTZALC);
629 HasRt = true;
630 } else if (Rs == Rt) {
631 MI.setOpcode(Mips::BLTZALC);
632 HasRs = true;
633 } else {
634 MI.setOpcode(Mips::BLTUC);
635 HasRs = true;
636 HasRt = true;
637 }
638
639 if (HasRs)
640 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
641 Rs)));
642
643 if (HasRt)
644 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
645 Rt)));
646
647 MI.addOperand(MCOperand::CreateImm(Imm));
648
649 return MCDisassembler::Success;
650}
651
652template <typename InsnType>
653static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
654 uint64_t Address,
655 const void *Decoder) {
656 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
657 // (otherwise we would have matched the BLEZL instruction from the earlier
658 // ISA's instead).
659 //
660 // We have:
661 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
662 // Invalid if rs == 0
663 // BLEZALC if rs == 0 && rt != 0
664 // BGEZALC if rs == rt && rt != 0
665 // BGEUC if rs != rt && rs != 0 && rt != 0
666
667 InsnType Rs = fieldFromInstruction(insn, 21, 5);
668 InsnType Rt = fieldFromInstruction(insn, 16, 5);
669 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
670 bool HasRs = false;
671
672 if (Rt == 0)
673 return MCDisassembler::Fail;
674 else if (Rs == 0)
675 MI.setOpcode(Mips::BLEZALC);
676 else if (Rs == Rt)
677 MI.setOpcode(Mips::BGEZALC);
678 else {
679 HasRs = true;
680 MI.setOpcode(Mips::BGEUC);
681 }
682
683 if (HasRs)
684 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
685 Rs)));
686 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
687 Rt)));
688
689 MI.addOperand(MCOperand::CreateImm(Imm));
690
691 return MCDisassembler::Success;
692}
693
694 /// readInstruction - read four bytes from the MemoryObject
695 /// and return 32 bit word sorted according to the given endianess
696static DecodeStatus readInstruction32(const MemoryObject &region,
697 uint64_t address,
698 uint64_t &size,
699 uint32_t &insn,
700 bool isBigEndian,
701 bool IsMicroMips) {
702 uint8_t Bytes[4];
703
704 // We want to read exactly 4 Bytes of data.
705 if (region.readBytes(address, 4, Bytes) == -1) {
706 size = 0;
707 return MCDisassembler::Fail;
708 }
709
710 if (isBigEndian) {
711 // Encoded as a big-endian 32-bit word in the stream.
712 insn = (Bytes[3] << 0) |
713 (Bytes[2] << 8) |
714 (Bytes[1] << 16) |
715 (Bytes[0] << 24);
716 }
717 else {
718 // Encoded as a small-endian 32-bit word in the stream.
719 // Little-endian byte ordering:
720 // mips32r2: 4 | 3 | 2 | 1
721 // microMIPS: 2 | 1 | 4 | 3
722 if (IsMicroMips) {
723 insn = (Bytes[2] << 0) |
724 (Bytes[3] << 8) |
725 (Bytes[0] << 16) |
726 (Bytes[1] << 24);
727 } else {
728 insn = (Bytes[0] << 0) |
729 (Bytes[1] << 8) |
730 (Bytes[2] << 16) |
731 (Bytes[3] << 24);
732 }
733 }
734
735 return MCDisassembler::Success;
736}
737
738DecodeStatus
739MipsDisassembler::getInstruction(MCInst &instr,
740 uint64_t &Size,
741 const MemoryObject &Region,
742 uint64_t Address,
743 raw_ostream &vStream,
744 raw_ostream &cStream) const {
745 uint32_t Insn;
746
747 DecodeStatus Result = readInstruction32(Region, Address, Size,
748 Insn, isBigEndian, IsMicroMips);
749 if (Result == MCDisassembler::Fail)
750 return MCDisassembler::Fail;
751
752 if (IsMicroMips) {
753 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit opcodes):\n");
754 // Calling the auto-generated decoder function.
755 Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
756 this, STI);
757 if (Result != MCDisassembler::Fail) {
758 Size = 4;
759 return Result;
760 }
761 return MCDisassembler::Fail;
762 }
763
764 if (hasCOP3()) {
765 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
766 Result =
767 decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, this, STI);
768 if (Result != MCDisassembler::Fail) {
769 Size = 4;
770 return Result;
771 }
772 }
773
774 if (hasMips32r6() && isGP64()) {
775 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
776 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn,
777 Address, this, STI);
778 if (Result != MCDisassembler::Fail) {
779 Size = 4;
780 return Result;
781 }
782 }
783
784 if (hasMips32r6()) {
785 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
786 Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn,
787 Address, this, STI);
788 if (Result != MCDisassembler::Fail) {
789 Size = 4;
790 return Result;
791 }
792 }
793
794 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
795 // Calling the auto-generated decoder function.
796 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
797 this, STI);
798 if (Result != MCDisassembler::Fail) {
799 Size = 4;
800 return Result;
801 }
802
803 return MCDisassembler::Fail;
804}
805
806DecodeStatus
807Mips64Disassembler::getInstruction(MCInst &instr,
808 uint64_t &Size,
809 const MemoryObject &Region,
810 uint64_t Address,
811 raw_ostream &vStream,
812 raw_ostream &cStream) const {
813 uint32_t Insn;
814
815 DecodeStatus Result = readInstruction32(Region, Address, Size,
816 Insn, isBigEndian, false);
817 if (Result == MCDisassembler::Fail)
818 return MCDisassembler::Fail;
819
820 // Calling the auto-generated decoder function.
821 Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
822 this, STI);
823 if (Result != MCDisassembler::Fail) {
824 Size = 4;
825 return Result;
826 }
827 // If we fail to decode in Mips64 decoder space we can try in Mips32
828 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
829 this, STI);
830 if (Result != MCDisassembler::Fail) {
831 Size = 4;
832 return Result;
833 }
834
835 return MCDisassembler::Fail;
836}
837
838static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
839 unsigned RegNo,
840 uint64_t Address,
841 const void *Decoder) {
842
843 return MCDisassembler::Fail;
844
845}
846
847static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
848 unsigned RegNo,
849 uint64_t Address,
850 const void *Decoder) {
851
852 if (RegNo > 31)
853 return MCDisassembler::Fail;
854
855 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
856 Inst.addOperand(MCOperand::CreateReg(Reg));
857 return MCDisassembler::Success;
858}
859
860static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
861 unsigned RegNo,
862 uint64_t Address,
863 const void *Decoder) {
864 if (RegNo > 31)
865 return MCDisassembler::Fail;
866 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
867 Inst.addOperand(MCOperand::CreateReg(Reg));
868 return MCDisassembler::Success;
869}
870
871static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
872 unsigned RegNo,
873 uint64_t Address,
874 const void *Decoder) {
875 if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
876 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
877
878 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
879}
880
881static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
882 unsigned RegNo,
883 uint64_t Address,
884 const void *Decoder) {
885 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
886}
887
888static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
889 unsigned RegNo,
890 uint64_t Address,
891 const void *Decoder) {
892 if (RegNo > 31)
893 return MCDisassembler::Fail;
894
895 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
896 Inst.addOperand(MCOperand::CreateReg(Reg));
897 return MCDisassembler::Success;
898}
899
900static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
901 unsigned RegNo,
902 uint64_t Address,
903 const void *Decoder) {
904 if (RegNo > 31)
905 return MCDisassembler::Fail;
906
907 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
908 Inst.addOperand(MCOperand::CreateReg(Reg));
909 return MCDisassembler::Success;
910}
911
912static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
913 unsigned RegNo,
914 uint64_t Address,
915 const void *Decoder) {
916 if (RegNo > 31)
917 return MCDisassembler::Fail;
918 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
919 Inst.addOperand(MCOperand::CreateReg(Reg));
920 return MCDisassembler::Success;
921}
922
923static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
924 unsigned RegNo,
925 uint64_t Address,
926 const void *Decoder) {
927 if (RegNo > 7)
928 return MCDisassembler::Fail;
929 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
930 Inst.addOperand(MCOperand::CreateReg(Reg));
931 return MCDisassembler::Success;
932}
933
934static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
935 uint64_t Address,
936 const void *Decoder) {
937 if (RegNo > 31)
938 return MCDisassembler::Fail;
939
940 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
941 Inst.addOperand(MCOperand::CreateReg(Reg));
942 return MCDisassembler::Success;
943}
944
945static DecodeStatus DecodeMem(MCInst &Inst,
946 unsigned Insn,
947 uint64_t Address,
948 const void *Decoder) {
949 int Offset = SignExtend32<16>(Insn & 0xffff);
950 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
951 unsigned Base = fieldFromInstruction(Insn, 21, 5);
952
953 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
954 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
955
956 if(Inst.getOpcode() == Mips::SC){
957 Inst.addOperand(MCOperand::CreateReg(Reg));
958 }
959
960 Inst.addOperand(MCOperand::CreateReg(Reg));
961 Inst.addOperand(MCOperand::CreateReg(Base));
962 Inst.addOperand(MCOperand::CreateImm(Offset));
963
964 return MCDisassembler::Success;
965}
966
967static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
968 uint64_t Address, const void *Decoder) {
969 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
970 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
971 unsigned Base = fieldFromInstruction(Insn, 11, 5);
972
973 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
974 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
975
976 Inst.addOperand(MCOperand::CreateReg(Reg));
977 Inst.addOperand(MCOperand::CreateReg(Base));
978
979 // The immediate field of an LD/ST instruction is scaled which means it must
980 // be multiplied (when decoding) by the size (in bytes) of the instructions'
981 // data format.
982 // .b - 1 byte
983 // .h - 2 bytes
984 // .w - 4 bytes
985 // .d - 8 bytes
986 switch(Inst.getOpcode())
987 {
988 default:
989 assert (0 && "Unexpected instruction");
990 return MCDisassembler::Fail;
991 break;
992 case Mips::LD_B:
993 case Mips::ST_B:
994 Inst.addOperand(MCOperand::CreateImm(Offset));
995 break;
996 case Mips::LD_H:
997 case Mips::ST_H:
998 Inst.addOperand(MCOperand::CreateImm(Offset << 1));
999 break;
1000 case Mips::LD_W:
1001 case Mips::ST_W:
1002 Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1003 break;
1004 case Mips::LD_D:
1005 case Mips::ST_D:
1006 Inst.addOperand(MCOperand::CreateImm(Offset << 3));
1007 break;
1008 }
1009
1010 return MCDisassembler::Success;
1011}
1012
1013static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1014 unsigned Insn,
1015 uint64_t Address,
1016 const void *Decoder) {
1017 int Offset = SignExtend32<12>(Insn & 0x0fff);
1018 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1019 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1020
1021 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1022 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1023
1024 if (Inst.getOpcode() == Mips::SC_MM)
1025 Inst.addOperand(MCOperand::CreateReg(Reg));
1026
1027 Inst.addOperand(MCOperand::CreateReg(Reg));
1028 Inst.addOperand(MCOperand::CreateReg(Base));
1029 Inst.addOperand(MCOperand::CreateImm(Offset));
1030
1031 return MCDisassembler::Success;
1032}
1033
1034static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1035 unsigned Insn,
1036 uint64_t Address,
1037 const void *Decoder) {
1038 int Offset = SignExtend32<16>(Insn & 0xffff);
1039 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1040 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1041
1042 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1043 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1044
1045 Inst.addOperand(MCOperand::CreateReg(Reg));
1046 Inst.addOperand(MCOperand::CreateReg(Base));
1047 Inst.addOperand(MCOperand::CreateImm(Offset));
1048
1049 return MCDisassembler::Success;
1050}
1051
1052static DecodeStatus DecodeFMem(MCInst &Inst,
1053 unsigned Insn,
1054 uint64_t Address,
1055 const void *Decoder) {
1056 int Offset = SignExtend32<16>(Insn & 0xffff);
1057 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1058 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1059
1060 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1061 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1062
1063 Inst.addOperand(MCOperand::CreateReg(Reg));
1064 Inst.addOperand(MCOperand::CreateReg(Base));
1065 Inst.addOperand(MCOperand::CreateImm(Offset));
1066
1067 return MCDisassembler::Success;
1068}
1069
1070static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1071 unsigned Insn,
1072 uint64_t Address,
1073 const void *Decoder) {
1074 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1075 unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1076 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1077
1078 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1079 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1080
1081 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1082 Inst.addOperand(MCOperand::CreateReg(Rt));
1083 }
1084
1085 Inst.addOperand(MCOperand::CreateReg(Rt));
1086 Inst.addOperand(MCOperand::CreateReg(Base));
1087 Inst.addOperand(MCOperand::CreateImm(Offset));
1088
1089 return MCDisassembler::Success;
1090}
1091
1092static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1093 unsigned RegNo,
1094 uint64_t Address,
1095 const void *Decoder) {
1096 // Currently only hardware register 29 is supported.
1097 if (RegNo != 29)
1098 return MCDisassembler::Fail;
1099 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1100 return MCDisassembler::Success;
1101}
1102
1103static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1104 unsigned RegNo,
1105 uint64_t Address,
1106 const void *Decoder) {
1107 if (RegNo > 30 || RegNo %2)
1108 return MCDisassembler::Fail;
1109
1110 ;
1111 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1112 Inst.addOperand(MCOperand::CreateReg(Reg));
1113 return MCDisassembler::Success;
1114}
1115
1116static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1117 unsigned RegNo,
1118 uint64_t Address,
1119 const void *Decoder) {
1120 if (RegNo >= 4)
1121 return MCDisassembler::Fail;
1122
1123 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1124 Inst.addOperand(MCOperand::CreateReg(Reg));
1125 return MCDisassembler::Success;
1126}
1127
1128static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1129 unsigned RegNo,
1130 uint64_t Address,
1131 const void *Decoder) {
1132 if (RegNo >= 4)
1133 return MCDisassembler::Fail;
1134
1135 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1136 Inst.addOperand(MCOperand::CreateReg(Reg));
1137 return MCDisassembler::Success;
1138}
1139
1140static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1141 unsigned RegNo,
1142 uint64_t Address,
1143 const void *Decoder) {
1144 if (RegNo >= 4)
1145 return MCDisassembler::Fail;
1146
1147 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1148 Inst.addOperand(MCOperand::CreateReg(Reg));
1149 return MCDisassembler::Success;
1150}
1151
1152static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1153 unsigned RegNo,
1154 uint64_t Address,
1155 const void *Decoder) {
1156 if (RegNo > 31)
1157 return MCDisassembler::Fail;
1158
1159 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1160 Inst.addOperand(MCOperand::CreateReg(Reg));
1161 return MCDisassembler::Success;
1162}
1163
1164static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1165 unsigned RegNo,
1166 uint64_t Address,
1167 const void *Decoder) {
1168 if (RegNo > 31)
1169 return MCDisassembler::Fail;
1170
1171 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1172 Inst.addOperand(MCOperand::CreateReg(Reg));
1173 return MCDisassembler::Success;
1174}
1175
1176static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1177 unsigned RegNo,
1178 uint64_t Address,
1179 const void *Decoder) {
1180 if (RegNo > 31)
1181 return MCDisassembler::Fail;
1182
1183 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1184 Inst.addOperand(MCOperand::CreateReg(Reg));
1185 return MCDisassembler::Success;
1186}
1187
1188static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1189 unsigned RegNo,
1190 uint64_t Address,
1191 const void *Decoder) {
1192 if (RegNo > 31)
1193 return MCDisassembler::Fail;
1194
1195 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1196 Inst.addOperand(MCOperand::CreateReg(Reg));
1197 return MCDisassembler::Success;
1198}
1199
1200static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1201 unsigned RegNo,
1202 uint64_t Address,
1203 const void *Decoder) {
1204 if (RegNo > 7)
1205 return MCDisassembler::Fail;
1206
1207 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1208 Inst.addOperand(MCOperand::CreateReg(Reg));
1209 return MCDisassembler::Success;
1210}
1211
1212static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1213 unsigned RegNo,
1214 uint64_t Address,
1215 const void *Decoder) {
1216 if (RegNo > 31)
1217 return MCDisassembler::Fail;
1218
1219 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1220 Inst.addOperand(MCOperand::CreateReg(Reg));
1221 return MCDisassembler::Success;
1222}
1223
1224static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1225 unsigned Offset,
1226 uint64_t Address,
1227 const void *Decoder) {
1228 int32_t BranchOffset = (SignExtend32<16>(Offset) << 2) + 4;
1229 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1230 return MCDisassembler::Success;
1231}
1232
1233static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1234 unsigned Insn,
1235 uint64_t Address,
1236 const void *Decoder) {
1237
1238 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1239 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1240 return MCDisassembler::Success;
1241}
1242
1243static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1244 unsigned Offset,
1245 uint64_t Address,
1246 const void *Decoder) {
1247 int32_t BranchOffset = SignExtend32<21>(Offset) << 2;
1248
1249 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1250 return MCDisassembler::Success;
1251}
1252
1253static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1254 unsigned Offset,
1255 uint64_t Address,
1256 const void *Decoder) {
1257 int32_t BranchOffset = SignExtend32<26>(Offset) << 2;
1258
1259 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1260 return MCDisassembler::Success;
1261}
1262
1263static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1264 unsigned Offset,
1265 uint64_t Address,
1266 const void *Decoder) {
1267 int32_t BranchOffset = SignExtend32<16>(Offset) << 1;
1268 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1269 return MCDisassembler::Success;
1270}
1271
1272static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1273 unsigned Insn,
1274 uint64_t Address,
1275 const void *Decoder) {
1276 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1277 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1278 return MCDisassembler::Success;
1279}
1280
1281static DecodeStatus DecodeSimm16(MCInst &Inst,
1282 unsigned Insn,
1283 uint64_t Address,
1284 const void *Decoder) {
1285 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1286 return MCDisassembler::Success;
1287}
1288
1289static DecodeStatus DecodeLSAImm(MCInst &Inst,
1290 unsigned Insn,
1291 uint64_t Address,
1292 const void *Decoder) {
1293 // We add one to the immediate field as it was encoded as 'imm - 1'.
1294 Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1295 return MCDisassembler::Success;
1296}
1297
1298static DecodeStatus DecodeInsSize(MCInst &Inst,
1299 unsigned Insn,
1300 uint64_t Address,
1301 const void *Decoder) {
1302 // First we need to grab the pos(lsb) from MCInst.
1303 int Pos = Inst.getOperand(2).getImm();
1304 int Size = (int) Insn - Pos + 1;
1305 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1306 return MCDisassembler::Success;
1307}
1308
1309static DecodeStatus DecodeExtSize(MCInst &Inst,
1310 unsigned Insn,
1311 uint64_t Address,
1312 const void *Decoder) {
1313 int Size = (int) Insn + 1;
1314 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1315 return MCDisassembler::Success;
1316}
1317
1318static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1319 uint64_t Address, const void *Decoder) {
1320 Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) << 2));
1321 return MCDisassembler::Success;
1322}
1323
1324static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1325 uint64_t Address, const void *Decoder) {
1326 Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) << 3));
1327 return MCDisassembler::Success;
1328}