| Thumb2InstrInfo.h (210299) | Thumb2InstrInfo.h (218893) |
|---|---|
| 1//===- Thumb2InstrInfo.h - Thumb-2 Instruction Information ------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 24 unchanged lines hidden (view full) --- 33 unsigned getUnindexedOpcode(unsigned Opc) const; 34 35 void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 36 MachineBasicBlock *NewDest) const; 37 38 bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 39 MachineBasicBlock::iterator MBBI) const; 40 | 1//===- Thumb2InstrInfo.h - Thumb-2 Instruction Information ------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 24 unchanged lines hidden (view full) --- 33 unsigned getUnindexedOpcode(unsigned Opc) const; 34 35 void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 36 MachineBasicBlock *NewDest) const; 37 38 bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 39 MachineBasicBlock::iterator MBBI) const; 40 |
| 41 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumInstrs) const; 42 43 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTInstrs, 44 MachineBasicBlock &FMBB, unsigned NumFInstrs) const; 45 | |
| 46 void copyPhysReg(MachineBasicBlock &MBB, 47 MachineBasicBlock::iterator I, DebugLoc DL, 48 unsigned DestReg, unsigned SrcReg, 49 bool KillSrc) const; 50 51 void storeRegToStackSlot(MachineBasicBlock &MBB, 52 MachineBasicBlock::iterator MBBI, 53 unsigned SrcReg, bool isKill, int FrameIndex, --- 11 unchanged lines hidden (view full) --- 65 void scheduleTwoAddrSource(MachineInstr *SrcMI, MachineInstr *UseMI, 66 const TargetRegisterInfo &TRI) const; 67 68 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 69 /// such, whenever a client has an instance of instruction info, it should 70 /// always be able to get register info as well (through this method). 71 /// 72 const Thumb2RegisterInfo &getRegisterInfo() const { return RI; } | 41 void copyPhysReg(MachineBasicBlock &MBB, 42 MachineBasicBlock::iterator I, DebugLoc DL, 43 unsigned DestReg, unsigned SrcReg, 44 bool KillSrc) const; 45 46 void storeRegToStackSlot(MachineBasicBlock &MBB, 47 MachineBasicBlock::iterator MBBI, 48 unsigned SrcReg, bool isKill, int FrameIndex, --- 11 unchanged lines hidden (view full) --- 60 void scheduleTwoAddrSource(MachineInstr *SrcMI, MachineInstr *UseMI, 61 const TargetRegisterInfo &TRI) const; 62 63 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 64 /// such, whenever a client has an instance of instruction info, it should 65 /// always be able to get register info as well (through this method). 66 /// 67 const Thumb2RegisterInfo &getRegisterInfo() const { return RI; } |
| 73 74 ScheduleHazardRecognizer * 75 CreateTargetPostRAHazardRecognizer(const InstrItineraryData &II) const; | |
| 76}; 77 78/// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical 79/// to llvm::getInstrPredicate except it returns AL for conditional branch 80/// instructions which are "predicated", but are not in IT blocks. 81ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg); 82 83 84} 85 86#endif // THUMB2INSTRUCTIONINFO_H | 68}; 69 70/// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical 71/// to llvm::getInstrPredicate except it returns AL for conditional branch 72/// instructions which are "predicated", but are not in IT blocks. 73ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg); 74 75 76} 77 78#endif // THUMB2INSTRUCTIONINFO_H |