1//===- Thumb2InstrInfo.h - Thumb-2 Instruction Information ------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
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26 Thumb2RegisterInfo RI;
27public:
28 explicit Thumb2InstrInfo(const ARMSubtarget &STI);
29
30 // Return the non-pre/post incrementing version of 'Opc'. Return 0
31 // if there is not such an opcode.
32 unsigned getUnindexedOpcode(unsigned Opc) const;
33
34 // Return true if the block does not fall through.
35 bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
36
37 bool copyRegToReg(MachineBasicBlock &MBB,
38 MachineBasicBlock::iterator I,
39 unsigned DestReg, unsigned SrcReg,
40 const TargetRegisterClass *DestRC,
41 const TargetRegisterClass *SrcRC) const;
42
43 void storeRegToStackSlot(MachineBasicBlock &MBB,
44 MachineBasicBlock::iterator MBBI,
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2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
--- 17 unchanged lines hidden (view full) ---
26 Thumb2RegisterInfo RI;
27public:
28 explicit Thumb2InstrInfo(const ARMSubtarget &STI);
29
30 // Return the non-pre/post incrementing version of 'Opc'. Return 0
31 // if there is not such an opcode.
32 unsigned getUnindexedOpcode(unsigned Opc) const;
33
34 // Return true if the block does not fall through.
35 bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
36
37 bool copyRegToReg(MachineBasicBlock &MBB,
38 MachineBasicBlock::iterator I,
39 unsigned DestReg, unsigned SrcReg,
40 const TargetRegisterClass *DestRC,
41 const TargetRegisterClass *SrcRC) const;
42
43 void storeRegToStackSlot(MachineBasicBlock &MBB,
44 MachineBasicBlock::iterator MBBI,
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