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sdiff udiff text old ( 206083 ) new ( 206124 )
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Thumb1InstrInfo.cpp (206083) Thumb1InstrInfo.cpp (206124)
1//===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information ----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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32 return 0;
33}
34
35bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
36 MachineBasicBlock::iterator I,
37 unsigned DestReg, unsigned SrcReg,
38 const TargetRegisterClass *DestRC,
39 const TargetRegisterClass *SrcRC) const {
1//===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information ----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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32 return 0;
33}
34
35bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
36 MachineBasicBlock::iterator I,
37 unsigned DestReg, unsigned SrcReg,
38 const TargetRegisterClass *DestRC,
39 const TargetRegisterClass *SrcRC) const {
40 DebugLoc DL = DebugLoc::getUnknownLoc();
40 DebugLoc DL;
41 if (I != MBB.end()) DL = I->getDebugLoc();
42
43 if (DestRC == ARM::GPRRegisterClass) {
44 if (SrcRC == ARM::GPRRegisterClass) {
45 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
46 return true;
47 } else if (SrcRC == ARM::tGPRRegisterClass) {
48 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);

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93
94 return false;
95}
96
97void Thumb1InstrInfo::
98storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
99 unsigned SrcReg, bool isKill, int FI,
100 const TargetRegisterClass *RC) const {
41 if (I != MBB.end()) DL = I->getDebugLoc();
42
43 if (DestRC == ARM::GPRRegisterClass) {
44 if (SrcRC == ARM::GPRRegisterClass) {
45 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
46 return true;
47 } else if (SrcRC == ARM::tGPRRegisterClass) {
48 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);

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93
94 return false;
95}
96
97void Thumb1InstrInfo::
98storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
99 unsigned SrcReg, bool isKill, int FI,
100 const TargetRegisterClass *RC) const {
101 DebugLoc DL = DebugLoc::getUnknownLoc();
101 DebugLoc DL;
102 if (I != MBB.end()) DL = I->getDebugLoc();
103
104 assert((RC == ARM::tGPRRegisterClass ||
105 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
106 isARMLowRegister(SrcReg))) && "Unknown regclass!");
107
108 if (RC == ARM::tGPRRegisterClass ||
109 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&

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120 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
121 }
122}
123
124void Thumb1InstrInfo::
125loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
126 unsigned DestReg, int FI,
127 const TargetRegisterClass *RC) const {
102 if (I != MBB.end()) DL = I->getDebugLoc();
103
104 assert((RC == ARM::tGPRRegisterClass ||
105 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
106 isARMLowRegister(SrcReg))) && "Unknown regclass!");
107
108 if (RC == ARM::tGPRRegisterClass ||
109 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&

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120 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
121 }
122}
123
124void Thumb1InstrInfo::
125loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
126 unsigned DestReg, int FI,
127 const TargetRegisterClass *RC) const {
128 DebugLoc DL = DebugLoc::getUnknownLoc();
128 DebugLoc DL;
129 if (I != MBB.end()) DL = I->getDebugLoc();
130
131 assert((RC == ARM::tGPRRegisterClass ||
132 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
133 isARMLowRegister(DestReg))) && "Unknown regclass!");
134
135 if (RC == ARM::tGPRRegisterClass ||
136 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&

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149
150bool Thumb1InstrInfo::
151spillCalleeSavedRegisters(MachineBasicBlock &MBB,
152 MachineBasicBlock::iterator MI,
153 const std::vector<CalleeSavedInfo> &CSI) const {
154 if (CSI.empty())
155 return false;
156
129 if (I != MBB.end()) DL = I->getDebugLoc();
130
131 assert((RC == ARM::tGPRRegisterClass ||
132 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
133 isARMLowRegister(DestReg))) && "Unknown regclass!");
134
135 if (RC == ARM::tGPRRegisterClass ||
136 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&

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149
150bool Thumb1InstrInfo::
151spillCalleeSavedRegisters(MachineBasicBlock &MBB,
152 MachineBasicBlock::iterator MI,
153 const std::vector<CalleeSavedInfo> &CSI) const {
154 if (CSI.empty())
155 return false;
156
157 DebugLoc DL = DebugLoc::getUnknownLoc();
157 DebugLoc DL;
158 if (MI != MBB.end()) DL = MI->getDebugLoc();
159
160 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
161 AddDefaultPred(MIB);
162 for (unsigned i = CSI.size(); i != 0; --i) {
163 unsigned Reg = CSI[i-1].getReg();
164 // Add the callee-saved register as live-in. It's killed at the spill.
165 MBB.addLiveIn(Reg);

--- 85 unchanged lines hidden --- 		158 if (MI != MBB.end()) DL = MI->getDebugLoc();
159
160 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
161 AddDefaultPred(MIB);
162 for (unsigned i = CSI.size(); i != 0; --i) {
163 unsigned Reg = CSI[i-1].getReg();
164 // Add the callee-saved register as live-in. It's killed at the spill.
165 MBB.addLiveIn(Reg);

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