1//===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information ----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
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27Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
28 : ARMBaseInstrInfo(STI), RI(*this, STI) {
29}
30
31unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
32 return 0;
33}
34
35bool
36Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
37 if (MBB.empty()) return false;
38
39 switch (MBB.back().getOpcode()) {
40 case ARM::tBX_RET:
41 case ARM::tBX_RET_vararg:
42 case ARM::tPOP_RET:
43 case ARM::tB:
44 case ARM::tBRIND:
45 case ARM::tBR_JTr:
46 return true;
47 default:
48 break;
49 }
50
51 return false;
52}
53
54bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
55 MachineBasicBlock::iterator I,
56 unsigned DestReg, unsigned SrcReg,
57 const TargetRegisterClass *DestRC,
58 const TargetRegisterClass *SrcRC) const {
59 DebugLoc DL = DebugLoc::getUnknownLoc();
60 if (I != MBB.end()) DL = I->getDebugLoc();
61
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2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
--- 18 unchanged lines hidden (view full) ---
27Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
28 : ARMBaseInstrInfo(STI), RI(*this, STI) {
29}
30
31unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
32 return 0;
33}
34
35bool
36Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
37 if (MBB.empty()) return false;
38
39 switch (MBB.back().getOpcode()) {
40 case ARM::tBX_RET:
41 case ARM::tBX_RET_vararg:
42 case ARM::tPOP_RET:
43 case ARM::tB:
44 case ARM::tBRIND:
45 case ARM::tBR_JTr:
46 return true;
47 default:
48 break;
49 }
50
51 return false;
52}
53
54bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
55 MachineBasicBlock::iterator I,
56 unsigned DestReg, unsigned SrcReg,
57 const TargetRegisterClass *DestRC,
58 const TargetRegisterClass *SrcRC) const {
59 DebugLoc DL = DebugLoc::getUnknownLoc();
60 if (I != MBB.end()) DL = I->getDebugLoc();
61
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