1//===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file provides ARM specific target descriptions.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMMCTARGETDESC_H
15#define ARMMCTARGETDESC_H
16
17#include "llvm/Support/DataTypes.h"
18#include <string>
19
20namespace llvm {
21class MCAsmBackend;
22class MCCodeEmitter;
23class MCContext;
24class MCInstrInfo;
25class MCObjectWriter;
26class MCRegisterInfo;
27class MCSubtargetInfo;
28class StringRef;
29class Target;
30class raw_ostream;
31
32extern Target TheARMTarget, TheThumbTarget;
33
34namespace ARM_MC {
35 std::string ParseARMTriple(StringRef TT, StringRef CPU);
36
37 /// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance.
38 /// This is exposed so Asm parser, etc. do not need to go through
39 /// TargetRegistry.
40 MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
41 StringRef FS);
42}
43
44MCCodeEmitter *createARMMCCodeEmitter(const MCInstrInfo &MCII,
45 const MCRegisterInfo &MRI,
46 const MCSubtargetInfo &STI,
47 MCContext &Ctx);
48
| 1//===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file provides ARM specific target descriptions.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMMCTARGETDESC_H
15#define ARMMCTARGETDESC_H
16
17#include "llvm/Support/DataTypes.h"
18#include <string>
19
20namespace llvm {
21class MCAsmBackend;
22class MCCodeEmitter;
23class MCContext;
24class MCInstrInfo;
25class MCObjectWriter;
26class MCRegisterInfo;
27class MCSubtargetInfo;
28class StringRef;
29class Target;
30class raw_ostream;
31
32extern Target TheARMTarget, TheThumbTarget;
33
34namespace ARM_MC {
35 std::string ParseARMTriple(StringRef TT, StringRef CPU);
36
37 /// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance.
38 /// This is exposed so Asm parser, etc. do not need to go through
39 /// TargetRegistry.
40 MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
41 StringRef FS);
42}
43
44MCCodeEmitter *createARMMCCodeEmitter(const MCInstrInfo &MCII,
45 const MCRegisterInfo &MRI,
46 const MCSubtargetInfo &STI,
47 MCContext &Ctx);
48
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49MCAsmBackend *createARMAsmBackend(const Target &T, StringRef TT);
| 49MCAsmBackend *createARMAsmBackend(const Target &T, StringRef TT, StringRef CPU);
|
50
51/// createARMELFObjectWriter - Construct an ELF Mach-O object writer.
52MCObjectWriter *createARMELFObjectWriter(raw_ostream &OS,
53 uint8_t OSABI);
54
55/// createARMMachObjectWriter - Construct an ARM Mach-O object writer.
56MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS,
57 bool Is64Bit,
58 uint32_t CPUType,
59 uint32_t CPUSubtype);
60
61} // End llvm namespace
62
63// Defines symbolic names for ARM registers. This defines a mapping from
64// register name to register number.
65//
66#define GET_REGINFO_ENUM
67#include "ARMGenRegisterInfo.inc"
68
69// Defines symbolic names for the ARM instructions.
70//
71#define GET_INSTRINFO_ENUM
72#include "ARMGenInstrInfo.inc"
73
74#define GET_SUBTARGETINFO_ENUM
75#include "ARMGenSubtargetInfo.inc"
76
77#endif
| 50
51/// createARMELFObjectWriter - Construct an ELF Mach-O object writer.
52MCObjectWriter *createARMELFObjectWriter(raw_ostream &OS,
53 uint8_t OSABI);
54
55/// createARMMachObjectWriter - Construct an ARM Mach-O object writer.
56MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS,
57 bool Is64Bit,
58 uint32_t CPUType,
59 uint32_t CPUSubtype);
60
61} // End llvm namespace
62
63// Defines symbolic names for ARM registers. This defines a mapping from
64// register name to register number.
65//
66#define GET_REGINFO_ENUM
67#include "ARMGenRegisterInfo.inc"
68
69// Defines symbolic names for the ARM instructions.
70//
71#define GET_INSTRINFO_ENUM
72#include "ARMGenInstrInfo.inc"
73
74#define GET_SUBTARGETINFO_ENUM
75#include "ARMGenSubtargetInfo.inc"
76
77#endif
|