1//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the ARM instructions in TableGen format.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// ARM specific DAG Nodes.
16//
17
18// Type profiles.
19def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21
22def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
23
24def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
25
26def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
28 SDTCisVT<3, i32>]>;
29
30def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
32
33def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
35 SDTCisVT<2, i32>]>;
36
37def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
40
41def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
42
43def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
44 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
45
46def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
47def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
48
49// Node definitions.
50def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
51def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
52
53def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
54 [SDNPHasChain, SDNPOutFlag]>;
55def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
56 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
57
58def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
59 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
60def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
61 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
62def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
63 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
64
65def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
66 [SDNPHasChain, SDNPOptInFlag]>;
67
68def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
69 [SDNPInFlag]>;
70def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
71 [SDNPInFlag]>;
72
73def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
74 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
75
76def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
77 [SDNPHasChain]>;
78def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
79 [SDNPHasChain]>;
80
81def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
82 [SDNPOutFlag]>;
83
84def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
85 [SDNPOutFlag,SDNPCommutative]>;
86
87def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
88
89def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
90def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
91def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
92
93def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
94def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>;
95
96//===----------------------------------------------------------------------===//
97// ARM Instruction Predicate Definitions.
98//
99def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
100def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
101def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
102def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">;
103def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
104def HasV7 : Predicate<"Subtarget->hasV7Ops()">;
105def HasVFP2 : Predicate<"Subtarget->hasVFP2()">;
106def HasVFP3 : Predicate<"Subtarget->hasVFP3()">;
107def HasNEON : Predicate<"Subtarget->hasNEON()">;
108def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
109def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
110def IsThumb : Predicate<"Subtarget->isThumb()">;
111def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
112def IsThumb2 : Predicate<"Subtarget->isThumb2()">;
113def IsARM : Predicate<"!Subtarget->isThumb()">;
114def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
115def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
116def CarryDefIsUnused : Predicate<"!N.getNode()->hasAnyUseOfValue(1)">;
117def CarryDefIsUsed : Predicate<"N.getNode()->hasAnyUseOfValue(1)">;
118
119//===----------------------------------------------------------------------===//
120// ARM Flag Definitions.
121
122class RegConstraint<string C> {
123 string Constraints = C;
124}
125
126//===----------------------------------------------------------------------===//
127// ARM specific transformation functions and pattern fragments.
128//
129
130// so_imm_neg_XFORM - Return a so_imm value packed into the format described for
131// so_imm_neg def below.
132def so_imm_neg_XFORM : SDNodeXForm<imm, [{
133 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
134}]>;
135
136// so_imm_not_XFORM - Return a so_imm value packed into the format described for
137// so_imm_not def below.
138def so_imm_not_XFORM : SDNodeXForm<imm, [{
139 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
140}]>;
141
142// rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
143def rot_imm : PatLeaf<(i32 imm), [{
144 int32_t v = (int32_t)N->getZExtValue();
145 return v == 8 || v == 16 || v == 24;
146}]>;
147
148/// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
149def imm1_15 : PatLeaf<(i32 imm), [{
150 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
151}]>;
152
153/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
154def imm16_31 : PatLeaf<(i32 imm), [{
155 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
156}]>;
157
158def so_imm_neg :
159 PatLeaf<(imm), [{
160 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
161 }], so_imm_neg_XFORM>;
162
163def so_imm_not :
164 PatLeaf<(imm), [{
165 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
166 }], so_imm_not_XFORM>;
167
168// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
169def sext_16_node : PatLeaf<(i32 GPR:$a), [{
170 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
171}]>;
172
173/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
174/// e.g., 0xf000ffff
175def bf_inv_mask_imm : Operand<i32>,
176 PatLeaf<(imm), [{
177 uint32_t v = (uint32_t)N->getZExtValue();
178 if (v == 0xffffffff)
179 return 0;
180 // there can be 1's on either or both "outsides", all the "inside"
181 // bits must be 0's
182 unsigned int lsb = 0, msb = 31;
183 while (v & (1 << msb)) --msb;
184 while (v & (1 << lsb)) ++lsb;
185 for (unsigned int i = lsb; i <= msb; ++i) {
186 if (v & (1 << i))
187 return 0;
188 }
189 return 1;
190}] > {
191 let PrintMethod = "printBitfieldInvMaskImmOperand";
192}
193
194/// Split a 32-bit immediate into two 16 bit parts.
195def lo16 : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
197 MVT::i32);
198}]>;
199
200def hi16 : SDNodeXForm<imm, [{
201 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
202}]>;
203
204def lo16AllZero : PatLeaf<(i32 imm), [{
205 // Returns true if all low 16-bits are 0.
206 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
207 }], hi16>;
208
209/// imm0_65535 predicate - True if the 32-bit immediate is in the range
210/// [0.65535].
211def imm0_65535 : PatLeaf<(i32 imm), [{
212 return (uint32_t)N->getZExtValue() < 65536;
213}]>;
214
215class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
216class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
217
218//===----------------------------------------------------------------------===//
219// Operand Definitions.
220//
221
222// Branch target.
223def brtarget : Operand<OtherVT>;
224
225// A list of registers separated by comma. Used by load/store multiple.
226def reglist : Operand<i32> {
227 let PrintMethod = "printRegisterList";
228}
229
230// An operand for the CONSTPOOL_ENTRY pseudo-instruction.
231def cpinst_operand : Operand<i32> {
232 let PrintMethod = "printCPInstOperand";
233}
234
235def jtblock_operand : Operand<i32> {
236 let PrintMethod = "printJTBlockOperand";
237}
238def jt2block_operand : Operand<i32> {
239 let PrintMethod = "printJT2BlockOperand";
240}
241
242// Local PC labels.
243def pclabel : Operand<i32> {
244 let PrintMethod = "printPCLabel";
245}
246
247// shifter_operand operands: so_reg and so_imm.
248def so_reg : Operand<i32>, // reg reg imm
249 ComplexPattern<i32, 3, "SelectShifterOperandReg",
250 [shl,srl,sra,rotr]> {
251 let PrintMethod = "printSORegOperand";
252 let MIOperandInfo = (ops GPR, GPR, i32imm);
253}
254
255// so_imm - Match a 32-bit shifter_operand immediate operand, which is an
256// 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
257// represented in the imm field in the same 12-bit form that they are encoded
258// into so_imm instructions: the 8-bit immediate is the least significant bits
259// [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
260def so_imm : Operand<i32>,
261 PatLeaf<(imm), [{
262 return ARM_AM::getSOImmVal(N->getZExtValue()) != -1;
263 }]> {
264 let PrintMethod = "printSOImmOperand";
265}
266
267// Break so_imm's up into two pieces. This handles immediates with up to 16
268// bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
269// get the first/second pieces.
270def so_imm2part : Operand<i32>,
271 PatLeaf<(imm), [{
272 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
273 }]> {
274 let PrintMethod = "printSOImm2PartOperand";
275}
276
277def so_imm2part_1 : SDNodeXForm<imm, [{
278 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
279 return CurDAG->getTargetConstant(V, MVT::i32);
280}]>;
281
282def so_imm2part_2 : SDNodeXForm<imm, [{
283 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
284 return CurDAG->getTargetConstant(V, MVT::i32);
285}]>;
286
287/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
288def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
289 return (int32_t)N->getZExtValue() < 32;
290}]>;
291
292// Define ARM specific addressing modes.
293
294// addrmode2 := reg +/- reg shop imm
295// addrmode2 := reg +/- imm12
296//
297def addrmode2 : Operand<i32>,
298 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
299 let PrintMethod = "printAddrMode2Operand";
300 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
301}
302
303def am2offset : Operand<i32>,
304 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
305 let PrintMethod = "printAddrMode2OffsetOperand";
306 let MIOperandInfo = (ops GPR, i32imm);
307}
308
309// addrmode3 := reg +/- reg
310// addrmode3 := reg +/- imm8
311//
312def addrmode3 : Operand<i32>,
313 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
314 let PrintMethod = "printAddrMode3Operand";
315 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
316}
317
318def am3offset : Operand<i32>,
319 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
320 let PrintMethod = "printAddrMode3OffsetOperand";
321 let MIOperandInfo = (ops GPR, i32imm);
322}
323
324// addrmode4 := reg, <mode|W>
325//
326def addrmode4 : Operand<i32>,
327 ComplexPattern<i32, 2, "SelectAddrMode4", []> {
328 let PrintMethod = "printAddrMode4Operand";
329 let MIOperandInfo = (ops GPR, i32imm);
330}
331
332// addrmode5 := reg +/- imm8*4
333//
334def addrmode5 : Operand<i32>,
335 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
336 let PrintMethod = "printAddrMode5Operand";
337 let MIOperandInfo = (ops GPR, i32imm);
338}
339
340// addrmode6 := reg with optional writeback
341//
342def addrmode6 : Operand<i32>,
343 ComplexPattern<i32, 4, "SelectAddrMode6", []> {
344 let PrintMethod = "printAddrMode6Operand";
345 let MIOperandInfo = (ops GPR:$addr, GPR:$upd, i32imm, i32imm);
346}
347
348// addrmodepc := pc + reg
349//
350def addrmodepc : Operand<i32>,
351 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
352 let PrintMethod = "printAddrModePCOperand";
353 let MIOperandInfo = (ops GPR, i32imm);
354}
355
356def nohash_imm : Operand<i32> {
357 let PrintMethod = "printNoHashImmediate";
358}
359
360//===----------------------------------------------------------------------===//
361
362include "ARMInstrFormats.td"
363
364//===----------------------------------------------------------------------===//
365// Multiclass helpers...
366//
367
368/// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
369/// binop that produces a value.
370multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
371 bit Commutable = 0> {
372 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
373 IIC_iALUi, opc, "\t$dst, $a, $b",
374 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
375 let Inst{25} = 1;
376 }
377 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
378 IIC_iALUr, opc, "\t$dst, $a, $b",
379 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
380 let Inst{11-4} = 0b00000000;
381 let Inst{25} = 0;
382 let isCommutable = Commutable;
383 }
384 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
385 IIC_iALUsr, opc, "\t$dst, $a, $b",
386 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
387 let Inst{25} = 0;
388 }
389}
390
391/// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
392/// instruction modifies the CPSR register.
393let Defs = [CPSR] in {
394multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
395 bit Commutable = 0> {
396 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
397 IIC_iALUi, opc, "\t$dst, $a, $b",
398 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
399 let Inst{20} = 1;
400 let Inst{25} = 1;
401 }
402 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
403 IIC_iALUr, opc, "\t$dst, $a, $b",
404 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
405 let isCommutable = Commutable;
406 let Inst{11-4} = 0b00000000;
407 let Inst{20} = 1;
408 let Inst{25} = 0;
409 }
410 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
411 IIC_iALUsr, opc, "\t$dst, $a, $b",
412 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
413 let Inst{20} = 1;
414 let Inst{25} = 0;
415 }
416}
417}
418
419/// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
420/// patterns. Similar to AsI1_bin_irs except the instruction does not produce
421/// a explicit result, only implicitly set CPSR.
422let Defs = [CPSR] in {
423multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
424 bit Commutable = 0> {
425 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm, IIC_iCMPi,
426 opc, "\t$a, $b",
427 [(opnode GPR:$a, so_imm:$b)]> {
428 let Inst{20} = 1;
429 let Inst{25} = 1;
430 }
431 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm, IIC_iCMPr,
432 opc, "\t$a, $b",
433 [(opnode GPR:$a, GPR:$b)]> {
434 let Inst{11-4} = 0b00000000;
435 let Inst{20} = 1;
436 let Inst{25} = 0;
437 let isCommutable = Commutable;
438 }
439 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm, IIC_iCMPsr,
440 opc, "\t$a, $b",
441 [(opnode GPR:$a, so_reg:$b)]> {
442 let Inst{20} = 1;
443 let Inst{25} = 0;
444 }
445}
446}
447
448/// AI_unary_rrot - A unary operation with two forms: one whose operand is a
449/// register and one whose operand is a register rotated by 8/16/24.
450/// FIXME: Remove the 'r' variant. Its rot_imm is zero.
451multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
452 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src),
453 IIC_iUNAr, opc, "\t$dst, $src",
454 [(set GPR:$dst, (opnode GPR:$src))]>,
455 Requires<[IsARM, HasV6]> {
456 let Inst{11-10} = 0b00;
457 let Inst{19-16} = 0b1111;
458 }
459 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
460 IIC_iUNAsi, opc, "\t$dst, $src, ror $rot",
461 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
462 Requires<[IsARM, HasV6]> {
463 let Inst{19-16} = 0b1111;
464 }
465}
466
467/// AI_bin_rrot - A binary operation with two forms: one whose operand is a
468/// register and one whose operand is a register rotated by 8/16/24.
469multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
470 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
471 IIC_iALUr, opc, "\t$dst, $LHS, $RHS",
472 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
473 Requires<[IsARM, HasV6]> {
474 let Inst{11-10} = 0b00;
475 }
476 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
477 IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot",
478 [(set GPR:$dst, (opnode GPR:$LHS,
479 (rotr GPR:$RHS, rot_imm:$rot)))]>,
480 Requires<[IsARM, HasV6]>;
481}
482
483/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
484let Uses = [CPSR] in {
485multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
486 bit Commutable = 0> {
487 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
488 DPFrm, IIC_iALUi, opc, "\t$dst, $a, $b",
489 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
490 Requires<[IsARM, CarryDefIsUnused]> {
491 let Inst{25} = 1;
492 }
493 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
494 DPFrm, IIC_iALUr, opc, "\t$dst, $a, $b",
495 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
496 Requires<[IsARM, CarryDefIsUnused]> {
497 let isCommutable = Commutable;
498 let Inst{11-4} = 0b00000000;
499 let Inst{25} = 0;
500 }
501 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
502 DPSoRegFrm, IIC_iALUsr, opc, "\t$dst, $a, $b",
503 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
504 Requires<[IsARM, CarryDefIsUnused]> {
505 let Inst{25} = 0;
506 }
507}
508// Carry setting variants
509let Defs = [CPSR] in {
510multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
511 bit Commutable = 0> {
512 def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
513 DPFrm, IIC_iALUi, !strconcat(opc, "\t$dst, $a, $b"),
514 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
515 Requires<[IsARM, CarryDefIsUsed]> {
516 let Defs = [CPSR];
517 let Inst{20} = 1;
518 let Inst{25} = 1;
519 }
520 def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
521 DPFrm, IIC_iALUr, !strconcat(opc, "\t$dst, $a, $b"),
522 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
523 Requires<[IsARM, CarryDefIsUsed]> {
524 let Defs = [CPSR];
525 let Inst{11-4} = 0b00000000;
526 let Inst{20} = 1;
527 let Inst{25} = 0;
528 }
529 def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
530 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$dst, $a, $b"),
531 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
532 Requires<[IsARM, CarryDefIsUsed]> {
533 let Defs = [CPSR];
534 let Inst{20} = 1;
535 let Inst{25} = 0;
536 }
537}
538}
539}
540
541//===----------------------------------------------------------------------===//
542// Instructions
543//===----------------------------------------------------------------------===//
544
545//===----------------------------------------------------------------------===//
546// Miscellaneous Instructions.
547//
548
549/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
550/// the function. The first operand is the ID# for this instruction, the second
551/// is the index into the MachineConstantPool that this is, the third is the
552/// size in bytes of this constant pool entry.
553let neverHasSideEffects = 1, isNotDuplicable = 1 in
554def CONSTPOOL_ENTRY :
555PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
556 i32imm:$size), NoItinerary,
557 "${instid:label} ${cpidx:cpentry}", []>;
558
559let Defs = [SP], Uses = [SP] in {
560def ADJCALLSTACKUP :
561PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
562 "@ ADJCALLSTACKUP $amt1",
563 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
564
565def ADJCALLSTACKDOWN :
566PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
567 "@ ADJCALLSTACKDOWN $amt",
568 [(ARMcallseq_start timm:$amt)]>;
569}
570
571def DWARF_LOC :
572PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), NoItinerary,
573 ".loc $file, $line, $col",
574 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
575
576
577// Address computation and loads and stores in PIC mode.
578let isNotDuplicable = 1 in {
579def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
580 Pseudo, IIC_iALUr, "\n$cp:\n\tadd$p\t$dst, pc, $a",
581 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
582
583let AddedComplexity = 10 in {
584let canFoldAsLoad = 1 in
585def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
586 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr$p\t$dst, $addr",
587 [(set GPR:$dst, (load addrmodepc:$addr))]>;
588
589def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
590 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}h\t$dst, $addr",
591 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
592
593def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
594 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}b\t$dst, $addr",
595 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
596
597def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
598 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}sh\t$dst, $addr",
599 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
600
601def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
602 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}sb\t$dst, $addr",
603 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
604}
605let AddedComplexity = 10 in {
606def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
607 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr$p\t$src, $addr",
608 [(store GPR:$src, addrmodepc:$addr)]>;
609
610def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
| 1//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the ARM instructions in TableGen format.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// ARM specific DAG Nodes.
16//
17
18// Type profiles.
19def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21
22def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
23
24def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
25
26def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
28 SDTCisVT<3, i32>]>;
29
30def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
32
33def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
35 SDTCisVT<2, i32>]>;
36
37def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
40
41def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
42
43def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
44 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
45
46def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
47def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
48
49// Node definitions.
50def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
51def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
52
53def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
54 [SDNPHasChain, SDNPOutFlag]>;
55def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
56 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
57
58def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
59 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
60def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
61 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
62def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
63 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
64
65def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
66 [SDNPHasChain, SDNPOptInFlag]>;
67
68def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
69 [SDNPInFlag]>;
70def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
71 [SDNPInFlag]>;
72
73def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
74 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
75
76def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
77 [SDNPHasChain]>;
78def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
79 [SDNPHasChain]>;
80
81def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
82 [SDNPOutFlag]>;
83
84def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
85 [SDNPOutFlag,SDNPCommutative]>;
86
87def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
88
89def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
90def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
91def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
92
93def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
94def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>;
95
96//===----------------------------------------------------------------------===//
97// ARM Instruction Predicate Definitions.
98//
99def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
100def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
101def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
102def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">;
103def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
104def HasV7 : Predicate<"Subtarget->hasV7Ops()">;
105def HasVFP2 : Predicate<"Subtarget->hasVFP2()">;
106def HasVFP3 : Predicate<"Subtarget->hasVFP3()">;
107def HasNEON : Predicate<"Subtarget->hasNEON()">;
108def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
109def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
110def IsThumb : Predicate<"Subtarget->isThumb()">;
111def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
112def IsThumb2 : Predicate<"Subtarget->isThumb2()">;
113def IsARM : Predicate<"!Subtarget->isThumb()">;
114def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
115def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
116def CarryDefIsUnused : Predicate<"!N.getNode()->hasAnyUseOfValue(1)">;
117def CarryDefIsUsed : Predicate<"N.getNode()->hasAnyUseOfValue(1)">;
118
119//===----------------------------------------------------------------------===//
120// ARM Flag Definitions.
121
122class RegConstraint<string C> {
123 string Constraints = C;
124}
125
126//===----------------------------------------------------------------------===//
127// ARM specific transformation functions and pattern fragments.
128//
129
130// so_imm_neg_XFORM - Return a so_imm value packed into the format described for
131// so_imm_neg def below.
132def so_imm_neg_XFORM : SDNodeXForm<imm, [{
133 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
134}]>;
135
136// so_imm_not_XFORM - Return a so_imm value packed into the format described for
137// so_imm_not def below.
138def so_imm_not_XFORM : SDNodeXForm<imm, [{
139 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
140}]>;
141
142// rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
143def rot_imm : PatLeaf<(i32 imm), [{
144 int32_t v = (int32_t)N->getZExtValue();
145 return v == 8 || v == 16 || v == 24;
146}]>;
147
148/// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
149def imm1_15 : PatLeaf<(i32 imm), [{
150 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
151}]>;
152
153/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
154def imm16_31 : PatLeaf<(i32 imm), [{
155 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
156}]>;
157
158def so_imm_neg :
159 PatLeaf<(imm), [{
160 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
161 }], so_imm_neg_XFORM>;
162
163def so_imm_not :
164 PatLeaf<(imm), [{
165 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
166 }], so_imm_not_XFORM>;
167
168// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
169def sext_16_node : PatLeaf<(i32 GPR:$a), [{
170 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
171}]>;
172
173/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
174/// e.g., 0xf000ffff
175def bf_inv_mask_imm : Operand<i32>,
176 PatLeaf<(imm), [{
177 uint32_t v = (uint32_t)N->getZExtValue();
178 if (v == 0xffffffff)
179 return 0;
180 // there can be 1's on either or both "outsides", all the "inside"
181 // bits must be 0's
182 unsigned int lsb = 0, msb = 31;
183 while (v & (1 << msb)) --msb;
184 while (v & (1 << lsb)) ++lsb;
185 for (unsigned int i = lsb; i <= msb; ++i) {
186 if (v & (1 << i))
187 return 0;
188 }
189 return 1;
190}] > {
191 let PrintMethod = "printBitfieldInvMaskImmOperand";
192}
193
194/// Split a 32-bit immediate into two 16 bit parts.
195def lo16 : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
197 MVT::i32);
198}]>;
199
200def hi16 : SDNodeXForm<imm, [{
201 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
202}]>;
203
204def lo16AllZero : PatLeaf<(i32 imm), [{
205 // Returns true if all low 16-bits are 0.
206 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
207 }], hi16>;
208
209/// imm0_65535 predicate - True if the 32-bit immediate is in the range
210/// [0.65535].
211def imm0_65535 : PatLeaf<(i32 imm), [{
212 return (uint32_t)N->getZExtValue() < 65536;
213}]>;
214
215class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
216class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
217
218//===----------------------------------------------------------------------===//
219// Operand Definitions.
220//
221
222// Branch target.
223def brtarget : Operand<OtherVT>;
224
225// A list of registers separated by comma. Used by load/store multiple.
226def reglist : Operand<i32> {
227 let PrintMethod = "printRegisterList";
228}
229
230// An operand for the CONSTPOOL_ENTRY pseudo-instruction.
231def cpinst_operand : Operand<i32> {
232 let PrintMethod = "printCPInstOperand";
233}
234
235def jtblock_operand : Operand<i32> {
236 let PrintMethod = "printJTBlockOperand";
237}
238def jt2block_operand : Operand<i32> {
239 let PrintMethod = "printJT2BlockOperand";
240}
241
242// Local PC labels.
243def pclabel : Operand<i32> {
244 let PrintMethod = "printPCLabel";
245}
246
247// shifter_operand operands: so_reg and so_imm.
248def so_reg : Operand<i32>, // reg reg imm
249 ComplexPattern<i32, 3, "SelectShifterOperandReg",
250 [shl,srl,sra,rotr]> {
251 let PrintMethod = "printSORegOperand";
252 let MIOperandInfo = (ops GPR, GPR, i32imm);
253}
254
255// so_imm - Match a 32-bit shifter_operand immediate operand, which is an
256// 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
257// represented in the imm field in the same 12-bit form that they are encoded
258// into so_imm instructions: the 8-bit immediate is the least significant bits
259// [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
260def so_imm : Operand<i32>,
261 PatLeaf<(imm), [{
262 return ARM_AM::getSOImmVal(N->getZExtValue()) != -1;
263 }]> {
264 let PrintMethod = "printSOImmOperand";
265}
266
267// Break so_imm's up into two pieces. This handles immediates with up to 16
268// bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
269// get the first/second pieces.
270def so_imm2part : Operand<i32>,
271 PatLeaf<(imm), [{
272 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
273 }]> {
274 let PrintMethod = "printSOImm2PartOperand";
275}
276
277def so_imm2part_1 : SDNodeXForm<imm, [{
278 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
279 return CurDAG->getTargetConstant(V, MVT::i32);
280}]>;
281
282def so_imm2part_2 : SDNodeXForm<imm, [{
283 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
284 return CurDAG->getTargetConstant(V, MVT::i32);
285}]>;
286
287/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
288def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
289 return (int32_t)N->getZExtValue() < 32;
290}]>;
291
292// Define ARM specific addressing modes.
293
294// addrmode2 := reg +/- reg shop imm
295// addrmode2 := reg +/- imm12
296//
297def addrmode2 : Operand<i32>,
298 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
299 let PrintMethod = "printAddrMode2Operand";
300 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
301}
302
303def am2offset : Operand<i32>,
304 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
305 let PrintMethod = "printAddrMode2OffsetOperand";
306 let MIOperandInfo = (ops GPR, i32imm);
307}
308
309// addrmode3 := reg +/- reg
310// addrmode3 := reg +/- imm8
311//
312def addrmode3 : Operand<i32>,
313 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
314 let PrintMethod = "printAddrMode3Operand";
315 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
316}
317
318def am3offset : Operand<i32>,
319 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
320 let PrintMethod = "printAddrMode3OffsetOperand";
321 let MIOperandInfo = (ops GPR, i32imm);
322}
323
324// addrmode4 := reg, <mode|W>
325//
326def addrmode4 : Operand<i32>,
327 ComplexPattern<i32, 2, "SelectAddrMode4", []> {
328 let PrintMethod = "printAddrMode4Operand";
329 let MIOperandInfo = (ops GPR, i32imm);
330}
331
332// addrmode5 := reg +/- imm8*4
333//
334def addrmode5 : Operand<i32>,
335 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
336 let PrintMethod = "printAddrMode5Operand";
337 let MIOperandInfo = (ops GPR, i32imm);
338}
339
340// addrmode6 := reg with optional writeback
341//
342def addrmode6 : Operand<i32>,
343 ComplexPattern<i32, 4, "SelectAddrMode6", []> {
344 let PrintMethod = "printAddrMode6Operand";
345 let MIOperandInfo = (ops GPR:$addr, GPR:$upd, i32imm, i32imm);
346}
347
348// addrmodepc := pc + reg
349//
350def addrmodepc : Operand<i32>,
351 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
352 let PrintMethod = "printAddrModePCOperand";
353 let MIOperandInfo = (ops GPR, i32imm);
354}
355
356def nohash_imm : Operand<i32> {
357 let PrintMethod = "printNoHashImmediate";
358}
359
360//===----------------------------------------------------------------------===//
361
362include "ARMInstrFormats.td"
363
364//===----------------------------------------------------------------------===//
365// Multiclass helpers...
366//
367
368/// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
369/// binop that produces a value.
370multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
371 bit Commutable = 0> {
372 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
373 IIC_iALUi, opc, "\t$dst, $a, $b",
374 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
375 let Inst{25} = 1;
376 }
377 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
378 IIC_iALUr, opc, "\t$dst, $a, $b",
379 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
380 let Inst{11-4} = 0b00000000;
381 let Inst{25} = 0;
382 let isCommutable = Commutable;
383 }
384 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
385 IIC_iALUsr, opc, "\t$dst, $a, $b",
386 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
387 let Inst{25} = 0;
388 }
389}
390
391/// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
392/// instruction modifies the CPSR register.
393let Defs = [CPSR] in {
394multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
395 bit Commutable = 0> {
396 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
397 IIC_iALUi, opc, "\t$dst, $a, $b",
398 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
399 let Inst{20} = 1;
400 let Inst{25} = 1;
401 }
402 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
403 IIC_iALUr, opc, "\t$dst, $a, $b",
404 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
405 let isCommutable = Commutable;
406 let Inst{11-4} = 0b00000000;
407 let Inst{20} = 1;
408 let Inst{25} = 0;
409 }
410 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
411 IIC_iALUsr, opc, "\t$dst, $a, $b",
412 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
413 let Inst{20} = 1;
414 let Inst{25} = 0;
415 }
416}
417}
418
419/// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
420/// patterns. Similar to AsI1_bin_irs except the instruction does not produce
421/// a explicit result, only implicitly set CPSR.
422let Defs = [CPSR] in {
423multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
424 bit Commutable = 0> {
425 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm, IIC_iCMPi,
426 opc, "\t$a, $b",
427 [(opnode GPR:$a, so_imm:$b)]> {
428 let Inst{20} = 1;
429 let Inst{25} = 1;
430 }
431 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm, IIC_iCMPr,
432 opc, "\t$a, $b",
433 [(opnode GPR:$a, GPR:$b)]> {
434 let Inst{11-4} = 0b00000000;
435 let Inst{20} = 1;
436 let Inst{25} = 0;
437 let isCommutable = Commutable;
438 }
439 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm, IIC_iCMPsr,
440 opc, "\t$a, $b",
441 [(opnode GPR:$a, so_reg:$b)]> {
442 let Inst{20} = 1;
443 let Inst{25} = 0;
444 }
445}
446}
447
448/// AI_unary_rrot - A unary operation with two forms: one whose operand is a
449/// register and one whose operand is a register rotated by 8/16/24.
450/// FIXME: Remove the 'r' variant. Its rot_imm is zero.
451multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
452 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src),
453 IIC_iUNAr, opc, "\t$dst, $src",
454 [(set GPR:$dst, (opnode GPR:$src))]>,
455 Requires<[IsARM, HasV6]> {
456 let Inst{11-10} = 0b00;
457 let Inst{19-16} = 0b1111;
458 }
459 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
460 IIC_iUNAsi, opc, "\t$dst, $src, ror $rot",
461 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
462 Requires<[IsARM, HasV6]> {
463 let Inst{19-16} = 0b1111;
464 }
465}
466
467/// AI_bin_rrot - A binary operation with two forms: one whose operand is a
468/// register and one whose operand is a register rotated by 8/16/24.
469multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
470 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
471 IIC_iALUr, opc, "\t$dst, $LHS, $RHS",
472 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
473 Requires<[IsARM, HasV6]> {
474 let Inst{11-10} = 0b00;
475 }
476 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
477 IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot",
478 [(set GPR:$dst, (opnode GPR:$LHS,
479 (rotr GPR:$RHS, rot_imm:$rot)))]>,
480 Requires<[IsARM, HasV6]>;
481}
482
483/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
484let Uses = [CPSR] in {
485multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
486 bit Commutable = 0> {
487 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
488 DPFrm, IIC_iALUi, opc, "\t$dst, $a, $b",
489 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
490 Requires<[IsARM, CarryDefIsUnused]> {
491 let Inst{25} = 1;
492 }
493 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
494 DPFrm, IIC_iALUr, opc, "\t$dst, $a, $b",
495 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
496 Requires<[IsARM, CarryDefIsUnused]> {
497 let isCommutable = Commutable;
498 let Inst{11-4} = 0b00000000;
499 let Inst{25} = 0;
500 }
501 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
502 DPSoRegFrm, IIC_iALUsr, opc, "\t$dst, $a, $b",
503 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
504 Requires<[IsARM, CarryDefIsUnused]> {
505 let Inst{25} = 0;
506 }
507}
508// Carry setting variants
509let Defs = [CPSR] in {
510multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
511 bit Commutable = 0> {
512 def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
513 DPFrm, IIC_iALUi, !strconcat(opc, "\t$dst, $a, $b"),
514 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
515 Requires<[IsARM, CarryDefIsUsed]> {
516 let Defs = [CPSR];
517 let Inst{20} = 1;
518 let Inst{25} = 1;
519 }
520 def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
521 DPFrm, IIC_iALUr, !strconcat(opc, "\t$dst, $a, $b"),
522 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
523 Requires<[IsARM, CarryDefIsUsed]> {
524 let Defs = [CPSR];
525 let Inst{11-4} = 0b00000000;
526 let Inst{20} = 1;
527 let Inst{25} = 0;
528 }
529 def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
530 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$dst, $a, $b"),
531 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
532 Requires<[IsARM, CarryDefIsUsed]> {
533 let Defs = [CPSR];
534 let Inst{20} = 1;
535 let Inst{25} = 0;
536 }
537}
538}
539}
540
541//===----------------------------------------------------------------------===//
542// Instructions
543//===----------------------------------------------------------------------===//
544
545//===----------------------------------------------------------------------===//
546// Miscellaneous Instructions.
547//
548
549/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
550/// the function. The first operand is the ID# for this instruction, the second
551/// is the index into the MachineConstantPool that this is, the third is the
552/// size in bytes of this constant pool entry.
553let neverHasSideEffects = 1, isNotDuplicable = 1 in
554def CONSTPOOL_ENTRY :
555PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
556 i32imm:$size), NoItinerary,
557 "${instid:label} ${cpidx:cpentry}", []>;
558
559let Defs = [SP], Uses = [SP] in {
560def ADJCALLSTACKUP :
561PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
562 "@ ADJCALLSTACKUP $amt1",
563 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
564
565def ADJCALLSTACKDOWN :
566PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
567 "@ ADJCALLSTACKDOWN $amt",
568 [(ARMcallseq_start timm:$amt)]>;
569}
570
571def DWARF_LOC :
572PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), NoItinerary,
573 ".loc $file, $line, $col",
574 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
575
576
577// Address computation and loads and stores in PIC mode.
578let isNotDuplicable = 1 in {
579def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
580 Pseudo, IIC_iALUr, "\n$cp:\n\tadd$p\t$dst, pc, $a",
581 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
582
583let AddedComplexity = 10 in {
584let canFoldAsLoad = 1 in
585def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
586 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr$p\t$dst, $addr",
587 [(set GPR:$dst, (load addrmodepc:$addr))]>;
588
589def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
590 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}h\t$dst, $addr",
591 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
592
593def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
594 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}b\t$dst, $addr",
595 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
596
597def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
598 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}sh\t$dst, $addr",
599 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
600
601def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
602 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}sb\t$dst, $addr",
603 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
604}
605let AddedComplexity = 10 in {
606def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
607 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr$p\t$src, $addr",
608 [(store GPR:$src, addrmodepc:$addr)]>;
609
610def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
|
616 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
617}
618} // isNotDuplicable = 1
619
620
621// LEApcrel - Load a pc-relative address into a register without offending the
622// assembler.
623def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
624 Pseudo, IIC_iALUi,
625 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, ($label-(",
626 "${:private}PCRELL${:uid}+8))\n"),
627 !strconcat("${:private}PCRELL${:uid}:\n\t",
628 "add$p\t$dst, pc, #${:private}PCRELV${:uid}")),
629 []>;
630
631def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
632 (ins i32imm:$label, nohash_imm:$id, pred:$p),
633 Pseudo, IIC_iALUi,
634 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, "
635 "(${label}_${id}-(",
636 "${:private}PCRELL${:uid}+8))\n"),
637 !strconcat("${:private}PCRELL${:uid}:\n\t",
638 "add$p\t$dst, pc, #${:private}PCRELV${:uid}")),
639 []> {
640 let Inst{25} = 1;
641}
642
643//===----------------------------------------------------------------------===//
644// Control Flow Instructions.
645//
646
647let isReturn = 1, isTerminator = 1, isBarrier = 1 in
648 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
649 "bx", "\tlr", [(ARMretflag)]> {
650 let Inst{3-0} = 0b1110;
651 let Inst{7-4} = 0b0001;
652 let Inst{19-8} = 0b111111111111;
653 let Inst{27-20} = 0b00010010;
654}
655
656// Indirect branches
657let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
658 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
659 [(brind GPR:$dst)]> {
660 let Inst{7-4} = 0b0001;
661 let Inst{19-8} = 0b111111111111;
662 let Inst{27-20} = 0b00010010;
663 let Inst{31-28} = 0b1110;
664 }
665}
666
667// FIXME: remove when we have a way to marking a MI with these properties.
668// FIXME: Should pc be an implicit operand like PICADD, etc?
669let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
670 hasExtraDefRegAllocReq = 1 in
671 def LDM_RET : AXI4ld<(outs),
672 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
673 LdStMulFrm, IIC_Br, "ldm${addr:submode}${p}\t$addr, $wb",
674 []>;
675
676// On non-Darwin platforms R9 is callee-saved.
677let isCall = 1,
678 Defs = [R0, R1, R2, R3, R12, LR,
679 D0, D1, D2, D3, D4, D5, D6, D7,
680 D16, D17, D18, D19, D20, D21, D22, D23,
681 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
682 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
683 IIC_Br, "bl\t${func:call}",
684 [(ARMcall tglobaladdr:$func)]>,
685 Requires<[IsARM, IsNotDarwin]> {
686 let Inst{31-28} = 0b1110;
687 }
688
689 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
690 IIC_Br, "bl", "\t${func:call}",
691 [(ARMcall_pred tglobaladdr:$func)]>,
692 Requires<[IsARM, IsNotDarwin]>;
693
694 // ARMv5T and above
695 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
696 IIC_Br, "blx\t$func",
697 [(ARMcall GPR:$func)]>,
698 Requires<[IsARM, HasV5T, IsNotDarwin]> {
699 let Inst{7-4} = 0b0011;
700 let Inst{19-8} = 0b111111111111;
701 let Inst{27-20} = 0b00010010;
702 }
703
704 // ARMv4T
705 def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
706 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
707 [(ARMcall_nolink GPR:$func)]>,
708 Requires<[IsARM, IsNotDarwin]> {
709 let Inst{7-4} = 0b0001;
710 let Inst{19-8} = 0b111111111111;
711 let Inst{27-20} = 0b00010010;
712 }
713}
714
715// On Darwin R9 is call-clobbered.
716let isCall = 1,
717 Defs = [R0, R1, R2, R3, R9, R12, LR,
718 D0, D1, D2, D3, D4, D5, D6, D7,
719 D16, D17, D18, D19, D20, D21, D22, D23,
720 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
721 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
722 IIC_Br, "bl\t${func:call}",
723 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
724 let Inst{31-28} = 0b1110;
725 }
726
727 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
728 IIC_Br, "bl", "\t${func:call}",
729 [(ARMcall_pred tglobaladdr:$func)]>,
730 Requires<[IsARM, IsDarwin]>;
731
732 // ARMv5T and above
733 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
734 IIC_Br, "blx\t$func",
735 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
736 let Inst{7-4} = 0b0011;
737 let Inst{19-8} = 0b111111111111;
738 let Inst{27-20} = 0b00010010;
739 }
740
741 // ARMv4T
742 def BXr9 : ABXIx2<(outs), (ins GPR:$func, variable_ops),
743 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
744 [(ARMcall_nolink GPR:$func)]>, Requires<[IsARM, IsDarwin]> {
745 let Inst{7-4} = 0b0001;
746 let Inst{19-8} = 0b111111111111;
747 let Inst{27-20} = 0b00010010;
748 }
749}
750
751let isBranch = 1, isTerminator = 1 in {
752 // B is "predicable" since it can be xformed into a Bcc.
753 let isBarrier = 1 in {
754 let isPredicable = 1 in
755 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
756 "b\t$target", [(br bb:$target)]>;
757
758 let isNotDuplicable = 1, isIndirectBranch = 1 in {
759 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
760 IIC_Br, "mov\tpc, $target \n$jt",
761 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
762 let Inst{15-12} = 0b1111;
763 let Inst{20} = 0; // S Bit
764 let Inst{24-21} = 0b1101;
765 let Inst{27-25} = 0b000;
766 }
767 def BR_JTm : JTI<(outs),
768 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
769 IIC_Br, "ldr\tpc, $target \n$jt",
770 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
771 imm:$id)]> {
772 let Inst{15-12} = 0b1111;
773 let Inst{20} = 1; // L bit
774 let Inst{21} = 0; // W bit
775 let Inst{22} = 0; // B bit
776 let Inst{24} = 1; // P bit
777 let Inst{27-25} = 0b011;
778 }
779 def BR_JTadd : JTI<(outs),
780 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
781 IIC_Br, "add\tpc, $target, $idx \n$jt",
782 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
783 imm:$id)]> {
784 let Inst{15-12} = 0b1111;
785 let Inst{20} = 0; // S bit
786 let Inst{24-21} = 0b0100;
787 let Inst{27-25} = 0b000;
788 }
789 } // isNotDuplicable = 1, isIndirectBranch = 1
790 } // isBarrier = 1
791
792 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
793 // a two-value operand where a dag node expects two operands. :(
794 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
795 IIC_Br, "b", "\t$target",
796 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
797}
798
799//===----------------------------------------------------------------------===//
800// Load / store Instructions.
801//
802
803// Load
804let canFoldAsLoad = 1, isReMaterializable = 1 in
805def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
806 "ldr", "\t$dst, $addr",
807 [(set GPR:$dst, (load addrmode2:$addr))]>;
808
809// Special LDR for loads from non-pc-relative constpools.
810let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
811def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
812 "ldr", "\t$dst, $addr", []>;
813
814// Loads with zero extension
815def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
816 IIC_iLoadr, "ldrh", "\t$dst, $addr",
817 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
818
819def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
820 IIC_iLoadr, "ldrb", "\t$dst, $addr",
821 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
822
823// Loads with sign extension
824def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
825 IIC_iLoadr, "ldrsh", "\t$dst, $addr",
826 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
827
828def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
829 IIC_iLoadr, "ldrsb", "\t$dst, $addr",
830 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
831
832let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
833// Load doubleword
834def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
835 IIC_iLoadr, "ldrd", "\t$dst1, $addr",
836 []>, Requires<[IsARM, HasV5TE]>;
837
838// Indexed loads
839def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
840 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
841 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
842
843def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
844 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru,
845 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
846
847def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
848 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
849 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
850
851def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
852 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
853 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
854
855def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
856 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
857 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
858
859def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
860 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru,
861 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
862
863def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
864 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
865 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
866
867def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
868 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
869 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
870
871def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
872 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
873 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
874
875def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
876 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
877 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
878}
879
880// Store
881def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
882 "str", "\t$src, $addr",
883 [(store GPR:$src, addrmode2:$addr)]>;
884
885// Stores with truncate
886def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, IIC_iStorer,
887 "strh", "\t$src, $addr",
888 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
889
890def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
891 "strb", "\t$src, $addr",
892 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
893
894// Store doubleword
895let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
896def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
897 StMiscFrm, IIC_iStorer,
898 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
899
900// Indexed stores
901def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
902 (ins GPR:$src, GPR:$base, am2offset:$offset),
903 StFrm, IIC_iStoreru,
904 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
905 [(set GPR:$base_wb,
906 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
907
908def STR_POST : AI2stwpo<(outs GPR:$base_wb),
909 (ins GPR:$src, GPR:$base,am2offset:$offset),
910 StFrm, IIC_iStoreru,
911 "str", "\t$src, [$base], $offset", "$base = $base_wb",
912 [(set GPR:$base_wb,
913 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
914
915def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
916 (ins GPR:$src, GPR:$base,am3offset:$offset),
917 StMiscFrm, IIC_iStoreru,
918 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
919 [(set GPR:$base_wb,
920 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
921
922def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
923 (ins GPR:$src, GPR:$base,am3offset:$offset),
924 StMiscFrm, IIC_iStoreru,
925 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
926 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
927 GPR:$base, am3offset:$offset))]>;
928
929def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
930 (ins GPR:$src, GPR:$base,am2offset:$offset),
931 StFrm, IIC_iStoreru,
932 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
933 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
934 GPR:$base, am2offset:$offset))]>;
935
936def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
937 (ins GPR:$src, GPR:$base,am2offset:$offset),
938 StFrm, IIC_iStoreru,
939 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
940 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
941 GPR:$base, am2offset:$offset))]>;
942
943//===----------------------------------------------------------------------===//
944// Load / store multiple Instructions.
945//
946
947let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
948def LDM : AXI4ld<(outs),
949 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
950 LdStMulFrm, IIC_iLoadm, "ldm${addr:submode}${p}\t$addr, $wb",
951 []>;
952
953let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
954def STM : AXI4st<(outs),
955 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
956 LdStMulFrm, IIC_iStorem, "stm${addr:submode}${p}\t$addr, $wb",
957 []>;
958
959//===----------------------------------------------------------------------===//
960// Move Instructions.
961//
962
963let neverHasSideEffects = 1 in
964def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
965 "mov", "\t$dst, $src", []>, UnaryDP {
966 let Inst{11-4} = 0b00000000;
967 let Inst{25} = 0;
968}
969
970def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
971 DPSoRegFrm, IIC_iMOVsr,
972 "mov", "\t$dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP {
973 let Inst{25} = 0;
974}
975
976let isReMaterializable = 1, isAsCheapAsAMove = 1 in
977def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, IIC_iMOVi,
978 "mov", "\t$dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP {
979 let Inst{25} = 1;
980}
981
982let isReMaterializable = 1, isAsCheapAsAMove = 1 in
983def MOVi16 : AI1<0b1000, (outs GPR:$dst), (ins i32imm:$src),
984 DPFrm, IIC_iMOVi,
985 "movw", "\t$dst, $src",
986 [(set GPR:$dst, imm0_65535:$src)]>,
987 Requires<[IsARM, HasV6T2]> {
988 let Inst{20} = 0;
989 let Inst{25} = 1;
990}
991
992let Constraints = "$src = $dst" in
993def MOVTi16 : AI1<0b1010, (outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
994 DPFrm, IIC_iMOVi,
995 "movt", "\t$dst, $imm",
996 [(set GPR:$dst,
997 (or (and GPR:$src, 0xffff),
998 lo16AllZero:$imm))]>, UnaryDP,
999 Requires<[IsARM, HasV6T2]> {
1000 let Inst{20} = 0;
1001 let Inst{25} = 1;
1002}
1003
1004def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1005 Requires<[IsARM, HasV6T2]>;
1006
1007let Uses = [CPSR] in
1008def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi,
1009 "mov", "\t$dst, $src, rrx",
1010 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
1011
1012// These aren't really mov instructions, but we have to define them this way
1013// due to flag operands.
1014
1015let Defs = [CPSR] in {
1016def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
1017 IIC_iMOVsi, "movs", "\t$dst, $src, lsr #1",
1018 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
1019def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
1020 IIC_iMOVsi, "movs", "\t$dst, $src, asr #1",
1021 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
1022}
1023
1024//===----------------------------------------------------------------------===//
1025// Extend Instructions.
1026//
1027
1028// Sign extenders
1029
1030defm SXTB : AI_unary_rrot<0b01101010,
1031 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1032defm SXTH : AI_unary_rrot<0b01101011,
1033 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1034
1035defm SXTAB : AI_bin_rrot<0b01101010,
1036 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1037defm SXTAH : AI_bin_rrot<0b01101011,
1038 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1039
1040// TODO: SXT(A){B|H}16
1041
1042// Zero extenders
1043
1044let AddedComplexity = 16 in {
1045defm UXTB : AI_unary_rrot<0b01101110,
1046 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1047defm UXTH : AI_unary_rrot<0b01101111,
1048 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1049defm UXTB16 : AI_unary_rrot<0b01101100,
1050 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1051
1052def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1053 (UXTB16r_rot GPR:$Src, 24)>;
1054def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1055 (UXTB16r_rot GPR:$Src, 8)>;
1056
1057defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
1058 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1059defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
1060 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1061}
1062
1063// This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
1064//defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
1065
1066// TODO: UXT(A){B|H}16
1067
1068def SBFX : I<(outs GPR:$dst),
1069 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1070 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1071 "sbfx", "\t$dst, $src, $lsb, $width", "", []>,
1072 Requires<[IsARM, HasV6T2]> {
1073 let Inst{27-21} = 0b0111101;
1074 let Inst{6-4} = 0b101;
1075}
1076
1077def UBFX : I<(outs GPR:$dst),
1078 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1079 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1080 "ubfx", "\t$dst, $src, $lsb, $width", "", []>,
1081 Requires<[IsARM, HasV6T2]> {
1082 let Inst{27-21} = 0b0111111;
1083 let Inst{6-4} = 0b101;
1084}
1085
1086//===----------------------------------------------------------------------===//
1087// Arithmetic Instructions.
1088//
1089
1090defm ADD : AsI1_bin_irs<0b0100, "add",
1091 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1092defm SUB : AsI1_bin_irs<0b0010, "sub",
1093 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1094
1095// ADD and SUB with 's' bit set.
1096defm ADDS : AI1_bin_s_irs<0b0100, "adds",
1097 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1098defm SUBS : AI1_bin_s_irs<0b0010, "subs",
1099 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1100
1101defm ADC : AI1_adde_sube_irs<0b0101, "adc",
1102 BinOpFrag<(adde node:$LHS, node:$RHS)>, 1>;
1103defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
1104 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
1105defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
1106 BinOpFrag<(adde node:$LHS, node:$RHS)>, 1>;
1107defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
1108 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
1109
1110// These don't define reg/reg forms, because they are handled above.
1111def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1112 IIC_iALUi, "rsb", "\t$dst, $a, $b",
1113 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
1114 let Inst{25} = 1;
1115}
1116
1117def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1118 IIC_iALUsr, "rsb", "\t$dst, $a, $b",
1119 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> {
1120 let Inst{25} = 0;
1121}
1122
1123// RSB with 's' bit set.
1124let Defs = [CPSR] in {
1125def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1126 IIC_iALUi, "rsbs", "\t$dst, $a, $b",
1127 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]> {
1128 let Inst{20} = 1;
1129 let Inst{25} = 1;
1130}
1131def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1132 IIC_iALUsr, "rsbs", "\t$dst, $a, $b",
1133 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]> {
1134 let Inst{20} = 1;
1135 let Inst{25} = 0;
1136}
1137}
1138
1139let Uses = [CPSR] in {
1140def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1141 DPFrm, IIC_iALUi, "rsc", "\t$dst, $a, $b",
1142 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1143 Requires<[IsARM, CarryDefIsUnused]> {
1144 let Inst{25} = 1;
1145}
1146def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1147 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$dst, $a, $b",
1148 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
1149 Requires<[IsARM, CarryDefIsUnused]> {
1150 let Inst{25} = 0;
1151}
1152}
1153
1154// FIXME: Allow these to be predicated.
1155let Defs = [CPSR], Uses = [CPSR] in {
1156def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1157 DPFrm, IIC_iALUi, "rscs\t$dst, $a, $b",
1158 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1159 Requires<[IsARM, CarryDefIsUnused]> {
1160 let Inst{20} = 1;
1161 let Inst{25} = 1;
1162}
1163def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1164 DPSoRegFrm, IIC_iALUsr, "rscs\t$dst, $a, $b",
1165 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
1166 Requires<[IsARM, CarryDefIsUnused]> {
1167 let Inst{20} = 1;
1168 let Inst{25} = 0;
1169}
1170}
1171
1172// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1173def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
1174 (SUBri GPR:$src, so_imm_neg:$imm)>;
1175
1176//def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
1177// (SUBSri GPR:$src, so_imm_neg:$imm)>;
1178//def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
1179// (SBCri GPR:$src, so_imm_neg:$imm)>;
1180
1181// Note: These are implemented in C++ code, because they have to generate
1182// ADD/SUBrs instructions, which use a complex pattern that a xform function
1183// cannot produce.
1184// (mul X, 2^n+1) -> (add (X << n), X)
1185// (mul X, 2^n-1) -> (rsb X, (X << n))
1186
1187
1188//===----------------------------------------------------------------------===//
1189// Bitwise Instructions.
1190//
1191
1192defm AND : AsI1_bin_irs<0b0000, "and",
1193 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1194defm ORR : AsI1_bin_irs<0b1100, "orr",
1195 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1196defm EOR : AsI1_bin_irs<0b0001, "eor",
1197 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1198defm BIC : AsI1_bin_irs<0b1110, "bic",
1199 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1200
1201def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1202 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1203 "bfc", "\t$dst, $imm", "$src = $dst",
1204 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
1205 Requires<[IsARM, HasV6T2]> {
1206 let Inst{27-21} = 0b0111110;
1207 let Inst{6-0} = 0b0011111;
1208}
1209
1210def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
1211 "mvn", "\t$dst, $src",
1212 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP {
1213 let Inst{11-4} = 0b00000000;
1214}
1215def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
1216 IIC_iMOVsr, "mvn", "\t$dst, $src",
1217 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP;
1218let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1219def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
1220 IIC_iMOVi, "mvn", "\t$dst, $imm",
1221 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP {
1222 let Inst{25} = 1;
1223}
1224
1225def : ARMPat<(and GPR:$src, so_imm_not:$imm),
1226 (BICri GPR:$src, so_imm_not:$imm)>;
1227
1228//===----------------------------------------------------------------------===//
1229// Multiply Instructions.
1230//
1231
1232let isCommutable = 1 in
1233def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1234 IIC_iMUL32, "mul", "\t$dst, $a, $b",
1235 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
1236
1237def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1238 IIC_iMAC32, "mla", "\t$dst, $a, $b, $c",
1239 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
1240
1241def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1242 IIC_iMAC32, "mls", "\t$dst, $a, $b, $c",
1243 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
1244 Requires<[IsARM, HasV6T2]>;
1245
1246// Extra precision multiplies with low / high results
1247let neverHasSideEffects = 1 in {
1248let isCommutable = 1 in {
1249def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
1250 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1251 "smull", "\t$ldst, $hdst, $a, $b", []>;
1252
1253def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
1254 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1255 "umull", "\t$ldst, $hdst, $a, $b", []>;
1256}
1257
1258// Multiply + accumulate
1259def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
1260 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1261 "smlal", "\t$ldst, $hdst, $a, $b", []>;
1262
1263def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
1264 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1265 "umlal", "\t$ldst, $hdst, $a, $b", []>;
1266
1267def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
1268 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1269 "umaal", "\t$ldst, $hdst, $a, $b", []>,
1270 Requires<[IsARM, HasV6]>;
1271} // neverHasSideEffects
1272
1273// Most significant word multiply
1274def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1275 IIC_iMUL32, "smmul", "\t$dst, $a, $b",
1276 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1277 Requires<[IsARM, HasV6]> {
1278 let Inst{7-4} = 0b0001;
1279 let Inst{15-12} = 0b1111;
1280}
1281
1282def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1283 IIC_iMAC32, "smmla", "\t$dst, $a, $b, $c",
1284 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1285 Requires<[IsARM, HasV6]> {
1286 let Inst{7-4} = 0b0001;
1287}
1288
1289
1290def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1291 IIC_iMAC32, "smmls", "\t$dst, $a, $b, $c",
1292 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1293 Requires<[IsARM, HasV6]> {
1294 let Inst{7-4} = 0b1101;
1295}
1296
1297multiclass AI_smul<string opc, PatFrag opnode> {
1298 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1299 IIC_iMUL32, !strconcat(opc, "bb"), "\t$dst, $a, $b",
1300 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1301 (sext_inreg GPR:$b, i16)))]>,
1302 Requires<[IsARM, HasV5TE]> {
1303 let Inst{5} = 0;
1304 let Inst{6} = 0;
1305 }
1306
1307 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1308 IIC_iMUL32, !strconcat(opc, "bt"), "\t$dst, $a, $b",
1309 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1310 (sra GPR:$b, (i32 16))))]>,
1311 Requires<[IsARM, HasV5TE]> {
1312 let Inst{5} = 0;
1313 let Inst{6} = 1;
1314 }
1315
1316 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1317 IIC_iMUL32, !strconcat(opc, "tb"), "\t$dst, $a, $b",
1318 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1319 (sext_inreg GPR:$b, i16)))]>,
1320 Requires<[IsARM, HasV5TE]> {
1321 let Inst{5} = 1;
1322 let Inst{6} = 0;
1323 }
1324
1325 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1326 IIC_iMUL32, !strconcat(opc, "tt"), "\t$dst, $a, $b",
1327 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1328 (sra GPR:$b, (i32 16))))]>,
1329 Requires<[IsARM, HasV5TE]> {
1330 let Inst{5} = 1;
1331 let Inst{6} = 1;
1332 }
1333
1334 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1335 IIC_iMUL16, !strconcat(opc, "wb"), "\t$dst, $a, $b",
1336 [(set GPR:$dst, (sra (opnode GPR:$a,
1337 (sext_inreg GPR:$b, i16)), (i32 16)))]>,
1338 Requires<[IsARM, HasV5TE]> {
1339 let Inst{5} = 1;
1340 let Inst{6} = 0;
1341 }
1342
1343 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1344 IIC_iMUL16, !strconcat(opc, "wt"), "\t$dst, $a, $b",
1345 [(set GPR:$dst, (sra (opnode GPR:$a,
1346 (sra GPR:$b, (i32 16))), (i32 16)))]>,
1347 Requires<[IsARM, HasV5TE]> {
1348 let Inst{5} = 1;
1349 let Inst{6} = 1;
1350 }
1351}
1352
1353
1354multiclass AI_smla<string opc, PatFrag opnode> {
1355 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1356 IIC_iMAC16, !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
1357 [(set GPR:$dst, (add GPR:$acc,
1358 (opnode (sext_inreg GPR:$a, i16),
1359 (sext_inreg GPR:$b, i16))))]>,
1360 Requires<[IsARM, HasV5TE]> {
1361 let Inst{5} = 0;
1362 let Inst{6} = 0;
1363 }
1364
1365 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1366 IIC_iMAC16, !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
1367 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1368 (sra GPR:$b, (i32 16)))))]>,
1369 Requires<[IsARM, HasV5TE]> {
1370 let Inst{5} = 0;
1371 let Inst{6} = 1;
1372 }
1373
1374 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1375 IIC_iMAC16, !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
1376 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1377 (sext_inreg GPR:$b, i16))))]>,
1378 Requires<[IsARM, HasV5TE]> {
1379 let Inst{5} = 1;
1380 let Inst{6} = 0;
1381 }
1382
1383 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1384 IIC_iMAC16, !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
1385 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1386 (sra GPR:$b, (i32 16)))))]>,
1387 Requires<[IsARM, HasV5TE]> {
1388 let Inst{5} = 1;
1389 let Inst{6} = 1;
1390 }
1391
1392 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1393 IIC_iMAC16, !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
1394 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1395 (sext_inreg GPR:$b, i16)), (i32 16))))]>,
1396 Requires<[IsARM, HasV5TE]> {
1397 let Inst{5} = 0;
1398 let Inst{6} = 0;
1399 }
1400
1401 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1402 IIC_iMAC16, !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
1403 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1404 (sra GPR:$b, (i32 16))), (i32 16))))]>,
1405 Requires<[IsARM, HasV5TE]> {
1406 let Inst{5} = 0;
1407 let Inst{6} = 1;
1408 }
1409}
1410
1411defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1412defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1413
1414// TODO: Halfword multiple accumulate long: SMLAL<x><y>
1415// TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1416
1417//===----------------------------------------------------------------------===//
1418// Misc. Arithmetic Instructions.
1419//
1420
1421def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1422 "clz", "\t$dst, $src",
1423 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
1424 let Inst{7-4} = 0b0001;
1425 let Inst{11-8} = 0b1111;
1426 let Inst{19-16} = 0b1111;
1427}
1428
1429def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1430 "rev", "\t$dst, $src",
1431 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
1432 let Inst{7-4} = 0b0011;
1433 let Inst{11-8} = 0b1111;
1434 let Inst{19-16} = 0b1111;
1435}
1436
1437def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1438 "rev16", "\t$dst, $src",
1439 [(set GPR:$dst,
1440 (or (and (srl GPR:$src, (i32 8)), 0xFF),
1441 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
1442 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
1443 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>,
1444 Requires<[IsARM, HasV6]> {
1445 let Inst{7-4} = 0b1011;
1446 let Inst{11-8} = 0b1111;
1447 let Inst{19-16} = 0b1111;
1448}
1449
1450def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1451 "revsh", "\t$dst, $src",
1452 [(set GPR:$dst,
1453 (sext_inreg
1454 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
1455 (shl GPR:$src, (i32 8))), i16))]>,
1456 Requires<[IsARM, HasV6]> {
1457 let Inst{7-4} = 0b1011;
1458 let Inst{11-8} = 0b1111;
1459 let Inst{19-16} = 0b1111;
1460}
1461
1462def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
1463 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1464 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, LSL $shamt",
1465 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1466 (and (shl GPR:$src2, (i32 imm:$shamt)),
1467 0xFFFF0000)))]>,
1468 Requires<[IsARM, HasV6]> {
1469 let Inst{6-4} = 0b001;
1470}
1471
1472// Alternate cases for PKHBT where identities eliminate some nodes.
1473def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1474 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1475def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1476 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1477
1478
1479def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
1480 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1481 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, ASR $shamt",
1482 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1483 (and (sra GPR:$src2, imm16_31:$shamt),
1484 0xFFFF)))]>, Requires<[IsARM, HasV6]> {
1485 let Inst{6-4} = 0b101;
1486}
1487
1488// Alternate cases for PKHTB where identities eliminate some nodes. Note that
1489// a shift amount of 0 is *not legal* here, it is PKHBT instead.
1490def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
1491 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1492def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1493 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1494 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1495
1496//===----------------------------------------------------------------------===//
1497// Comparison Instructions...
1498//
1499
1500defm CMP : AI1_cmp_irs<0b1010, "cmp",
1501 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1502defm CMN : AI1_cmp_irs<0b1011, "cmn",
1503 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1504
1505// Note that TST/TEQ don't set all the same flags that CMP does!
1506defm TST : AI1_cmp_irs<0b1000, "tst",
1507 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
1508defm TEQ : AI1_cmp_irs<0b1001, "teq",
1509 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
1510
1511defm CMPz : AI1_cmp_irs<0b1010, "cmp",
1512 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
1513defm CMNz : AI1_cmp_irs<0b1011, "cmn",
1514 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
1515
1516def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1517 (CMNri GPR:$src, so_imm_neg:$imm)>;
1518
1519def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
1520 (CMNri GPR:$src, so_imm_neg:$imm)>;
1521
1522
1523// Conditional moves
1524// FIXME: should be able to write a pattern for ARMcmov, but can't use
1525// a two-value operand where a dag node expects two operands. :(
1526def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
1527 IIC_iCMOVr, "mov", "\t$dst, $true",
1528 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1529 RegConstraint<"$false = $dst">, UnaryDP {
1530 let Inst{11-4} = 0b00000000;
1531 let Inst{25} = 0;
1532}
1533
1534def MOVCCs : AI1<0b1101, (outs GPR:$dst),
1535 (ins GPR:$false, so_reg:$true), DPSoRegFrm, IIC_iCMOVsr,
1536 "mov", "\t$dst, $true",
1537 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1538 RegConstraint<"$false = $dst">, UnaryDP {
1539 let Inst{25} = 0;
1540}
1541
1542def MOVCCi : AI1<0b1101, (outs GPR:$dst),
1543 (ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi,
1544 "mov", "\t$dst, $true",
1545 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1546 RegConstraint<"$false = $dst">, UnaryDP {
1547 let Inst{25} = 1;
1548}
1549
1550
1551//===----------------------------------------------------------------------===//
1552// TLS Instructions
1553//
1554
1555// __aeabi_read_tp preserves the registers r1-r3.
1556let isCall = 1,
1557 Defs = [R0, R12, LR, CPSR] in {
1558 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
1559 "bl\t__aeabi_read_tp",
1560 [(set R0, ARMthread_pointer)]>;
1561}
1562
1563//===----------------------------------------------------------------------===//
1564// SJLJ Exception handling intrinsics
1565// eh_sjlj_setjmp() is an instruction sequence to store the return
1566// address and save #0 in R0 for the non-longjmp case.
1567// Since by its nature we may be coming from some other function to get
1568// here, and we're using the stack frame for the containing function to
1569// save/restore registers, we can't keep anything live in regs across
1570// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
1571// when we get here from a longjmp(). We force everthing out of registers
1572// except for our own input by listing the relevant registers in Defs. By
1573// doing so, we also cause the prologue/epilogue code to actively preserve
1574// all of the callee-saved resgisters, which is exactly what we want.
1575let Defs =
1576 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
1577 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
1578 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
1579 D31 ] in {
1580 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src),
1581 AddrModeNone, SizeSpecial, IndexModeNone,
1582 Pseudo, NoItinerary,
1583 "str\tsp, [$src, #+8] @ eh_setjmp begin\n\t"
1584 "add\tr12, pc, #8\n\t"
1585 "str\tr12, [$src, #+4]\n\t"
1586 "mov\tr0, #0\n\t"
1587 "add\tpc, pc, #0\n\t"
1588 "mov\tr0, #1 @ eh_setjmp end", "",
1589 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>;
1590}
1591
1592//===----------------------------------------------------------------------===//
1593// Non-Instruction Patterns
1594//
1595
1596// ConstantPool, GlobalAddress, and JumpTable
1597def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1598def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1599def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1600 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1601
1602// Large immediate handling.
1603
1604// Two piece so_imms.
1605let isReMaterializable = 1 in
1606def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src),
1607 Pseudo, IIC_iMOVi,
1608 "mov", "\t$dst, $src",
1609 [(set GPR:$dst, so_imm2part:$src)]>,
1610 Requires<[IsARM, NoV6T2]>;
1611
1612def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1613 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1614 (so_imm2part_2 imm:$RHS))>;
1615def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1616 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1617 (so_imm2part_2 imm:$RHS))>;
1618def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS),
1619 (ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1620 (so_imm2part_2 imm:$RHS))>;
1621def : ARMPat<(sub GPR:$LHS, so_imm2part:$RHS),
1622 (SUBri (SUBri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1623 (so_imm2part_2 imm:$RHS))>;
1624
1625// 32-bit immediate using movw + movt.
1626// This is a single pseudo instruction, the benefit is that it can be remat'd
1627// as a single unit instead of having to handle reg inputs.
1628// FIXME: Remove this when we can do generalized remat.
1629let isReMaterializable = 1 in
1630def MOVi32imm : AI1x2<(outs GPR:$dst), (ins i32imm:$src), Pseudo, IIC_iMOVi,
1631 "movw", "\t$dst, ${src:lo16}\n\tmovt${p} $dst, ${src:hi16}",
1632 [(set GPR:$dst, (i32 imm:$src))]>,
1633 Requires<[IsARM, HasV6T2]>;
1634
1635// TODO: add,sub,and, 3-instr forms?
1636
1637
1638// Direct calls
1639def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
1640 Requires<[IsARM, IsNotDarwin]>;
1641def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
1642 Requires<[IsARM, IsDarwin]>;
1643
1644// zextload i1 -> zextload i8
1645def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1646
1647// extload -> zextload
1648def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1649def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1650def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1651
1652def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
1653def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
1654
1655// smul* and smla*
1656def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1657 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1658 (SMULBB GPR:$a, GPR:$b)>;
1659def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1660 (SMULBB GPR:$a, GPR:$b)>;
1661def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1662 (sra GPR:$b, (i32 16))),
1663 (SMULBT GPR:$a, GPR:$b)>;
1664def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
1665 (SMULBT GPR:$a, GPR:$b)>;
1666def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
1667 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1668 (SMULTB GPR:$a, GPR:$b)>;
1669def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
1670 (SMULTB GPR:$a, GPR:$b)>;
1671def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1672 (i32 16)),
1673 (SMULWB GPR:$a, GPR:$b)>;
1674def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
1675 (SMULWB GPR:$a, GPR:$b)>;
1676
1677def : ARMV5TEPat<(add GPR:$acc,
1678 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1679 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1680 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1681def : ARMV5TEPat<(add GPR:$acc,
1682 (mul sext_16_node:$a, sext_16_node:$b)),
1683 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1684def : ARMV5TEPat<(add GPR:$acc,
1685 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1686 (sra GPR:$b, (i32 16)))),
1687 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1688def : ARMV5TEPat<(add GPR:$acc,
1689 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
1690 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1691def : ARMV5TEPat<(add GPR:$acc,
1692 (mul (sra GPR:$a, (i32 16)),
1693 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1694 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1695def : ARMV5TEPat<(add GPR:$acc,
1696 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
1697 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1698def : ARMV5TEPat<(add GPR:$acc,
1699 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1700 (i32 16))),
1701 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1702def : ARMV5TEPat<(add GPR:$acc,
1703 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
1704 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1705
1706//===----------------------------------------------------------------------===//
1707// Thumb Support
1708//
1709
1710include "ARMInstrThumb.td"
1711
1712//===----------------------------------------------------------------------===//
1713// Thumb2 Support
1714//
1715
1716include "ARMInstrThumb2.td"
1717
1718//===----------------------------------------------------------------------===//
1719// Floating Point Support
1720//
1721
1722include "ARMInstrVFP.td"
1723
1724//===----------------------------------------------------------------------===//
1725// Advanced SIMD (NEON) Support
1726//
1727
1728include "ARMInstrNEON.td"
| 616 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
617}
618} // isNotDuplicable = 1
619
620
621// LEApcrel - Load a pc-relative address into a register without offending the
622// assembler.
623def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
624 Pseudo, IIC_iALUi,
625 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, ($label-(",
626 "${:private}PCRELL${:uid}+8))\n"),
627 !strconcat("${:private}PCRELL${:uid}:\n\t",
628 "add$p\t$dst, pc, #${:private}PCRELV${:uid}")),
629 []>;
630
631def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
632 (ins i32imm:$label, nohash_imm:$id, pred:$p),
633 Pseudo, IIC_iALUi,
634 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, "
635 "(${label}_${id}-(",
636 "${:private}PCRELL${:uid}+8))\n"),
637 !strconcat("${:private}PCRELL${:uid}:\n\t",
638 "add$p\t$dst, pc, #${:private}PCRELV${:uid}")),
639 []> {
640 let Inst{25} = 1;
641}
642
643//===----------------------------------------------------------------------===//
644// Control Flow Instructions.
645//
646
647let isReturn = 1, isTerminator = 1, isBarrier = 1 in
648 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
649 "bx", "\tlr", [(ARMretflag)]> {
650 let Inst{3-0} = 0b1110;
651 let Inst{7-4} = 0b0001;
652 let Inst{19-8} = 0b111111111111;
653 let Inst{27-20} = 0b00010010;
654}
655
656// Indirect branches
657let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
658 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
659 [(brind GPR:$dst)]> {
660 let Inst{7-4} = 0b0001;
661 let Inst{19-8} = 0b111111111111;
662 let Inst{27-20} = 0b00010010;
663 let Inst{31-28} = 0b1110;
664 }
665}
666
667// FIXME: remove when we have a way to marking a MI with these properties.
668// FIXME: Should pc be an implicit operand like PICADD, etc?
669let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
670 hasExtraDefRegAllocReq = 1 in
671 def LDM_RET : AXI4ld<(outs),
672 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
673 LdStMulFrm, IIC_Br, "ldm${addr:submode}${p}\t$addr, $wb",
674 []>;
675
676// On non-Darwin platforms R9 is callee-saved.
677let isCall = 1,
678 Defs = [R0, R1, R2, R3, R12, LR,
679 D0, D1, D2, D3, D4, D5, D6, D7,
680 D16, D17, D18, D19, D20, D21, D22, D23,
681 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
682 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
683 IIC_Br, "bl\t${func:call}",
684 [(ARMcall tglobaladdr:$func)]>,
685 Requires<[IsARM, IsNotDarwin]> {
686 let Inst{31-28} = 0b1110;
687 }
688
689 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
690 IIC_Br, "bl", "\t${func:call}",
691 [(ARMcall_pred tglobaladdr:$func)]>,
692 Requires<[IsARM, IsNotDarwin]>;
693
694 // ARMv5T and above
695 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
696 IIC_Br, "blx\t$func",
697 [(ARMcall GPR:$func)]>,
698 Requires<[IsARM, HasV5T, IsNotDarwin]> {
699 let Inst{7-4} = 0b0011;
700 let Inst{19-8} = 0b111111111111;
701 let Inst{27-20} = 0b00010010;
702 }
703
704 // ARMv4T
705 def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
706 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
707 [(ARMcall_nolink GPR:$func)]>,
708 Requires<[IsARM, IsNotDarwin]> {
709 let Inst{7-4} = 0b0001;
710 let Inst{19-8} = 0b111111111111;
711 let Inst{27-20} = 0b00010010;
712 }
713}
714
715// On Darwin R9 is call-clobbered.
716let isCall = 1,
717 Defs = [R0, R1, R2, R3, R9, R12, LR,
718 D0, D1, D2, D3, D4, D5, D6, D7,
719 D16, D17, D18, D19, D20, D21, D22, D23,
720 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
721 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
722 IIC_Br, "bl\t${func:call}",
723 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
724 let Inst{31-28} = 0b1110;
725 }
726
727 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
728 IIC_Br, "bl", "\t${func:call}",
729 [(ARMcall_pred tglobaladdr:$func)]>,
730 Requires<[IsARM, IsDarwin]>;
731
732 // ARMv5T and above
733 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
734 IIC_Br, "blx\t$func",
735 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
736 let Inst{7-4} = 0b0011;
737 let Inst{19-8} = 0b111111111111;
738 let Inst{27-20} = 0b00010010;
739 }
740
741 // ARMv4T
742 def BXr9 : ABXIx2<(outs), (ins GPR:$func, variable_ops),
743 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
744 [(ARMcall_nolink GPR:$func)]>, Requires<[IsARM, IsDarwin]> {
745 let Inst{7-4} = 0b0001;
746 let Inst{19-8} = 0b111111111111;
747 let Inst{27-20} = 0b00010010;
748 }
749}
750
751let isBranch = 1, isTerminator = 1 in {
752 // B is "predicable" since it can be xformed into a Bcc.
753 let isBarrier = 1 in {
754 let isPredicable = 1 in
755 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
756 "b\t$target", [(br bb:$target)]>;
757
758 let isNotDuplicable = 1, isIndirectBranch = 1 in {
759 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
760 IIC_Br, "mov\tpc, $target \n$jt",
761 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
762 let Inst{15-12} = 0b1111;
763 let Inst{20} = 0; // S Bit
764 let Inst{24-21} = 0b1101;
765 let Inst{27-25} = 0b000;
766 }
767 def BR_JTm : JTI<(outs),
768 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
769 IIC_Br, "ldr\tpc, $target \n$jt",
770 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
771 imm:$id)]> {
772 let Inst{15-12} = 0b1111;
773 let Inst{20} = 1; // L bit
774 let Inst{21} = 0; // W bit
775 let Inst{22} = 0; // B bit
776 let Inst{24} = 1; // P bit
777 let Inst{27-25} = 0b011;
778 }
779 def BR_JTadd : JTI<(outs),
780 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
781 IIC_Br, "add\tpc, $target, $idx \n$jt",
782 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
783 imm:$id)]> {
784 let Inst{15-12} = 0b1111;
785 let Inst{20} = 0; // S bit
786 let Inst{24-21} = 0b0100;
787 let Inst{27-25} = 0b000;
788 }
789 } // isNotDuplicable = 1, isIndirectBranch = 1
790 } // isBarrier = 1
791
792 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
793 // a two-value operand where a dag node expects two operands. :(
794 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
795 IIC_Br, "b", "\t$target",
796 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
797}
798
799//===----------------------------------------------------------------------===//
800// Load / store Instructions.
801//
802
803// Load
804let canFoldAsLoad = 1, isReMaterializable = 1 in
805def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
806 "ldr", "\t$dst, $addr",
807 [(set GPR:$dst, (load addrmode2:$addr))]>;
808
809// Special LDR for loads from non-pc-relative constpools.
810let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
811def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
812 "ldr", "\t$dst, $addr", []>;
813
814// Loads with zero extension
815def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
816 IIC_iLoadr, "ldrh", "\t$dst, $addr",
817 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
818
819def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
820 IIC_iLoadr, "ldrb", "\t$dst, $addr",
821 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
822
823// Loads with sign extension
824def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
825 IIC_iLoadr, "ldrsh", "\t$dst, $addr",
826 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
827
828def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
829 IIC_iLoadr, "ldrsb", "\t$dst, $addr",
830 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
831
832let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
833// Load doubleword
834def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
835 IIC_iLoadr, "ldrd", "\t$dst1, $addr",
836 []>, Requires<[IsARM, HasV5TE]>;
837
838// Indexed loads
839def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
840 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
841 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
842
843def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
844 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru,
845 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
846
847def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
848 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
849 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
850
851def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
852 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
853 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
854
855def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
856 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
857 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
858
859def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
860 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru,
861 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
862
863def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
864 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
865 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
866
867def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
868 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
869 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
870
871def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
872 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
873 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
874
875def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
876 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
877 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
878}
879
880// Store
881def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
882 "str", "\t$src, $addr",
883 [(store GPR:$src, addrmode2:$addr)]>;
884
885// Stores with truncate
886def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, IIC_iStorer,
887 "strh", "\t$src, $addr",
888 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
889
890def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
891 "strb", "\t$src, $addr",
892 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
893
894// Store doubleword
895let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
896def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
897 StMiscFrm, IIC_iStorer,
898 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
899
900// Indexed stores
901def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
902 (ins GPR:$src, GPR:$base, am2offset:$offset),
903 StFrm, IIC_iStoreru,
904 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
905 [(set GPR:$base_wb,
906 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
907
908def STR_POST : AI2stwpo<(outs GPR:$base_wb),
909 (ins GPR:$src, GPR:$base,am2offset:$offset),
910 StFrm, IIC_iStoreru,
911 "str", "\t$src, [$base], $offset", "$base = $base_wb",
912 [(set GPR:$base_wb,
913 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
914
915def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
916 (ins GPR:$src, GPR:$base,am3offset:$offset),
917 StMiscFrm, IIC_iStoreru,
918 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
919 [(set GPR:$base_wb,
920 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
921
922def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
923 (ins GPR:$src, GPR:$base,am3offset:$offset),
924 StMiscFrm, IIC_iStoreru,
925 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
926 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
927 GPR:$base, am3offset:$offset))]>;
928
929def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
930 (ins GPR:$src, GPR:$base,am2offset:$offset),
931 StFrm, IIC_iStoreru,
932 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
933 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
934 GPR:$base, am2offset:$offset))]>;
935
936def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
937 (ins GPR:$src, GPR:$base,am2offset:$offset),
938 StFrm, IIC_iStoreru,
939 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
940 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
941 GPR:$base, am2offset:$offset))]>;
942
943//===----------------------------------------------------------------------===//
944// Load / store multiple Instructions.
945//
946
947let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
948def LDM : AXI4ld<(outs),
949 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
950 LdStMulFrm, IIC_iLoadm, "ldm${addr:submode}${p}\t$addr, $wb",
951 []>;
952
953let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
954def STM : AXI4st<(outs),
955 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
956 LdStMulFrm, IIC_iStorem, "stm${addr:submode}${p}\t$addr, $wb",
957 []>;
958
959//===----------------------------------------------------------------------===//
960// Move Instructions.
961//
962
963let neverHasSideEffects = 1 in
964def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
965 "mov", "\t$dst, $src", []>, UnaryDP {
966 let Inst{11-4} = 0b00000000;
967 let Inst{25} = 0;
968}
969
970def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
971 DPSoRegFrm, IIC_iMOVsr,
972 "mov", "\t$dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP {
973 let Inst{25} = 0;
974}
975
976let isReMaterializable = 1, isAsCheapAsAMove = 1 in
977def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, IIC_iMOVi,
978 "mov", "\t$dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP {
979 let Inst{25} = 1;
980}
981
982let isReMaterializable = 1, isAsCheapAsAMove = 1 in
983def MOVi16 : AI1<0b1000, (outs GPR:$dst), (ins i32imm:$src),
984 DPFrm, IIC_iMOVi,
985 "movw", "\t$dst, $src",
986 [(set GPR:$dst, imm0_65535:$src)]>,
987 Requires<[IsARM, HasV6T2]> {
988 let Inst{20} = 0;
989 let Inst{25} = 1;
990}
991
992let Constraints = "$src = $dst" in
993def MOVTi16 : AI1<0b1010, (outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
994 DPFrm, IIC_iMOVi,
995 "movt", "\t$dst, $imm",
996 [(set GPR:$dst,
997 (or (and GPR:$src, 0xffff),
998 lo16AllZero:$imm))]>, UnaryDP,
999 Requires<[IsARM, HasV6T2]> {
1000 let Inst{20} = 0;
1001 let Inst{25} = 1;
1002}
1003
1004def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1005 Requires<[IsARM, HasV6T2]>;
1006
1007let Uses = [CPSR] in
1008def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi,
1009 "mov", "\t$dst, $src, rrx",
1010 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
1011
1012// These aren't really mov instructions, but we have to define them this way
1013// due to flag operands.
1014
1015let Defs = [CPSR] in {
1016def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
1017 IIC_iMOVsi, "movs", "\t$dst, $src, lsr #1",
1018 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
1019def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
1020 IIC_iMOVsi, "movs", "\t$dst, $src, asr #1",
1021 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
1022}
1023
1024//===----------------------------------------------------------------------===//
1025// Extend Instructions.
1026//
1027
1028// Sign extenders
1029
1030defm SXTB : AI_unary_rrot<0b01101010,
1031 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1032defm SXTH : AI_unary_rrot<0b01101011,
1033 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1034
1035defm SXTAB : AI_bin_rrot<0b01101010,
1036 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1037defm SXTAH : AI_bin_rrot<0b01101011,
1038 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1039
1040// TODO: SXT(A){B|H}16
1041
1042// Zero extenders
1043
1044let AddedComplexity = 16 in {
1045defm UXTB : AI_unary_rrot<0b01101110,
1046 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1047defm UXTH : AI_unary_rrot<0b01101111,
1048 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1049defm UXTB16 : AI_unary_rrot<0b01101100,
1050 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1051
1052def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1053 (UXTB16r_rot GPR:$Src, 24)>;
1054def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1055 (UXTB16r_rot GPR:$Src, 8)>;
1056
1057defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
1058 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1059defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
1060 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1061}
1062
1063// This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
1064//defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
1065
1066// TODO: UXT(A){B|H}16
1067
1068def SBFX : I<(outs GPR:$dst),
1069 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1070 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1071 "sbfx", "\t$dst, $src, $lsb, $width", "", []>,
1072 Requires<[IsARM, HasV6T2]> {
1073 let Inst{27-21} = 0b0111101;
1074 let Inst{6-4} = 0b101;
1075}
1076
1077def UBFX : I<(outs GPR:$dst),
1078 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1079 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1080 "ubfx", "\t$dst, $src, $lsb, $width", "", []>,
1081 Requires<[IsARM, HasV6T2]> {
1082 let Inst{27-21} = 0b0111111;
1083 let Inst{6-4} = 0b101;
1084}
1085
1086//===----------------------------------------------------------------------===//
1087// Arithmetic Instructions.
1088//
1089
1090defm ADD : AsI1_bin_irs<0b0100, "add",
1091 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1092defm SUB : AsI1_bin_irs<0b0010, "sub",
1093 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1094
1095// ADD and SUB with 's' bit set.
1096defm ADDS : AI1_bin_s_irs<0b0100, "adds",
1097 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1098defm SUBS : AI1_bin_s_irs<0b0010, "subs",
1099 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1100
1101defm ADC : AI1_adde_sube_irs<0b0101, "adc",
1102 BinOpFrag<(adde node:$LHS, node:$RHS)>, 1>;
1103defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
1104 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
1105defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
1106 BinOpFrag<(adde node:$LHS, node:$RHS)>, 1>;
1107defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
1108 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
1109
1110// These don't define reg/reg forms, because they are handled above.
1111def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1112 IIC_iALUi, "rsb", "\t$dst, $a, $b",
1113 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
1114 let Inst{25} = 1;
1115}
1116
1117def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1118 IIC_iALUsr, "rsb", "\t$dst, $a, $b",
1119 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> {
1120 let Inst{25} = 0;
1121}
1122
1123// RSB with 's' bit set.
1124let Defs = [CPSR] in {
1125def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1126 IIC_iALUi, "rsbs", "\t$dst, $a, $b",
1127 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]> {
1128 let Inst{20} = 1;
1129 let Inst{25} = 1;
1130}
1131def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1132 IIC_iALUsr, "rsbs", "\t$dst, $a, $b",
1133 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]> {
1134 let Inst{20} = 1;
1135 let Inst{25} = 0;
1136}
1137}
1138
1139let Uses = [CPSR] in {
1140def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1141 DPFrm, IIC_iALUi, "rsc", "\t$dst, $a, $b",
1142 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1143 Requires<[IsARM, CarryDefIsUnused]> {
1144 let Inst{25} = 1;
1145}
1146def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1147 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$dst, $a, $b",
1148 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
1149 Requires<[IsARM, CarryDefIsUnused]> {
1150 let Inst{25} = 0;
1151}
1152}
1153
1154// FIXME: Allow these to be predicated.
1155let Defs = [CPSR], Uses = [CPSR] in {
1156def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1157 DPFrm, IIC_iALUi, "rscs\t$dst, $a, $b",
1158 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1159 Requires<[IsARM, CarryDefIsUnused]> {
1160 let Inst{20} = 1;
1161 let Inst{25} = 1;
1162}
1163def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1164 DPSoRegFrm, IIC_iALUsr, "rscs\t$dst, $a, $b",
1165 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
1166 Requires<[IsARM, CarryDefIsUnused]> {
1167 let Inst{20} = 1;
1168 let Inst{25} = 0;
1169}
1170}
1171
1172// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1173def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
1174 (SUBri GPR:$src, so_imm_neg:$imm)>;
1175
1176//def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
1177// (SUBSri GPR:$src, so_imm_neg:$imm)>;
1178//def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
1179// (SBCri GPR:$src, so_imm_neg:$imm)>;
1180
1181// Note: These are implemented in C++ code, because they have to generate
1182// ADD/SUBrs instructions, which use a complex pattern that a xform function
1183// cannot produce.
1184// (mul X, 2^n+1) -> (add (X << n), X)
1185// (mul X, 2^n-1) -> (rsb X, (X << n))
1186
1187
1188//===----------------------------------------------------------------------===//
1189// Bitwise Instructions.
1190//
1191
1192defm AND : AsI1_bin_irs<0b0000, "and",
1193 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1194defm ORR : AsI1_bin_irs<0b1100, "orr",
1195 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1196defm EOR : AsI1_bin_irs<0b0001, "eor",
1197 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1198defm BIC : AsI1_bin_irs<0b1110, "bic",
1199 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1200
1201def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1202 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1203 "bfc", "\t$dst, $imm", "$src = $dst",
1204 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
1205 Requires<[IsARM, HasV6T2]> {
1206 let Inst{27-21} = 0b0111110;
1207 let Inst{6-0} = 0b0011111;
1208}
1209
1210def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
1211 "mvn", "\t$dst, $src",
1212 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP {
1213 let Inst{11-4} = 0b00000000;
1214}
1215def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
1216 IIC_iMOVsr, "mvn", "\t$dst, $src",
1217 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP;
1218let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1219def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
1220 IIC_iMOVi, "mvn", "\t$dst, $imm",
1221 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP {
1222 let Inst{25} = 1;
1223}
1224
1225def : ARMPat<(and GPR:$src, so_imm_not:$imm),
1226 (BICri GPR:$src, so_imm_not:$imm)>;
1227
1228//===----------------------------------------------------------------------===//
1229// Multiply Instructions.
1230//
1231
1232let isCommutable = 1 in
1233def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1234 IIC_iMUL32, "mul", "\t$dst, $a, $b",
1235 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
1236
1237def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1238 IIC_iMAC32, "mla", "\t$dst, $a, $b, $c",
1239 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
1240
1241def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1242 IIC_iMAC32, "mls", "\t$dst, $a, $b, $c",
1243 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
1244 Requires<[IsARM, HasV6T2]>;
1245
1246// Extra precision multiplies with low / high results
1247let neverHasSideEffects = 1 in {
1248let isCommutable = 1 in {
1249def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
1250 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1251 "smull", "\t$ldst, $hdst, $a, $b", []>;
1252
1253def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
1254 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1255 "umull", "\t$ldst, $hdst, $a, $b", []>;
1256}
1257
1258// Multiply + accumulate
1259def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
1260 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1261 "smlal", "\t$ldst, $hdst, $a, $b", []>;
1262
1263def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
1264 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1265 "umlal", "\t$ldst, $hdst, $a, $b", []>;
1266
1267def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
1268 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1269 "umaal", "\t$ldst, $hdst, $a, $b", []>,
1270 Requires<[IsARM, HasV6]>;
1271} // neverHasSideEffects
1272
1273// Most significant word multiply
1274def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1275 IIC_iMUL32, "smmul", "\t$dst, $a, $b",
1276 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1277 Requires<[IsARM, HasV6]> {
1278 let Inst{7-4} = 0b0001;
1279 let Inst{15-12} = 0b1111;
1280}
1281
1282def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1283 IIC_iMAC32, "smmla", "\t$dst, $a, $b, $c",
1284 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1285 Requires<[IsARM, HasV6]> {
1286 let Inst{7-4} = 0b0001;
1287}
1288
1289
1290def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1291 IIC_iMAC32, "smmls", "\t$dst, $a, $b, $c",
1292 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1293 Requires<[IsARM, HasV6]> {
1294 let Inst{7-4} = 0b1101;
1295}
1296
1297multiclass AI_smul<string opc, PatFrag opnode> {
1298 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1299 IIC_iMUL32, !strconcat(opc, "bb"), "\t$dst, $a, $b",
1300 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1301 (sext_inreg GPR:$b, i16)))]>,
1302 Requires<[IsARM, HasV5TE]> {
1303 let Inst{5} = 0;
1304 let Inst{6} = 0;
1305 }
1306
1307 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1308 IIC_iMUL32, !strconcat(opc, "bt"), "\t$dst, $a, $b",
1309 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1310 (sra GPR:$b, (i32 16))))]>,
1311 Requires<[IsARM, HasV5TE]> {
1312 let Inst{5} = 0;
1313 let Inst{6} = 1;
1314 }
1315
1316 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1317 IIC_iMUL32, !strconcat(opc, "tb"), "\t$dst, $a, $b",
1318 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1319 (sext_inreg GPR:$b, i16)))]>,
1320 Requires<[IsARM, HasV5TE]> {
1321 let Inst{5} = 1;
1322 let Inst{6} = 0;
1323 }
1324
1325 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1326 IIC_iMUL32, !strconcat(opc, "tt"), "\t$dst, $a, $b",
1327 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1328 (sra GPR:$b, (i32 16))))]>,
1329 Requires<[IsARM, HasV5TE]> {
1330 let Inst{5} = 1;
1331 let Inst{6} = 1;
1332 }
1333
1334 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1335 IIC_iMUL16, !strconcat(opc, "wb"), "\t$dst, $a, $b",
1336 [(set GPR:$dst, (sra (opnode GPR:$a,
1337 (sext_inreg GPR:$b, i16)), (i32 16)))]>,
1338 Requires<[IsARM, HasV5TE]> {
1339 let Inst{5} = 1;
1340 let Inst{6} = 0;
1341 }
1342
1343 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1344 IIC_iMUL16, !strconcat(opc, "wt"), "\t$dst, $a, $b",
1345 [(set GPR:$dst, (sra (opnode GPR:$a,
1346 (sra GPR:$b, (i32 16))), (i32 16)))]>,
1347 Requires<[IsARM, HasV5TE]> {
1348 let Inst{5} = 1;
1349 let Inst{6} = 1;
1350 }
1351}
1352
1353
1354multiclass AI_smla<string opc, PatFrag opnode> {
1355 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1356 IIC_iMAC16, !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
1357 [(set GPR:$dst, (add GPR:$acc,
1358 (opnode (sext_inreg GPR:$a, i16),
1359 (sext_inreg GPR:$b, i16))))]>,
1360 Requires<[IsARM, HasV5TE]> {
1361 let Inst{5} = 0;
1362 let Inst{6} = 0;
1363 }
1364
1365 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1366 IIC_iMAC16, !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
1367 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1368 (sra GPR:$b, (i32 16)))))]>,
1369 Requires<[IsARM, HasV5TE]> {
1370 let Inst{5} = 0;
1371 let Inst{6} = 1;
1372 }
1373
1374 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1375 IIC_iMAC16, !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
1376 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1377 (sext_inreg GPR:$b, i16))))]>,
1378 Requires<[IsARM, HasV5TE]> {
1379 let Inst{5} = 1;
1380 let Inst{6} = 0;
1381 }
1382
1383 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1384 IIC_iMAC16, !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
1385 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1386 (sra GPR:$b, (i32 16)))))]>,
1387 Requires<[IsARM, HasV5TE]> {
1388 let Inst{5} = 1;
1389 let Inst{6} = 1;
1390 }
1391
1392 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1393 IIC_iMAC16, !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
1394 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1395 (sext_inreg GPR:$b, i16)), (i32 16))))]>,
1396 Requires<[IsARM, HasV5TE]> {
1397 let Inst{5} = 0;
1398 let Inst{6} = 0;
1399 }
1400
1401 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1402 IIC_iMAC16, !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
1403 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1404 (sra GPR:$b, (i32 16))), (i32 16))))]>,
1405 Requires<[IsARM, HasV5TE]> {
1406 let Inst{5} = 0;
1407 let Inst{6} = 1;
1408 }
1409}
1410
1411defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1412defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1413
1414// TODO: Halfword multiple accumulate long: SMLAL<x><y>
1415// TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1416
1417//===----------------------------------------------------------------------===//
1418// Misc. Arithmetic Instructions.
1419//
1420
1421def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1422 "clz", "\t$dst, $src",
1423 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
1424 let Inst{7-4} = 0b0001;
1425 let Inst{11-8} = 0b1111;
1426 let Inst{19-16} = 0b1111;
1427}
1428
1429def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1430 "rev", "\t$dst, $src",
1431 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
1432 let Inst{7-4} = 0b0011;
1433 let Inst{11-8} = 0b1111;
1434 let Inst{19-16} = 0b1111;
1435}
1436
1437def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1438 "rev16", "\t$dst, $src",
1439 [(set GPR:$dst,
1440 (or (and (srl GPR:$src, (i32 8)), 0xFF),
1441 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
1442 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
1443 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>,
1444 Requires<[IsARM, HasV6]> {
1445 let Inst{7-4} = 0b1011;
1446 let Inst{11-8} = 0b1111;
1447 let Inst{19-16} = 0b1111;
1448}
1449
1450def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1451 "revsh", "\t$dst, $src",
1452 [(set GPR:$dst,
1453 (sext_inreg
1454 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
1455 (shl GPR:$src, (i32 8))), i16))]>,
1456 Requires<[IsARM, HasV6]> {
1457 let Inst{7-4} = 0b1011;
1458 let Inst{11-8} = 0b1111;
1459 let Inst{19-16} = 0b1111;
1460}
1461
1462def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
1463 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1464 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, LSL $shamt",
1465 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1466 (and (shl GPR:$src2, (i32 imm:$shamt)),
1467 0xFFFF0000)))]>,
1468 Requires<[IsARM, HasV6]> {
1469 let Inst{6-4} = 0b001;
1470}
1471
1472// Alternate cases for PKHBT where identities eliminate some nodes.
1473def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1474 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1475def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1476 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1477
1478
1479def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
1480 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1481 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, ASR $shamt",
1482 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1483 (and (sra GPR:$src2, imm16_31:$shamt),
1484 0xFFFF)))]>, Requires<[IsARM, HasV6]> {
1485 let Inst{6-4} = 0b101;
1486}
1487
1488// Alternate cases for PKHTB where identities eliminate some nodes. Note that
1489// a shift amount of 0 is *not legal* here, it is PKHBT instead.
1490def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
1491 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1492def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1493 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1494 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1495
1496//===----------------------------------------------------------------------===//
1497// Comparison Instructions...
1498//
1499
1500defm CMP : AI1_cmp_irs<0b1010, "cmp",
1501 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1502defm CMN : AI1_cmp_irs<0b1011, "cmn",
1503 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1504
1505// Note that TST/TEQ don't set all the same flags that CMP does!
1506defm TST : AI1_cmp_irs<0b1000, "tst",
1507 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
1508defm TEQ : AI1_cmp_irs<0b1001, "teq",
1509 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
1510
1511defm CMPz : AI1_cmp_irs<0b1010, "cmp",
1512 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
1513defm CMNz : AI1_cmp_irs<0b1011, "cmn",
1514 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
1515
1516def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1517 (CMNri GPR:$src, so_imm_neg:$imm)>;
1518
1519def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
1520 (CMNri GPR:$src, so_imm_neg:$imm)>;
1521
1522
1523// Conditional moves
1524// FIXME: should be able to write a pattern for ARMcmov, but can't use
1525// a two-value operand where a dag node expects two operands. :(
1526def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
1527 IIC_iCMOVr, "mov", "\t$dst, $true",
1528 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1529 RegConstraint<"$false = $dst">, UnaryDP {
1530 let Inst{11-4} = 0b00000000;
1531 let Inst{25} = 0;
1532}
1533
1534def MOVCCs : AI1<0b1101, (outs GPR:$dst),
1535 (ins GPR:$false, so_reg:$true), DPSoRegFrm, IIC_iCMOVsr,
1536 "mov", "\t$dst, $true",
1537 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1538 RegConstraint<"$false = $dst">, UnaryDP {
1539 let Inst{25} = 0;
1540}
1541
1542def MOVCCi : AI1<0b1101, (outs GPR:$dst),
1543 (ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi,
1544 "mov", "\t$dst, $true",
1545 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1546 RegConstraint<"$false = $dst">, UnaryDP {
1547 let Inst{25} = 1;
1548}
1549
1550
1551//===----------------------------------------------------------------------===//
1552// TLS Instructions
1553//
1554
1555// __aeabi_read_tp preserves the registers r1-r3.
1556let isCall = 1,
1557 Defs = [R0, R12, LR, CPSR] in {
1558 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
1559 "bl\t__aeabi_read_tp",
1560 [(set R0, ARMthread_pointer)]>;
1561}
1562
1563//===----------------------------------------------------------------------===//
1564// SJLJ Exception handling intrinsics
1565// eh_sjlj_setjmp() is an instruction sequence to store the return
1566// address and save #0 in R0 for the non-longjmp case.
1567// Since by its nature we may be coming from some other function to get
1568// here, and we're using the stack frame for the containing function to
1569// save/restore registers, we can't keep anything live in regs across
1570// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
1571// when we get here from a longjmp(). We force everthing out of registers
1572// except for our own input by listing the relevant registers in Defs. By
1573// doing so, we also cause the prologue/epilogue code to actively preserve
1574// all of the callee-saved resgisters, which is exactly what we want.
1575let Defs =
1576 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
1577 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
1578 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
1579 D31 ] in {
1580 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src),
1581 AddrModeNone, SizeSpecial, IndexModeNone,
1582 Pseudo, NoItinerary,
1583 "str\tsp, [$src, #+8] @ eh_setjmp begin\n\t"
1584 "add\tr12, pc, #8\n\t"
1585 "str\tr12, [$src, #+4]\n\t"
1586 "mov\tr0, #0\n\t"
1587 "add\tpc, pc, #0\n\t"
1588 "mov\tr0, #1 @ eh_setjmp end", "",
1589 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>;
1590}
1591
1592//===----------------------------------------------------------------------===//
1593// Non-Instruction Patterns
1594//
1595
1596// ConstantPool, GlobalAddress, and JumpTable
1597def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1598def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1599def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1600 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1601
1602// Large immediate handling.
1603
1604// Two piece so_imms.
1605let isReMaterializable = 1 in
1606def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src),
1607 Pseudo, IIC_iMOVi,
1608 "mov", "\t$dst, $src",
1609 [(set GPR:$dst, so_imm2part:$src)]>,
1610 Requires<[IsARM, NoV6T2]>;
1611
1612def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1613 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1614 (so_imm2part_2 imm:$RHS))>;
1615def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1616 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1617 (so_imm2part_2 imm:$RHS))>;
1618def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS),
1619 (ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1620 (so_imm2part_2 imm:$RHS))>;
1621def : ARMPat<(sub GPR:$LHS, so_imm2part:$RHS),
1622 (SUBri (SUBri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1623 (so_imm2part_2 imm:$RHS))>;
1624
1625// 32-bit immediate using movw + movt.
1626// This is a single pseudo instruction, the benefit is that it can be remat'd
1627// as a single unit instead of having to handle reg inputs.
1628// FIXME: Remove this when we can do generalized remat.
1629let isReMaterializable = 1 in
1630def MOVi32imm : AI1x2<(outs GPR:$dst), (ins i32imm:$src), Pseudo, IIC_iMOVi,
1631 "movw", "\t$dst, ${src:lo16}\n\tmovt${p} $dst, ${src:hi16}",
1632 [(set GPR:$dst, (i32 imm:$src))]>,
1633 Requires<[IsARM, HasV6T2]>;
1634
1635// TODO: add,sub,and, 3-instr forms?
1636
1637
1638// Direct calls
1639def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
1640 Requires<[IsARM, IsNotDarwin]>;
1641def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
1642 Requires<[IsARM, IsDarwin]>;
1643
1644// zextload i1 -> zextload i8
1645def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1646
1647// extload -> zextload
1648def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1649def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1650def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1651
1652def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
1653def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
1654
1655// smul* and smla*
1656def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1657 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1658 (SMULBB GPR:$a, GPR:$b)>;
1659def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1660 (SMULBB GPR:$a, GPR:$b)>;
1661def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1662 (sra GPR:$b, (i32 16))),
1663 (SMULBT GPR:$a, GPR:$b)>;
1664def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
1665 (SMULBT GPR:$a, GPR:$b)>;
1666def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
1667 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1668 (SMULTB GPR:$a, GPR:$b)>;
1669def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
1670 (SMULTB GPR:$a, GPR:$b)>;
1671def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1672 (i32 16)),
1673 (SMULWB GPR:$a, GPR:$b)>;
1674def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
1675 (SMULWB GPR:$a, GPR:$b)>;
1676
1677def : ARMV5TEPat<(add GPR:$acc,
1678 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1679 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1680 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1681def : ARMV5TEPat<(add GPR:$acc,
1682 (mul sext_16_node:$a, sext_16_node:$b)),
1683 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1684def : ARMV5TEPat<(add GPR:$acc,
1685 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1686 (sra GPR:$b, (i32 16)))),
1687 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1688def : ARMV5TEPat<(add GPR:$acc,
1689 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
1690 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1691def : ARMV5TEPat<(add GPR:$acc,
1692 (mul (sra GPR:$a, (i32 16)),
1693 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1694 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1695def : ARMV5TEPat<(add GPR:$acc,
1696 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
1697 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1698def : ARMV5TEPat<(add GPR:$acc,
1699 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1700 (i32 16))),
1701 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1702def : ARMV5TEPat<(add GPR:$acc,
1703 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
1704 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1705
1706//===----------------------------------------------------------------------===//
1707// Thumb Support
1708//
1709
1710include "ARMInstrThumb.td"
1711
1712//===----------------------------------------------------------------------===//
1713// Thumb2 Support
1714//
1715
1716include "ARMInstrThumb2.td"
1717
1718//===----------------------------------------------------------------------===//
1719// Floating Point Support
1720//
1721
1722include "ARMInstrVFP.td"
1723
1724//===----------------------------------------------------------------------===//
1725// Advanced SIMD (NEON) Support
1726//
1727
1728include "ARMInstrNEON.td"
|