ARMInstrInfo.h (199481) | ARMInstrInfo.h (200581) |
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1//===- ARMInstrInfo.h - ARM Instruction Information -------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the ARM implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef ARMINSTRUCTIONINFO_H 15#define ARMINSTRUCTIONINFO_H 16 17#include "llvm/Target/TargetInstrInfo.h" 18#include "ARMBaseInstrInfo.h" 19#include "ARMRegisterInfo.h" 20#include "ARMSubtarget.h" 21#include "ARM.h" 22 23namespace llvm { 24 class ARMSubtarget; 25 26class ARMInstrInfo : public ARMBaseInstrInfo { 27 ARMRegisterInfo RI; 28public: 29 explicit ARMInstrInfo(const ARMSubtarget &STI); 30 31 // Return the non-pre/post incrementing version of 'Opc'. Return 0 32 // if there is not such an opcode. 33 unsigned getUnindexedOpcode(unsigned Opc) const; 34 | 1//===- ARMInstrInfo.h - ARM Instruction Information -------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the ARM implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef ARMINSTRUCTIONINFO_H 15#define ARMINSTRUCTIONINFO_H 16 17#include "llvm/Target/TargetInstrInfo.h" 18#include "ARMBaseInstrInfo.h" 19#include "ARMRegisterInfo.h" 20#include "ARMSubtarget.h" 21#include "ARM.h" 22 23namespace llvm { 24 class ARMSubtarget; 25 26class ARMInstrInfo : public ARMBaseInstrInfo { 27 ARMRegisterInfo RI; 28public: 29 explicit ARMInstrInfo(const ARMSubtarget &STI); 30 31 // Return the non-pre/post incrementing version of 'Opc'. Return 0 32 // if there is not such an opcode. 33 unsigned getUnindexedOpcode(unsigned Opc) const; 34 |
35 // Return true if the block does not fall through. 36 bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const; 37 | |
38 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 39 unsigned DestReg, unsigned SubIdx, 40 const MachineInstr *Orig, 41 const TargetRegisterInfo *TRI) const; 42 43 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 44 /// such, whenever a client has an instance of instruction info, it should 45 /// always be able to get register info as well (through this method). 46 /// 47 const ARMRegisterInfo &getRegisterInfo() const { return RI; } 48}; 49 50} 51 52#endif | 35 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 36 unsigned DestReg, unsigned SubIdx, 37 const MachineInstr *Orig, 38 const TargetRegisterInfo *TRI) const; 39 40 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 41 /// such, whenever a client has an instance of instruction info, it should 42 /// always be able to get register info as well (through this method). 43 /// 44 const ARMRegisterInfo &getRegisterInfo() const { return RI; } 45}; 46 47} 48 49#endif |