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ARMFrameLowering.cpp (276479) ARMFrameLowering.cpp (277320)
1//===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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561
562 // If the frame has variable sized objects then the epilogue must restore
563 // the sp from fp. We can assume there's an FP here since hasFP already
564 // checks for hasVarSizedObjects.
565 if (MFI->hasVarSizedObjects())
566 AFI->setShouldRestoreSPFromFP(true);
567}
568
1//===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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561
562 // If the frame has variable sized objects then the epilogue must restore
563 // the sp from fp. We can assume there's an FP here since hasFP already
564 // checks for hasVarSizedObjects.
565 if (MFI->hasVarSizedObjects())
566 AFI->setShouldRestoreSPFromFP(true);
567}
568
569// Resolve TCReturn pseudo-instruction
570void ARMFrameLowering::fixTCReturn(MachineFunction &MF,
571 MachineBasicBlock &MBB) const {
572 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
573 assert(MBBI->isReturn() && "Can only insert epilog into returning blocks");
574 unsigned RetOpcode = MBBI->getOpcode();
575 DebugLoc dl = MBBI->getDebugLoc();
576 const ARMBaseInstrInfo &TII =
577 *MF.getTarget().getSubtarget<ARMSubtarget>().getInstrInfo();
578
579 if (!(RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri))
580 return;
581
582 // Tail call return: adjust the stack pointer and jump to callee.
583 MBBI = MBB.getLastNonDebugInstr();
584 MachineOperand &JumpTarget = MBBI->getOperand(0);
585
586 // Jump to label or value in register.
587 if (RetOpcode == ARM::TCRETURNdi) {
588 unsigned TCOpcode = STI.isThumb() ?
589 (STI.isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) :
590 ARM::TAILJMPd;
591 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
592 if (JumpTarget.isGlobal())
593 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
594 JumpTarget.getTargetFlags());
595 else {
596 assert(JumpTarget.isSymbol());
597 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
598 JumpTarget.getTargetFlags());
599 }
600
601 // Add the default predicate in Thumb mode.
602 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);
603 } else if (RetOpcode == ARM::TCRETURNri) {
604 BuildMI(MBB, MBBI, dl,
605 TII.get(STI.isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)).
606 addReg(JumpTarget.getReg(), RegState::Kill);
607 }
608
609 MachineInstr *NewMI = std::prev(MBBI);
610 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
611 NewMI->addOperand(MBBI->getOperand(i));
612
613 // Delete the pseudo instruction TCRETURN.
614 MBB.erase(MBBI);
615 MBBI = NewMI;
616}
617
569void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
570 MachineBasicBlock &MBB) const {
571 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
572 assert(MBBI->isReturn() && "Can only insert epilog into returning blocks");
618void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
619 MachineBasicBlock &MBB) const {
620 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
621 assert(MBBI->isReturn() && "Can only insert epilog into returning blocks");
573 unsigned RetOpcode = MBBI->getOpcode();
574 DebugLoc dl = MBBI->getDebugLoc();
575 MachineFrameInfo *MFI = MF.getFrameInfo();
576 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
577 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
578 const ARMBaseInstrInfo &TII =
579 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
580 assert(!AFI->isThumb1OnlyFunction() &&
581 "This emitEpilogue does not support Thumb1!");
582 bool isARM = !AFI->isThumbFunction();
583
584 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
585 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
586 int NumBytes = (int)MFI->getStackSize();
587 unsigned FramePtr = RegInfo->getFrameRegister(MF);
588
589 // All calls are tail calls in GHC calling conv, and functions have no
590 // prologue/epilogue.
622 DebugLoc dl = MBBI->getDebugLoc();
623 MachineFrameInfo *MFI = MF.getFrameInfo();
624 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
625 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
626 const ARMBaseInstrInfo &TII =
627 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
628 assert(!AFI->isThumb1OnlyFunction() &&
629 "This emitEpilogue does not support Thumb1!");
630 bool isARM = !AFI->isThumbFunction();
631
632 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
633 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
634 int NumBytes = (int)MFI->getStackSize();
635 unsigned FramePtr = RegInfo->getFrameRegister(MF);
636
637 // All calls are tail calls in GHC calling conv, and functions have no
638 // prologue/epilogue.
591 if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
639 if (MF.getFunction()->getCallingConv() == CallingConv::GHC) {
640 fixTCReturn(MF, MBB);
592 return;
641 return;
642 }
593
594 if (!AFI->hasStackFrame()) {
595 if (NumBytes - ArgRegsSaveSize != 0)
596 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes - ArgRegsSaveSize);
597 } else {
598 // Unwind MBBI to point to first LDR / VLDRD.
599 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
600 if (MBBI != MBB.begin()) {

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656 // instructions in the epilogue.
657 while (MBBI->getOpcode() == ARM::VLDMDIA_UPD)
658 MBBI++;
659 }
660 if (AFI->getGPRCalleeSavedArea2Size()) MBBI++;
661 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;
662 }
663
643
644 if (!AFI->hasStackFrame()) {
645 if (NumBytes - ArgRegsSaveSize != 0)
646 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes - ArgRegsSaveSize);
647 } else {
648 // Unwind MBBI to point to first LDR / VLDRD.
649 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
650 if (MBBI != MBB.begin()) {

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706 // instructions in the epilogue.
707 while (MBBI->getOpcode() == ARM::VLDMDIA_UPD)
708 MBBI++;
709 }
710 if (AFI->getGPRCalleeSavedArea2Size()) MBBI++;
711 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;
712 }
713
664 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri) {
665 // Tail call return: adjust the stack pointer and jump to callee.
666 MBBI = MBB.getLastNonDebugInstr();
667 MachineOperand &JumpTarget = MBBI->getOperand(0);
714 fixTCReturn(MF, MBB);
668
715
669 // Jump to label or value in register.
670 if (RetOpcode == ARM::TCRETURNdi) {
671 unsigned TCOpcode = STI.isThumb() ?
672 (STI.isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) :
673 ARM::TAILJMPd;
674 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
675 if (JumpTarget.isGlobal())
676 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
677 JumpTarget.getTargetFlags());
678 else {
679 assert(JumpTarget.isSymbol());
680 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
681 JumpTarget.getTargetFlags());
682 }
683
684 // Add the default predicate in Thumb mode.
685 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);
686 } else if (RetOpcode == ARM::TCRETURNri) {
687 BuildMI(MBB, MBBI, dl,
688 TII.get(STI.isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)).
689 addReg(JumpTarget.getReg(), RegState::Kill);
690 }
691
692 MachineInstr *NewMI = std::prev(MBBI);
693 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
694 NewMI->addOperand(MBBI->getOperand(i));
695
696 // Delete the pseudo instruction TCRETURN.
697 MBB.erase(MBBI);
698 MBBI = NewMI;
699 }
700
701 if (ArgRegsSaveSize)
702 emitSPUpdate(isARM, MBB, MBBI, dl, TII, ArgRegsSaveSize);
703}
704
705/// getFrameIndexReference - Provide a base+offset reference to an FI slot for
706/// debug info. It's the same as what we use for resolving the code-gen
707/// references for now. FIXME: This can go wrong when references are
708/// SP-relative and simple call frames aren't used.

--- 1331 unchanged lines hidden --- 		716 if (ArgRegsSaveSize)
717 emitSPUpdate(isARM, MBB, MBBI, dl, TII, ArgRegsSaveSize);
718}
719
720/// getFrameIndexReference - Provide a base+offset reference to an FI slot for
721/// debug info. It's the same as what we use for resolving the code-gen
722/// references for now. FIXME: This can go wrong when references are
723/// SP-relative and simple call frames aren't used.

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