1//===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the ARM implementation of TargetFrameLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMFrameLowering.h"
15#include "ARMBaseInstrInfo.h"
16#include "ARMBaseRegisterInfo.h"
17#include "ARMConstantPoolValue.h"
18#include "ARMMachineFunctionInfo.h"
19#include "MCTargetDesc/ARMAddressingModes.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineModuleInfo.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/RegisterScavenging.h"
26#include "llvm/IR/CallingConv.h"
27#include "llvm/IR/Function.h"
28#include "llvm/MC/MCContext.h"
29#include "llvm/Support/CommandLine.h"
30#include "llvm/Target/TargetOptions.h"
31
32using namespace llvm;
33
34static cl::opt<bool>
35SpillAlignedNEONRegs("align-neon-spills", cl::Hidden, cl::init(true),
36 cl::desc("Align ARM NEON spills in prolog and epilog"));
37
38static MachineBasicBlock::iterator
39skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
40 unsigned NumAlignedDPRCS2Regs);
41
42ARMFrameLowering::ARMFrameLowering(const ARMSubtarget &sti)
43 : TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), 0, 4),
44 STI(sti) {}
45
46/// hasFP - Return true if the specified function should have a dedicated frame
47/// pointer register. This is true if the function has variable sized allocas
48/// or if frame pointer elimination is disabled.
49bool ARMFrameLowering::hasFP(const MachineFunction &MF) const {
50 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
51
52 // iOS requires FP not to be clobbered for backtracing purpose.
53 if (STI.isTargetIOS())
54 return true;
55
56 const MachineFrameInfo *MFI = MF.getFrameInfo();
57 // Always eliminate non-leaf frame pointers.
58 return ((MF.getTarget().Options.DisableFramePointerElim(MF) &&
59 MFI->hasCalls()) ||
60 RegInfo->needsStackRealignment(MF) ||
61 MFI->hasVarSizedObjects() ||
62 MFI->isFrameAddressTaken());
63}
64
65/// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
66/// not required, we reserve argument space for call sites in the function
67/// immediately on entry to the current function. This eliminates the need for
68/// add/sub sp brackets around call sites. Returns true if the call frame is
69/// included as part of the stack frame.
70bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
71 const MachineFrameInfo *FFI = MF.getFrameInfo();
72 unsigned CFSize = FFI->getMaxCallFrameSize();
73 // It's not always a good idea to include the call frame as part of the
74 // stack frame. ARM (especially Thumb) has small immediate offset to
75 // address the stack frame. So a large call frame can cause poor codegen
76 // and may even makes it impossible to scavenge a register.
77 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
78 return false;
79
80 return !MF.getFrameInfo()->hasVarSizedObjects();
81}
82
83/// canSimplifyCallFramePseudos - If there is a reserved call frame, the
84/// call frame pseudos can be simplified. Unlike most targets, having a FP
85/// is not sufficient here since we still may reference some objects via SP
86/// even when FP is available in Thumb2 mode.
87bool
88ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
89 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
90}
91
92static bool isCSRestore(MachineInstr *MI,
93 const ARMBaseInstrInfo &TII,
94 const MCPhysReg *CSRegs) {
95 // Integer spill area is handled with "pop".
96 if (isPopOpcode(MI->getOpcode())) {
97 // The first two operands are predicates. The last two are
98 // imp-def and imp-use of SP. Check everything in between.
99 for (int i = 5, e = MI->getNumOperands(); i != e; ++i)
100 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
101 return false;
102 return true;
103 }
104 if ((MI->getOpcode() == ARM::LDR_POST_IMM ||
105 MI->getOpcode() == ARM::LDR_POST_REG ||
106 MI->getOpcode() == ARM::t2LDR_POST) &&
107 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) &&
108 MI->getOperand(1).getReg() == ARM::SP)
109 return true;
110
111 return false;
112}
113
114static void emitRegPlusImmediate(bool isARM, MachineBasicBlock &MBB,
115 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
116 const ARMBaseInstrInfo &TII, unsigned DestReg,
117 unsigned SrcReg, int NumBytes,
118 unsigned MIFlags = MachineInstr::NoFlags,
119 ARMCC::CondCodes Pred = ARMCC::AL,
120 unsigned PredReg = 0) {
121 if (isARM)
122 emitARMRegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
123 Pred, PredReg, TII, MIFlags);
124 else
125 emitT2RegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
126 Pred, PredReg, TII, MIFlags);
127}
128
129static void emitSPUpdate(bool isARM, MachineBasicBlock &MBB,
130 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
131 const ARMBaseInstrInfo &TII, int NumBytes,
132 unsigned MIFlags = MachineInstr::NoFlags,
133 ARMCC::CondCodes Pred = ARMCC::AL,
134 unsigned PredReg = 0) {
135 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes,
136 MIFlags, Pred, PredReg);
137}
138
139static int sizeOfSPAdjustment(const MachineInstr *MI) {
140 assert(MI->getOpcode() == ARM::VSTMDDB_UPD);
141 int count = 0;
142 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
143 // pred) so the list starts at 4.
144 for (int i = MI->getNumOperands() - 1; i >= 4; --i)
145 count += 8;
146 return count;
147}
148
149static bool WindowsRequiresStackProbe(const MachineFunction &MF,
150 size_t StackSizeInBytes) {
151 const MachineFrameInfo *MFI = MF.getFrameInfo();
152 if (MFI->getStackProtectorIndex() > 0)
153 return StackSizeInBytes >= 4080;
154 return StackSizeInBytes >= 4096;
155}
156
157void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
158 MachineBasicBlock &MBB = MF.front();
159 MachineBasicBlock::iterator MBBI = MBB.begin();
160 MachineFrameInfo *MFI = MF.getFrameInfo();
161 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
162 MachineModuleInfo &MMI = MF.getMMI();
163 MCContext &Context = MMI.getContext();
164 const TargetMachine &TM = MF.getTarget();
165 const MCRegisterInfo *MRI = Context.getRegisterInfo();
166 const ARMBaseRegisterInfo *RegInfo =
167 static_cast<const ARMBaseRegisterInfo*>(TM.getRegisterInfo());
168 const ARMBaseInstrInfo &TII =
169 *static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo());
170 assert(!AFI->isThumb1OnlyFunction() &&
171 "This emitPrologue does not support Thumb1!");
172 bool isARM = !AFI->isThumbFunction();
173 unsigned Align = TM.getFrameLowering()->getStackAlignment();
174 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
175 unsigned NumBytes = MFI->getStackSize();
176 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
177 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
178 unsigned FramePtr = RegInfo->getFrameRegister(MF);
179 int CFAOffset = 0;
180
181 // Determine the sizes of each callee-save spill areas and record which frame
182 // belongs to which callee-save spill areas.
183 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
184 int FramePtrSpillFI = 0;
185 int D8SpillFI = 0;
186
187 // All calls are tail calls in GHC calling conv, and functions have no
188 // prologue/epilogue.
189 if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
190 return;
191
192 // Allocate the vararg register save area.
193 if (ArgRegsSaveSize) {
194 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize,
195 MachineInstr::FrameSetup);
196 CFAOffset -= ArgRegsSaveSize;
197 unsigned CFIIndex = MMI.addFrameInst(
198 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
199 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
200 .addCFIIndex(CFIIndex);
201 }
202
203 if (!AFI->hasStackFrame() &&
204 (!STI.isTargetWindows() || !WindowsRequiresStackProbe(MF, NumBytes))) {
205 if (NumBytes - ArgRegsSaveSize != 0) {
206 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -(NumBytes - ArgRegsSaveSize),
207 MachineInstr::FrameSetup);
208 CFAOffset -= NumBytes - ArgRegsSaveSize;
209 unsigned CFIIndex = MMI.addFrameInst(
210 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
211 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
212 .addCFIIndex(CFIIndex);
213 }
214 return;
215 }
216
217 // Determine spill area sizes.
218 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
219 unsigned Reg = CSI[i].getReg();
220 int FI = CSI[i].getFrameIdx();
221 switch (Reg) {
222 case ARM::R8:
223 case ARM::R9:
224 case ARM::R10:
225 case ARM::R11:
226 case ARM::R12:
227 if (STI.isTargetDarwin()) {
228 GPRCS2Size += 4;
229 break;
230 }
231 // fallthrough
232 case ARM::R0:
233 case ARM::R1:
234 case ARM::R2:
235 case ARM::R3:
236 case ARM::R4:
237 case ARM::R5:
238 case ARM::R6:
239 case ARM::R7:
240 case ARM::LR:
241 if (Reg == FramePtr)
242 FramePtrSpillFI = FI;
243 GPRCS1Size += 4;
244 break;
245 default:
246 // This is a DPR. Exclude the aligned DPRCS2 spills.
247 if (Reg == ARM::D8)
248 D8SpillFI = FI;
249 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())
250 DPRCSSize += 8;
251 }
252 }
253
254 // Move past area 1.
255 MachineBasicBlock::iterator LastPush = MBB.end(), GPRCS1Push, GPRCS2Push,
256 DPRCSPush;
257 if (GPRCS1Size > 0)
258 GPRCS1Push = LastPush = MBBI++;
259
260 // Determine starting offsets of spill areas.
261 bool HasFP = hasFP(MF);
262 unsigned DPRCSOffset = NumBytes - (ArgRegsSaveSize + GPRCS1Size
263 + GPRCS2Size + DPRCSSize);
264 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
265 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
266 int FramePtrOffsetInPush = 0;
267 if (HasFP) {
268 FramePtrOffsetInPush = MFI->getObjectOffset(FramePtrSpillFI)
269 + GPRCS1Size + ArgRegsSaveSize;
270 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
271 NumBytes);
272 }
273 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
274 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
275 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
276
277 // Move past area 2.
278 if (GPRCS2Size > 0)
279 GPRCS2Push = LastPush = MBBI++;
280
281 // Move past area 3.
282 if (DPRCSSize > 0) {
283 DPRCSPush = MBBI;
284 // Since vpush register list cannot have gaps, there may be multiple vpush
285 // instructions in the prologue.
286 while (MBBI->getOpcode() == ARM::VSTMDDB_UPD)
287 LastPush = MBBI++;
288 }
289
290 // Move past the aligned DPRCS2 area.
291 if (AFI->getNumAlignedDPRCS2Regs() > 0) {
292 MBBI = skipAlignedDPRCS2Spills(MBBI, AFI->getNumAlignedDPRCS2Regs());
293 // The code inserted by emitAlignedDPRCS2Spills realigns the stack, and
294 // leaves the stack pointer pointing to the DPRCS2 area.
295 //
296 // Adjust NumBytes to represent the stack slots below the DPRCS2 area.
297 NumBytes += MFI->getObjectOffset(D8SpillFI);
298 } else
299 NumBytes = DPRCSOffset;
300
301 if (STI.isTargetWindows() && WindowsRequiresStackProbe(MF, NumBytes)) {
302 uint32_t NumWords = NumBytes >> 2;
303
304 if (NumWords < 65536)
305 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)
306 .addImm(NumWords)
307 .setMIFlags(MachineInstr::FrameSetup));
308 else
309 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4)
310 .addImm(NumWords)
311 .setMIFlags(MachineInstr::FrameSetup);
312
313 switch (TM.getCodeModel()) {
314 case CodeModel::Small:
315 case CodeModel::Medium:
316 case CodeModel::Default:
317 case CodeModel::Kernel:
318 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL))
319 .addImm((unsigned)ARMCC::AL).addReg(0)
320 .addExternalSymbol("__chkstk")
321 .addReg(ARM::R4, RegState::Implicit)
322 .setMIFlags(MachineInstr::FrameSetup);
323 break;
324 case CodeModel::Large:
325 case CodeModel::JITDefault:
326 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12)
327 .addExternalSymbol("__chkstk")
328 .setMIFlags(MachineInstr::FrameSetup);
329
330 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr))
331 .addImm((unsigned)ARMCC::AL).addReg(0)
332 .addReg(ARM::R12, RegState::Kill)
333 .addReg(ARM::R4, RegState::Implicit)
334 .setMIFlags(MachineInstr::FrameSetup);
335 break;
336 }
337
338 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr),
339 ARM::SP)
340 .addReg(ARM::SP, RegState::Define)
341 .addReg(ARM::R4, RegState::Kill)
342 .setMIFlags(MachineInstr::FrameSetup)));
343 NumBytes = 0;
344 }
345
346 unsigned adjustedGPRCS1Size = GPRCS1Size;
347 if (NumBytes) {
348 // Adjust SP after all the callee-save spills.
349 if (tryFoldSPUpdateIntoPushPop(STI, MF, LastPush, NumBytes)) {
350 if (LastPush == GPRCS1Push) {
351 FramePtrOffsetInPush += NumBytes;
352 adjustedGPRCS1Size += NumBytes;
353 NumBytes = 0;
354 }
355 } else
356 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
357 MachineInstr::FrameSetup);
358
359 if (HasFP && isARM)
360 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24
361 // Note it's not safe to do this in Thumb2 mode because it would have
362 // taken two instructions:
363 // mov sp, r7
364 // sub sp, #24
365 // If an interrupt is taken between the two instructions, then sp is in
366 // an inconsistent state (pointing to the middle of callee-saved area).
367 // The interrupt handler can end up clobbering the registers.
368 AFI->setShouldRestoreSPFromFP(true);
369 }
370
371 if (adjustedGPRCS1Size > 0) {
372 CFAOffset -= adjustedGPRCS1Size;
373 unsigned CFIIndex = MMI.addFrameInst(
374 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
375 MachineBasicBlock::iterator Pos = ++GPRCS1Push;
376 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
377 .addCFIIndex(CFIIndex);
378 for (const auto &Entry : CSI) {
379 unsigned Reg = Entry.getReg();
380 int FI = Entry.getFrameIdx();
381 switch (Reg) {
382 case ARM::R8:
383 case ARM::R9:
384 case ARM::R10:
385 case ARM::R11:
386 case ARM::R12:
387 if (STI.isTargetDarwin())
388 break;
389 // fallthrough
390 case ARM::R0:
391 case ARM::R1:
392 case ARM::R2:
393 case ARM::R3:
394 case ARM::R4:
395 case ARM::R5:
396 case ARM::R6:
397 case ARM::R7:
398 case ARM::LR:
399 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
400 nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI)));
401 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
402 .addCFIIndex(CFIIndex);
403 break;
404 }
405 }
406 }
407
408 // Set FP to point to the stack slot that contains the previous FP.
409 // For iOS, FP is R7, which has now been stored in spill area 1.
410 // Otherwise, if this is not iOS, all the callee-saved registers go
411 // into spill area 1, including the FP in R11. In either case, it
412 // is in area one and the adjustment needs to take place just after
413 // that push.
414 if (HasFP) {
415 emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, GPRCS1Push, dl, TII,
416 FramePtr, ARM::SP, FramePtrOffsetInPush,
417 MachineInstr::FrameSetup);
418 if (FramePtrOffsetInPush) {
419 CFAOffset += FramePtrOffsetInPush;
420 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfa(
421 nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
422 BuildMI(MBB, GPRCS1Push, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
423 .addCFIIndex(CFIIndex);
424
425 } else {
426 unsigned CFIIndex =
427 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
428 nullptr, MRI->getDwarfRegNum(FramePtr, true)));
429 BuildMI(MBB, GPRCS1Push, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
430 .addCFIIndex(CFIIndex);
431 }
432 }
433
434 if (GPRCS2Size > 0) {
435 MachineBasicBlock::iterator Pos = ++GPRCS2Push;
436 if (!HasFP) {
437 CFAOffset -= GPRCS2Size;
438 unsigned CFIIndex = MMI.addFrameInst(
439 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
440 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
441 .addCFIIndex(CFIIndex);
442 }
443 for (const auto &Entry : CSI) {
444 unsigned Reg = Entry.getReg();
445 int FI = Entry.getFrameIdx();
446 switch (Reg) {
447 case ARM::R8:
448 case ARM::R9:
449 case ARM::R10:
450 case ARM::R11:
451 case ARM::R12:
452 if (STI.isTargetDarwin()) {
453 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
454 unsigned Offset = MFI->getObjectOffset(FI);
455 unsigned CFIIndex = MMI.addFrameInst(
456 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
457 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
458 .addCFIIndex(CFIIndex);
459 }
460 break;
461 }
462 }
463 }
464
465 if (DPRCSSize > 0) {
466 // Since vpush register list cannot have gaps, there may be multiple vpush
467 // instructions in the prologue.
468 do {
469 MachineBasicBlock::iterator Push = DPRCSPush++;
470 if (!HasFP) {
471 CFAOffset -= sizeOfSPAdjustment(Push);
472 unsigned CFIIndex = MMI.addFrameInst(
473 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
474 BuildMI(MBB, DPRCSPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
475 .addCFIIndex(CFIIndex);
476 }
477 } while (DPRCSPush->getOpcode() == ARM::VSTMDDB_UPD);
478
479 for (const auto &Entry : CSI) {
480 unsigned Reg = Entry.getReg();
481 int FI = Entry.getFrameIdx();
482 if ((Reg >= ARM::D0 && Reg <= ARM::D31) &&
483 (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) {
484 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
485 unsigned Offset = MFI->getObjectOffset(FI);
486 unsigned CFIIndex = MMI.addFrameInst(
487 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
488 BuildMI(MBB, DPRCSPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
489 .addCFIIndex(CFIIndex);
490 }
491 }
492 }
493
494 if (NumBytes) {
495 if (!HasFP) {
496 CFAOffset -= NumBytes;
497 unsigned CFIIndex = MMI.addFrameInst(
498 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
499 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
500 .addCFIIndex(CFIIndex);
501 }
502 }
503
504 if (STI.isTargetELF() && hasFP(MF))
505 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
506 AFI->getFramePtrSpillOffset());
507
508 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
509 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
510 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
511
512 // If we need dynamic stack realignment, do it here. Be paranoid and make
513 // sure if we also have VLAs, we have a base pointer for frame access.
514 // If aligned NEON registers were spilled, the stack has already been
515 // realigned.
516 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) {
517 unsigned MaxAlign = MFI->getMaxAlignment();
518 assert (!AFI->isThumb1OnlyFunction());
519 if (!AFI->isThumbFunction()) {
520 // Emit bic sp, sp, MaxAlign
521 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
522 TII.get(ARM::BICri), ARM::SP)
523 .addReg(ARM::SP, RegState::Kill)
524 .addImm(MaxAlign-1)));
525 } else {
526 // We cannot use sp as source/dest register here, thus we're emitting the
527 // following sequence:
528 // mov r4, sp
529 // bic r4, r4, MaxAlign
530 // mov sp, r4
531 // FIXME: It will be better just to find spare register here.
532 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
533 .addReg(ARM::SP, RegState::Kill));
534 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
535 TII.get(ARM::t2BICri), ARM::R4)
536 .addReg(ARM::R4, RegState::Kill)
537 .addImm(MaxAlign-1)));
538 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
539 .addReg(ARM::R4, RegState::Kill));
540 }
541
542 AFI->setShouldRestoreSPFromFP(true);
543 }
544
545 // If we need a base pointer, set it up here. It's whatever the value
546 // of the stack pointer is at this point. Any variable size objects
547 // will be allocated after this, so we can still use the base pointer
548 // to reference locals.
549 // FIXME: Clarify FrameSetup flags here.
550 if (RegInfo->hasBasePointer(MF)) {
551 if (isARM)
552 BuildMI(MBB, MBBI, dl,
553 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
554 .addReg(ARM::SP)
555 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
556 else
557 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
558 RegInfo->getBaseRegister())
559 .addReg(ARM::SP));
560 }
561
562 // If the frame has variable sized objects then the epilogue must restore
563 // the sp from fp. We can assume there's an FP here since hasFP already
564 // checks for hasVarSizedObjects.
565 if (MFI->hasVarSizedObjects())
566 AFI->setShouldRestoreSPFromFP(true);
567}
568
569void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
570 MachineBasicBlock &MBB) const {
571 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
572 assert(MBBI->isReturn() && "Can only insert epilog into returning blocks");
573 unsigned RetOpcode = MBBI->getOpcode();
574 DebugLoc dl = MBBI->getDebugLoc();
575 MachineFrameInfo *MFI = MF.getFrameInfo();
576 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
577 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
578 const ARMBaseInstrInfo &TII =
579 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
580 assert(!AFI->isThumb1OnlyFunction() &&
581 "This emitEpilogue does not support Thumb1!");
582 bool isARM = !AFI->isThumbFunction();
583
584 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
585 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
586 int NumBytes = (int)MFI->getStackSize();
587 unsigned FramePtr = RegInfo->getFrameRegister(MF);
588
589 // All calls are tail calls in GHC calling conv, and functions have no
590 // prologue/epilogue.
591 if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
592 return;
593
594 if (!AFI->hasStackFrame()) {
595 if (NumBytes - ArgRegsSaveSize != 0)
596 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes - ArgRegsSaveSize);
597 } else {
598 // Unwind MBBI to point to first LDR / VLDRD.
599 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
600 if (MBBI != MBB.begin()) {
601 do {
602 --MBBI;
603 } while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
604 if (!isCSRestore(MBBI, TII, CSRegs))
605 ++MBBI;
606 }
607
608 // Move SP to start of FP callee save spill area.
609 NumBytes -= (ArgRegsSaveSize +
610 AFI->getGPRCalleeSavedArea1Size() +
611 AFI->getGPRCalleeSavedArea2Size() +
612 AFI->getDPRCalleeSavedAreaSize());
613
614 // Reset SP based on frame pointer only if the stack frame extends beyond
615 // frame pointer stack slot or target is ELF and the function has FP.
616 if (AFI->shouldRestoreSPFromFP()) {
617 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
618 if (NumBytes) {
619 if (isARM)
620 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
621 ARMCC::AL, 0, TII);
622 else {
623 // It's not possible to restore SP from FP in a single instruction.
624 // For iOS, this looks like:
625 // mov sp, r7
626 // sub sp, #24
627 // This is bad, if an interrupt is taken after the mov, sp is in an
628 // inconsistent state.
629 // Use the first callee-saved register as a scratch register.
630 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
631 "No scratch register to restore SP from FP!");
632 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
633 ARMCC::AL, 0, TII);
634 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
635 ARM::SP)
636 .addReg(ARM::R4));
637 }
638 } else {
639 // Thumb2 or ARM.
640 if (isARM)
641 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
642 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
643 else
644 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
645 ARM::SP)
646 .addReg(FramePtr));
647 }
648 } else if (NumBytes &&
649 !tryFoldSPUpdateIntoPushPop(STI, MF, MBBI, NumBytes))
650 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
651
652 // Increment past our save areas.
653 if (AFI->getDPRCalleeSavedAreaSize()) {
654 MBBI++;
655 // Since vpop register list cannot have gaps, there may be multiple vpop
656 // instructions in the epilogue.
657 while (MBBI->getOpcode() == ARM::VLDMDIA_UPD)
658 MBBI++;
659 }
660 if (AFI->getGPRCalleeSavedArea2Size()) MBBI++;
661 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;
662 }
663
664 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri) {
665 // Tail call return: adjust the stack pointer and jump to callee.
666 MBBI = MBB.getLastNonDebugInstr();
667 MachineOperand &JumpTarget = MBBI->getOperand(0);
668
669 // Jump to label or value in register.
670 if (RetOpcode == ARM::TCRETURNdi) {
671 unsigned TCOpcode = STI.isThumb() ?
672 (STI.isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) :
673 ARM::TAILJMPd;
674 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
675 if (JumpTarget.isGlobal())
676 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
677 JumpTarget.getTargetFlags());
678 else {
679 assert(JumpTarget.isSymbol());
680 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
681 JumpTarget.getTargetFlags());
682 }
683
684 // Add the default predicate in Thumb mode.
685 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);
686 } else if (RetOpcode == ARM::TCRETURNri) {
687 BuildMI(MBB, MBBI, dl,
688 TII.get(STI.isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)).
689 addReg(JumpTarget.getReg(), RegState::Kill);
690 }
691
692 MachineInstr *NewMI = std::prev(MBBI);
693 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
694 NewMI->addOperand(MBBI->getOperand(i));
695
696 // Delete the pseudo instruction TCRETURN.
697 MBB.erase(MBBI);
698 MBBI = NewMI;
699 }
700
701 if (ArgRegsSaveSize)
702 emitSPUpdate(isARM, MBB, MBBI, dl, TII, ArgRegsSaveSize);
703}
704
705/// getFrameIndexReference - Provide a base+offset reference to an FI slot for
706/// debug info. It's the same as what we use for resolving the code-gen
707/// references for now. FIXME: This can go wrong when references are
708/// SP-relative and simple call frames aren't used.
709int
710ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
711 unsigned &FrameReg) const {
712 return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
713}
714
715int
716ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF,
717 int FI, unsigned &FrameReg,
718 int SPAdj) const {
719 const MachineFrameInfo *MFI = MF.getFrameInfo();
720 const ARMBaseRegisterInfo *RegInfo =
721 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
722 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
723 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
724 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
725 bool isFixed = MFI->isFixedObjectIndex(FI);
726
727 FrameReg = ARM::SP;
728 Offset += SPAdj;
729
730 // SP can move around if there are allocas. We may also lose track of SP
731 // when emergency spilling inside a non-reserved call frame setup.
732 bool hasMovingSP = !hasReservedCallFrame(MF);
733
734 // When dynamically realigning the stack, use the frame pointer for
735 // parameters, and the stack/base pointer for locals.
736 if (RegInfo->needsStackRealignment(MF)) {
737 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
738 if (isFixed) {
739 FrameReg = RegInfo->getFrameRegister(MF);
740 Offset = FPOffset;
741 } else if (hasMovingSP) {
742 assert(RegInfo->hasBasePointer(MF) &&
743 "VLAs and dynamic stack alignment, but missing base pointer!");
744 FrameReg = RegInfo->getBaseRegister();
745 }
746 return Offset;
747 }
748
749 // If there is a frame pointer, use it when we can.
750 if (hasFP(MF) && AFI->hasStackFrame()) {
751 // Use frame pointer to reference fixed objects. Use it for locals if
752 // there are VLAs (and thus the SP isn't reliable as a base).
753 if (isFixed || (hasMovingSP && !RegInfo->hasBasePointer(MF))) {
754 FrameReg = RegInfo->getFrameRegister(MF);
755 return FPOffset;
756 } else if (hasMovingSP) {
757 assert(RegInfo->hasBasePointer(MF) && "missing base pointer!");
758 if (AFI->isThumb2Function()) {
759 // Try to use the frame pointer if we can, else use the base pointer
760 // since it's available. This is handy for the emergency spill slot, in
761 // particular.
762 if (FPOffset >= -255 && FPOffset < 0) {
763 FrameReg = RegInfo->getFrameRegister(MF);
764 return FPOffset;
765 }
766 }
767 } else if (AFI->isThumb2Function()) {
768 // Use add <rd>, sp, #<imm8>
769 // ldr <rd>, [sp, #<imm8>]
770 // if at all possible to save space.
771 if (Offset >= 0 && (Offset & 3) == 0 && Offset <= 1020)
772 return Offset;
773 // In Thumb2 mode, the negative offset is very limited. Try to avoid
774 // out of range references. ldr <rt>,[<rn>, #-<imm8>]
775 if (FPOffset >= -255 && FPOffset < 0) {
776 FrameReg = RegInfo->getFrameRegister(MF);
777 return FPOffset;
778 }
779 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
780 // Otherwise, use SP or FP, whichever is closer to the stack slot.
781 FrameReg = RegInfo->getFrameRegister(MF);
782 return FPOffset;
783 }
784 }
785 // Use the base pointer if we have one.
786 if (RegInfo->hasBasePointer(MF))
787 FrameReg = RegInfo->getBaseRegister();
788 return Offset;
789}
790
791int ARMFrameLowering::getFrameIndexOffset(const MachineFunction &MF,
792 int FI) const {
793 unsigned FrameReg;
794 return getFrameIndexReference(MF, FI, FrameReg);
795}
796
797void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
798 MachineBasicBlock::iterator MI,
799 const std::vector<CalleeSavedInfo> &CSI,
800 unsigned StmOpc, unsigned StrOpc,
801 bool NoGap,
802 bool(*Func)(unsigned, bool),
803 unsigned NumAlignedDPRCS2Regs,
804 unsigned MIFlags) const {
805 MachineFunction &MF = *MBB.getParent();
806 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
807
808 DebugLoc DL;
809 if (MI != MBB.end()) DL = MI->getDebugLoc();
810
811 SmallVector<std::pair<unsigned,bool>, 4> Regs;
812 unsigned i = CSI.size();
813 while (i != 0) {
814 unsigned LastReg = 0;
815 for (; i != 0; --i) {
816 unsigned Reg = CSI[i-1].getReg();
817 if (!(Func)(Reg, STI.isTargetDarwin())) continue;
818
819 // D-registers in the aligned area DPRCS2 are NOT spilled here.
820 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
821 continue;
822
823 // Add the callee-saved register as live-in unless it's LR and
824 // @llvm.returnaddress is called. If LR is returned for
825 // @llvm.returnaddress then it's already added to the function and
826 // entry block live-in sets.
827 bool isKill = true;
828 if (Reg == ARM::LR) {
829 if (MF.getFrameInfo()->isReturnAddressTaken() &&
830 MF.getRegInfo().isLiveIn(Reg))
831 isKill = false;
832 }
833
834 if (isKill)
835 MBB.addLiveIn(Reg);
836
837 // If NoGap is true, push consecutive registers and then leave the rest
838 // for other instructions. e.g.
839 // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11}
840 if (NoGap && LastReg && LastReg != Reg-1)
841 break;
842 LastReg = Reg;
843 Regs.push_back(std::make_pair(Reg, isKill));
844 }
845
846 if (Regs.empty())
847 continue;
848 if (Regs.size() > 1 || StrOpc== 0) {
849 MachineInstrBuilder MIB =
850 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
851 .addReg(ARM::SP).setMIFlags(MIFlags));
852 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
853 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
854 } else if (Regs.size() == 1) {
855 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc),
856 ARM::SP)
857 .addReg(Regs[0].first, getKillRegState(Regs[0].second))
858 .addReg(ARM::SP).setMIFlags(MIFlags)
859 .addImm(-4);
860 AddDefaultPred(MIB);
861 }
862 Regs.clear();
863
864 // Put any subsequent vpush instructions before this one: they will refer to
865 // higher register numbers so need to be pushed first in order to preserve
866 // monotonicity.
867 --MI;
868 }
869}
870
871void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
872 MachineBasicBlock::iterator MI,
873 const std::vector<CalleeSavedInfo> &CSI,
874 unsigned LdmOpc, unsigned LdrOpc,
875 bool isVarArg, bool NoGap,
876 bool(*Func)(unsigned, bool),
877 unsigned NumAlignedDPRCS2Regs) const {
878 MachineFunction &MF = *MBB.getParent();
879 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
880 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
881 DebugLoc DL = MI->getDebugLoc();
882 unsigned RetOpcode = MI->getOpcode();
883 bool isTailCall = (RetOpcode == ARM::TCRETURNdi ||
884 RetOpcode == ARM::TCRETURNri);
885 bool isInterrupt =
886 RetOpcode == ARM::SUBS_PC_LR || RetOpcode == ARM::t2SUBS_PC_LR;
887
888 SmallVector<unsigned, 4> Regs;
889 unsigned i = CSI.size();
890 while (i != 0) {
891 unsigned LastReg = 0;
892 bool DeleteRet = false;
893 for (; i != 0; --i) {
894 unsigned Reg = CSI[i-1].getReg();
895 if (!(Func)(Reg, STI.isTargetDarwin())) continue;
896
897 // The aligned reloads from area DPRCS2 are not inserted here.
898 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
899 continue;
900
901 if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt &&
902 STI.hasV5TOps()) {
903 Reg = ARM::PC;
904 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
905 // Fold the return instruction into the LDM.
906 DeleteRet = true;
907 }
908
909 // If NoGap is true, pop consecutive registers and then leave the rest
910 // for other instructions. e.g.
911 // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11}
912 if (NoGap && LastReg && LastReg != Reg-1)
913 break;
914
915 LastReg = Reg;
916 Regs.push_back(Reg);
917 }
918
919 if (Regs.empty())
920 continue;
921 if (Regs.size() > 1 || LdrOpc == 0) {
922 MachineInstrBuilder MIB =
923 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
924 .addReg(ARM::SP));
925 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
926 MIB.addReg(Regs[i], getDefRegState(true));
927 if (DeleteRet) {
928 MIB.copyImplicitOps(&*MI);
929 MI->eraseFromParent();
930 }
931 MI = MIB;
932 } else if (Regs.size() == 1) {
933 // If we adjusted the reg to PC from LR above, switch it back here. We
934 // only do that for LDM.
935 if (Regs[0] == ARM::PC)
936 Regs[0] = ARM::LR;
937 MachineInstrBuilder MIB =
938 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
939 .addReg(ARM::SP, RegState::Define)
940 .addReg(ARM::SP);
941 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once
942 // that refactoring is complete (eventually).
943 if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) {
944 MIB.addReg(0);
945 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
946 } else
947 MIB.addImm(4);
948 AddDefaultPred(MIB);
949 }
950 Regs.clear();
951
952 // Put any subsequent vpop instructions after this one: they will refer to
953 // higher register numbers so need to be popped afterwards.
954 ++MI;
955 }
956}
957
958/// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers
959/// starting from d8. Also insert stack realignment code and leave the stack
960/// pointer pointing to the d8 spill slot.
961static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
962 MachineBasicBlock::iterator MI,
963 unsigned NumAlignedDPRCS2Regs,
964 const std::vector<CalleeSavedInfo> &CSI,
965 const TargetRegisterInfo *TRI) {
966 MachineFunction &MF = *MBB.getParent();
967 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
968 DebugLoc DL = MI->getDebugLoc();
969 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
970 MachineFrameInfo &MFI = *MF.getFrameInfo();
971
972 // Mark the D-register spill slots as properly aligned. Since MFI computes
973 // stack slot layout backwards, this can actually mean that the d-reg stack
974 // slot offsets can be wrong. The offset for d8 will always be correct.
975 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
976 unsigned DNum = CSI[i].getReg() - ARM::D8;
977 if (DNum >= 8)
978 continue;
979 int FI = CSI[i].getFrameIdx();
980 // The even-numbered registers will be 16-byte aligned, the odd-numbered
981 // registers will be 8-byte aligned.
982 MFI.setObjectAlignment(FI, DNum % 2 ? 8 : 16);
983
984 // The stack slot for D8 needs to be maximally aligned because this is
985 // actually the point where we align the stack pointer. MachineFrameInfo
986 // computes all offsets relative to the incoming stack pointer which is a
987 // bit weird when realigning the stack. Any extra padding for this
988 // over-alignment is not realized because the code inserted below adjusts
989 // the stack pointer by numregs * 8 before aligning the stack pointer.
990 if (DNum == 0)
991 MFI.setObjectAlignment(FI, MFI.getMaxAlignment());
992 }
993
994 // Move the stack pointer to the d8 spill slot, and align it at the same
995 // time. Leave the stack slot address in the scratch register r4.
996 //
997 // sub r4, sp, #numregs * 8
998 // bic r4, r4, #align - 1
999 // mov sp, r4
1000 //
1001 bool isThumb = AFI->isThumbFunction();
1002 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
1003 AFI->setShouldRestoreSPFromFP(true);
1004
1005 // sub r4, sp, #numregs * 8
1006 // The immediate is <= 64, so it doesn't need any special encoding.
1007 unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri;
1008 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1009 .addReg(ARM::SP)
1010 .addImm(8 * NumAlignedDPRCS2Regs)));
1011
1012 // bic r4, r4, #align-1
1013 Opc = isThumb ? ARM::t2BICri : ARM::BICri;
1014 unsigned MaxAlign = MF.getFrameInfo()->getMaxAlignment();
1015 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1016 .addReg(ARM::R4, RegState::Kill)
1017 .addImm(MaxAlign - 1)));
1018
1019 // mov sp, r4
1020 // The stack pointer must be adjusted before spilling anything, otherwise
1021 // the stack slots could be clobbered by an interrupt handler.
1022 // Leave r4 live, it is used below.
1023 Opc = isThumb ? ARM::tMOVr : ARM::MOVr;
1024 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
1025 .addReg(ARM::R4);
1026 MIB = AddDefaultPred(MIB);
1027 if (!isThumb)
1028 AddDefaultCC(MIB);
1029
1030 // Now spill NumAlignedDPRCS2Regs registers starting from d8.
1031 // r4 holds the stack slot address.
1032 unsigned NextReg = ARM::D8;
1033
1034 // 16-byte aligned vst1.64 with 4 d-regs and address writeback.
1035 // The writeback is only needed when emitting two vst1.64 instructions.
1036 if (NumAlignedDPRCS2Regs >= 6) {
1037 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1038 &ARM::QQPRRegClass);
1039 MBB.addLiveIn(SupReg);
1040 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed),
1041 ARM::R4)
1042 .addReg(ARM::R4, RegState::Kill).addImm(16)
1043 .addReg(NextReg)
1044 .addReg(SupReg, RegState::ImplicitKill));
1045 NextReg += 4;
1046 NumAlignedDPRCS2Regs -= 4;
1047 }
1048
1049 // We won't modify r4 beyond this point. It currently points to the next
1050 // register to be spilled.
1051 unsigned R4BaseReg = NextReg;
1052
1053 // 16-byte aligned vst1.64 with 4 d-regs, no writeback.
1054 if (NumAlignedDPRCS2Regs >= 4) {
1055 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1056 &ARM::QQPRRegClass);
1057 MBB.addLiveIn(SupReg);
1058 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q))
1059 .addReg(ARM::R4).addImm(16).addReg(NextReg)
1060 .addReg(SupReg, RegState::ImplicitKill));
1061 NextReg += 4;
1062 NumAlignedDPRCS2Regs -= 4;
1063 }
1064
1065 // 16-byte aligned vst1.64 with 2 d-regs.
1066 if (NumAlignedDPRCS2Regs >= 2) {
1067 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1068 &ARM::QPRRegClass);
1069 MBB.addLiveIn(SupReg);
1070 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))
1071 .addReg(ARM::R4).addImm(16).addReg(SupReg));
1072 NextReg += 2;
1073 NumAlignedDPRCS2Regs -= 2;
1074 }
1075
1076 // Finally, use a vanilla vstr.64 for the odd last register.
1077 if (NumAlignedDPRCS2Regs) {
1078 MBB.addLiveIn(NextReg);
1079 // vstr.64 uses addrmode5 which has an offset scale of 4.
1080 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD))
1081 .addReg(NextReg)
1082 .addReg(ARM::R4).addImm((NextReg-R4BaseReg)*2));
1083 }
1084
1085 // The last spill instruction inserted should kill the scratch register r4.
1086 std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
1087}
1088
1089/// Skip past the code inserted by emitAlignedDPRCS2Spills, and return an
1090/// iterator to the following instruction.
1091static MachineBasicBlock::iterator
1092skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
1093 unsigned NumAlignedDPRCS2Regs) {
1094 // sub r4, sp, #numregs * 8
1095 // bic r4, r4, #align - 1
1096 // mov sp, r4
1097 ++MI; ++MI; ++MI;
1098 assert(MI->mayStore() && "Expecting spill instruction");
1099
1100 // These switches all fall through.
1101 switch(NumAlignedDPRCS2Regs) {
1102 case 7:
1103 ++MI;
1104 assert(MI->mayStore() && "Expecting spill instruction");
1105 default:
1106 ++MI;
1107 assert(MI->mayStore() && "Expecting spill instruction");
1108 case 1:
1109 case 2:
1110 case 4:
1111 assert(MI->killsRegister(ARM::R4) && "Missed kill flag");
1112 ++MI;
1113 }
1114 return MI;
1115}
1116
1117/// Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers
1118/// starting from d8. These instructions are assumed to execute while the
1119/// stack is still aligned, unlike the code inserted by emitPopInst.
1120static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB,
1121 MachineBasicBlock::iterator MI,
1122 unsigned NumAlignedDPRCS2Regs,
1123 const std::vector<CalleeSavedInfo> &CSI,
1124 const TargetRegisterInfo *TRI) {
1125 MachineFunction &MF = *MBB.getParent();
1126 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1127 DebugLoc DL = MI->getDebugLoc();
1128 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1129
1130 // Find the frame index assigned to d8.
1131 int D8SpillFI = 0;
1132 for (unsigned i = 0, e = CSI.size(); i != e; ++i)
1133 if (CSI[i].getReg() == ARM::D8) {
1134 D8SpillFI = CSI[i].getFrameIdx();
1135 break;
1136 }
1137
1138 // Materialize the address of the d8 spill slot into the scratch register r4.
1139 // This can be fairly complicated if the stack frame is large, so just use
1140 // the normal frame index elimination mechanism to do it. This code runs as
1141 // the initial part of the epilog where the stack and base pointers haven't
1142 // been changed yet.
1143 bool isThumb = AFI->isThumbFunction();
1144 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
1145
1146 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
1147 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1148 .addFrameIndex(D8SpillFI).addImm(0)));
1149
1150 // Now restore NumAlignedDPRCS2Regs registers starting from d8.
1151 unsigned NextReg = ARM::D8;
1152
1153 // 16-byte aligned vld1.64 with 4 d-regs and writeback.
1154 if (NumAlignedDPRCS2Regs >= 6) {
1155 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1156 &ARM::QQPRRegClass);
1157 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
1158 .addReg(ARM::R4, RegState::Define)
1159 .addReg(ARM::R4, RegState::Kill).addImm(16)
1160 .addReg(SupReg, RegState::ImplicitDefine));
1161 NextReg += 4;
1162 NumAlignedDPRCS2Regs -= 4;
1163 }
1164
1165 // We won't modify r4 beyond this point. It currently points to the next
1166 // register to be spilled.
1167 unsigned R4BaseReg = NextReg;
1168
1169 // 16-byte aligned vld1.64 with 4 d-regs, no writeback.
1170 if (NumAlignedDPRCS2Regs >= 4) {
1171 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1172 &ARM::QQPRRegClass);
1173 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
1174 .addReg(ARM::R4).addImm(16)
1175 .addReg(SupReg, RegState::ImplicitDefine));
1176 NextReg += 4;
1177 NumAlignedDPRCS2Regs -= 4;
1178 }
1179
1180 // 16-byte aligned vld1.64 with 2 d-regs.
1181 if (NumAlignedDPRCS2Regs >= 2) {
1182 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1183 &ARM::QPRRegClass);
1184 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)
1185 .addReg(ARM::R4).addImm(16));
1186 NextReg += 2;
1187 NumAlignedDPRCS2Regs -= 2;
1188 }
1189
1190 // Finally, use a vanilla vldr.64 for the remaining odd register.
1191 if (NumAlignedDPRCS2Regs)
1192 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg)
1193 .addReg(ARM::R4).addImm(2*(NextReg-R4BaseReg)));
1194
1195 // Last store kills r4.
1196 std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
1197}
1198
1199bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1200 MachineBasicBlock::iterator MI,
1201 const std::vector<CalleeSavedInfo> &CSI,
1202 const TargetRegisterInfo *TRI) const {
1203 if (CSI.empty())
1204 return false;
1205
1206 MachineFunction &MF = *MBB.getParent();
1207 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1208
1209 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
1210 unsigned PushOneOpc = AFI->isThumbFunction() ?
1211 ARM::t2STR_PRE : ARM::STR_PRE_IMM;
1212 unsigned FltOpc = ARM::VSTMDDB_UPD;
1213 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1214 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register, 0,
1215 MachineInstr::FrameSetup);
1216 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register, 0,
1217 MachineInstr::FrameSetup);
1218 emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register,
1219 NumAlignedDPRCS2Regs, MachineInstr::FrameSetup);
1220
1221 // The code above does not insert spill code for the aligned DPRCS2 registers.
1222 // The stack realignment code will be inserted between the push instructions
1223 // and these spills.
1224 if (NumAlignedDPRCS2Regs)
1225 emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1226
1227 return true;
1228}
1229
1230bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1231 MachineBasicBlock::iterator MI,
1232 const std::vector<CalleeSavedInfo> &CSI,
1233 const TargetRegisterInfo *TRI) const {
1234 if (CSI.empty())
1235 return false;
1236
1237 MachineFunction &MF = *MBB.getParent();
1238 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1239 bool isVarArg = AFI->getArgRegsSaveSize() > 0;
1240 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1241
1242 // The emitPopInst calls below do not insert reloads for the aligned DPRCS2
1243 // registers. Do that here instead.
1244 if (NumAlignedDPRCS2Regs)
1245 emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1246
1247 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
1248 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST :ARM::LDR_POST_IMM;
1249 unsigned FltOpc = ARM::VLDMDIA_UPD;
1250 emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register,
1251 NumAlignedDPRCS2Regs);
1252 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1253 &isARMArea2Register, 0);
1254 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1255 &isARMArea1Register, 0);
1256
1257 return true;
1258}
1259
1260// FIXME: Make generic?
1261static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
1262 const ARMBaseInstrInfo &TII) {
1263 unsigned FnSize = 0;
1264 for (auto &MBB : MF) {
1265 for (auto &MI : MBB)
1266 FnSize += TII.GetInstSizeInBytes(&MI);
1267 }
1268 return FnSize;
1269}
1270
1271/// estimateRSStackSizeLimit - Look at each instruction that references stack
1272/// frames and return the stack size limit beyond which some of these
1273/// instructions will require a scratch register during their expansion later.
1274// FIXME: Move to TII?
1275static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
1276 const TargetFrameLowering *TFI) {
1277 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1278 unsigned Limit = (1 << 12) - 1;
1279 for (auto &MBB : MF) {
1280 for (auto &MI : MBB) {
1281 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1282 if (!MI.getOperand(i).isFI())
1283 continue;
1284
1285 // When using ADDri to get the address of a stack object, 255 is the
1286 // largest offset guaranteed to fit in the immediate offset.
1287 if (MI.getOpcode() == ARM::ADDri) {
1288 Limit = std::min(Limit, (1U << 8) - 1);
1289 break;
1290 }
1291
1292 // Otherwise check the addressing mode.
1293 switch (MI.getDesc().TSFlags & ARMII::AddrModeMask) {
1294 case ARMII::AddrMode3:
1295 case ARMII::AddrModeT2_i8:
1296 Limit = std::min(Limit, (1U << 8) - 1);
1297 break;
1298 case ARMII::AddrMode5:
1299 case ARMII::AddrModeT2_i8s4:
1300 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
1301 break;
1302 case ARMII::AddrModeT2_i12:
1303 // i12 supports only positive offset so these will be converted to
1304 // i8 opcodes. See llvm::rewriteT2FrameIndex.
1305 if (TFI->hasFP(MF) && AFI->hasStackFrame())
1306 Limit = std::min(Limit, (1U << 8) - 1);
1307 break;
1308 case ARMII::AddrMode4:
1309 case ARMII::AddrMode6:
1310 // Addressing modes 4 & 6 (load/store) instructions can't encode an
1311 // immediate offset for stack references.
1312 return 0;
1313 default:
1314 break;
1315 }
1316 break; // At most one FI per instruction
1317 }
1318 }
1319 }
1320
1321 return Limit;
1322}
1323
1324// In functions that realign the stack, it can be an advantage to spill the
1325// callee-saved vector registers after realigning the stack. The vst1 and vld1
1326// instructions take alignment hints that can improve performance.
1327//
1328static void checkNumAlignedDPRCS2Regs(MachineFunction &MF) {
1329 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(0);
1330 if (!SpillAlignedNEONRegs)
1331 return;
1332
1333 // Naked functions don't spill callee-saved registers.
1334 if (MF.getFunction()->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1335 Attribute::Naked))
1336 return;
1337
1338 // We are planning to use NEON instructions vst1 / vld1.
1339 if (!MF.getTarget().getSubtarget<ARMSubtarget>().hasNEON())
1340 return;
1341
1342 // Don't bother if the default stack alignment is sufficiently high.
1343 if (MF.getTarget().getFrameLowering()->getStackAlignment() >= 8)
1344 return;
1345
1346 // Aligned spills require stack realignment.
1347 const ARMBaseRegisterInfo *RegInfo =
1348 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
1349 if (!RegInfo->canRealignStack(MF))
1350 return;
1351
1352 // We always spill contiguous d-registers starting from d8. Count how many
1353 // needs spilling. The register allocator will almost always use the
1354 // callee-saved registers in order, but it can happen that there are holes in
1355 // the range. Registers above the hole will be spilled to the standard DPRCS
1356 // area.
1357 MachineRegisterInfo &MRI = MF.getRegInfo();
1358 unsigned NumSpills = 0;
1359 for (; NumSpills < 8; ++NumSpills)
1360 if (!MRI.isPhysRegUsed(ARM::D8 + NumSpills))
1361 break;
1362
1363 // Don't do this for just one d-register. It's not worth it.
1364 if (NumSpills < 2)
1365 return;
1366
1367 // Spill the first NumSpills D-registers after realigning the stack.
1368 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(NumSpills);
1369
1370 // A scratch register is required for the vst1 / vld1 instructions.
1371 MF.getRegInfo().setPhysRegUsed(ARM::R4);
1372}
1373
1374void
1375ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1376 RegScavenger *RS) const {
1377 // This tells PEI to spill the FP as if it is any other callee-save register
1378 // to take advantage the eliminateFrameIndex machinery. This also ensures it
1379 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
1380 // to combine multiple loads / stores.
1381 bool CanEliminateFrame = true;
1382 bool CS1Spilled = false;
1383 bool LRSpilled = false;
1384 unsigned NumGPRSpills = 0;
1385 SmallVector<unsigned, 4> UnspilledCS1GPRs;
1386 SmallVector<unsigned, 4> UnspilledCS2GPRs;
1387 const ARMBaseRegisterInfo *RegInfo =
1388 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
1389 const ARMBaseInstrInfo &TII =
1390 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
1391 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1392 MachineFrameInfo *MFI = MF.getFrameInfo();
1393 MachineRegisterInfo &MRI = MF.getRegInfo();
1394 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1395
1396 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
1397 // scratch register. Also spill R4 if Thumb2 function has varsized objects,
1398 // since it's not always possible to restore sp from fp in a single
1399 // instruction.
1400 // FIXME: It will be better just to find spare register here.
1401 if (AFI->isThumb2Function() &&
1402 (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF)))
1403 MRI.setPhysRegUsed(ARM::R4);
1404
1405 if (AFI->isThumb1OnlyFunction()) {
1406 // Spill LR if Thumb1 function uses variable length argument lists.
1407 if (AFI->getArgRegsSaveSize() > 0)
1408 MRI.setPhysRegUsed(ARM::LR);
1409
1410 // Spill R4 if Thumb1 epilogue has to restore SP from FP. We don't know
1411 // for sure what the stack size will be, but for this, an estimate is good
1412 // enough. If there anything changes it, it'll be a spill, which implies
1413 // we've used all the registers and so R4 is already used, so not marking
1414 // it here will be OK.
1415 // FIXME: It will be better just to find spare register here.
1416 unsigned StackSize = MFI->estimateStackSize(MF);
1417 if (MFI->hasVarSizedObjects() || StackSize > 508)
1418 MRI.setPhysRegUsed(ARM::R4);
1419 }
1420
1421 // See if we can spill vector registers to aligned stack.
1422 checkNumAlignedDPRCS2Regs(MF);
1423
1424 // Spill the BasePtr if it's used.
1425 if (RegInfo->hasBasePointer(MF))
1426 MRI.setPhysRegUsed(RegInfo->getBaseRegister());
1427
1428 // Don't spill FP if the frame can be eliminated. This is determined
1429 // by scanning the callee-save registers to see if any is used.
1430 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
1431 for (unsigned i = 0; CSRegs[i]; ++i) {
1432 unsigned Reg = CSRegs[i];
1433 bool Spilled = false;
1434 if (MRI.isPhysRegUsed(Reg)) {
1435 Spilled = true;
1436 CanEliminateFrame = false;
1437 }
1438
1439 if (!ARM::GPRRegClass.contains(Reg))
1440 continue;
1441
1442 if (Spilled) {
1443 NumGPRSpills++;
1444
1445 if (!STI.isTargetDarwin()) {
1446 if (Reg == ARM::LR)
1447 LRSpilled = true;
1448 CS1Spilled = true;
1449 continue;
1450 }
1451
1452 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
1453 switch (Reg) {
1454 case ARM::LR:
1455 LRSpilled = true;
1456 // Fallthrough
1457 case ARM::R0: case ARM::R1:
1458 case ARM::R2: case ARM::R3:
1459 case ARM::R4: case ARM::R5:
1460 case ARM::R6: case ARM::R7:
1461 CS1Spilled = true;
1462 break;
1463 default:
1464 break;
1465 }
1466 } else {
1467 if (!STI.isTargetDarwin()) {
1468 UnspilledCS1GPRs.push_back(Reg);
1469 continue;
1470 }
1471
1472 switch (Reg) {
1473 case ARM::R0: case ARM::R1:
1474 case ARM::R2: case ARM::R3:
1475 case ARM::R4: case ARM::R5:
1476 case ARM::R6: case ARM::R7:
1477 case ARM::LR:
1478 UnspilledCS1GPRs.push_back(Reg);
1479 break;
1480 default:
1481 UnspilledCS2GPRs.push_back(Reg);
1482 break;
1483 }
1484 }
1485 }
1486
1487 bool ForceLRSpill = false;
1488 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
1489 unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
1490 // Force LR to be spilled if the Thumb function size is > 2048. This enables
1491 // use of BL to implement far jump. If it turns out that it's not needed
1492 // then the branch fix up path will undo it.
1493 if (FnSize >= (1 << 11)) {
1494 CanEliminateFrame = false;
1495 ForceLRSpill = true;
1496 }
1497 }
1498
1499 // If any of the stack slot references may be out of range of an immediate
1500 // offset, make sure a register (or a spill slot) is available for the
1501 // register scavenger. Note that if we're indexing off the frame pointer, the
1502 // effective stack size is 4 bytes larger since the FP points to the stack
1503 // slot of the previous FP. Also, if we have variable sized objects in the
1504 // function, stack slot references will often be negative, and some of
1505 // our instructions are positive-offset only, so conservatively consider
1506 // that case to want a spill slot (or register) as well. Similarly, if
1507 // the function adjusts the stack pointer during execution and the
1508 // adjustments aren't already part of our stack size estimate, our offset
1509 // calculations may be off, so be conservative.
1510 // FIXME: We could add logic to be more precise about negative offsets
1511 // and which instructions will need a scratch register for them. Is it
1512 // worth the effort and added fragility?
1513 bool BigStack =
1514 (RS &&
1515 (MFI->estimateStackSize(MF) +
1516 ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
1517 estimateRSStackSizeLimit(MF, this)))
1518 || MFI->hasVarSizedObjects()
1519 || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
1520
1521 bool ExtraCSSpill = false;
1522 if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) {
1523 AFI->setHasStackFrame(true);
1524
1525 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
1526 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
1527 if (!LRSpilled && CS1Spilled) {
1528 MRI.setPhysRegUsed(ARM::LR);
1529 NumGPRSpills++;
1530 SmallVectorImpl<unsigned>::iterator LRPos;
1531 LRPos = std::find(UnspilledCS1GPRs.begin(), UnspilledCS1GPRs.end(),
1532 (unsigned)ARM::LR);
1533 if (LRPos != UnspilledCS1GPRs.end())
1534 UnspilledCS1GPRs.erase(LRPos);
1535
1536 ForceLRSpill = false;
1537 ExtraCSSpill = true;
1538 }
1539
1540 if (hasFP(MF)) {
1541 MRI.setPhysRegUsed(FramePtr);
1542 auto FPPos = std::find(UnspilledCS1GPRs.begin(), UnspilledCS1GPRs.end(),
1543 FramePtr);
1544 if (FPPos != UnspilledCS1GPRs.end())
1545 UnspilledCS1GPRs.erase(FPPos);
1546 NumGPRSpills++;
1547 }
1548
1549 // If stack and double are 8-byte aligned and we are spilling an odd number
1550 // of GPRs, spill one extra callee save GPR so we won't have to pad between
1551 // the integer and double callee save areas.
1552 unsigned TargetAlign = getStackAlignment();
1553 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
1554 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
1555 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
1556 unsigned Reg = UnspilledCS1GPRs[i];
1557 // Don't spill high register if the function is thumb1
1558 if (!AFI->isThumb1OnlyFunction() ||
1559 isARMLowRegister(Reg) || Reg == ARM::LR) {
1560 MRI.setPhysRegUsed(Reg);
1561 if (!MRI.isReserved(Reg))
1562 ExtraCSSpill = true;
1563 break;
1564 }
1565 }
1566 } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) {
1567 unsigned Reg = UnspilledCS2GPRs.front();
1568 MRI.setPhysRegUsed(Reg);
1569 if (!MRI.isReserved(Reg))
1570 ExtraCSSpill = true;
1571 }
1572 }
1573
1574 // Estimate if we might need to scavenge a register at some point in order
1575 // to materialize a stack offset. If so, either spill one additional
1576 // callee-saved register or reserve a special spill slot to facilitate
1577 // register scavenging. Thumb1 needs a spill slot for stack pointer
1578 // adjustments also, even when the frame itself is small.
1579 if (BigStack && !ExtraCSSpill) {
1580 // If any non-reserved CS register isn't spilled, just spill one or two
1581 // extra. That should take care of it!
1582 unsigned NumExtras = TargetAlign / 4;
1583 SmallVector<unsigned, 2> Extras;
1584 while (NumExtras && !UnspilledCS1GPRs.empty()) {
1585 unsigned Reg = UnspilledCS1GPRs.back();
1586 UnspilledCS1GPRs.pop_back();
1587 if (!MRI.isReserved(Reg) &&
1588 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
1589 Reg == ARM::LR)) {
1590 Extras.push_back(Reg);
1591 NumExtras--;
1592 }
1593 }
1594 // For non-Thumb1 functions, also check for hi-reg CS registers
1595 if (!AFI->isThumb1OnlyFunction()) {
1596 while (NumExtras && !UnspilledCS2GPRs.empty()) {
1597 unsigned Reg = UnspilledCS2GPRs.back();
1598 UnspilledCS2GPRs.pop_back();
1599 if (!MRI.isReserved(Reg)) {
1600 Extras.push_back(Reg);
1601 NumExtras--;
1602 }
1603 }
1604 }
1605 if (Extras.size() && NumExtras == 0) {
1606 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
1607 MRI.setPhysRegUsed(Extras[i]);
1608 }
1609 } else if (!AFI->isThumb1OnlyFunction()) {
1610 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
1611 // closest to SP or frame pointer.
1612 const TargetRegisterClass *RC = &ARM::GPRRegClass;
1613 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1614 RC->getAlignment(),
1615 false));
1616 }
1617 }
1618 }
1619
1620 if (ForceLRSpill) {
1621 MRI.setPhysRegUsed(ARM::LR);
1622 AFI->setLRIsSpilledForFarJump(true);
1623 }
1624}
1625
1626
1627void ARMFrameLowering::
1628eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1629 MachineBasicBlock::iterator I) const {
1630 const ARMBaseInstrInfo &TII =
1631 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
1632 if (!hasReservedCallFrame(MF)) {
1633 // If we have alloca, convert as follows:
1634 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1635 // ADJCALLSTACKUP -> add, sp, sp, amount
1636 MachineInstr *Old = I;
1637 DebugLoc dl = Old->getDebugLoc();
1638 unsigned Amount = Old->getOperand(0).getImm();
1639 if (Amount != 0) {
1640 // We need to keep the stack aligned properly. To do this, we round the
1641 // amount of space needed for the outgoing arguments up to the next
1642 // alignment boundary.
1643 unsigned Align = getStackAlignment();
1644 Amount = (Amount+Align-1)/Align*Align;
1645
1646 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1647 assert(!AFI->isThumb1OnlyFunction() &&
1648 "This eliminateCallFramePseudoInstr does not support Thumb1!");
1649 bool isARM = !AFI->isThumbFunction();
1650
1651 // Replace the pseudo instruction with a new instruction...
1652 unsigned Opc = Old->getOpcode();
1653 int PIdx = Old->findFirstPredOperandIdx();
1654 ARMCC::CondCodes Pred = (PIdx == -1)
1655 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1656 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1657 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1658 unsigned PredReg = Old->getOperand(2).getReg();
1659 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, MachineInstr::NoFlags,
1660 Pred, PredReg);
1661 } else {
1662 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1663 unsigned PredReg = Old->getOperand(3).getReg();
1664 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1665 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, MachineInstr::NoFlags,
1666 Pred, PredReg);
1667 }
1668 }
1669 }
1670 MBB.erase(I);
1671}
1672
1673/// Get the minimum constant for ARM that is greater than or equal to the
1674/// argument. In ARM, constants can have any value that can be produced by
1675/// rotating an 8-bit value to the right by an even number of bits within a
1676/// 32-bit word.
1677static uint32_t alignToARMConstant(uint32_t Value) {
1678 unsigned Shifted = 0;
1679
1680 if (Value == 0)
1681 return 0;
1682
1683 while (!(Value & 0xC0000000)) {
1684 Value = Value << 2;
1685 Shifted += 2;
1686 }
1687
1688 bool Carry = (Value & 0x00FFFFFF);
1689 Value = ((Value & 0xFF000000) >> 24) + Carry;
1690
1691 if (Value & 0x0000100)
1692 Value = Value & 0x000001FC;
1693
1694 if (Shifted > 24)
1695 Value = Value >> (Shifted - 24);
1696 else
1697 Value = Value << (24 - Shifted);
1698
1699 return Value;
1700}
1701
1702// The stack limit in the TCB is set to this many bytes above the actual
1703// stack limit.
1704static const uint64_t kSplitStackAvailable = 256;
1705
1706// Adjust the function prologue to enable split stacks. This currently only
1707// supports android and linux.
1708//
1709// The ABI of the segmented stack prologue is a little arbitrarily chosen, but
1710// must be well defined in order to allow for consistent implementations of the
1711// __morestack helper function. The ABI is also not a normal ABI in that it
1712// doesn't follow the normal calling conventions because this allows the
1713// prologue of each function to be optimized further.
1714//
1715// Currently, the ABI looks like (when calling __morestack)
1716//
1717// * r4 holds the minimum stack size requested for this function call
1718// * r5 holds the stack size of the arguments to the function
1719// * the beginning of the function is 3 instructions after the call to
1720// __morestack
1721//
1722// Implementations of __morestack should use r4 to allocate a new stack, r5 to
1723// place the arguments on to the new stack, and the 3-instruction knowledge to
1724// jump directly to the body of the function when working on the new stack.
1725//
1726// An old (and possibly no longer compatible) implementation of __morestack for
1727// ARM can be found at [1].
1728//
1729// [1] - https://github.com/mozilla/rust/blob/86efd9/src/rt/arch/arm/morestack.S
1730void ARMFrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
1731 unsigned Opcode;
1732 unsigned CFIIndex;
1733 const ARMSubtarget *ST = &MF.getTarget().getSubtarget<ARMSubtarget>();
1734 bool Thumb = ST->isThumb();
1735
1736 // Sadly, this currently doesn't support varargs, platforms other than
1737 // android/linux. Note that thumb1/thumb2 are support for android/linux.
1738 if (MF.getFunction()->isVarArg())
1739 report_fatal_error("Segmented stacks do not support vararg functions.");
1740 if (!ST->isTargetAndroid() && !ST->isTargetLinux())
1741 report_fatal_error("Segmented stacks not supported on this platform.");
1742
1743 MachineBasicBlock &prologueMBB = MF.front();
1744 MachineFrameInfo *MFI = MF.getFrameInfo();
1745 MachineModuleInfo &MMI = MF.getMMI();
1746 MCContext &Context = MMI.getContext();
1747 const MCRegisterInfo *MRI = Context.getRegisterInfo();
1748 const ARMBaseInstrInfo &TII =
1749 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
1750 ARMFunctionInfo *ARMFI = MF.getInfo<ARMFunctionInfo>();
1751 DebugLoc DL;
1752
1753 uint64_t StackSize = MFI->getStackSize();
1754
1755 // Do not generate a prologue for functions with a stack of size zero
1756 if (StackSize == 0)
1757 return;
1758
1759 // Use R4 and R5 as scratch registers.
1760 // We save R4 and R5 before use and restore them before leaving the function.
1761 unsigned ScratchReg0 = ARM::R4;
1762 unsigned ScratchReg1 = ARM::R5;
1763 uint64_t AlignedStackSize;
1764
1765 MachineBasicBlock *PrevStackMBB = MF.CreateMachineBasicBlock();
1766 MachineBasicBlock *PostStackMBB = MF.CreateMachineBasicBlock();
1767 MachineBasicBlock *AllocMBB = MF.CreateMachineBasicBlock();
1768 MachineBasicBlock *GetMBB = MF.CreateMachineBasicBlock();
1769 MachineBasicBlock *McrMBB = MF.CreateMachineBasicBlock();
1770
1771 for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(),
1772 e = prologueMBB.livein_end();
1773 i != e; ++i) {
1774 AllocMBB->addLiveIn(*i);
1775 GetMBB->addLiveIn(*i);
1776 McrMBB->addLiveIn(*i);
1777 PrevStackMBB->addLiveIn(*i);
1778 PostStackMBB->addLiveIn(*i);
1779 }
1780
1781 MF.push_front(PostStackMBB);
1782 MF.push_front(AllocMBB);
1783 MF.push_front(GetMBB);
1784 MF.push_front(McrMBB);
1785 MF.push_front(PrevStackMBB);
1786
1787 // The required stack size that is aligned to ARM constant criterion.
1788 AlignedStackSize = alignToARMConstant(StackSize);
1789
1790 // When the frame size is less than 256 we just compare the stack
1791 // boundary directly to the value of the stack pointer, per gcc.
1792 bool CompareStackPointer = AlignedStackSize < kSplitStackAvailable;
1793
1794 // We will use two of the callee save registers as scratch registers so we
1795 // need to save those registers onto the stack.
1796 // We will use SR0 to hold stack limit and SR1 to hold the stack size
1797 // requested and arguments for __morestack().
1798 // SR0: Scratch Register #0
1799 // SR1: Scratch Register #1
1800 // push {SR0, SR1}
1801 if (Thumb) {
1802 AddDefaultPred(BuildMI(PrevStackMBB, DL, TII.get(ARM::tPUSH)))
1803 .addReg(ScratchReg0).addReg(ScratchReg1);
1804 } else {
1805 AddDefaultPred(BuildMI(PrevStackMBB, DL, TII.get(ARM::STMDB_UPD))
1806 .addReg(ARM::SP, RegState::Define).addReg(ARM::SP))
1807 .addReg(ScratchReg0).addReg(ScratchReg1);
1808 }
1809
1810 // Emit the relevant DWARF information about the change in stack pointer as
1811 // well as where to find both r4 and r5 (the callee-save registers)
1812 CFIIndex =
1813 MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -8));
1814 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1815 .addCFIIndex(CFIIndex);
1816 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
1817 nullptr, MRI->getDwarfRegNum(ScratchReg1, true), -4));
1818 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1819 .addCFIIndex(CFIIndex);
1820 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
1821 nullptr, MRI->getDwarfRegNum(ScratchReg0, true), -8));
1822 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1823 .addCFIIndex(CFIIndex);
1824
1825 // mov SR1, sp
1826 if (Thumb) {
1827 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1)
1828 .addReg(ARM::SP));
1829 } else if (CompareStackPointer) {
1830 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1)
1831 .addReg(ARM::SP)).addReg(0);
1832 }
1833
1834 // sub SR1, sp, #StackSize
1835 if (!CompareStackPointer && Thumb) {
1836 AddDefaultPred(
1837 AddDefaultCC(BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1))
1838 .addReg(ScratchReg1).addImm(AlignedStackSize));
1839 } else if (!CompareStackPointer) {
1840 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1)
1841 .addReg(ARM::SP).addImm(AlignedStackSize)).addReg(0);
1842 }
1843
1844 if (Thumb && ST->isThumb1Only()) {
1845 unsigned PCLabelId = ARMFI->createPICLabelUId();
1846 ARMConstantPoolValue *NewCPV = ARMConstantPoolSymbol::Create(
1847 MF.getFunction()->getContext(), "__STACK_LIMIT", PCLabelId, 0);
1848 MachineConstantPool *MCP = MF.getConstantPool();
1849 unsigned CPI = MCP->getConstantPoolIndex(NewCPV, MF.getAlignment());
1850
1851 // ldr SR0, [pc, offset(STACK_LIMIT)]
1852 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::tLDRpci), ScratchReg0)
1853 .addConstantPoolIndex(CPI));
1854
1855 // ldr SR0, [SR0]
1856 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::tLDRi), ScratchReg0)
1857 .addReg(ScratchReg0).addImm(0));
1858 } else {
1859 // Get TLS base address from the coprocessor
1860 // mrc p15, #0, SR0, c13, c0, #3
1861 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::MRC), ScratchReg0)
1862 .addImm(15)
1863 .addImm(0)
1864 .addImm(13)
1865 .addImm(0)
1866 .addImm(3));
1867
1868 // Use the last tls slot on android and a private field of the TCP on linux.
1869 assert(ST->isTargetAndroid() || ST->isTargetLinux());
1870 unsigned TlsOffset = ST->isTargetAndroid() ? 63 : 1;
1871
1872 // Get the stack limit from the right offset
1873 // ldr SR0, [sr0, #4 * TlsOffset]
1874 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::LDRi12), ScratchReg0)
1875 .addReg(ScratchReg0).addImm(4 * TlsOffset));
1876 }
1877
1878 // Compare stack limit with stack size requested.
1879 // cmp SR0, SR1
1880 Opcode = Thumb ? ARM::tCMPr : ARM::CMPrr;
1881 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(Opcode))
1882 .addReg(ScratchReg0)
1883 .addReg(ScratchReg1));
1884
1885 // This jump is taken if StackLimit < SP - stack required.
1886 Opcode = Thumb ? ARM::tBcc : ARM::Bcc;
1887 BuildMI(GetMBB, DL, TII.get(Opcode)).addMBB(PostStackMBB)
1888 .addImm(ARMCC::LO)
1889 .addReg(ARM::CPSR);
1890
1891
1892 // Calling __morestack(StackSize, Size of stack arguments).
1893 // __morestack knows that the stack size requested is in SR0(r4)
1894 // and amount size of stack arguments is in SR1(r5).
1895
1896 // Pass first argument for the __morestack by Scratch Register #0.
1897 // The amount size of stack required
1898 if (Thumb) {
1899 AddDefaultPred(AddDefaultCC(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8),
1900 ScratchReg0)).addImm(AlignedStackSize));
1901 } else {
1902 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0)
1903 .addImm(AlignedStackSize)).addReg(0);
1904 }
1905 // Pass second argument for the __morestack by Scratch Register #1.
1906 // The amount size of stack consumed to save function arguments.
1907 if (Thumb) {
1908 AddDefaultPred(
1909 AddDefaultCC(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1))
1910 .addImm(alignToARMConstant(ARMFI->getArgumentStackSize())));
1911 } else {
1912 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1)
1913 .addImm(alignToARMConstant(ARMFI->getArgumentStackSize())))
1914 .addReg(0);
1915 }
1916
1917 // push {lr} - Save return address of this function.
1918 if (Thumb) {
1919 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPUSH)))
1920 .addReg(ARM::LR);
1921 } else {
1922 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::STMDB_UPD))
1923 .addReg(ARM::SP, RegState::Define)
1924 .addReg(ARM::SP))
1925 .addReg(ARM::LR);
1926 }
1927
1928 // Emit the DWARF info about the change in stack as well as where to find the
1929 // previous link register
1930 CFIIndex =
1931 MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -12));
1932 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1933 .addCFIIndex(CFIIndex);
1934 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
1935 nullptr, MRI->getDwarfRegNum(ARM::LR, true), -12));
1936 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1937 .addCFIIndex(CFIIndex);
1938
1939 // Call __morestack().
1940 if (Thumb) {
1941 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tBL)))
1942 .addExternalSymbol("__morestack");
1943 } else {
1944 BuildMI(AllocMBB, DL, TII.get(ARM::BL))
1945 .addExternalSymbol("__morestack");
1946 }
1947
1948 // pop {lr} - Restore return address of this original function.
1949 if (Thumb) {
1950 if (ST->isThumb1Only()) {
1951 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPOP)))
1952 .addReg(ScratchReg0);
1953 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::LR)
1954 .addReg(ScratchReg0));
1955 } else {
1956 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::t2LDR_POST))
1957 .addReg(ARM::LR, RegState::Define)
1958 .addReg(ARM::SP, RegState::Define)
1959 .addReg(ARM::SP)
1960 .addImm(4));
1961 }
1962 } else {
1963 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
1964 .addReg(ARM::SP, RegState::Define)
1965 .addReg(ARM::SP))
1966 .addReg(ARM::LR);
1967 }
1968
1969 // Restore SR0 and SR1 in case of __morestack() was called.
1970 // __morestack() will skip PostStackMBB block so we need to restore
1971 // scratch registers from here.
1972 // pop {SR0, SR1}
1973 if (Thumb) {
1974 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPOP)))
1975 .addReg(ScratchReg0)
1976 .addReg(ScratchReg1);
1977 } else {
1978 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
1979 .addReg(ARM::SP, RegState::Define)
1980 .addReg(ARM::SP))
1981 .addReg(ScratchReg0)
1982 .addReg(ScratchReg1);
1983 }
1984
1985 // Update the CFA offset now that we've popped
1986 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
1987 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1988 .addCFIIndex(CFIIndex);
1989
1990 // bx lr - Return from this function.
1991 Opcode = Thumb ? ARM::tBX_RET : ARM::BX_RET;
1992 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(Opcode)));
1993
1994 // Restore SR0 and SR1 in case of __morestack() was not called.
1995 // pop {SR0, SR1}
1996 if (Thumb) {
1997 AddDefaultPred(BuildMI(PostStackMBB, DL, TII.get(ARM::tPOP)))
1998 .addReg(ScratchReg0)
1999 .addReg(ScratchReg1);
2000 } else {
2001 AddDefaultPred(BuildMI(PostStackMBB, DL, TII.get(ARM::LDMIA_UPD))
2002 .addReg(ARM::SP, RegState::Define)
2003 .addReg(ARM::SP))
2004 .addReg(ScratchReg0)
2005 .addReg(ScratchReg1);
2006 }
2007
2008 // Update the CFA offset now that we've popped
2009 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
2010 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2011 .addCFIIndex(CFIIndex);
2012
2013 // Tell debuggers that r4 and r5 are now the same as they were in the
2014 // previous function, that they're the "Same Value".
2015 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createSameValue(
2016 nullptr, MRI->getDwarfRegNum(ScratchReg0, true)));
2017 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2018 .addCFIIndex(CFIIndex);
2019 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createSameValue(
2020 nullptr, MRI->getDwarfRegNum(ScratchReg1, true)));
2021 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2022 .addCFIIndex(CFIIndex);
2023
2024 // Organizing MBB lists
2025 PostStackMBB->addSuccessor(&prologueMBB);
2026
2027 AllocMBB->addSuccessor(PostStackMBB);
2028
2029 GetMBB->addSuccessor(PostStackMBB);
2030 GetMBB->addSuccessor(AllocMBB);
2031
2032 McrMBB->addSuccessor(GetMBB);
2033
2034 PrevStackMBB->addSuccessor(McrMBB);
2035
2036#ifdef XDEBUG
2037 MF.verify();
2038#endif
2039}