| InstrEmitter.cpp (261991) | InstrEmitter.cpp (262613) |
|---|---|
| 1//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 206 unchanged lines hidden (view full) --- 215 unsigned NumResults = CountResults(Node); 216 for (unsigned i = 0; i < II.getNumDefs(); ++i) { 217 // If the specific node value is only used by a CopyToReg and the dest reg 218 // is a vreg in the same register class, use the CopyToReg'd destination 219 // register instead of creating a new vreg. 220 unsigned VRBase = 0; 221 const TargetRegisterClass *RC = 222 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); | 1//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 206 unchanged lines hidden (view full) --- 215 unsigned NumResults = CountResults(Node); 216 for (unsigned i = 0; i < II.getNumDefs(); ++i) { 217 // If the specific node value is only used by a CopyToReg and the dest reg 218 // is a vreg in the same register class, use the CopyToReg'd destination 219 // register instead of creating a new vreg. 220 unsigned VRBase = 0; 221 const TargetRegisterClass *RC = 222 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); |
| 223 // If the register class is unknown for the given definition, then try to 224 // infer one from the value type. 225 if (!RC && i < NumResults) 226 RC = TLI->getRegClassFor(Node->getSimpleValueType(i)); | 223 // Always let the value type influence the used register class. The 224 // constraints on the instruction may be too lax to represent the value 225 // type correctly. For example, a 64-bit float (X86::FR64) can't live in 226 // the 32-bit float super-class (X86::FR32). 227 if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) { 228 const TargetRegisterClass *VTRC = 229 TLI->getRegClassFor(Node->getSimpleValueType(i)); 230 if (RC) 231 VTRC = TRI->getCommonSubClass(RC, VTRC); 232 if (VTRC) 233 RC = VTRC; 234 } 235 |
| 227 if (II.OpInfo[i].isOptionalDef()) { 228 // Optional def must be a physical register. 229 unsigned NumResults = CountResults(Node); 230 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); 231 assert(TargetRegisterInfo::isPhysicalRegister(VRBase)); 232 MIB.addReg(VRBase, RegState::Define); 233 } 234 --- 776 unchanged lines hidden --- | 236 if (II.OpInfo[i].isOptionalDef()) { 237 // Optional def must be a physical register. 238 unsigned NumResults = CountResults(Node); 239 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); 240 assert(TargetRegisterInfo::isPhysicalRegister(VRBase)); 241 MIB.addReg(VRBase, RegState::Define); 242 } 243 --- 776 unchanged lines hidden --- |