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1//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the Emit routines for the SelectionDAG class, which creates
11// MachineInstrs based on the decisions of the SelectionDAG instruction
12// selection.
13//
14//===----------------------------------------------------------------------===//
15
16#define DEBUG_TYPE "instr-emitter"
17#include "InstrEmitter.h"
18#include "SDNodeDbgValue.h"
19#include "llvm/ADT/Statistic.h"
20#include "llvm/CodeGen/MachineConstantPool.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/StackMaps.h"
25#include "llvm/IR/DataLayout.h"
26#include "llvm/Support/Debug.h"
27#include "llvm/Support/ErrorHandling.h"
28#include "llvm/Support/MathExtras.h"
29#include "llvm/Target/TargetInstrInfo.h"
30#include "llvm/Target/TargetLowering.h"
31#include "llvm/Target/TargetMachine.h"
32using namespace llvm;
33
34/// MinRCSize - Smallest register class we allow when constraining virtual
35/// registers. If satisfying all register class constraints would require
36/// using a smaller register class, emit a COPY to a new virtual register
37/// instead.
38const unsigned MinRCSize = 4;
39
40/// CountResults - The results of target nodes have register or immediate
41/// operands first, then an optional chain, and optional glue operands (which do
42/// not go into the resulting MachineInstr).
43unsigned InstrEmitter::CountResults(SDNode *Node) {
44 unsigned N = Node->getNumValues();
45 while (N && Node->getValueType(N - 1) == MVT::Glue)
46 --N;
47 if (N && Node->getValueType(N - 1) == MVT::Other)
48 --N; // Skip over chain result.
49 return N;
50}
51
52/// countOperands - The inputs to target nodes have any actual inputs first,
53/// followed by an optional chain operand, then an optional glue operand.
54/// Compute the number of actual operands that will go into the resulting
55/// MachineInstr.
56///
57/// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
58/// the chain and glue. These operands may be implicit on the machine instr.
59static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
60 unsigned &NumImpUses) {
61 unsigned N = Node->getNumOperands();
62 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
63 --N;
64 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
65 --N; // Ignore chain if it exists.
66
67 // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
68 NumImpUses = N - NumExpUses;
69 for (unsigned I = N; I > NumExpUses; --I) {
70 if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
71 continue;
72 if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
73 if (TargetRegisterInfo::isPhysicalRegister(RN->getReg()))
74 continue;
75 NumImpUses = N - I;
76 break;
77 }
78
79 return N;
80}
81
82/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
83/// implicit physical register output.
84void InstrEmitter::
85EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
86 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
87 unsigned VRBase = 0;
88 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
89 // Just use the input register directly!
90 SDValue Op(Node, ResNo);
91 if (IsClone)
92 VRBaseMap.erase(Op);
93 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
94 (void)isNew; // Silence compiler warning.
95 assert(isNew && "Node emitted out of order - early");
96 return;
97 }
98
99 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
100 // the CopyToReg'd destination register instead of creating a new vreg.
101 bool MatchReg = true;
102 const TargetRegisterClass *UseRC = NULL;
103 MVT VT = Node->getSimpleValueType(ResNo);
104
105 // Stick to the preferred register classes for legal types.
106 if (TLI->isTypeLegal(VT))
107 UseRC = TLI->getRegClassFor(VT);
108
109 if (!IsClone && !IsCloned)
110 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
111 UI != E; ++UI) {
112 SDNode *User = *UI;
113 bool Match = true;
114 if (User->getOpcode() == ISD::CopyToReg &&
115 User->getOperand(2).getNode() == Node &&
116 User->getOperand(2).getResNo() == ResNo) {
117 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
118 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
119 VRBase = DestReg;
120 Match = false;
121 } else if (DestReg != SrcReg)
122 Match = false;
123 } else {
124 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
125 SDValue Op = User->getOperand(i);
126 if (Op.getNode() != Node || Op.getResNo() != ResNo)
127 continue;
128 MVT VT = Node->getSimpleValueType(Op.getResNo());
129 if (VT == MVT::Other || VT == MVT::Glue)
130 continue;
131 Match = false;
132 if (User->isMachineOpcode()) {
133 const MCInstrDesc &II = TII->get(User->getMachineOpcode());
134 const TargetRegisterClass *RC = 0;
135 if (i+II.getNumDefs() < II.getNumOperands()) {
136 RC = TRI->getAllocatableClass(
137 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
138 }
139 if (!UseRC)
140 UseRC = RC;
141 else if (RC) {
142 const TargetRegisterClass *ComRC =
143 TRI->getCommonSubClass(UseRC, RC);
144 // If multiple uses expect disjoint register classes, we emit
145 // copies in AddRegisterOperand.
146 if (ComRC)
147 UseRC = ComRC;
148 }
149 }
150 }
151 }
152 MatchReg &= Match;
153 if (VRBase)
154 break;
155 }
156
157 const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
158 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
159
160 // Figure out the register class to create for the destreg.
161 if (VRBase) {
162 DstRC = MRI->getRegClass(VRBase);
163 } else if (UseRC) {
164 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
165 DstRC = UseRC;
166 } else {
167 DstRC = TLI->getRegClassFor(VT);
168 }
169
170 // If all uses are reading from the src physical register and copying the
171 // register is either impossible or very expensive, then don't create a copy.
172 if (MatchReg && SrcRC->getCopyCost() < 0) {
173 VRBase = SrcReg;
174 } else {
175 // Create the reg, emit the copy.
176 VRBase = MRI->createVirtualRegister(DstRC);
177 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
178 VRBase).addReg(SrcReg);
179 }
180
181 SDValue Op(Node, ResNo);
182 if (IsClone)
183 VRBaseMap.erase(Op);
184 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
185 (void)isNew; // Silence compiler warning.
186 assert(isNew && "Node emitted out of order - early");
187}
188
189/// getDstOfCopyToRegUse - If the only use of the specified result number of
190/// node is a CopyToReg, return its destination register. Return 0 otherwise.
191unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
192 unsigned ResNo) const {
193 if (!Node->hasOneUse())
194 return 0;
195
196 SDNode *User = *Node->use_begin();
197 if (User->getOpcode() == ISD::CopyToReg &&
198 User->getOperand(2).getNode() == Node &&
199 User->getOperand(2).getResNo() == ResNo) {
200 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
201 if (TargetRegisterInfo::isVirtualRegister(Reg))
202 return Reg;
203 }
204 return 0;
205}
206
207void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
208 MachineInstrBuilder &MIB,
209 const MCInstrDesc &II,
210 bool IsClone, bool IsCloned,
211 DenseMap<SDValue, unsigned> &VRBaseMap) {
212 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
213 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
214
215 unsigned NumResults = CountResults(Node);
216 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
217 // If the specific node value is only used by a CopyToReg and the dest reg
218 // is a vreg in the same register class, use the CopyToReg'd destination
219 // register instead of creating a new vreg.
220 unsigned VRBase = 0;
221 const TargetRegisterClass *RC =
222 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
223 // If the register class is unknown for the given definition, then try to
224 // infer one from the value type.
225 if (!RC && i < NumResults)
226 RC = TLI->getRegClassFor(Node->getSimpleValueType(i));
223 // Always let the value type influence the used register class. The
224 // constraints on the instruction may be too lax to represent the value
225 // type correctly. For example, a 64-bit float (X86::FR64) can't live in
226 // the 32-bit float super-class (X86::FR32).
227 if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
228 const TargetRegisterClass *VTRC =
229 TLI->getRegClassFor(Node->getSimpleValueType(i));
230 if (RC)
231 VTRC = TRI->getCommonSubClass(RC, VTRC);
232 if (VTRC)
233 RC = VTRC;
234 }
235
236 if (II.OpInfo[i].isOptionalDef()) {
237 // Optional def must be a physical register.
238 unsigned NumResults = CountResults(Node);
239 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
240 assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
241 MIB.addReg(VRBase, RegState::Define);
242 }
243
244 if (!VRBase && !IsClone && !IsCloned)
245 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
246 UI != E; ++UI) {
247 SDNode *User = *UI;
248 if (User->getOpcode() == ISD::CopyToReg &&
249 User->getOperand(2).getNode() == Node &&
250 User->getOperand(2).getResNo() == i) {
251 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
252 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
253 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
254 if (RegRC == RC) {
255 VRBase = Reg;
256 MIB.addReg(VRBase, RegState::Define);
257 break;
258 }
259 }
260 }
261 }
262
263 // Create the result registers for this node and add the result regs to
264 // the machine instruction.
265 if (VRBase == 0) {
266 assert(RC && "Isn't a register operand!");
267 VRBase = MRI->createVirtualRegister(RC);
268 MIB.addReg(VRBase, RegState::Define);
269 }
270
271 SDValue Op(Node, i);
272 if (IsClone)
273 VRBaseMap.erase(Op);
274 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
275 (void)isNew; // Silence compiler warning.
276 assert(isNew && "Node emitted out of order - early");
277 }
278}
279
280/// getVR - Return the virtual register corresponding to the specified result
281/// of the specified node.
282unsigned InstrEmitter::getVR(SDValue Op,
283 DenseMap<SDValue, unsigned> &VRBaseMap) {
284 if (Op.isMachineOpcode() &&
285 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
286 // Add an IMPLICIT_DEF instruction before every use.
287 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
288 // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
289 // does not include operand register class info.
290 if (!VReg) {
291 const TargetRegisterClass *RC =
292 TLI->getRegClassFor(Op.getSimpleValueType());
293 VReg = MRI->createVirtualRegister(RC);
294 }
295 BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
296 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
297 return VReg;
298 }
299
300 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
301 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
302 return I->second;
303}
304
305
306/// AddRegisterOperand - Add the specified register as an operand to the
307/// specified machine instr. Insert register copies if the register is
308/// not in the required register class.
309void
310InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
311 SDValue Op,
312 unsigned IIOpNum,
313 const MCInstrDesc *II,
314 DenseMap<SDValue, unsigned> &VRBaseMap,
315 bool IsDebug, bool IsClone, bool IsCloned) {
316 assert(Op.getValueType() != MVT::Other &&
317 Op.getValueType() != MVT::Glue &&
318 "Chain and glue operands should occur at end of operand list!");
319 // Get/emit the operand.
320 unsigned VReg = getVR(Op, VRBaseMap);
321 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
322
323 const MCInstrDesc &MCID = MIB->getDesc();
324 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
325 MCID.OpInfo[IIOpNum].isOptionalDef();
326
327 // If the instruction requires a register in a different class, create
328 // a new virtual register and copy the value into it, but first attempt to
329 // shrink VReg's register class within reason. For example, if VReg == GR32
330 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
331 if (II) {
332 const TargetRegisterClass *DstRC = 0;
333 if (IIOpNum < II->getNumOperands())
334 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
335 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
336 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
337 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
338 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
339 VReg = NewVReg;
340 }
341 }
342
343 // If this value has only one use, that use is a kill. This is a
344 // conservative approximation. InstrEmitter does trivial coalescing
345 // with CopyFromReg nodes, so don't emit kill flags for them.
346 // Avoid kill flags on Schedule cloned nodes, since there will be
347 // multiple uses.
348 // Tied operands are never killed, so we need to check that. And that
349 // means we need to determine the index of the operand.
350 bool isKill = Op.hasOneUse() &&
351 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
352 !IsDebug &&
353 !(IsClone || IsCloned);
354 if (isKill) {
355 unsigned Idx = MIB->getNumOperands();
356 while (Idx > 0 &&
357 MIB->getOperand(Idx-1).isReg() &&
358 MIB->getOperand(Idx-1).isImplicit())
359 --Idx;
360 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
361 if (isTied)
362 isKill = false;
363 }
364
365 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
366 getDebugRegState(IsDebug));
367}
368
369/// AddOperand - Add the specified operand to the specified machine instr. II
370/// specifies the instruction information for the node, and IIOpNum is the
371/// operand number (in the II) that we are adding.
372void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
373 SDValue Op,
374 unsigned IIOpNum,
375 const MCInstrDesc *II,
376 DenseMap<SDValue, unsigned> &VRBaseMap,
377 bool IsDebug, bool IsClone, bool IsCloned) {
378 if (Op.isMachineOpcode()) {
379 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
380 IsDebug, IsClone, IsCloned);
381 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
382 MIB.addImm(C->getSExtValue());
383 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
384 MIB.addFPImm(F->getConstantFPValue());
385 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
386 // Turn additional physreg operands into implicit uses on non-variadic
387 // instructions. This is used by call and return instructions passing
388 // arguments in registers.
389 bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
390 MIB.addReg(R->getReg(), getImplRegState(Imp));
391 } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
392 MIB.addRegMask(RM->getRegMask());
393 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
394 MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
395 TGA->getTargetFlags());
396 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
397 MIB.addMBB(BBNode->getBasicBlock());
398 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
399 MIB.addFrameIndex(FI->getIndex());
400 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
401 MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
402 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
403 int Offset = CP->getOffset();
404 unsigned Align = CP->getAlignment();
405 Type *Type = CP->getType();
406 // MachineConstantPool wants an explicit alignment.
407 if (Align == 0) {
408 Align = TM->getDataLayout()->getPrefTypeAlignment(Type);
409 if (Align == 0) {
410 // Alignment of vector types. FIXME!
411 Align = TM->getDataLayout()->getTypeAllocSize(Type);
412 }
413 }
414
415 unsigned Idx;
416 MachineConstantPool *MCP = MF->getConstantPool();
417 if (CP->isMachineConstantPoolEntry())
418 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
419 else
420 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
421 MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
422 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
423 MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
424 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
425 MIB.addBlockAddress(BA->getBlockAddress(),
426 BA->getOffset(),
427 BA->getTargetFlags());
428 } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
429 MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
430 } else {
431 assert(Op.getValueType() != MVT::Other &&
432 Op.getValueType() != MVT::Glue &&
433 "Chain and glue operands should occur at end of operand list!");
434 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
435 IsDebug, IsClone, IsCloned);
436 }
437}
438
439unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
440 MVT VT, DebugLoc DL) {
441 const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
442 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
443
444 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
445 // within reason.
446 if (RC && RC != VRC)
447 RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
448
449 // VReg has been adjusted. It can be used with SubIdx operands now.
450 if (RC)
451 return VReg;
452
453 // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
454 // register instead.
455 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx);
456 assert(RC && "No legal register class for VT supports that SubIdx");
457 unsigned NewReg = MRI->createVirtualRegister(RC);
458 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
459 .addReg(VReg);
460 return NewReg;
461}
462
463/// EmitSubregNode - Generate machine code for subreg nodes.
464///
465void InstrEmitter::EmitSubregNode(SDNode *Node,
466 DenseMap<SDValue, unsigned> &VRBaseMap,
467 bool IsClone, bool IsCloned) {
468 unsigned VRBase = 0;
469 unsigned Opc = Node->getMachineOpcode();
470
471 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
472 // the CopyToReg'd destination register instead of creating a new vreg.
473 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
474 UI != E; ++UI) {
475 SDNode *User = *UI;
476 if (User->getOpcode() == ISD::CopyToReg &&
477 User->getOperand(2).getNode() == Node) {
478 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
479 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
480 VRBase = DestReg;
481 break;
482 }
483 }
484 }
485
486 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
487 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
488 // constraints on the %dst register, COPY can target all legal register
489 // classes.
490 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
491 const TargetRegisterClass *TRC =
492 TLI->getRegClassFor(Node->getSimpleValueType(0));
493
494 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
495 MachineInstr *DefMI = MRI->getVRegDef(VReg);
496 unsigned SrcReg, DstReg, DefSubIdx;
497 if (DefMI &&
498 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
499 SubIdx == DefSubIdx &&
500 TRC == MRI->getRegClass(SrcReg)) {
501 // Optimize these:
502 // r1025 = s/zext r1024, 4
503 // r1026 = extract_subreg r1025, 4
504 // to a copy
505 // r1026 = copy r1024
506 VRBase = MRI->createVirtualRegister(TRC);
507 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
508 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
509 MRI->clearKillFlags(SrcReg);
510 } else {
511 // VReg may not support a SubIdx sub-register, and we may need to
512 // constrain its register class or issue a COPY to a compatible register
513 // class.
514 VReg = ConstrainForSubReg(VReg, SubIdx,
515 Node->getOperand(0).getSimpleValueType(),
516 Node->getDebugLoc());
517
518 // Create the destreg if it is missing.
519 if (VRBase == 0)
520 VRBase = MRI->createVirtualRegister(TRC);
521
522 // Create the extract_subreg machine instruction.
523 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
524 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx);
525 }
526 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
527 Opc == TargetOpcode::SUBREG_TO_REG) {
528 SDValue N0 = Node->getOperand(0);
529 SDValue N1 = Node->getOperand(1);
530 SDValue N2 = Node->getOperand(2);
531 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
532
533 // Figure out the register class to create for the destreg. It should be
534 // the largest legal register class supporting SubIdx sub-registers.
535 // RegisterCoalescer will constrain it further if it decides to eliminate
536 // the INSERT_SUBREG instruction.
537 //
538 // %dst = INSERT_SUBREG %src, %sub, SubIdx
539 //
540 // is lowered by TwoAddressInstructionPass to:
541 //
542 // %dst = COPY %src
543 // %dst:SubIdx = COPY %sub
544 //
545 // There is no constraint on the %src register class.
546 //
547 const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0));
548 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
549 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
550
551 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
552 VRBase = MRI->createVirtualRegister(SRC);
553
554 // Create the insert_subreg or subreg_to_reg machine instruction.
555 MachineInstrBuilder MIB =
556 BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
557
558 // If creating a subreg_to_reg, then the first input operand
559 // is an implicit value immediate, otherwise it's a register
560 if (Opc == TargetOpcode::SUBREG_TO_REG) {
561 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
562 MIB.addImm(SD->getZExtValue());
563 } else
564 AddOperand(MIB, N0, 0, 0, VRBaseMap, /*IsDebug=*/false,
565 IsClone, IsCloned);
566 // Add the subregster being inserted
567 AddOperand(MIB, N1, 0, 0, VRBaseMap, /*IsDebug=*/false,
568 IsClone, IsCloned);
569 MIB.addImm(SubIdx);
570 MBB->insert(InsertPos, MIB);
571 } else
572 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
573
574 SDValue Op(Node, 0);
575 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
576 (void)isNew; // Silence compiler warning.
577 assert(isNew && "Node emitted out of order - early");
578}
579
580/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
581/// COPY_TO_REGCLASS is just a normal copy, except that the destination
582/// register is constrained to be in a particular register class.
583///
584void
585InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
586 DenseMap<SDValue, unsigned> &VRBaseMap) {
587 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
588
589 // Create the new VReg in the destination class and emit a copy.
590 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
591 const TargetRegisterClass *DstRC =
592 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
593 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
594 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
595 NewVReg).addReg(VReg);
596
597 SDValue Op(Node, 0);
598 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
599 (void)isNew; // Silence compiler warning.
600 assert(isNew && "Node emitted out of order - early");
601}
602
603/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
604///
605void InstrEmitter::EmitRegSequence(SDNode *Node,
606 DenseMap<SDValue, unsigned> &VRBaseMap,
607 bool IsClone, bool IsCloned) {
608 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
609 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
610 unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
611 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
612 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
613 unsigned NumOps = Node->getNumOperands();
614 assert((NumOps & 1) == 1 &&
615 "REG_SEQUENCE must have an odd number of operands!");
616 for (unsigned i = 1; i != NumOps; ++i) {
617 SDValue Op = Node->getOperand(i);
618 if ((i & 1) == 0) {
619 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
620 // Skip physical registers as they don't have a vreg to get and we'll
621 // insert copies for them in TwoAddressInstructionPass anyway.
622 if (!R || !TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
623 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
624 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
625 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
626 const TargetRegisterClass *SRC =
627 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
628 if (SRC && SRC != RC) {
629 MRI->setRegClass(NewVReg, SRC);
630 RC = SRC;
631 }
632 }
633 }
634 AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
635 IsClone, IsCloned);
636 }
637
638 MBB->insert(InsertPos, MIB);
639 SDValue Op(Node, 0);
640 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
641 (void)isNew; // Silence compiler warning.
642 assert(isNew && "Node emitted out of order - early");
643}
644
645/// EmitDbgValue - Generate machine instruction for a dbg_value node.
646///
647MachineInstr *
648InstrEmitter::EmitDbgValue(SDDbgValue *SD,
649 DenseMap<SDValue, unsigned> &VRBaseMap) {
650 uint64_t Offset = SD->getOffset();
651 MDNode* MDPtr = SD->getMDPtr();
652 DebugLoc DL = SD->getDebugLoc();
653
654 if (SD->getKind() == SDDbgValue::FRAMEIX) {
655 // Stack address; this needs to be lowered in target-dependent fashion.
656 // EmitTargetCodeForFrameDebugValue is responsible for allocation.
657 return BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
658 .addFrameIndex(SD->getFrameIx()).addImm(Offset).addMetadata(MDPtr);
659 }
660 // Otherwise, we're going to create an instruction here.
661 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
662 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
663 if (SD->getKind() == SDDbgValue::SDNODE) {
664 SDNode *Node = SD->getSDNode();
665 SDValue Op = SDValue(Node, SD->getResNo());
666 // It's possible we replaced this SDNode with other(s) and therefore
667 // didn't generate code for it. It's better to catch these cases where
668 // they happen and transfer the debug info, but trying to guarantee that
669 // in all cases would be very fragile; this is a safeguard for any
670 // that were missed.
671 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
672 if (I==VRBaseMap.end())
673 MIB.addReg(0U); // undef
674 else
675 AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
676 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
677 } else if (SD->getKind() == SDDbgValue::CONST) {
678 const Value *V = SD->getConst();
679 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
680 if (CI->getBitWidth() > 64)
681 MIB.addCImm(CI);
682 else
683 MIB.addImm(CI->getSExtValue());
684 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
685 MIB.addFPImm(CF);
686 } else {
687 // Could be an Undef. In any case insert an Undef so we can see what we
688 // dropped.
689 MIB.addReg(0U);
690 }
691 } else {
692 // Insert an Undef so we can see what we dropped.
693 MIB.addReg(0U);
694 }
695
696 if (Offset != 0) // Indirect addressing.
697 MIB.addImm(Offset);
698 else
699 MIB.addReg(0U, RegState::Debug);
700
701 MIB.addMetadata(MDPtr);
702
703 return &*MIB;
704}
705
706/// EmitMachineNode - Generate machine code for a target-specific node and
707/// needed dependencies.
708///
709void InstrEmitter::
710EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
711 DenseMap<SDValue, unsigned> &VRBaseMap) {
712 unsigned Opc = Node->getMachineOpcode();
713
714 // Handle subreg insert/extract specially
715 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
716 Opc == TargetOpcode::INSERT_SUBREG ||
717 Opc == TargetOpcode::SUBREG_TO_REG) {
718 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
719 return;
720 }
721
722 // Handle COPY_TO_REGCLASS specially.
723 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
724 EmitCopyToRegClassNode(Node, VRBaseMap);
725 return;
726 }
727
728 // Handle REG_SEQUENCE specially.
729 if (Opc == TargetOpcode::REG_SEQUENCE) {
730 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
731 return;
732 }
733
734 if (Opc == TargetOpcode::IMPLICIT_DEF)
735 // We want a unique VR for each IMPLICIT_DEF use.
736 return;
737
738 const MCInstrDesc &II = TII->get(Opc);
739 unsigned NumResults = CountResults(Node);
740 unsigned NumDefs = II.getNumDefs();
741 const uint16_t *ScratchRegs = NULL;
742
743 // Handle PATCHPOINT specially and then use the generic code.
744 if (Opc == TargetOpcode::PATCHPOINT) {
745 unsigned CC = Node->getConstantOperandVal(PatchPointOpers::CCPos);
746 NumDefs = NumResults;
747 ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
748 }
749
750 unsigned NumImpUses = 0;
751 unsigned NodeOperands =
752 countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
753 bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=0;
754#ifndef NDEBUG
755 unsigned NumMIOperands = NodeOperands + NumResults;
756 if (II.isVariadic())
757 assert(NumMIOperands >= II.getNumOperands() &&
758 "Too few operands for a variadic node!");
759 else
760 assert(NumMIOperands >= II.getNumOperands() &&
761 NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +
762 NumImpUses &&
763 "#operands for dag node doesn't match .td file!");
764#endif
765
766 // Create the new machine instruction.
767 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
768
769 // Add result register values for things that are defined by this
770 // instruction.
771 if (NumResults)
772 CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
773
774 // Emit all of the actual operands of this instruction, adding them to the
775 // instruction as appropriate.
776 bool HasOptPRefs = NumDefs > NumResults;
777 assert((!HasOptPRefs || !HasPhysRegOuts) &&
778 "Unable to cope with optional defs and phys regs defs!");
779 unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
780 for (unsigned i = NumSkip; i != NodeOperands; ++i)
781 AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
782 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
783
784 // Add scratch registers as implicit def and early clobber
785 if (ScratchRegs)
786 for (unsigned i = 0; ScratchRegs[i]; ++i)
787 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
788 RegState::EarlyClobber);
789
790 // Transfer all of the memory reference descriptions of this instruction.
791 MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
792 cast<MachineSDNode>(Node)->memoperands_end());
793
794 // Insert the instruction into position in the block. This needs to
795 // happen before any custom inserter hook is called so that the
796 // hook knows where in the block to insert the replacement code.
797 MBB->insert(InsertPos, MIB);
798
799 // The MachineInstr may also define physregs instead of virtregs. These
800 // physreg values can reach other instructions in different ways:
801 //
802 // 1. When there is a use of a Node value beyond the explicitly defined
803 // virtual registers, we emit a CopyFromReg for one of the implicitly
804 // defined physregs. This only happens when HasPhysRegOuts is true.
805 //
806 // 2. A CopyFromReg reading a physreg may be glued to this instruction.
807 //
808 // 3. A glued instruction may implicitly use a physreg.
809 //
810 // 4. A glued instruction may use a RegisterSDNode operand.
811 //
812 // Collect all the used physreg defs, and make sure that any unused physreg
813 // defs are marked as dead.
814 SmallVector<unsigned, 8> UsedRegs;
815
816 // Additional results must be physical register defs.
817 if (HasPhysRegOuts) {
818 for (unsigned i = NumDefs; i < NumResults; ++i) {
819 unsigned Reg = II.getImplicitDefs()[i - NumDefs];
820 if (!Node->hasAnyUseOfValue(i))
821 continue;
822 // This implicitly defined physreg has a use.
823 UsedRegs.push_back(Reg);
824 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
825 }
826 }
827
828 // Scan the glue chain for any used physregs.
829 if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
830 for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
831 if (F->getOpcode() == ISD::CopyFromReg) {
832 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
833 continue;
834 } else if (F->getOpcode() == ISD::CopyToReg) {
835 // Skip CopyToReg nodes that are internal to the glue chain.
836 continue;
837 }
838 // Collect declared implicit uses.
839 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
840 UsedRegs.append(MCID.getImplicitUses(),
841 MCID.getImplicitUses() + MCID.getNumImplicitUses());
842 // In addition to declared implicit uses, we must also check for
843 // direct RegisterSDNode operands.
844 for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
845 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
846 unsigned Reg = R->getReg();
847 if (TargetRegisterInfo::isPhysicalRegister(Reg))
848 UsedRegs.push_back(Reg);
849 }
850 }
851 }
852
853 // Finally mark unused registers as dead.
854 if (!UsedRegs.empty() || II.getImplicitDefs())
855 MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
856
857 // Run post-isel target hook to adjust this instruction if needed.
858#ifdef NDEBUG
859 if (II.hasPostISelHook())
860#endif
861 TLI->AdjustInstrPostInstrSelection(MIB, Node);
862}
863
864/// EmitSpecialNode - Generate machine code for a target-independent node and
865/// needed dependencies.
866void InstrEmitter::
867EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
868 DenseMap<SDValue, unsigned> &VRBaseMap) {
869 switch (Node->getOpcode()) {
870 default:
871#ifndef NDEBUG
872 Node->dump();
873#endif
874 llvm_unreachable("This target-independent node should have been selected!");
875 case ISD::EntryToken:
876 llvm_unreachable("EntryToken should have been excluded from the schedule!");
877 case ISD::MERGE_VALUES:
878 case ISD::TokenFactor: // fall thru
879 break;
880 case ISD::CopyToReg: {
881 unsigned SrcReg;
882 SDValue SrcVal = Node->getOperand(2);
883 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
884 SrcReg = R->getReg();
885 else
886 SrcReg = getVR(SrcVal, VRBaseMap);
887
888 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
889 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
890 break;
891
892 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
893 DestReg).addReg(SrcReg);
894 break;
895 }
896 case ISD::CopyFromReg: {
897 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
898 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
899 break;
900 }
901 case ISD::EH_LABEL: {
902 MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel();
903 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
904 TII->get(TargetOpcode::EH_LABEL)).addSym(S);
905 break;
906 }
907
908 case ISD::LIFETIME_START:
909 case ISD::LIFETIME_END: {
910 unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ?
911 TargetOpcode::LIFETIME_START : TargetOpcode::LIFETIME_END;
912
913 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Node->getOperand(1));
914 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
915 .addFrameIndex(FI->getIndex());
916 break;
917 }
918
919 case ISD::INLINEASM: {
920 unsigned NumOps = Node->getNumOperands();
921 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
922 --NumOps; // Ignore the glue operand.
923
924 // Create the inline asm machine instruction.
925 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(),
926 TII->get(TargetOpcode::INLINEASM));
927
928 // Add the asm string as an external symbol operand.
929 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
930 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
931 MIB.addExternalSymbol(AsmStr);
932
933 // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
934 // bits.
935 int64_t ExtraInfo =
936 cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
937 getZExtValue();
938 MIB.addImm(ExtraInfo);
939
940 // Remember to operand index of the group flags.
941 SmallVector<unsigned, 8> GroupIdx;
942
943 // Add all of the operand registers to the instruction.
944 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
945 unsigned Flags =
946 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
947 const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
948
949 GroupIdx.push_back(MIB->getNumOperands());
950 MIB.addImm(Flags);
951 ++i; // Skip the ID value.
952
953 switch (InlineAsm::getKind(Flags)) {
954 default: llvm_unreachable("Bad flags!");
955 case InlineAsm::Kind_RegDef:
956 for (unsigned j = 0; j != NumVals; ++j, ++i) {
957 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
958 // FIXME: Add dead flags for physical and virtual registers defined.
959 // For now, mark physical register defs as implicit to help fast
960 // regalloc. This makes inline asm look a lot like calls.
961 MIB.addReg(Reg, RegState::Define |
962 getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg)));
963 }
964 break;
965 case InlineAsm::Kind_RegDefEarlyClobber:
966 case InlineAsm::Kind_Clobber:
967 for (unsigned j = 0; j != NumVals; ++j, ++i) {
968 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
969 MIB.addReg(Reg, RegState::Define | RegState::EarlyClobber |
970 getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg)));
971 }
972 break;
973 case InlineAsm::Kind_RegUse: // Use of register.
974 case InlineAsm::Kind_Imm: // Immediate.
975 case InlineAsm::Kind_Mem: // Addressing mode.
976 // The addressing mode has been selected, just add all of the
977 // operands to the machine instruction.
978 for (unsigned j = 0; j != NumVals; ++j, ++i)
979 AddOperand(MIB, Node->getOperand(i), 0, 0, VRBaseMap,
980 /*IsDebug=*/false, IsClone, IsCloned);
981
982 // Manually set isTied bits.
983 if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) {
984 unsigned DefGroup = 0;
985 if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
986 unsigned DefIdx = GroupIdx[DefGroup] + 1;
987 unsigned UseIdx = GroupIdx.back() + 1;
988 for (unsigned j = 0; j != NumVals; ++j)
989 MIB->tieOperands(DefIdx + j, UseIdx + j);
990 }
991 }
992 break;
993 }
994 }
995
996 // Get the mdnode from the asm if it exists and add it to the instruction.
997 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
998 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
999 if (MD)
1000 MIB.addMetadata(MD);
1001
1002 MBB->insert(InsertPos, MIB);
1003 break;
1004 }
1005 }
1006}
1007
1008/// InstrEmitter - Construct an InstrEmitter and set it to start inserting
1009/// at the given position in the given block.
1010InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
1011 MachineBasicBlock::iterator insertpos)
1012 : MF(mbb->getParent()),
1013 MRI(&MF->getRegInfo()),
1014 TM(&MF->getTarget()),
1015 TII(TM->getInstrInfo()),
1016 TRI(TM->getRegisterInfo()),
1017 TLI(TM->getTargetLowering()),
1018 MBB(mbb), InsertPos(insertpos) {
1019}