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< struct MachineVerifier : public MachineFunctionPass {
< static char ID; // Pass ID, replacement for typeid
---
> struct MachineVerifier {
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< MachineVerifier(bool allowDoubleDefs = false) :
< MachineFunctionPass(&ID),
---
> MachineVerifier(Pass *pass, bool allowDoubleDefs) :
> PASS(pass),
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< {}
---
> {}
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< void getAnalysisUsage(AnalysisUsage &AU) const {
< AU.setPreservesAll();
< MachineFunctionPass::getAnalysisUsage(AU);
< }
<
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> Pass *const PASS;
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> // Vregs that must pass through MBB because they are needed by a successor
> // block. This set is disjoint from regsLiveOut.
> RegSet vregsRequired;
>
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> // Add register to vregsRequired if it belongs there. Return true if
> // anything changed.
> bool addRequired(unsigned Reg) {
> if (!TargetRegisterInfo::isVirtualRegister(Reg))
> return false;
> if (regsLiveOut.count(Reg))
> return false;
> return vregsRequired.insert(Reg).second;
> }
>
> // Same for a full set.
> bool addRequired(const RegSet &RS) {
> bool changed = false;
> for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
> if (addRequired(*I))
> changed = true;
> return changed;
> }
>
> // Same for a full map.
> bool addRequired(const RegMap &RM) {
> bool changed = false;
> for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
> if (addRequired(I->first))
> changed = true;
> return changed;
> }
>
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> // Analysis information if available
> LiveVariables *LiveVars;
>
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>
> void calcRegsRequired();
> void verifyLiveVariables();
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>
> struct MachineVerifierPass : public MachineFunctionPass {
> static char ID; // Pass ID, replacement for typeid
> bool AllowDoubleDefs;
>
> explicit MachineVerifierPass(bool allowDoubleDefs = false)
> : MachineFunctionPass(&ID),
> AllowDoubleDefs(allowDoubleDefs) {}
>
> void getAnalysisUsage(AnalysisUsage &AU) const {
> AU.setPreservesAll();
> MachineFunctionPass::getAnalysisUsage(AU);
> }
>
> bool runOnMachineFunction(MachineFunction &MF) {
> MF.verify(this, AllowDoubleDefs);
> return false;
> }
> };
>
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< char MachineVerifier::ID = 0;
< static RegisterPass<MachineVerifier>
---
> char MachineVerifierPass::ID = 0;
> static RegisterPass<MachineVerifierPass>
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< return new MachineVerifier(allowPhysDoubleDefs);
---
> return new MachineVerifierPass(allowPhysDoubleDefs);
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< void MachineFunction::verify() const {
< MachineVerifier().runOnMachineFunction(const_cast<MachineFunction&>(*this));
---
> void MachineFunction::verify(Pass *p, bool allowDoubleDefs) const {
> MachineVerifier(p, allowDoubleDefs)
> .runOnMachineFunction(const_cast<MachineFunction&>(*this));
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> if (PASS) {
> LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
> } else {
> LiveVars = NULL;
> }
>
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> bool isKill = false;
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< addRegWithSubRegs(regsKilled, Reg);
---
> isKill = true;
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< addRegWithSubRegs(regsKilled, Reg);
---
> isKill = true;
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> if (isKill) {
> addRegWithSubRegs(regsKilled, Reg);
>
> // Check that LiveVars knows this kill
> if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg)) {
> LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
> if (std::find(VI.Kills.begin(),
> VI.Kills.end(), MI) == VI.Kills.end())
> report("Kill missing from LiveVariables", MO, MONum);
> }
> }
>
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> // Calculate the set of virtual registers that must be passed through each basic
> // block in order to satisfy the requirements of successor blocks. This is very
> // similar to calcMaxRegsPassed, only backwards.
> void MachineVerifier::calcRegsRequired() {
> // First push live-in regs to predecessors' vregsRequired.
> DenseSet<const MachineBasicBlock*> todo;
> for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
> MFI != MFE; ++MFI) {
> const MachineBasicBlock &MBB(*MFI);
> BBInfo &MInfo = MBBInfoMap[&MBB];
> for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
> PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
> BBInfo &PInfo = MBBInfoMap[*PrI];
> if (PInfo.addRequired(MInfo.vregsLiveIn))
> todo.insert(*PrI);
> }
> }
>
> // Iteratively push vregsRequired to predecessors. This will converge to the
> // same final state regardless of DenseSet iteration order.
> while (!todo.empty()) {
> const MachineBasicBlock *MBB = *todo.begin();
> todo.erase(MBB);
> BBInfo &MInfo = MBBInfoMap[MBB];
> for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
> PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
> if (*PrI == MBB)
> continue;
> BBInfo &SInfo = MBBInfoMap[*PrI];
> if (SInfo.addRequired(MInfo.vregsRequired))
> todo.insert(*PrI);
> }
> }
> }
>
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>
> // Now check LiveVariables info if available
> if (LiveVars) {
> calcRegsRequired();
> verifyLiveVariables();
> }
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>
> void MachineVerifier::verifyLiveVariables() {
> assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
> for (unsigned Reg = TargetRegisterInfo::FirstVirtualRegister,
> RegE = MRI->getLastVirtReg()-1; Reg != RegE; ++Reg) {
> LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
> for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
> MFI != MFE; ++MFI) {
> BBInfo &MInfo = MBBInfoMap[MFI];
>
> // Our vregsRequired should be identical to LiveVariables' AliveBlocks
> if (MInfo.vregsRequired.count(Reg)) {
> if (!VI.AliveBlocks.test(MFI->getNumber())) {
> report("LiveVariables: Block missing from AliveBlocks", MFI);
> *OS << "Virtual register %reg" << Reg
> << " must be live through the block.\n";
> }
> } else {
> if (VI.AliveBlocks.test(MFI->getNumber())) {
> report("LiveVariables: Block should not be in AliveBlocks", MFI);
> *OS << "Virtual register %reg" << Reg
> << " is not needed live through the block.\n";
> }
> }
> }
> }
> }
>
>