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reload.c (146906) reload.c (169699)
1/* Search an insn for pseudo regs that must be in hard regs and are not.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
1/* Search an insn for pseudo regs that must be in hard regs and are not.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation,
4 Inc.
4
5This file is part of GCC.
6
7GCC is free software; you can redistribute it and/or modify it under
8the terms of the GNU General Public License as published by the Free
9Software Foundation; either version 2, or (at your option) any later
10version.
11
12GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13WARRANTY; without even the implied warranty of MERCHANTABILITY or
14FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15for more details.
16
17You should have received a copy of the GNU General Public License
18along with GCC; see the file COPYING. If not, write to the Free
5
6This file is part of GCC.
7
8GCC is free software; you can redistribute it and/or modify it under
9the terms of the GNU General Public License as published by the Free
10Software Foundation; either version 2, or (at your option) any later
11version.
12
13GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14WARRANTY; without even the implied warranty of MERCHANTABILITY or
15FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16for more details.
17
18You should have received a copy of the GNU General Public License
19along with GCC; see the file COPYING. If not, write to the Free
19Software Foundation, 59 Temple Place - Suite 330, Boston, MA
2002111-1307, USA. */
20Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
2102110-1301, USA. */
21
22/* This file contains subroutines used only from the file reload1.c.
23 It knows how to scan one insn for operands and values
24 that need to be copied into registers to make valid code.
25 It also finds other operands and values which are valid
26 but for which equivalent values in registers exist and
27 ought to be used instead.
28
29 Before processing the first insn of the function, call `init_reload'.
22
23/* This file contains subroutines used only from the file reload1.c.
24 It knows how to scan one insn for operands and values
25 that need to be copied into registers to make valid code.
26 It also finds other operands and values which are valid
27 but for which equivalent values in registers exist and
28 ought to be used instead.
29
30 Before processing the first insn of the function, call `init_reload'.
31 init_reload actually has to be called earlier anyway.
30
31 To scan an insn, call `find_reloads'. This does two things:
32 1. sets up tables describing which values must be reloaded
33 for this insn, and what kind of hard regs they must be reloaded into;
34 2. optionally record the locations where those values appear in
35 the data, so they can be replaced properly later.
36 This is done only if the second arg to `find_reloads' is nonzero.
37

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93#include "rtl.h"
94#include "tm_p.h"
95#include "insn-config.h"
96#include "expr.h"
97#include "optabs.h"
98#include "recog.h"
99#include "reload.h"
100#include "regs.h"
32
33 To scan an insn, call `find_reloads'. This does two things:
34 1. sets up tables describing which values must be reloaded
35 for this insn, and what kind of hard regs they must be reloaded into;
36 2. optionally record the locations where those values appear in
37 the data, so they can be replaced properly later.
38 This is done only if the second arg to `find_reloads' is nonzero.
39

--- 55 unchanged lines hidden (view full) ---

95#include "rtl.h"
96#include "tm_p.h"
97#include "insn-config.h"
98#include "expr.h"
99#include "optabs.h"
100#include "recog.h"
101#include "reload.h"
102#include "regs.h"
103#include "addresses.h"
101#include "hard-reg-set.h"
102#include "flags.h"
103#include "real.h"
104#include "output.h"
105#include "function.h"
106#include "toplev.h"
107#include "params.h"
104#include "hard-reg-set.h"
105#include "flags.h"
106#include "real.h"
107#include "output.h"
108#include "function.h"
109#include "toplev.h"
110#include "params.h"
111#include "target.h"
108
112
109#ifndef REGNO_MODE_OK_FOR_BASE_P
110#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) REGNO_OK_FOR_BASE_P (REGNO)
111#endif
113/* True if X is a constant that can be forced into the constant pool. */
114#define CONST_POOL_OK_P(X) \
115 (CONSTANT_P (X) \
116 && GET_CODE (X) != HIGH \
117 && !targetm.cannot_force_const_mem (X))
112
118
113#ifndef REG_MODE_OK_FOR_BASE_P
114#define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
115#endif
119/* True if C is a non-empty register class that has too few registers
120 to be safely used as a reload target class. */
121#define SMALL_REGISTER_CLASS_P(C) \
122 (reg_class_size [(C)] == 1 \
123 || (reg_class_size [(C)] >= 1 && CLASS_LIKELY_SPILLED_P (C)))
124
116
117/* All reloads of the current insn are recorded here. See reload.h for
118 comments. */
119int n_reloads;
120struct reload rld[MAX_RELOADS];
121
122/* All the "earlyclobber" operands of the current insn
123 are recorded here. */

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198static int subst_reg_equivs_changed;
199
200/* On return from push_reload, holds the reload-number for the OUT
201 operand, which can be different for that from the input operand. */
202static int output_reloadnum;
203
204 /* Compare two RTX's. */
205#define MATCHES(x, y) \
125
126/* All reloads of the current insn are recorded here. See reload.h for
127 comments. */
128int n_reloads;
129struct reload rld[MAX_RELOADS];
130
131/* All the "earlyclobber" operands of the current insn
132 are recorded here. */

--- 74 unchanged lines hidden (view full) ---

207static int subst_reg_equivs_changed;
208
209/* On return from push_reload, holds the reload-number for the OUT
210 operand, which can be different for that from the input operand. */
211static int output_reloadnum;
212
213 /* Compare two RTX's. */
214#define MATCHES(x, y) \
206 (x == y || (x != 0 && (GET_CODE (x) == REG \
207 ? GET_CODE (y) == REG && REGNO (x) == REGNO (y) \
215 (x == y || (x != 0 && (REG_P (x) \
216 ? REG_P (y) && REGNO (x) == REGNO (y) \
208 : rtx_equal_p (x, y) && ! side_effects_p (x))))
209
210 /* Indicates if two reloads purposes are for similar enough things that we
211 can merge their reloads. */
212#define MERGABLE_RELOADS(when1, when2, op1, op2) \
213 ((when1) == RELOAD_OTHER || (when2) == RELOAD_OTHER \
214 || ((when1) == (when2) && (op1) == (op2)) \
215 || ((when1) == RELOAD_FOR_INPUT && (when2) == RELOAD_FOR_INPUT) \

--- 14 unchanged lines hidden (view full) ---

230 use. */
231#define ADDR_TYPE(type) \
232 ((type) == RELOAD_FOR_INPUT_ADDRESS \
233 ? RELOAD_FOR_INPADDR_ADDRESS \
234 : ((type) == RELOAD_FOR_OUTPUT_ADDRESS \
235 ? RELOAD_FOR_OUTADDR_ADDRESS \
236 : (type)))
237
217 : rtx_equal_p (x, y) && ! side_effects_p (x))))
218
219 /* Indicates if two reloads purposes are for similar enough things that we
220 can merge their reloads. */
221#define MERGABLE_RELOADS(when1, when2, op1, op2) \
222 ((when1) == RELOAD_OTHER || (when2) == RELOAD_OTHER \
223 || ((when1) == (when2) && (op1) == (op2)) \
224 || ((when1) == RELOAD_FOR_INPUT && (when2) == RELOAD_FOR_INPUT) \

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239 use. */
240#define ADDR_TYPE(type) \
241 ((type) == RELOAD_FOR_INPUT_ADDRESS \
242 ? RELOAD_FOR_INPADDR_ADDRESS \
243 : ((type) == RELOAD_FOR_OUTPUT_ADDRESS \
244 ? RELOAD_FOR_OUTADDR_ADDRESS \
245 : (type)))
246
238#ifdef HAVE_SECONDARY_RELOADS
239static int push_secondary_reload (int, rtx, int, int, enum reg_class,
240 enum machine_mode, enum reload_type,
247static int push_secondary_reload (int, rtx, int, int, enum reg_class,
248 enum machine_mode, enum reload_type,
241 enum insn_code *);
242#endif
243static enum reg_class find_valid_class (enum machine_mode, int, unsigned int);
249 enum insn_code *, secondary_reload_info *);
250static enum reg_class find_valid_class (enum machine_mode, enum machine_mode,
251 int, unsigned int);
244static int reload_inner_reg_of_subreg (rtx, enum machine_mode, int);
245static void push_replacement (rtx *, int, enum machine_mode);
246static void dup_replacements (rtx *, rtx *);
247static void combine_reloads (void);
248static int find_reusable_reload (rtx *, rtx, enum reg_class,
249 enum reload_type, int, int);
250static rtx find_dummy_reload (rtx, rtx, rtx *, rtx *, enum machine_mode,
251 enum machine_mode, enum reg_class, int, int);

--- 5 unchanged lines hidden (view full) ---

257 int *);
258static rtx make_memloc (rtx, int);
259static int maybe_memory_address_p (enum machine_mode, rtx, rtx *);
260static int find_reloads_address (enum machine_mode, rtx *, rtx, rtx *,
261 int, enum reload_type, int, rtx);
262static rtx subst_reg_equivs (rtx, rtx);
263static rtx subst_indexed_address (rtx);
264static void update_auto_inc_notes (rtx, int, int);
252static int reload_inner_reg_of_subreg (rtx, enum machine_mode, int);
253static void push_replacement (rtx *, int, enum machine_mode);
254static void dup_replacements (rtx *, rtx *);
255static void combine_reloads (void);
256static int find_reusable_reload (rtx *, rtx, enum reg_class,
257 enum reload_type, int, int);
258static rtx find_dummy_reload (rtx, rtx, rtx *, rtx *, enum machine_mode,
259 enum machine_mode, enum reg_class, int, int);

--- 5 unchanged lines hidden (view full) ---

265 int *);
266static rtx make_memloc (rtx, int);
267static int maybe_memory_address_p (enum machine_mode, rtx, rtx *);
268static int find_reloads_address (enum machine_mode, rtx *, rtx, rtx *,
269 int, enum reload_type, int, rtx);
270static rtx subst_reg_equivs (rtx, rtx);
271static rtx subst_indexed_address (rtx);
272static void update_auto_inc_notes (rtx, int, int);
265static int find_reloads_address_1 (enum machine_mode, rtx, int, rtx *,
273static int find_reloads_address_1 (enum machine_mode, rtx, int,
274 enum rtx_code, enum rtx_code, rtx *,
266 int, enum reload_type,int, rtx);
267static void find_reloads_address_part (rtx, rtx *, enum reg_class,
268 enum machine_mode, int,
269 enum reload_type, int);
270static rtx find_reloads_subreg_address (rtx, int, int, enum reload_type,
271 int, rtx);
272static void copy_replacements_1 (rtx *, rtx *, int);
273static int find_inc_amount (rtx, rtx);
275 int, enum reload_type,int, rtx);
276static void find_reloads_address_part (rtx, rtx *, enum reg_class,
277 enum machine_mode, int,
278 enum reload_type, int);
279static rtx find_reloads_subreg_address (rtx, int, int, enum reload_type,
280 int, rtx);
281static void copy_replacements_1 (rtx *, rtx *, int);
282static int find_inc_amount (rtx, rtx);
274
275#ifdef HAVE_SECONDARY_RELOADS
283static int refers_to_mem_for_reload_p (rtx);
284static int refers_to_regno_for_reload_p (unsigned int, unsigned int,
285 rtx, rtx *);
276
286
287/* Add NEW to reg_equiv_alt_mem_list[REGNO] if it's not present in the
288 list yet. */
289
290static void
291push_reg_equiv_alt_mem (int regno, rtx mem)
292{
293 rtx it;
294
295 for (it = reg_equiv_alt_mem_list [regno]; it; it = XEXP (it, 1))
296 if (rtx_equal_p (XEXP (it, 0), mem))
297 return;
298
299 reg_equiv_alt_mem_list [regno]
300 = alloc_EXPR_LIST (REG_EQUIV, mem,
301 reg_equiv_alt_mem_list [regno]);
302}
303
277/* Determine if any secondary reloads are needed for loading (if IN_P is
278 nonzero) or storing (if IN_P is zero) X to or from a reload register of
279 register class RELOAD_CLASS in mode RELOAD_MODE. If secondary reloads
280 are needed, push them.
281
282 Return the reload number of the secondary reload we made, or -1 if
283 we didn't need one. *PICODE is set to the insn_code to use if we do
284 need a secondary reload. */
285
286static int
287push_secondary_reload (int in_p, rtx x, int opnum, int optional,
288 enum reg_class reload_class,
289 enum machine_mode reload_mode, enum reload_type type,
304/* Determine if any secondary reloads are needed for loading (if IN_P is
305 nonzero) or storing (if IN_P is zero) X to or from a reload register of
306 register class RELOAD_CLASS in mode RELOAD_MODE. If secondary reloads
307 are needed, push them.
308
309 Return the reload number of the secondary reload we made, or -1 if
310 we didn't need one. *PICODE is set to the insn_code to use if we do
311 need a secondary reload. */
312
313static int
314push_secondary_reload (int in_p, rtx x, int opnum, int optional,
315 enum reg_class reload_class,
316 enum machine_mode reload_mode, enum reload_type type,
290 enum insn_code *picode)
317 enum insn_code *picode, secondary_reload_info *prev_sri)
291{
292 enum reg_class class = NO_REGS;
318{
319 enum reg_class class = NO_REGS;
320 enum reg_class scratch_class;
293 enum machine_mode mode = reload_mode;
294 enum insn_code icode = CODE_FOR_nothing;
321 enum machine_mode mode = reload_mode;
322 enum insn_code icode = CODE_FOR_nothing;
295 enum reg_class t_class = NO_REGS;
296 enum machine_mode t_mode = VOIDmode;
297 enum insn_code t_icode = CODE_FOR_nothing;
298 enum reload_type secondary_type;
299 int s_reload, t_reload = -1;
323 enum insn_code t_icode = CODE_FOR_nothing;
324 enum reload_type secondary_type;
325 int s_reload, t_reload = -1;
326 const char *scratch_constraint;
327 char letter;
328 secondary_reload_info sri;
300
301 if (type == RELOAD_FOR_INPUT_ADDRESS
302 || type == RELOAD_FOR_OUTPUT_ADDRESS
303 || type == RELOAD_FOR_INPADDR_ADDRESS
304 || type == RELOAD_FOR_OUTADDR_ADDRESS)
305 secondary_type = type;
306 else
307 secondary_type = in_p ? RELOAD_FOR_INPUT_ADDRESS : RELOAD_FOR_OUTPUT_ADDRESS;

--- 11 unchanged lines hidden (view full) ---

319 }
320
321 /* If X is a pseudo-register that has an equivalent MEM (actually, if it
322 is still a pseudo-register by now, it *must* have an equivalent MEM
323 but we don't want to assume that), use that equivalent when seeing if
324 a secondary reload is needed since whether or not a reload is needed
325 might be sensitive to the form of the MEM. */
326
329
330 if (type == RELOAD_FOR_INPUT_ADDRESS
331 || type == RELOAD_FOR_OUTPUT_ADDRESS
332 || type == RELOAD_FOR_INPADDR_ADDRESS
333 || type == RELOAD_FOR_OUTADDR_ADDRESS)
334 secondary_type = type;
335 else
336 secondary_type = in_p ? RELOAD_FOR_INPUT_ADDRESS : RELOAD_FOR_OUTPUT_ADDRESS;

--- 11 unchanged lines hidden (view full) ---

348 }
349
350 /* If X is a pseudo-register that has an equivalent MEM (actually, if it
351 is still a pseudo-register by now, it *must* have an equivalent MEM
352 but we don't want to assume that), use that equivalent when seeing if
353 a secondary reload is needed since whether or not a reload is needed
354 might be sensitive to the form of the MEM. */
355
327 if (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER
356 if (REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER
328 && reg_equiv_mem[REGNO (x)] != 0)
329 x = reg_equiv_mem[REGNO (x)];
330
357 && reg_equiv_mem[REGNO (x)] != 0)
358 x = reg_equiv_mem[REGNO (x)];
359
331#ifdef SECONDARY_INPUT_RELOAD_CLASS
332 if (in_p)
333 class = SECONDARY_INPUT_RELOAD_CLASS (reload_class, reload_mode, x);
334#endif
360 sri.icode = CODE_FOR_nothing;
361 sri.prev_sri = prev_sri;
362 class = targetm.secondary_reload (in_p, x, reload_class, reload_mode, &sri);
363 icode = sri.icode;
335
364
336#ifdef SECONDARY_OUTPUT_RELOAD_CLASS
337 if (! in_p)
338 class = SECONDARY_OUTPUT_RELOAD_CLASS (reload_class, reload_mode, x);
339#endif
340
341 /* If we don't need any secondary registers, done. */
365 /* If we don't need any secondary registers, done. */
342 if (class == NO_REGS)
366 if (class == NO_REGS && icode == CODE_FOR_nothing)
343 return -1;
344
367 return -1;
368
345 /* Get a possible insn to use. If the predicate doesn't accept X, don't
346 use the insn. */
369 if (class != NO_REGS)
370 t_reload = push_secondary_reload (in_p, x, opnum, optional, class,
371 reload_mode, type, &t_icode, &sri);
347
372
348 icode = (in_p ? reload_in_optab[(int) reload_mode]
349 : reload_out_optab[(int) reload_mode]);
373 /* If we will be using an insn, the secondary reload is for a
374 scratch register. */
350
375
351 if (icode != CODE_FOR_nothing
352 && insn_data[(int) icode].operand[in_p].predicate
353 && (! (insn_data[(int) icode].operand[in_p].predicate) (x, reload_mode)))
354 icode = CODE_FOR_nothing;
355
356 /* If we will be using an insn, see if it can directly handle the reload
357 register we will be using. If it can, the secondary reload is for a
358 scratch register. If it can't, we will use the secondary reload for
359 an intermediate register and require a tertiary reload for the scratch
360 register. */
361
362 if (icode != CODE_FOR_nothing)
363 {
364 /* If IN_P is nonzero, the reload register will be the output in
365 operand 0. If IN_P is zero, the reload register will be the input
366 in operand 1. Outputs should have an initial "=", which we must
367 skip. */
368
376 if (icode != CODE_FOR_nothing)
377 {
378 /* If IN_P is nonzero, the reload register will be the output in
379 operand 0. If IN_P is zero, the reload register will be the input
380 in operand 1. Outputs should have an initial "=", which we must
381 skip. */
382
369 enum reg_class insn_class;
383 /* ??? It would be useful to be able to handle only two, or more than
384 three, operands, but for now we can only handle the case of having
385 exactly three: output, input and one temp/scratch. */
386 gcc_assert (insn_data[(int) icode].n_operands == 3);
370
387
371 if (insn_data[(int) icode].operand[!in_p].constraint[0] == 0)
372 insn_class = ALL_REGS;
373 else
374 {
375 const char *insn_constraint
376 = &insn_data[(int) icode].operand[!in_p].constraint[in_p];
377 char insn_letter = *insn_constraint;
378 insn_class
379 = (insn_letter == 'r' ? GENERAL_REGS
380 : REG_CLASS_FROM_CONSTRAINT ((unsigned char) insn_letter,
381 insn_constraint));
388 /* ??? We currently have no way to represent a reload that needs
389 an icode to reload from an intermediate tertiary reload register.
390 We should probably have a new field in struct reload to tag a
391 chain of scratch operand reloads onto. */
392 gcc_assert (class == NO_REGS);
382
393
383 if (insn_class == NO_REGS)
384 abort ();
385 if (in_p
386 && insn_data[(int) icode].operand[!in_p].constraint[0] != '=')
387 abort ();
388 }
394 scratch_constraint = insn_data[(int) icode].operand[2].constraint;
395 gcc_assert (*scratch_constraint == '=');
396 scratch_constraint++;
397 if (*scratch_constraint == '&')
398 scratch_constraint++;
399 letter = *scratch_constraint;
400 scratch_class = (letter == 'r' ? GENERAL_REGS
401 : REG_CLASS_FROM_CONSTRAINT ((unsigned char) letter,
402 scratch_constraint));
389
403
390 /* The scratch register's constraint must start with "=&". */
391 if (insn_data[(int) icode].operand[2].constraint[0] != '='
392 || insn_data[(int) icode].operand[2].constraint[1] != '&')
393 abort ();
394
395 if (reg_class_subset_p (reload_class, insn_class))
396 mode = insn_data[(int) icode].operand[2].mode;
397 else
398 {
399 const char *t_constraint
400 = &insn_data[(int) icode].operand[2].constraint[2];
401 char t_letter = *t_constraint;
402 class = insn_class;
403 t_mode = insn_data[(int) icode].operand[2].mode;
404 t_class = (t_letter == 'r' ? GENERAL_REGS
405 : REG_CLASS_FROM_CONSTRAINT ((unsigned char) t_letter,
406 t_constraint));
407 t_icode = icode;
408 icode = CODE_FOR_nothing;
409 }
404 class = scratch_class;
405 mode = insn_data[(int) icode].operand[2].mode;
410 }
411
412 /* This case isn't valid, so fail. Reload is allowed to use the same
413 register for RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT reloads, but
414 in the case of a secondary register, we actually need two different
415 registers for correct code. We fail here to prevent the possibility of
416 silently generating incorrect code later.
417
418 The convention is that secondary input reloads are valid only if the
419 secondary_class is different from class. If you have such a case, you
420 can not use secondary reloads, you must work around the problem some
421 other way.
422
423 Allow this when a reload_in/out pattern is being used. I.e. assume
424 that the generated code handles this case. */
425
406 }
407
408 /* This case isn't valid, so fail. Reload is allowed to use the same
409 register for RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT reloads, but
410 in the case of a secondary register, we actually need two different
411 registers for correct code. We fail here to prevent the possibility of
412 silently generating incorrect code later.
413
414 The convention is that secondary input reloads are valid only if the
415 secondary_class is different from class. If you have such a case, you
416 can not use secondary reloads, you must work around the problem some
417 other way.
418
419 Allow this when a reload_in/out pattern is being used. I.e. assume
420 that the generated code handles this case. */
421
426 if (in_p && class == reload_class && icode == CODE_FOR_nothing
427 && t_icode == CODE_FOR_nothing)
428 abort ();
422 gcc_assert (!in_p || class != reload_class || icode != CODE_FOR_nothing
423 || t_icode != CODE_FOR_nothing);
429
424
430 /* If we need a tertiary reload, see if we have one we can reuse or else
431 make a new one. */
432
433 if (t_class != NO_REGS)
434 {
435 for (t_reload = 0; t_reload < n_reloads; t_reload++)
436 if (rld[t_reload].secondary_p
437 && (reg_class_subset_p (t_class, rld[t_reload].class)
438 || reg_class_subset_p (rld[t_reload].class, t_class))
439 && ((in_p && rld[t_reload].inmode == t_mode)
440 || (! in_p && rld[t_reload].outmode == t_mode))
441 && ((in_p && (rld[t_reload].secondary_in_icode
442 == CODE_FOR_nothing))
443 || (! in_p &&(rld[t_reload].secondary_out_icode
444 == CODE_FOR_nothing)))
445 && (reg_class_size[(int) t_class] == 1 || SMALL_REGISTER_CLASSES)
446 && MERGABLE_RELOADS (secondary_type,
447 rld[t_reload].when_needed,
448 opnum, rld[t_reload].opnum))
449 {
450 if (in_p)
451 rld[t_reload].inmode = t_mode;
452 if (! in_p)
453 rld[t_reload].outmode = t_mode;
454
455 if (reg_class_subset_p (t_class, rld[t_reload].class))
456 rld[t_reload].class = t_class;
457
458 rld[t_reload].opnum = MIN (rld[t_reload].opnum, opnum);
459 rld[t_reload].optional &= optional;
460 rld[t_reload].secondary_p = 1;
461 if (MERGE_TO_OTHER (secondary_type, rld[t_reload].when_needed,
462 opnum, rld[t_reload].opnum))
463 rld[t_reload].when_needed = RELOAD_OTHER;
464 }
465
466 if (t_reload == n_reloads)
467 {
468 /* We need to make a new tertiary reload for this register class. */
469 rld[t_reload].in = rld[t_reload].out = 0;
470 rld[t_reload].class = t_class;
471 rld[t_reload].inmode = in_p ? t_mode : VOIDmode;
472 rld[t_reload].outmode = ! in_p ? t_mode : VOIDmode;
473 rld[t_reload].reg_rtx = 0;
474 rld[t_reload].optional = optional;
475 rld[t_reload].inc = 0;
476 /* Maybe we could combine these, but it seems too tricky. */
477 rld[t_reload].nocombine = 1;
478 rld[t_reload].in_reg = 0;
479 rld[t_reload].out_reg = 0;
480 rld[t_reload].opnum = opnum;
481 rld[t_reload].when_needed = secondary_type;
482 rld[t_reload].secondary_in_reload = -1;
483 rld[t_reload].secondary_out_reload = -1;
484 rld[t_reload].secondary_in_icode = CODE_FOR_nothing;
485 rld[t_reload].secondary_out_icode = CODE_FOR_nothing;
486 rld[t_reload].secondary_p = 1;
487
488 n_reloads++;
489 }
490 }
491
492 /* See if we can reuse an existing secondary reload. */
493 for (s_reload = 0; s_reload < n_reloads; s_reload++)
494 if (rld[s_reload].secondary_p
495 && (reg_class_subset_p (class, rld[s_reload].class)
496 || reg_class_subset_p (rld[s_reload].class, class))
497 && ((in_p && rld[s_reload].inmode == mode)
498 || (! in_p && rld[s_reload].outmode == mode))
499 && ((in_p && rld[s_reload].secondary_in_reload == t_reload)
500 || (! in_p && rld[s_reload].secondary_out_reload == t_reload))
501 && ((in_p && rld[s_reload].secondary_in_icode == t_icode)
502 || (! in_p && rld[s_reload].secondary_out_icode == t_icode))
425 /* See if we can reuse an existing secondary reload. */
426 for (s_reload = 0; s_reload < n_reloads; s_reload++)
427 if (rld[s_reload].secondary_p
428 && (reg_class_subset_p (class, rld[s_reload].class)
429 || reg_class_subset_p (rld[s_reload].class, class))
430 && ((in_p && rld[s_reload].inmode == mode)
431 || (! in_p && rld[s_reload].outmode == mode))
432 && ((in_p && rld[s_reload].secondary_in_reload == t_reload)
433 || (! in_p && rld[s_reload].secondary_out_reload == t_reload))
434 && ((in_p && rld[s_reload].secondary_in_icode == t_icode)
435 || (! in_p && rld[s_reload].secondary_out_icode == t_icode))
503 && (reg_class_size[(int) class] == 1 || SMALL_REGISTER_CLASSES)
436 && (SMALL_REGISTER_CLASS_P (class) || SMALL_REGISTER_CLASSES)
504 && MERGABLE_RELOADS (secondary_type, rld[s_reload].when_needed,
505 opnum, rld[s_reload].opnum))
506 {
507 if (in_p)
508 rld[s_reload].inmode = mode;
509 if (! in_p)
510 rld[s_reload].outmode = mode;
511

--- 56 unchanged lines hidden (view full) ---

568 && SECONDARY_MEMORY_NEEDED (reload_class, class, mode))
569 get_secondary_mem (x, mode, opnum, type);
570#endif
571 }
572
573 *picode = icode;
574 return s_reload;
575}
437 && MERGABLE_RELOADS (secondary_type, rld[s_reload].when_needed,
438 opnum, rld[s_reload].opnum))
439 {
440 if (in_p)
441 rld[s_reload].inmode = mode;
442 if (! in_p)
443 rld[s_reload].outmode = mode;
444

--- 56 unchanged lines hidden (view full) ---

501 && SECONDARY_MEMORY_NEEDED (reload_class, class, mode))
502 get_secondary_mem (x, mode, opnum, type);
503#endif
504 }
505
506 *picode = icode;
507 return s_reload;
508}
576#endif /* HAVE_SECONDARY_RELOADS */
509
510/* If a secondary reload is needed, return its class. If both an intermediate
511 register and a scratch register is needed, we return the class of the
512 intermediate register. */
513enum reg_class
514secondary_reload_class (bool in_p, enum reg_class class,
515 enum machine_mode mode, rtx x)
516{
517 enum insn_code icode;
518 secondary_reload_info sri;
519
520 sri.icode = CODE_FOR_nothing;
521 sri.prev_sri = NULL;
522 class = targetm.secondary_reload (in_p, x, class, mode, &sri);
523 icode = sri.icode;
524
525 /* If there are no secondary reloads at all, we return NO_REGS.
526 If an intermediate register is needed, we return its class. */
527 if (icode == CODE_FOR_nothing || class != NO_REGS)
528 return class;
529
530 /* No intermediate register is needed, but we have a special reload
531 pattern, which we assume for now needs a scratch register. */
532 return scratch_reload_class (icode);
533}
534
535/* ICODE is the insn_code of a reload pattern. Check that it has exactly
536 three operands, verify that operand 2 is an output operand, and return
537 its register class.
538 ??? We'd like to be able to handle any pattern with at least 2 operands,
539 for zero or more scratch registers, but that needs more infrastructure. */
540enum reg_class
541scratch_reload_class (enum insn_code icode)
542{
543 const char *scratch_constraint;
544 char scratch_letter;
545 enum reg_class class;
546
547 gcc_assert (insn_data[(int) icode].n_operands == 3);
548 scratch_constraint = insn_data[(int) icode].operand[2].constraint;
549 gcc_assert (*scratch_constraint == '=');
550 scratch_constraint++;
551 if (*scratch_constraint == '&')
552 scratch_constraint++;
553 scratch_letter = *scratch_constraint;
554 if (scratch_letter == 'r')
555 return GENERAL_REGS;
556 class = REG_CLASS_FROM_CONSTRAINT ((unsigned char) scratch_letter,
557 scratch_constraint);
558 gcc_assert (class != NO_REGS);
559 return class;
560}
577
578#ifdef SECONDARY_MEMORY_NEEDED
579
580/* Return a memory location that will be used to copy X in mode MODE.
581 If we haven't already made a location for this mode in this insn,
582 call find_reloads_address on the location being returned. */
583
584rtx

--- 69 unchanged lines hidden (view full) ---

654
655void
656clear_secondary_mem (void)
657{
658 memset (secondary_memlocs, 0, sizeof secondary_memlocs);
659}
660#endif /* SECONDARY_MEMORY_NEEDED */
661
561
562#ifdef SECONDARY_MEMORY_NEEDED
563
564/* Return a memory location that will be used to copy X in mode MODE.
565 If we haven't already made a location for this mode in this insn,
566 call find_reloads_address on the location being returned. */
567
568rtx

--- 69 unchanged lines hidden (view full) ---

638
639void
640clear_secondary_mem (void)
641{
642 memset (secondary_memlocs, 0, sizeof secondary_memlocs);
643}
644#endif /* SECONDARY_MEMORY_NEEDED */
645
662/* Find the largest class for which every register number plus N is valid in
663 M1 (if in range) and is cheap to move into REGNO.
664 Abort if no such class exists. */
665
646
647/* Find the largest class which has at least one register valid in
648 mode INNER, and which for every such register, that register number
649 plus N is also valid in OUTER (if in range) and is cheap to move
650 into REGNO. Such a class must exist. */
651
666static enum reg_class
652static enum reg_class
667find_valid_class (enum machine_mode m1 ATTRIBUTE_UNUSED, int n,
653find_valid_class (enum machine_mode outer ATTRIBUTE_UNUSED,
654 enum machine_mode inner ATTRIBUTE_UNUSED, int n,
668 unsigned int dest_regno ATTRIBUTE_UNUSED)
669{
670 int best_cost = -1;
671 int class;
672 int regno;
673 enum reg_class best_class = NO_REGS;
674 enum reg_class dest_class ATTRIBUTE_UNUSED = REGNO_REG_CLASS (dest_regno);
675 unsigned int best_size = 0;
676 int cost;
677
678 for (class = 1; class < N_REG_CLASSES; class++)
679 {
680 int bad = 0;
655 unsigned int dest_regno ATTRIBUTE_UNUSED)
656{
657 int best_cost = -1;
658 int class;
659 int regno;
660 enum reg_class best_class = NO_REGS;
661 enum reg_class dest_class ATTRIBUTE_UNUSED = REGNO_REG_CLASS (dest_regno);
662 unsigned int best_size = 0;
663 int cost;
664
665 for (class = 1; class < N_REG_CLASSES; class++)
666 {
667 int bad = 0;
681 for (regno = 0; regno < FIRST_PSEUDO_REGISTER && ! bad; regno++)
682 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
683 && TEST_HARD_REG_BIT (reg_class_contents[class], regno + n)
684 && ! HARD_REGNO_MODE_OK (regno + n, m1))
685 bad = 1;
668 int good = 0;
669 for (regno = 0; regno < FIRST_PSEUDO_REGISTER - n && ! bad; regno++)
670 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno))
671 {
672 if (HARD_REGNO_MODE_OK (regno, inner))
673 {
674 good = 1;
675 if (! TEST_HARD_REG_BIT (reg_class_contents[class], regno + n)
676 || ! HARD_REGNO_MODE_OK (regno + n, outer))
677 bad = 1;
678 }
679 }
686
680
687 if (bad)
681 if (bad || !good)
688 continue;
682 continue;
689 cost = REGISTER_MOVE_COST (m1, class, dest_class);
683 cost = REGISTER_MOVE_COST (outer, class, dest_class);
690
691 if ((reg_class_size[class] > best_size
692 && (best_cost < 0 || best_cost >= cost))
693 || best_cost > cost)
694 {
695 best_class = class;
696 best_size = reg_class_size[class];
684
685 if ((reg_class_size[class] > best_size
686 && (best_cost < 0 || best_cost >= cost))
687 || best_cost > cost)
688 {
689 best_class = class;
690 best_size = reg_class_size[class];
697 best_cost = REGISTER_MOVE_COST (m1, class, dest_class);
691 best_cost = REGISTER_MOVE_COST (outer, class, dest_class);
698 }
699 }
700
692 }
693 }
694
701 if (best_size == 0)
702 abort ();
695 gcc_assert (best_size != 0);
703
704 return best_class;
705}
706
707/* Return the number of a previously made reload that can be combined with
708 a new one, or n_reloads if none of the existing reloads can be used.
709 OUT, CLASS, TYPE and OPNUM are the same arguments as passed to
710 push_reload, they determine the kind of the new reload that we try to

--- 29 unchanged lines hidden (view full) ---

740 && (rld[i].reg_rtx == 0
741 || TEST_HARD_REG_BIT (reg_class_contents[(int) class],
742 true_regnum (rld[i].reg_rtx)))
743 && ((in != 0 && MATCHES (rld[i].in, in) && ! dont_share
744 && (out == 0 || rld[i].out == 0 || MATCHES (rld[i].out, out)))
745 || (out != 0 && MATCHES (rld[i].out, out)
746 && (in == 0 || rld[i].in == 0 || MATCHES (rld[i].in, in))))
747 && (rld[i].out == 0 || ! earlyclobber_operand_p (rld[i].out))
696
697 return best_class;
698}
699
700/* Return the number of a previously made reload that can be combined with
701 a new one, or n_reloads if none of the existing reloads can be used.
702 OUT, CLASS, TYPE and OPNUM are the same arguments as passed to
703 push_reload, they determine the kind of the new reload that we try to

--- 29 unchanged lines hidden (view full) ---

733 && (rld[i].reg_rtx == 0
734 || TEST_HARD_REG_BIT (reg_class_contents[(int) class],
735 true_regnum (rld[i].reg_rtx)))
736 && ((in != 0 && MATCHES (rld[i].in, in) && ! dont_share
737 && (out == 0 || rld[i].out == 0 || MATCHES (rld[i].out, out)))
738 || (out != 0 && MATCHES (rld[i].out, out)
739 && (in == 0 || rld[i].in == 0 || MATCHES (rld[i].in, in))))
740 && (rld[i].out == 0 || ! earlyclobber_operand_p (rld[i].out))
748 && (reg_class_size[(int) class] == 1 || SMALL_REGISTER_CLASSES)
741 && (SMALL_REGISTER_CLASS_P (class) || SMALL_REGISTER_CLASSES)
749 && MERGABLE_RELOADS (type, rld[i].when_needed, opnum, rld[i].opnum))
750 return i;
751
752 /* Reloading a plain reg for input can match a reload to postincrement
753 that reg, since the postincrement's value is the right value.
754 Likewise, it can match a preincrement reload, since we regard
755 the preincrementation as happening before any ref in this insn
756 to that register. */
757 for (i = 0; i < n_reloads; i++)
758 if ((reg_class_subset_p (class, rld[i].class)
759 || reg_class_subset_p (rld[i].class, class))
760 /* If the existing reload has a register, it must fit our
761 class. */
762 && (rld[i].reg_rtx == 0
763 || TEST_HARD_REG_BIT (reg_class_contents[(int) class],
764 true_regnum (rld[i].reg_rtx)))
765 && out == 0 && rld[i].out == 0 && rld[i].in != 0
742 && MERGABLE_RELOADS (type, rld[i].when_needed, opnum, rld[i].opnum))
743 return i;
744
745 /* Reloading a plain reg for input can match a reload to postincrement
746 that reg, since the postincrement's value is the right value.
747 Likewise, it can match a preincrement reload, since we regard
748 the preincrementation as happening before any ref in this insn
749 to that register. */
750 for (i = 0; i < n_reloads; i++)
751 if ((reg_class_subset_p (class, rld[i].class)
752 || reg_class_subset_p (rld[i].class, class))
753 /* If the existing reload has a register, it must fit our
754 class. */
755 && (rld[i].reg_rtx == 0
756 || TEST_HARD_REG_BIT (reg_class_contents[(int) class],
757 true_regnum (rld[i].reg_rtx)))
758 && out == 0 && rld[i].out == 0 && rld[i].in != 0
766 && ((GET_CODE (in) == REG
767 && GET_RTX_CLASS (GET_CODE (rld[i].in)) == 'a'
759 && ((REG_P (in)
760 && GET_RTX_CLASS (GET_CODE (rld[i].in)) == RTX_AUTOINC
768 && MATCHES (XEXP (rld[i].in, 0), in))
761 && MATCHES (XEXP (rld[i].in, 0), in))
769 || (GET_CODE (rld[i].in) == REG
770 && GET_RTX_CLASS (GET_CODE (in)) == 'a'
762 || (REG_P (rld[i].in)
763 && GET_RTX_CLASS (GET_CODE (in)) == RTX_AUTOINC
771 && MATCHES (XEXP (in, 0), rld[i].in)))
772 && (rld[i].out == 0 || ! earlyclobber_operand_p (rld[i].out))
764 && MATCHES (XEXP (in, 0), rld[i].in)))
765 && (rld[i].out == 0 || ! earlyclobber_operand_p (rld[i].out))
773 && (reg_class_size[(int) class] == 1 || SMALL_REGISTER_CLASSES)
766 && (SMALL_REGISTER_CLASS_P (class) || SMALL_REGISTER_CLASSES)
774 && MERGABLE_RELOADS (type, rld[i].when_needed,
775 opnum, rld[i].opnum))
776 {
777 /* Make sure reload_in ultimately has the increment,
778 not the plain register. */
767 && MERGABLE_RELOADS (type, rld[i].when_needed,
768 opnum, rld[i].opnum))
769 {
770 /* Make sure reload_in ultimately has the increment,
771 not the plain register. */
779 if (GET_CODE (in) == REG)
772 if (REG_P (in))
780 *p_in = rld[i].in;
781 return i;
782 }
783 return n_reloads;
784}
785
786/* Return nonzero if X is a SUBREG which will require reloading of its
787 SUBREG_REG expression. */

--- 10 unchanged lines hidden (view full) ---

798 inner = SUBREG_REG (x);
799
800 /* If INNER is a constant or PLUS, then INNER must be reloaded. */
801 if (CONSTANT_P (inner) || GET_CODE (inner) == PLUS)
802 return 1;
803
804 /* If INNER is not a hard register, then INNER will not need to
805 be reloaded. */
773 *p_in = rld[i].in;
774 return i;
775 }
776 return n_reloads;
777}
778
779/* Return nonzero if X is a SUBREG which will require reloading of its
780 SUBREG_REG expression. */

--- 10 unchanged lines hidden (view full) ---

791 inner = SUBREG_REG (x);
792
793 /* If INNER is a constant or PLUS, then INNER must be reloaded. */
794 if (CONSTANT_P (inner) || GET_CODE (inner) == PLUS)
795 return 1;
796
797 /* If INNER is not a hard register, then INNER will not need to
798 be reloaded. */
806 if (GET_CODE (inner) != REG
799 if (!REG_P (inner)
807 || REGNO (inner) >= FIRST_PSEUDO_REGISTER)
808 return 0;
809
810 /* If INNER is not ok for MODE, then INNER will need reloading. */
811 if (! HARD_REGNO_MODE_OK (subreg_regno (x), mode))
812 return 1;
813
814 /* If the outer part is a word or smaller, INNER larger than a
815 word and the number of regs for INNER is not the same as the
816 number of words in INNER, then INNER will need reloading. */
817 return (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
818 && output
819 && GET_MODE_SIZE (GET_MODE (inner)) > UNITS_PER_WORD
820 && ((GET_MODE_SIZE (GET_MODE (inner)) / UNITS_PER_WORD)
800 || REGNO (inner) >= FIRST_PSEUDO_REGISTER)
801 return 0;
802
803 /* If INNER is not ok for MODE, then INNER will need reloading. */
804 if (! HARD_REGNO_MODE_OK (subreg_regno (x), mode))
805 return 1;
806
807 /* If the outer part is a word or smaller, INNER larger than a
808 word and the number of regs for INNER is not the same as the
809 number of words in INNER, then INNER will need reloading. */
810 return (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
811 && output
812 && GET_MODE_SIZE (GET_MODE (inner)) > UNITS_PER_WORD
813 && ((GET_MODE_SIZE (GET_MODE (inner)) / UNITS_PER_WORD)
821 != (int) HARD_REGNO_NREGS (REGNO (inner), GET_MODE (inner))));
814 != (int) hard_regno_nregs[REGNO (inner)][GET_MODE (inner)]));
822}
823
824/* Return nonzero if IN can be reloaded into REGNO with mode MODE without
825 requiring an extra reload register. The caller has already found that
826 IN contains some reference to REGNO, so check that we can produce the
827 new value in a single step. E.g. if we have
828 (set (reg r13) (plus (reg r13) (const int 1))), and there is an
829 instruction that adds one to a register, this should succeed.

--- 12 unchanged lines hidden (view full) ---

842 int r = 0;
843 struct recog_data save_recog_data;
844
845 /* For matching constraints, we often get notional input reloads where
846 we want to use the original register as the reload register. I.e.
847 technically this is a non-optional input-output reload, but IN is
848 already a valid register, and has been chosen as the reload register.
849 Speed this up, since it trivially works. */
815}
816
817/* Return nonzero if IN can be reloaded into REGNO with mode MODE without
818 requiring an extra reload register. The caller has already found that
819 IN contains some reference to REGNO, so check that we can produce the
820 new value in a single step. E.g. if we have
821 (set (reg r13) (plus (reg r13) (const int 1))), and there is an
822 instruction that adds one to a register, this should succeed.

--- 12 unchanged lines hidden (view full) ---

835 int r = 0;
836 struct recog_data save_recog_data;
837
838 /* For matching constraints, we often get notional input reloads where
839 we want to use the original register as the reload register. I.e.
840 technically this is a non-optional input-output reload, but IN is
841 already a valid register, and has been chosen as the reload register.
842 Speed this up, since it trivially works. */
850 if (GET_CODE (in) == REG)
843 if (REG_P (in))
851 return 1;
852
853 /* To test MEMs properly, we'd have to take into account all the reloads
854 that are already scheduled, which can become quite complicated.
855 And since we've already handled address reloads for this MEM, it
856 should always succeed anyway. */
844 return 1;
845
846 /* To test MEMs properly, we'd have to take into account all the reloads
847 that are already scheduled, which can become quite complicated.
848 And since we've already handled address reloads for this MEM, it
849 should always succeed anyway. */
857 if (GET_CODE (in) == MEM)
850 if (MEM_P (in))
858 return 1;
859
860 /* If we can make a simple SET insn that does the job, everything should
861 be fine. */
862 dst = gen_rtx_REG (mode, regno);
863 test_insn = make_insn_raw (gen_rtx_SET (VOIDmode, dst, in));
864 save_recog_data = recog_data;
865 if (recog_memoized (test_insn) >= 0)

--- 59 unchanged lines hidden (view full) ---

925 inmode = GET_MODE (in);
926 if (outmode == VOIDmode && out != 0)
927 outmode = GET_MODE (out);
928
929 /* If IN is a pseudo register everywhere-equivalent to a constant, and
930 it is not in a hard register, reload straight from the constant,
931 since we want to get rid of such pseudo registers.
932 Often this is done earlier, but not always in find_reloads_address. */
851 return 1;
852
853 /* If we can make a simple SET insn that does the job, everything should
854 be fine. */
855 dst = gen_rtx_REG (mode, regno);
856 test_insn = make_insn_raw (gen_rtx_SET (VOIDmode, dst, in));
857 save_recog_data = recog_data;
858 if (recog_memoized (test_insn) >= 0)

--- 59 unchanged lines hidden (view full) ---

918 inmode = GET_MODE (in);
919 if (outmode == VOIDmode && out != 0)
920 outmode = GET_MODE (out);
921
922 /* If IN is a pseudo register everywhere-equivalent to a constant, and
923 it is not in a hard register, reload straight from the constant,
924 since we want to get rid of such pseudo registers.
925 Often this is done earlier, but not always in find_reloads_address. */
933 if (in != 0 && GET_CODE (in) == REG)
926 if (in != 0 && REG_P (in))
934 {
935 int regno = REGNO (in);
936
937 if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
938 && reg_equiv_constant[regno] != 0)
939 in = reg_equiv_constant[regno];
940 }
941
942 /* Likewise for OUT. Of course, OUT will never be equivalent to
943 an actual constant, but it might be equivalent to a memory location
944 (in the case of a parameter). */
927 {
928 int regno = REGNO (in);
929
930 if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
931 && reg_equiv_constant[regno] != 0)
932 in = reg_equiv_constant[regno];
933 }
934
935 /* Likewise for OUT. Of course, OUT will never be equivalent to
936 an actual constant, but it might be equivalent to a memory location
937 (in the case of a parameter). */
945 if (out != 0 && GET_CODE (out) == REG)
938 if (out != 0 && REG_P (out))
946 {
947 int regno = REGNO (out);
948
949 if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
950 && reg_equiv_constant[regno] != 0)
951 out = reg_equiv_constant[regno];
952 }
953
954 /* If we have a read-write operand with an address side-effect,
955 change either IN or OUT so the side-effect happens only once. */
939 {
940 int regno = REGNO (out);
941
942 if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
943 && reg_equiv_constant[regno] != 0)
944 out = reg_equiv_constant[regno];
945 }
946
947 /* If we have a read-write operand with an address side-effect,
948 change either IN or OUT so the side-effect happens only once. */
956 if (in != 0 && out != 0 && GET_CODE (in) == MEM && rtx_equal_p (in, out))
949 if (in != 0 && out != 0 && MEM_P (in) && rtx_equal_p (in, out))
957 switch (GET_CODE (XEXP (in, 0)))
958 {
959 case POST_INC: case POST_DEC: case POST_MODIFY:
960 in = replace_equiv_address_nv (in, XEXP (XEXP (in, 0), 0));
961 break;
962
963 case PRE_INC: case PRE_DEC: case PRE_MODIFY:
964 out = replace_equiv_address_nv (out, XEXP (XEXP (out, 0), 0));

--- 36 unchanged lines hidden (view full) ---

1001 if (in != 0 && GET_CODE (in) == SUBREG
1002 && (subreg_lowpart_p (in) || strict_low)
1003#ifdef CANNOT_CHANGE_MODE_CLASS
1004 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SUBREG_REG (in)), inmode, class)
1005#endif
1006 && (CONSTANT_P (SUBREG_REG (in))
1007 || GET_CODE (SUBREG_REG (in)) == PLUS
1008 || strict_low
950 switch (GET_CODE (XEXP (in, 0)))
951 {
952 case POST_INC: case POST_DEC: case POST_MODIFY:
953 in = replace_equiv_address_nv (in, XEXP (XEXP (in, 0), 0));
954 break;
955
956 case PRE_INC: case PRE_DEC: case PRE_MODIFY:
957 out = replace_equiv_address_nv (out, XEXP (XEXP (out, 0), 0));

--- 36 unchanged lines hidden (view full) ---

994 if (in != 0 && GET_CODE (in) == SUBREG
995 && (subreg_lowpart_p (in) || strict_low)
996#ifdef CANNOT_CHANGE_MODE_CLASS
997 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SUBREG_REG (in)), inmode, class)
998#endif
999 && (CONSTANT_P (SUBREG_REG (in))
1000 || GET_CODE (SUBREG_REG (in)) == PLUS
1001 || strict_low
1009 || (((GET_CODE (SUBREG_REG (in)) == REG
1002 || (((REG_P (SUBREG_REG (in))
1010 && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER)
1003 && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER)
1011 || GET_CODE (SUBREG_REG (in)) == MEM)
1004 || MEM_P (SUBREG_REG (in)))
1012 && ((GET_MODE_SIZE (inmode)
1013 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
1014#ifdef LOAD_EXTEND_OP
1015 || (GET_MODE_SIZE (inmode) <= UNITS_PER_WORD
1016 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
1017 <= UNITS_PER_WORD)
1018 && (GET_MODE_SIZE (inmode)
1019 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
1020 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (in)))
1005 && ((GET_MODE_SIZE (inmode)
1006 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
1007#ifdef LOAD_EXTEND_OP
1008 || (GET_MODE_SIZE (inmode) <= UNITS_PER_WORD
1009 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
1010 <= UNITS_PER_WORD)
1011 && (GET_MODE_SIZE (inmode)
1012 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
1013 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (in)))
1021 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (in))) != NIL)
1014 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (in))) != UNKNOWN)
1022#endif
1023#ifdef WORD_REGISTER_OPERATIONS
1024 || ((GET_MODE_SIZE (inmode)
1025 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
1026 && ((GET_MODE_SIZE (inmode) - 1) / UNITS_PER_WORD ==
1027 ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) - 1)
1028 / UNITS_PER_WORD)))
1029#endif
1030 ))
1015#endif
1016#ifdef WORD_REGISTER_OPERATIONS
1017 || ((GET_MODE_SIZE (inmode)
1018 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
1019 && ((GET_MODE_SIZE (inmode) - 1) / UNITS_PER_WORD ==
1020 ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) - 1)
1021 / UNITS_PER_WORD)))
1022#endif
1023 ))
1031 || (GET_CODE (SUBREG_REG (in)) == REG
1024 || (REG_P (SUBREG_REG (in))
1032 && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER
1033 /* The case where out is nonzero
1034 is handled differently in the following statement. */
1035 && (out == 0 || subreg_lowpart_p (in))
1036 && ((GET_MODE_SIZE (inmode) <= UNITS_PER_WORD
1037 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
1038 > UNITS_PER_WORD)
1039 && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
1040 / UNITS_PER_WORD)
1025 && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER
1026 /* The case where out is nonzero
1027 is handled differently in the following statement. */
1028 && (out == 0 || subreg_lowpart_p (in))
1029 && ((GET_MODE_SIZE (inmode) <= UNITS_PER_WORD
1030 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
1031 > UNITS_PER_WORD)
1032 && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
1033 / UNITS_PER_WORD)
1041 != (int) HARD_REGNO_NREGS (REGNO (SUBREG_REG (in)),
1042 GET_MODE (SUBREG_REG (in)))))
1034 != (int) hard_regno_nregs[REGNO (SUBREG_REG (in))]
1035 [GET_MODE (SUBREG_REG (in))]))
1043 || ! HARD_REGNO_MODE_OK (subreg_regno (in), inmode)))
1036 || ! HARD_REGNO_MODE_OK (subreg_regno (in), inmode)))
1044#ifdef SECONDARY_INPUT_RELOAD_CLASS
1045 || (SECONDARY_INPUT_RELOAD_CLASS (class, inmode, in) != NO_REGS
1046 && (SECONDARY_INPUT_RELOAD_CLASS (class,
1047 GET_MODE (SUBREG_REG (in)),
1048 SUBREG_REG (in))
1037 || (secondary_reload_class (1, class, inmode, in) != NO_REGS
1038 && (secondary_reload_class (1, class, GET_MODE (SUBREG_REG (in)),
1039 SUBREG_REG (in))
1049 == NO_REGS))
1040 == NO_REGS))
1050#endif
1051#ifdef CANNOT_CHANGE_MODE_CLASS
1041#ifdef CANNOT_CHANGE_MODE_CLASS
1052 || (GET_CODE (SUBREG_REG (in)) == REG
1042 || (REG_P (SUBREG_REG (in))
1053 && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER
1054 && REG_CANNOT_CHANGE_MODE_P
1055 (REGNO (SUBREG_REG (in)), GET_MODE (SUBREG_REG (in)), inmode))
1056#endif
1057 ))
1058 {
1059 in_subreg_loc = inloc;
1060 inloc = &SUBREG_REG (in);
1061 in = *inloc;
1062#if ! defined (LOAD_EXTEND_OP) && ! defined (WORD_REGISTER_OPERATIONS)
1043 && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER
1044 && REG_CANNOT_CHANGE_MODE_P
1045 (REGNO (SUBREG_REG (in)), GET_MODE (SUBREG_REG (in)), inmode))
1046#endif
1047 ))
1048 {
1049 in_subreg_loc = inloc;
1050 inloc = &SUBREG_REG (in);
1051 in = *inloc;
1052#if ! defined (LOAD_EXTEND_OP) && ! defined (WORD_REGISTER_OPERATIONS)
1063 if (GET_CODE (in) == MEM)
1053 if (MEM_P (in))
1064 /* This is supposed to happen only for paradoxical subregs made by
1065 combine.c. (SUBREG (MEM)) isn't supposed to occur other ways. */
1054 /* This is supposed to happen only for paradoxical subregs made by
1055 combine.c. (SUBREG (MEM)) isn't supposed to occur other ways. */
1066 if (GET_MODE_SIZE (GET_MODE (in)) > GET_MODE_SIZE (inmode))
1067 abort ();
1056 gcc_assert (GET_MODE_SIZE (GET_MODE (in)) <= GET_MODE_SIZE (inmode));
1068#endif
1069 inmode = GET_MODE (in);
1070 }
1071
1072 /* Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where
1073 either M1 is not valid for R or M2 is wider than a word but we only
1074 need one word to store an M2-sized quantity in R.
1075
1076 However, we must reload the inner reg *as well as* the subreg in
1077 that case. */
1078
1079 /* Similar issue for (SUBREG constant ...) if it was not handled by the
1080 code above. This can happen if SUBREG_BYTE != 0. */
1081
1082 if (in != 0 && reload_inner_reg_of_subreg (in, inmode, 0))
1083 {
1084 enum reg_class in_class = class;
1085
1057#endif
1058 inmode = GET_MODE (in);
1059 }
1060
1061 /* Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where
1062 either M1 is not valid for R or M2 is wider than a word but we only
1063 need one word to store an M2-sized quantity in R.
1064
1065 However, we must reload the inner reg *as well as* the subreg in
1066 that case. */
1067
1068 /* Similar issue for (SUBREG constant ...) if it was not handled by the
1069 code above. This can happen if SUBREG_BYTE != 0. */
1070
1071 if (in != 0 && reload_inner_reg_of_subreg (in, inmode, 0))
1072 {
1073 enum reg_class in_class = class;
1074
1086 if (GET_CODE (SUBREG_REG (in)) == REG)
1075 if (REG_P (SUBREG_REG (in)))
1087 in_class
1076 in_class
1088 = find_valid_class (inmode,
1077 = find_valid_class (inmode, GET_MODE (SUBREG_REG (in)),
1089 subreg_regno_offset (REGNO (SUBREG_REG (in)),
1090 GET_MODE (SUBREG_REG (in)),
1091 SUBREG_BYTE (in),
1092 GET_MODE (in)),
1093 REGNO (SUBREG_REG (in)));
1094
1095 /* This relies on the fact that emit_reload_insns outputs the
1096 instructions for input reloads of type RELOAD_OTHER in the same

--- 13 unchanged lines hidden (view full) ---

1110 and in that case the constraint should label it input-output.) */
1111 if (out != 0 && GET_CODE (out) == SUBREG
1112 && (subreg_lowpart_p (out) || strict_low)
1113#ifdef CANNOT_CHANGE_MODE_CLASS
1114 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SUBREG_REG (out)), outmode, class)
1115#endif
1116 && (CONSTANT_P (SUBREG_REG (out))
1117 || strict_low
1078 subreg_regno_offset (REGNO (SUBREG_REG (in)),
1079 GET_MODE (SUBREG_REG (in)),
1080 SUBREG_BYTE (in),
1081 GET_MODE (in)),
1082 REGNO (SUBREG_REG (in)));
1083
1084 /* This relies on the fact that emit_reload_insns outputs the
1085 instructions for input reloads of type RELOAD_OTHER in the same

--- 13 unchanged lines hidden (view full) ---

1099 and in that case the constraint should label it input-output.) */
1100 if (out != 0 && GET_CODE (out) == SUBREG
1101 && (subreg_lowpart_p (out) || strict_low)
1102#ifdef CANNOT_CHANGE_MODE_CLASS
1103 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SUBREG_REG (out)), outmode, class)
1104#endif
1105 && (CONSTANT_P (SUBREG_REG (out))
1106 || strict_low
1118 || (((GET_CODE (SUBREG_REG (out)) == REG
1107 || (((REG_P (SUBREG_REG (out))
1119 && REGNO (SUBREG_REG (out)) >= FIRST_PSEUDO_REGISTER)
1108 && REGNO (SUBREG_REG (out)) >= FIRST_PSEUDO_REGISTER)
1120 || GET_CODE (SUBREG_REG (out)) == MEM)
1109 || MEM_P (SUBREG_REG (out)))
1121 && ((GET_MODE_SIZE (outmode)
1122 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
1123#ifdef WORD_REGISTER_OPERATIONS
1124 || ((GET_MODE_SIZE (outmode)
1125 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
1126 && ((GET_MODE_SIZE (outmode) - 1) / UNITS_PER_WORD ==
1127 ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) - 1)
1128 / UNITS_PER_WORD)))
1129#endif
1130 ))
1110 && ((GET_MODE_SIZE (outmode)
1111 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
1112#ifdef WORD_REGISTER_OPERATIONS
1113 || ((GET_MODE_SIZE (outmode)
1114 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
1115 && ((GET_MODE_SIZE (outmode) - 1) / UNITS_PER_WORD ==
1116 ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) - 1)
1117 / UNITS_PER_WORD)))
1118#endif
1119 ))
1131 || (GET_CODE (SUBREG_REG (out)) == REG
1120 || (REG_P (SUBREG_REG (out))
1132 && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER
1133 && ((GET_MODE_SIZE (outmode) <= UNITS_PER_WORD
1134 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))
1135 > UNITS_PER_WORD)
1136 && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))
1137 / UNITS_PER_WORD)
1121 && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER
1122 && ((GET_MODE_SIZE (outmode) <= UNITS_PER_WORD
1123 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))
1124 > UNITS_PER_WORD)
1125 && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))
1126 / UNITS_PER_WORD)
1138 != (int) HARD_REGNO_NREGS (REGNO (SUBREG_REG (out)),
1139 GET_MODE (SUBREG_REG (out)))))
1127 != (int) hard_regno_nregs[REGNO (SUBREG_REG (out))]
1128 [GET_MODE (SUBREG_REG (out))]))
1140 || ! HARD_REGNO_MODE_OK (subreg_regno (out), outmode)))
1129 || ! HARD_REGNO_MODE_OK (subreg_regno (out), outmode)))
1141#ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1142 || (SECONDARY_OUTPUT_RELOAD_CLASS (class, outmode, out) != NO_REGS
1143 && (SECONDARY_OUTPUT_RELOAD_CLASS (class,
1144 GET_MODE (SUBREG_REG (out)),
1145 SUBREG_REG (out))
1130 || (secondary_reload_class (0, class, outmode, out) != NO_REGS
1131 && (secondary_reload_class (0, class, GET_MODE (SUBREG_REG (out)),
1132 SUBREG_REG (out))
1146 == NO_REGS))
1133 == NO_REGS))
1147#endif
1148#ifdef CANNOT_CHANGE_MODE_CLASS
1134#ifdef CANNOT_CHANGE_MODE_CLASS
1149 || (GET_CODE (SUBREG_REG (out)) == REG
1135 || (REG_P (SUBREG_REG (out))
1150 && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER
1151 && REG_CANNOT_CHANGE_MODE_P (REGNO (SUBREG_REG (out)),
1152 GET_MODE (SUBREG_REG (out)),
1153 outmode))
1154#endif
1155 ))
1156 {
1157 out_subreg_loc = outloc;
1158 outloc = &SUBREG_REG (out);
1159 out = *outloc;
1160#if ! defined (LOAD_EXTEND_OP) && ! defined (WORD_REGISTER_OPERATIONS)
1136 && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER
1137 && REG_CANNOT_CHANGE_MODE_P (REGNO (SUBREG_REG (out)),
1138 GET_MODE (SUBREG_REG (out)),
1139 outmode))
1140#endif
1141 ))
1142 {
1143 out_subreg_loc = outloc;
1144 outloc = &SUBREG_REG (out);
1145 out = *outloc;
1146#if ! defined (LOAD_EXTEND_OP) && ! defined (WORD_REGISTER_OPERATIONS)
1161 if (GET_CODE (out) == MEM
1162 && GET_MODE_SIZE (GET_MODE (out)) > GET_MODE_SIZE (outmode))
1163 abort ();
1147 gcc_assert (!MEM_P (out)
1148 || GET_MODE_SIZE (GET_MODE (out))
1149 <= GET_MODE_SIZE (outmode));
1164#endif
1165 outmode = GET_MODE (out);
1166 }
1167
1168 /* Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where
1169 either M1 is not valid for R or M2 is wider than a word but we only
1170 need one word to store an M2-sized quantity in R.
1171

--- 5 unchanged lines hidden (view full) ---

1177 /* This relies on the fact that emit_reload_insns outputs the
1178 instructions for output reloads of type RELOAD_OTHER in reverse
1179 order of the reloads. Thus if the outer reload is also of type
1180 RELOAD_OTHER, we are guaranteed that this inner reload will be
1181 output after the outer reload. */
1182 dont_remove_subreg = 1;
1183 push_reload (SUBREG_REG (out), SUBREG_REG (out), &SUBREG_REG (out),
1184 &SUBREG_REG (out),
1150#endif
1151 outmode = GET_MODE (out);
1152 }
1153
1154 /* Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where
1155 either M1 is not valid for R or M2 is wider than a word but we only
1156 need one word to store an M2-sized quantity in R.
1157

--- 5 unchanged lines hidden (view full) ---

1163 /* This relies on the fact that emit_reload_insns outputs the
1164 instructions for output reloads of type RELOAD_OTHER in reverse
1165 order of the reloads. Thus if the outer reload is also of type
1166 RELOAD_OTHER, we are guaranteed that this inner reload will be
1167 output after the outer reload. */
1168 dont_remove_subreg = 1;
1169 push_reload (SUBREG_REG (out), SUBREG_REG (out), &SUBREG_REG (out),
1170 &SUBREG_REG (out),
1185 find_valid_class (outmode,
1171 find_valid_class (outmode, GET_MODE (SUBREG_REG (out)),
1186 subreg_regno_offset (REGNO (SUBREG_REG (out)),
1187 GET_MODE (SUBREG_REG (out)),
1188 SUBREG_BYTE (out),
1189 GET_MODE (out)),
1190 REGNO (SUBREG_REG (out))),
1191 VOIDmode, VOIDmode, 0, 0,
1192 opnum, RELOAD_OTHER);
1193 }
1194
1195 /* If IN appears in OUT, we can't share any input-only reload for IN. */
1172 subreg_regno_offset (REGNO (SUBREG_REG (out)),
1173 GET_MODE (SUBREG_REG (out)),
1174 SUBREG_BYTE (out),
1175 GET_MODE (out)),
1176 REGNO (SUBREG_REG (out))),
1177 VOIDmode, VOIDmode, 0, 0,
1178 opnum, RELOAD_OTHER);
1179 }
1180
1181 /* If IN appears in OUT, we can't share any input-only reload for IN. */
1196 if (in != 0 && out != 0 && GET_CODE (out) == MEM
1197 && (GET_CODE (in) == REG || GET_CODE (in) == MEM)
1182 if (in != 0 && out != 0 && MEM_P (out)
1183 && (REG_P (in) || MEM_P (in))
1198 && reg_overlap_mentioned_for_reload_p (in, XEXP (out, 0)))
1199 dont_share = 1;
1200
1201 /* If IN is a SUBREG of a hard register, make a new REG. This
1202 simplifies some of the cases below. */
1203
1184 && reg_overlap_mentioned_for_reload_p (in, XEXP (out, 0)))
1185 dont_share = 1;
1186
1187 /* If IN is a SUBREG of a hard register, make a new REG. This
1188 simplifies some of the cases below. */
1189
1204 if (in != 0 && GET_CODE (in) == SUBREG && GET_CODE (SUBREG_REG (in)) == REG
1190 if (in != 0 && GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))
1205 && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER
1206 && ! dont_remove_subreg)
1207 in = gen_rtx_REG (GET_MODE (in), subreg_regno (in));
1208
1209 /* Similarly for OUT. */
1210 if (out != 0 && GET_CODE (out) == SUBREG
1191 && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER
1192 && ! dont_remove_subreg)
1193 in = gen_rtx_REG (GET_MODE (in), subreg_regno (in));
1194
1195 /* Similarly for OUT. */
1196 if (out != 0 && GET_CODE (out) == SUBREG
1211 && GET_CODE (SUBREG_REG (out)) == REG
1197 && REG_P (SUBREG_REG (out))
1212 && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER
1213 && ! dont_remove_subreg)
1214 out = gen_rtx_REG (GET_MODE (out), subreg_regno (out));
1215
1216 /* Narrow down the class of register wanted if that is
1217 desirable on this machine for efficiency. */
1198 && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER
1199 && ! dont_remove_subreg)
1200 out = gen_rtx_REG (GET_MODE (out), subreg_regno (out));
1201
1202 /* Narrow down the class of register wanted if that is
1203 desirable on this machine for efficiency. */
1218 if (in != 0)
1219 class = PREFERRED_RELOAD_CLASS (in, class);
1204 {
1205 enum reg_class preferred_class = class;
1220
1206
1207 if (in != 0)
1208 preferred_class = PREFERRED_RELOAD_CLASS (in, class);
1209
1221 /* Output reloads may need analogous treatment, different in detail. */
1222#ifdef PREFERRED_OUTPUT_RELOAD_CLASS
1210 /* Output reloads may need analogous treatment, different in detail. */
1211#ifdef PREFERRED_OUTPUT_RELOAD_CLASS
1223 if (out != 0)
1224 class = PREFERRED_OUTPUT_RELOAD_CLASS (out, class);
1212 if (out != 0)
1213 preferred_class = PREFERRED_OUTPUT_RELOAD_CLASS (out, preferred_class);
1225#endif
1226
1214#endif
1215
1216 /* Discard what the target said if we cannot do it. */
1217 if (preferred_class != NO_REGS
1218 || (optional && type == RELOAD_FOR_OUTPUT))
1219 class = preferred_class;
1220 }
1221
1227 /* Make sure we use a class that can handle the actual pseudo
1228 inside any subreg. For example, on the 386, QImode regs
1229 can appear within SImode subregs. Although GENERAL_REGS
1230 can handle SImode, QImode needs a smaller class. */
1231#ifdef LIMIT_RELOAD_CLASS
1232 if (in_subreg_loc)
1233 class = LIMIT_RELOAD_CLASS (inmode, class);
1234 else if (in != 0 && GET_CODE (in) == SUBREG)

--- 11 unchanged lines hidden (view full) ---

1246 {
1247 enum machine_mode mode;
1248 if (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (outmode))
1249 mode = inmode;
1250 else
1251 mode = outmode;
1252 if (mode == VOIDmode)
1253 {
1222 /* Make sure we use a class that can handle the actual pseudo
1223 inside any subreg. For example, on the 386, QImode regs
1224 can appear within SImode subregs. Although GENERAL_REGS
1225 can handle SImode, QImode needs a smaller class. */
1226#ifdef LIMIT_RELOAD_CLASS
1227 if (in_subreg_loc)
1228 class = LIMIT_RELOAD_CLASS (inmode, class);
1229 else if (in != 0 && GET_CODE (in) == SUBREG)

--- 11 unchanged lines hidden (view full) ---

1241 {
1242 enum machine_mode mode;
1243 if (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (outmode))
1244 mode = inmode;
1245 else
1246 mode = outmode;
1247 if (mode == VOIDmode)
1248 {
1254 error_for_asm (this_insn, "cannot reload integer constant operand in `asm'");
1249 error_for_asm (this_insn, "cannot reload integer constant "
1250 "operand in %<asm%>");
1255 mode = word_mode;
1256 if (in != 0)
1257 inmode = word_mode;
1258 if (out != 0)
1259 outmode = word_mode;
1260 }
1261 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1262 if (HARD_REGNO_MODE_OK (i, mode)
1263 && TEST_HARD_REG_BIT (reg_class_contents[(int) class], i))
1264 {
1251 mode = word_mode;
1252 if (in != 0)
1253 inmode = word_mode;
1254 if (out != 0)
1255 outmode = word_mode;
1256 }
1257 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1258 if (HARD_REGNO_MODE_OK (i, mode)
1259 && TEST_HARD_REG_BIT (reg_class_contents[(int) class], i))
1260 {
1265 int nregs = HARD_REGNO_NREGS (i, mode);
1261 int nregs = hard_regno_nregs[i][mode];
1266
1267 int j;
1268 for (j = 1; j < nregs; j++)
1269 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], i + j))
1270 break;
1271 if (j == nregs)
1272 break;
1273 }
1274 if (i == FIRST_PSEUDO_REGISTER)
1275 {
1262
1263 int j;
1264 for (j = 1; j < nregs; j++)
1265 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], i + j))
1266 break;
1267 if (j == nregs)
1268 break;
1269 }
1270 if (i == FIRST_PSEUDO_REGISTER)
1271 {
1276 error_for_asm (this_insn, "impossible register constraint in `asm'");
1277 class = ALL_REGS;
1272 error_for_asm (this_insn, "impossible register constraint "
1273 "in %<asm%>");
1274 /* Avoid further trouble with this insn. */
1275 PATTERN (this_insn) = gen_rtx_USE (VOIDmode, const0_rtx);
1276 /* We used to continue here setting class to ALL_REGS, but it triggers
1277 sanity check on i386 for:
1278 void foo(long double d)
1279 {
1280 asm("" :: "a" (d));
1281 }
1282 Returning zero here ought to be safe as we take care in
1283 find_reloads to not process the reloads when instruction was
1284 replaced by USE. */
1285
1286 return 0;
1278 }
1279 }
1280
1281 /* Optional output reloads are always OK even if we have no register class,
1282 since the function of these reloads is only to have spill_reg_store etc.
1283 set, so that the storing insn can be deleted later. */
1287 }
1288 }
1289
1290 /* Optional output reloads are always OK even if we have no register class,
1291 since the function of these reloads is only to have spill_reg_store etc.
1292 set, so that the storing insn can be deleted later. */
1284 if (class == NO_REGS
1285 && (optional == 0 || type != RELOAD_FOR_OUTPUT))
1286 abort ();
1293 gcc_assert (class != NO_REGS
1294 || (optional != 0 && type == RELOAD_FOR_OUTPUT));
1287
1288 i = find_reusable_reload (&in, out, class, type, opnum, dont_share);
1289
1290 if (i == n_reloads)
1291 {
1292 /* See if we need a secondary reload register to move between CLASS
1293 and IN or CLASS and OUT. Get the icode and push any required reloads
1294 needed for each of them if so. */
1295
1295
1296 i = find_reusable_reload (&in, out, class, type, opnum, dont_share);
1297
1298 if (i == n_reloads)
1299 {
1300 /* See if we need a secondary reload register to move between CLASS
1301 and IN or CLASS and OUT. Get the icode and push any required reloads
1302 needed for each of them if so. */
1303
1296#ifdef SECONDARY_INPUT_RELOAD_CLASS
1297 if (in != 0)
1298 secondary_in_reload
1299 = push_secondary_reload (1, in, opnum, optional, class, inmode, type,
1304 if (in != 0)
1305 secondary_in_reload
1306 = push_secondary_reload (1, in, opnum, optional, class, inmode, type,
1300 &secondary_in_icode);
1301#endif
1302
1303#ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1307 &secondary_in_icode, NULL);
1304 if (out != 0 && GET_CODE (out) != SCRATCH)
1305 secondary_out_reload
1306 = push_secondary_reload (0, out, opnum, optional, class, outmode,
1308 if (out != 0 && GET_CODE (out) != SCRATCH)
1309 secondary_out_reload
1310 = push_secondary_reload (0, out, opnum, optional, class, outmode,
1307 type, &secondary_out_icode);
1308#endif
1311 type, &secondary_out_icode, NULL);
1309
1310 /* We found no existing reload suitable for re-use.
1311 So add an additional reload. */
1312
1313#ifdef SECONDARY_MEMORY_NEEDED
1314 /* If a memory location is needed for the copy, make one. */
1312
1313 /* We found no existing reload suitable for re-use.
1314 So add an additional reload. */
1315
1316#ifdef SECONDARY_MEMORY_NEEDED
1317 /* If a memory location is needed for the copy, make one. */
1315 if (in != 0 && (GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
1318 if (in != 0
1319 && (REG_P (in)
1320 || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
1316 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
1317 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
1318 class, inmode))
1319 get_secondary_mem (in, inmode, opnum, type);
1320#endif
1321
1322 i = n_reloads;
1323 rld[i].in = in;

--- 13 unchanged lines hidden (view full) ---

1337 rld[i].secondary_out_reload = secondary_out_reload;
1338 rld[i].secondary_in_icode = secondary_in_icode;
1339 rld[i].secondary_out_icode = secondary_out_icode;
1340 rld[i].secondary_p = 0;
1341
1342 n_reloads++;
1343
1344#ifdef SECONDARY_MEMORY_NEEDED
1321 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
1322 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
1323 class, inmode))
1324 get_secondary_mem (in, inmode, opnum, type);
1325#endif
1326
1327 i = n_reloads;
1328 rld[i].in = in;

--- 13 unchanged lines hidden (view full) ---

1342 rld[i].secondary_out_reload = secondary_out_reload;
1343 rld[i].secondary_in_icode = secondary_in_icode;
1344 rld[i].secondary_out_icode = secondary_out_icode;
1345 rld[i].secondary_p = 0;
1346
1347 n_reloads++;
1348
1349#ifdef SECONDARY_MEMORY_NEEDED
1345 if (out != 0 && (GET_CODE (out) == REG || GET_CODE (out) == SUBREG)
1350 if (out != 0
1351 && (REG_P (out)
1352 || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
1346 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
1347 && SECONDARY_MEMORY_NEEDED (class,
1348 REGNO_REG_CLASS (reg_or_subregno (out)),
1349 outmode))
1350 get_secondary_mem (out, outmode, opnum, type);
1351#endif
1352 }
1353 else

--- 78 unchanged lines hidden (view full) ---

1432 if (out != 0 && sets_cc0_p (PATTERN (this_insn)))
1433 {
1434 out = 0;
1435 rld[i].out = 0;
1436 rld[i].inc = find_inc_amount (PATTERN (this_insn), in);
1437 /* If we did not find a nonzero amount-to-increment-by,
1438 that contradicts the belief that IN is being incremented
1439 in an address in this insn. */
1353 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
1354 && SECONDARY_MEMORY_NEEDED (class,
1355 REGNO_REG_CLASS (reg_or_subregno (out)),
1356 outmode))
1357 get_secondary_mem (out, outmode, opnum, type);
1358#endif
1359 }
1360 else

--- 78 unchanged lines hidden (view full) ---

1439 if (out != 0 && sets_cc0_p (PATTERN (this_insn)))
1440 {
1441 out = 0;
1442 rld[i].out = 0;
1443 rld[i].inc = find_inc_amount (PATTERN (this_insn), in);
1444 /* If we did not find a nonzero amount-to-increment-by,
1445 that contradicts the belief that IN is being incremented
1446 in an address in this insn. */
1440 if (rld[i].inc == 0)
1441 abort ();
1447 gcc_assert (rld[i].inc != 0);
1442 }
1443#endif
1444
1445 /* If we will replace IN and OUT with the reload-reg,
1446 record where they are located so that substitution need
1447 not do a tree walk. */
1448
1449 if (replace_reloads)

--- 31 unchanged lines hidden (view full) ---

1481 rld[i].class, i,
1482 earlyclobber_operand_p (out));
1483
1484 /* If the outgoing register already contains the same value
1485 as the incoming one, we can dispense with loading it.
1486 The easiest way to tell the caller that is to give a phony
1487 value for the incoming operand (same as outgoing one). */
1488 if (rld[i].reg_rtx == out
1448 }
1449#endif
1450
1451 /* If we will replace IN and OUT with the reload-reg,
1452 record where they are located so that substitution need
1453 not do a tree walk. */
1454
1455 if (replace_reloads)

--- 31 unchanged lines hidden (view full) ---

1487 rld[i].class, i,
1488 earlyclobber_operand_p (out));
1489
1490 /* If the outgoing register already contains the same value
1491 as the incoming one, we can dispense with loading it.
1492 The easiest way to tell the caller that is to give a phony
1493 value for the incoming operand (same as outgoing one). */
1494 if (rld[i].reg_rtx == out
1489 && (GET_CODE (in) == REG || CONSTANT_P (in))
1495 && (REG_P (in) || CONSTANT_P (in))
1490 && 0 != find_equiv_reg (in, this_insn, 0, REGNO (out),
1491 static_reload_reg_p, i, inmode))
1492 rld[i].in = out;
1493 }
1494
1495 /* If this is an input reload and the operand contains a register that
1496 dies in this insn and is used nowhere else, see if it is the right class
1497 to be used for this reload. Use it if so. (This occurs most commonly
1498 in the case of paradoxical SUBREGs and in-out reloads). We cannot do
1499 this if it is also an output reload that mentions the register unless
1500 the output is a SUBREG that clobbers an entire register.
1501
1502 Note that the operand might be one of the spill regs, if it is a
1503 pseudo reg and we are in a block where spilling has not taken place.
1504 But if there is no spilling in this block, that is OK.
1505 An explicitly used hard reg cannot be a spill reg. */
1506
1496 && 0 != find_equiv_reg (in, this_insn, 0, REGNO (out),
1497 static_reload_reg_p, i, inmode))
1498 rld[i].in = out;
1499 }
1500
1501 /* If this is an input reload and the operand contains a register that
1502 dies in this insn and is used nowhere else, see if it is the right class
1503 to be used for this reload. Use it if so. (This occurs most commonly
1504 in the case of paradoxical SUBREGs and in-out reloads). We cannot do
1505 this if it is also an output reload that mentions the register unless
1506 the output is a SUBREG that clobbers an entire register.
1507
1508 Note that the operand might be one of the spill regs, if it is a
1509 pseudo reg and we are in a block where spilling has not taken place.
1510 But if there is no spilling in this block, that is OK.
1511 An explicitly used hard reg cannot be a spill reg. */
1512
1507 if (rld[i].reg_rtx == 0 && in != 0)
1513 if (rld[i].reg_rtx == 0 && in != 0 && hard_regs_live_known)
1508 {
1509 rtx note;
1510 int regno;
1511 enum machine_mode rel_mode = inmode;
1512
1513 if (out && GET_MODE_SIZE (outmode) > GET_MODE_SIZE (inmode))
1514 rel_mode = outmode;
1515
1516 for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1))
1517 if (REG_NOTE_KIND (note) == REG_DEAD
1514 {
1515 rtx note;
1516 int regno;
1517 enum machine_mode rel_mode = inmode;
1518
1519 if (out && GET_MODE_SIZE (outmode) > GET_MODE_SIZE (inmode))
1520 rel_mode = outmode;
1521
1522 for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1))
1523 if (REG_NOTE_KIND (note) == REG_DEAD
1518 && GET_CODE (XEXP (note, 0)) == REG
1524 && REG_P (XEXP (note, 0))
1519 && (regno = REGNO (XEXP (note, 0))) < FIRST_PSEUDO_REGISTER
1520 && reg_mentioned_p (XEXP (note, 0), in)
1525 && (regno = REGNO (XEXP (note, 0))) < FIRST_PSEUDO_REGISTER
1526 && reg_mentioned_p (XEXP (note, 0), in)
1527 /* Check that we don't use a hardreg for an uninitialized
1528 pseudo. See also find_dummy_reload(). */
1529 && (ORIGINAL_REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER
1530 || ! bitmap_bit_p (ENTRY_BLOCK_PTR->il.rtl->global_live_at_end,
1531 ORIGINAL_REGNO (XEXP (note, 0))))
1521 && ! refers_to_regno_for_reload_p (regno,
1522 (regno
1532 && ! refers_to_regno_for_reload_p (regno,
1533 (regno
1523 + HARD_REGNO_NREGS (regno,
1524 rel_mode)),
1534 + hard_regno_nregs[regno]
1535 [rel_mode]),
1525 PATTERN (this_insn), inloc)
1526 /* If this is also an output reload, IN cannot be used as
1527 the reload register if it is set in this insn unless IN
1528 is also OUT. */
1529 && (out == 0 || in == out
1530 || ! hard_reg_set_here_p (regno,
1531 (regno
1536 PATTERN (this_insn), inloc)
1537 /* If this is also an output reload, IN cannot be used as
1538 the reload register if it is set in this insn unless IN
1539 is also OUT. */
1540 && (out == 0 || in == out
1541 || ! hard_reg_set_here_p (regno,
1542 (regno
1532 + HARD_REGNO_NREGS (regno,
1533 rel_mode)),
1543 + hard_regno_nregs[regno]
1544 [rel_mode]),
1534 PATTERN (this_insn)))
1535 /* ??? Why is this code so different from the previous?
1536 Is there any simple coherent way to describe the two together?
1537 What's going on here. */
1538 && (in != out
1539 || (GET_CODE (in) == SUBREG
1540 && (((GET_MODE_SIZE (GET_MODE (in)) + (UNITS_PER_WORD - 1))
1541 / UNITS_PER_WORD)
1542 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
1543 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
1544 /* Make sure the operand fits in the reg that dies. */
1545 && (GET_MODE_SIZE (rel_mode)
1546 <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0))))
1547 && HARD_REGNO_MODE_OK (regno, inmode)
1548 && HARD_REGNO_MODE_OK (regno, outmode))
1549 {
1550 unsigned int offs;
1545 PATTERN (this_insn)))
1546 /* ??? Why is this code so different from the previous?
1547 Is there any simple coherent way to describe the two together?
1548 What's going on here. */
1549 && (in != out
1550 || (GET_CODE (in) == SUBREG
1551 && (((GET_MODE_SIZE (GET_MODE (in)) + (UNITS_PER_WORD - 1))
1552 / UNITS_PER_WORD)
1553 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
1554 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
1555 /* Make sure the operand fits in the reg that dies. */
1556 && (GET_MODE_SIZE (rel_mode)
1557 <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0))))
1558 && HARD_REGNO_MODE_OK (regno, inmode)
1559 && HARD_REGNO_MODE_OK (regno, outmode))
1560 {
1561 unsigned int offs;
1551 unsigned int nregs = MAX (HARD_REGNO_NREGS (regno, inmode),
1552 HARD_REGNO_NREGS (regno, outmode));
1562 unsigned int nregs = MAX (hard_regno_nregs[regno][inmode],
1563 hard_regno_nregs[regno][outmode]);
1553
1554 for (offs = 0; offs < nregs; offs++)
1555 if (fixed_regs[regno + offs]
1556 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) class],
1557 regno + offs))
1558 break;
1559
1560 if (offs == nregs
1561 && (! (refers_to_regno_for_reload_p
1564
1565 for (offs = 0; offs < nregs; offs++)
1566 if (fixed_regs[regno + offs]
1567 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) class],
1568 regno + offs))
1569 break;
1570
1571 if (offs == nregs
1572 && (! (refers_to_regno_for_reload_p
1562 (regno, (regno + HARD_REGNO_NREGS (regno, inmode)),
1573 (regno, (regno + hard_regno_nregs[regno][inmode]),
1563 in, (rtx *)0))
1564 || can_reload_into (in, regno, inmode)))
1565 {
1566 rld[i].reg_rtx = gen_rtx_REG (rel_mode, regno);
1567 break;
1568 }
1569 }
1570 }

--- 178 unchanged lines hidden (view full) ---

1749 || (! reg_overlap_mentioned_for_reload_p (rld[output_reload].out,
1750 rld[i].in)
1751 /* However, if the input is a register that appears inside
1752 the output, then we also can't share.
1753 Imagine (set (mem (reg 69)) (plus (reg 69) ...)).
1754 If the same reload reg is used for both reg 69 and the
1755 result to be stored in memory, then that result
1756 will clobber the address of the memory ref. */
1574 in, (rtx *)0))
1575 || can_reload_into (in, regno, inmode)))
1576 {
1577 rld[i].reg_rtx = gen_rtx_REG (rel_mode, regno);
1578 break;
1579 }
1580 }
1581 }

--- 178 unchanged lines hidden (view full) ---

1760 || (! reg_overlap_mentioned_for_reload_p (rld[output_reload].out,
1761 rld[i].in)
1762 /* However, if the input is a register that appears inside
1763 the output, then we also can't share.
1764 Imagine (set (mem (reg 69)) (plus (reg 69) ...)).
1765 If the same reload reg is used for both reg 69 and the
1766 result to be stored in memory, then that result
1767 will clobber the address of the memory ref. */
1757 && ! (GET_CODE (rld[i].in) == REG
1768 && ! (REG_P (rld[i].in)
1758 && reg_overlap_mentioned_for_reload_p (rld[i].in,
1759 rld[output_reload].out))))
1760 && ! reload_inner_reg_of_subreg (rld[i].in, rld[i].inmode,
1761 rld[i].when_needed != RELOAD_FOR_INPUT)
1762 && (reg_class_size[(int) rld[i].class]
1763 || SMALL_REGISTER_CLASSES)
1764 /* We will allow making things slightly worse by combining an
1765 input and an output, but no worse than that. */

--- 52 unchanged lines hidden (view full) ---

1818 || insn_data[INSN_CODE (this_insn)].operand[i].constraint[0] == '+')
1819 return;
1820
1821 /* See if some hard register that dies in this insn and is not used in
1822 the output is the right class. Only works if the register we pick
1823 up can fully hold our output reload. */
1824 for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1))
1825 if (REG_NOTE_KIND (note) == REG_DEAD
1769 && reg_overlap_mentioned_for_reload_p (rld[i].in,
1770 rld[output_reload].out))))
1771 && ! reload_inner_reg_of_subreg (rld[i].in, rld[i].inmode,
1772 rld[i].when_needed != RELOAD_FOR_INPUT)
1773 && (reg_class_size[(int) rld[i].class]
1774 || SMALL_REGISTER_CLASSES)
1775 /* We will allow making things slightly worse by combining an
1776 input and an output, but no worse than that. */

--- 52 unchanged lines hidden (view full) ---

1829 || insn_data[INSN_CODE (this_insn)].operand[i].constraint[0] == '+')
1830 return;
1831
1832 /* See if some hard register that dies in this insn and is not used in
1833 the output is the right class. Only works if the register we pick
1834 up can fully hold our output reload. */
1835 for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1))
1836 if (REG_NOTE_KIND (note) == REG_DEAD
1826 && GET_CODE (XEXP (note, 0)) == REG
1837 && REG_P (XEXP (note, 0))
1827 && ! reg_overlap_mentioned_for_reload_p (XEXP (note, 0),
1828 rld[output_reload].out)
1829 && REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER
1830 && HARD_REGNO_MODE_OK (REGNO (XEXP (note, 0)), rld[output_reload].outmode)
1831 && TEST_HARD_REG_BIT (reg_class_contents[(int) rld[output_reload].class],
1832 REGNO (XEXP (note, 0)))
1838 && ! reg_overlap_mentioned_for_reload_p (XEXP (note, 0),
1839 rld[output_reload].out)
1840 && REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER
1841 && HARD_REGNO_MODE_OK (REGNO (XEXP (note, 0)), rld[output_reload].outmode)
1842 && TEST_HARD_REG_BIT (reg_class_contents[(int) rld[output_reload].class],
1843 REGNO (XEXP (note, 0)))
1833 && (HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), rld[output_reload].outmode)
1834 <= HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), GET_MODE (XEXP (note, 0))))
1844 && (hard_regno_nregs[REGNO (XEXP (note, 0))][rld[output_reload].outmode]
1845 <= hard_regno_nregs[REGNO (XEXP (note, 0))][GET_MODE (XEXP (note, 0))])
1835 /* Ensure that a secondary or tertiary reload for this output
1836 won't want this register. */
1837 && ((secondary_out = rld[output_reload].secondary_out_reload) == -1
1838 || (! (TEST_HARD_REG_BIT
1839 (reg_class_contents[(int) rld[secondary_out].class],
1840 REGNO (XEXP (note, 0))))
1841 && ((secondary_out = rld[secondary_out].secondary_out_reload) == -1
1842 || ! (TEST_HARD_REG_BIT
1843 (reg_class_contents[(int) rld[secondary_out].class],
1844 REGNO (XEXP (note, 0)))))))
1846 /* Ensure that a secondary or tertiary reload for this output
1847 won't want this register. */
1848 && ((secondary_out = rld[output_reload].secondary_out_reload) == -1
1849 || (! (TEST_HARD_REG_BIT
1850 (reg_class_contents[(int) rld[secondary_out].class],
1851 REGNO (XEXP (note, 0))))
1852 && ((secondary_out = rld[secondary_out].secondary_out_reload) == -1
1853 || ! (TEST_HARD_REG_BIT
1854 (reg_class_contents[(int) rld[secondary_out].class],
1855 REGNO (XEXP (note, 0)))))))
1845 && ! fixed_regs[REGNO (XEXP (note, 0))])
1856 && ! fixed_regs[REGNO (XEXP (note, 0))]
1857 /* Check that we don't use a hardreg for an uninitialized
1858 pseudo. See also find_dummy_reload(). */
1859 && (ORIGINAL_REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER
1860 || ! bitmap_bit_p (ENTRY_BLOCK_PTR->il.rtl->global_live_at_end,
1861 ORIGINAL_REGNO (XEXP (note, 0)))))
1846 {
1847 rld[output_reload].reg_rtx
1848 = gen_rtx_REG (rld[output_reload].outmode,
1849 REGNO (XEXP (note, 0)));
1850 return;
1851 }
1852}
1853

--- 36 unchanged lines hidden (view full) ---

1890 return 0;
1891
1892 /* Note that {in,out}_offset are needed only when 'in' or 'out'
1893 respectively refers to a hard register. */
1894
1895 /* Find the inside of any subregs. */
1896 while (GET_CODE (out) == SUBREG)
1897 {
1862 {
1863 rld[output_reload].reg_rtx
1864 = gen_rtx_REG (rld[output_reload].outmode,
1865 REGNO (XEXP (note, 0)));
1866 return;
1867 }
1868}
1869

--- 36 unchanged lines hidden (view full) ---

1906 return 0;
1907
1908 /* Note that {in,out}_offset are needed only when 'in' or 'out'
1909 respectively refers to a hard register. */
1910
1911 /* Find the inside of any subregs. */
1912 while (GET_CODE (out) == SUBREG)
1913 {
1898 if (GET_CODE (SUBREG_REG (out)) == REG
1914 if (REG_P (SUBREG_REG (out))
1899 && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER)
1900 out_offset += subreg_regno_offset (REGNO (SUBREG_REG (out)),
1901 GET_MODE (SUBREG_REG (out)),
1902 SUBREG_BYTE (out),
1903 GET_MODE (out));
1904 out = SUBREG_REG (out);
1905 }
1906 while (GET_CODE (in) == SUBREG)
1907 {
1915 && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER)
1916 out_offset += subreg_regno_offset (REGNO (SUBREG_REG (out)),
1917 GET_MODE (SUBREG_REG (out)),
1918 SUBREG_BYTE (out),
1919 GET_MODE (out));
1920 out = SUBREG_REG (out);
1921 }
1922 while (GET_CODE (in) == SUBREG)
1923 {
1908 if (GET_CODE (SUBREG_REG (in)) == REG
1924 if (REG_P (SUBREG_REG (in))
1909 && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER)
1910 in_offset += subreg_regno_offset (REGNO (SUBREG_REG (in)),
1911 GET_MODE (SUBREG_REG (in)),
1912 SUBREG_BYTE (in),
1913 GET_MODE (in));
1914 in = SUBREG_REG (in);
1915 }
1916
1917 /* Narrow down the reg class, the same way push_reload will;
1918 otherwise we might find a dummy now, but push_reload won't. */
1925 && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER)
1926 in_offset += subreg_regno_offset (REGNO (SUBREG_REG (in)),
1927 GET_MODE (SUBREG_REG (in)),
1928 SUBREG_BYTE (in),
1929 GET_MODE (in));
1930 in = SUBREG_REG (in);
1931 }
1932
1933 /* Narrow down the reg class, the same way push_reload will;
1934 otherwise we might find a dummy now, but push_reload won't. */
1919 class = PREFERRED_RELOAD_CLASS (in, class);
1935 {
1936 enum reg_class preferred_class = PREFERRED_RELOAD_CLASS (in, class);
1937 if (preferred_class != NO_REGS)
1938 class = preferred_class;
1939 }
1920
1921 /* See if OUT will do. */
1940
1941 /* See if OUT will do. */
1922 if (GET_CODE (out) == REG
1942 if (REG_P (out)
1923 && REGNO (out) < FIRST_PSEUDO_REGISTER)
1924 {
1925 unsigned int regno = REGNO (out) + out_offset;
1943 && REGNO (out) < FIRST_PSEUDO_REGISTER)
1944 {
1945 unsigned int regno = REGNO (out) + out_offset;
1926 unsigned int nwords = HARD_REGNO_NREGS (regno, outmode);
1946 unsigned int nwords = hard_regno_nregs[regno][outmode];
1927 rtx saved_rtx;
1928
1929 /* When we consider whether the insn uses OUT,
1930 ignore references within IN. They don't prevent us
1931 from copying IN into OUT, because those refs would
1932 move into the insn that reloads IN.
1933
1934 However, we only ignore IN in its role as this reload.

--- 12 unchanged lines hidden (view full) ---

1947
1948 for (i = 0; i < nwords; i++)
1949 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class],
1950 regno + i))
1951 break;
1952
1953 if (i == nwords)
1954 {
1947 rtx saved_rtx;
1948
1949 /* When we consider whether the insn uses OUT,
1950 ignore references within IN. They don't prevent us
1951 from copying IN into OUT, because those refs would
1952 move into the insn that reloads IN.
1953
1954 However, we only ignore IN in its role as this reload.

--- 12 unchanged lines hidden (view full) ---

1967
1968 for (i = 0; i < nwords; i++)
1969 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class],
1970 regno + i))
1971 break;
1972
1973 if (i == nwords)
1974 {
1955 if (GET_CODE (real_out) == REG)
1975 if (REG_P (real_out))
1956 value = real_out;
1957 else
1958 value = gen_rtx_REG (outmode, regno);
1959 }
1960 }
1961
1962 *inloc = saved_rtx;
1963 }
1964
1965 /* Consider using IN if OUT was not acceptable
1966 or if OUT dies in this insn (like the quotient in a divmod insn).
1967 We can't use IN unless it is dies in this insn,
1968 which means we must know accurately which hard regs are live.
1969 Also, the result can't go in IN if IN is used within OUT,
1970 or if OUT is an earlyclobber and IN appears elsewhere in the insn. */
1971 if (hard_regs_live_known
1976 value = real_out;
1977 else
1978 value = gen_rtx_REG (outmode, regno);
1979 }
1980 }
1981
1982 *inloc = saved_rtx;
1983 }
1984
1985 /* Consider using IN if OUT was not acceptable
1986 or if OUT dies in this insn (like the quotient in a divmod insn).
1987 We can't use IN unless it is dies in this insn,
1988 which means we must know accurately which hard regs are live.
1989 Also, the result can't go in IN if IN is used within OUT,
1990 or if OUT is an earlyclobber and IN appears elsewhere in the insn. */
1991 if (hard_regs_live_known
1972 && GET_CODE (in) == REG
1992 && REG_P (in)
1973 && REGNO (in) < FIRST_PSEUDO_REGISTER
1974 && (value == 0
1975 || find_reg_note (this_insn, REG_UNUSED, real_out))
1976 && find_reg_note (this_insn, REG_DEAD, real_in)
1977 && !fixed_regs[REGNO (in)]
1978 && HARD_REGNO_MODE_OK (REGNO (in),
1979 /* The only case where out and real_out might
1980 have different modes is where real_out
1981 is a subreg, and in that case, out
1982 has a real mode. */
1983 (GET_MODE (out) != VOIDmode
1993 && REGNO (in) < FIRST_PSEUDO_REGISTER
1994 && (value == 0
1995 || find_reg_note (this_insn, REG_UNUSED, real_out))
1996 && find_reg_note (this_insn, REG_DEAD, real_in)
1997 && !fixed_regs[REGNO (in)]
1998 && HARD_REGNO_MODE_OK (REGNO (in),
1999 /* The only case where out and real_out might
2000 have different modes is where real_out
2001 is a subreg, and in that case, out
2002 has a real mode. */
2003 (GET_MODE (out) != VOIDmode
1984 ? GET_MODE (out) : outmode)))
2004 ? GET_MODE (out) : outmode))
2005 /* But only do all this if we can be sure, that this input
2006 operand doesn't correspond with an uninitialized pseudoreg.
2007 global can assign some hardreg to it, which is the same as
2008 a different pseudo also currently live (as it can ignore the
2009 conflict). So we never must introduce writes to such hardregs,
2010 as they would clobber the other live pseudo using the same.
2011 See also PR20973. */
2012 && (ORIGINAL_REGNO (in) < FIRST_PSEUDO_REGISTER
2013 || ! bitmap_bit_p (ENTRY_BLOCK_PTR->il.rtl->global_live_at_end,
2014 ORIGINAL_REGNO (in))))
1985 {
1986 unsigned int regno = REGNO (in) + in_offset;
2015 {
2016 unsigned int regno = REGNO (in) + in_offset;
1987 unsigned int nwords = HARD_REGNO_NREGS (regno, inmode);
2017 unsigned int nwords = hard_regno_nregs[regno][inmode];
1988
1989 if (! refers_to_regno_for_reload_p (regno, regno + nwords, out, (rtx*) 0)
1990 && ! hard_reg_set_here_p (regno, regno + nwords,
1991 PATTERN (this_insn))
1992 && (! earlyclobber
1993 || ! refers_to_regno_for_reload_p (regno, regno + nwords,
1994 PATTERN (this_insn), inloc)))
1995 {

--- 6 unchanged lines hidden (view full) ---

2002
2003 if (i == nwords)
2004 {
2005 /* If we were going to use OUT as the reload reg
2006 and changed our mind, it means OUT is a dummy that
2007 dies here. So don't bother copying value to it. */
2008 if (for_real >= 0 && value == real_out)
2009 rld[for_real].out = 0;
2018
2019 if (! refers_to_regno_for_reload_p (regno, regno + nwords, out, (rtx*) 0)
2020 && ! hard_reg_set_here_p (regno, regno + nwords,
2021 PATTERN (this_insn))
2022 && (! earlyclobber
2023 || ! refers_to_regno_for_reload_p (regno, regno + nwords,
2024 PATTERN (this_insn), inloc)))
2025 {

--- 6 unchanged lines hidden (view full) ---

2032
2033 if (i == nwords)
2034 {
2035 /* If we were going to use OUT as the reload reg
2036 and changed our mind, it means OUT is a dummy that
2037 dies here. So don't bother copying value to it. */
2038 if (for_real >= 0 && value == real_out)
2039 rld[for_real].out = 0;
2010 if (GET_CODE (real_in) == REG)
2040 if (REG_P (real_in))
2011 value = real_in;
2012 else
2013 value = gen_rtx_REG (inmode, regno);
2014 }
2015 }
2016 }
2017
2018 return value;

--- 26 unchanged lines hidden (view full) ---

2045hard_reg_set_here_p (unsigned int beg_regno, unsigned int end_regno, rtx x)
2046{
2047 if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER)
2048 {
2049 rtx op0 = SET_DEST (x);
2050
2051 while (GET_CODE (op0) == SUBREG)
2052 op0 = SUBREG_REG (op0);
2041 value = real_in;
2042 else
2043 value = gen_rtx_REG (inmode, regno);
2044 }
2045 }
2046 }
2047
2048 return value;

--- 26 unchanged lines hidden (view full) ---

2075hard_reg_set_here_p (unsigned int beg_regno, unsigned int end_regno, rtx x)
2076{
2077 if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER)
2078 {
2079 rtx op0 = SET_DEST (x);
2080
2081 while (GET_CODE (op0) == SUBREG)
2082 op0 = SUBREG_REG (op0);
2053 if (GET_CODE (op0) == REG)
2083 if (REG_P (op0))
2054 {
2055 unsigned int r = REGNO (op0);
2056
2057 /* See if this reg overlaps range under consideration. */
2058 if (r < end_regno
2084 {
2085 unsigned int r = REGNO (op0);
2086
2087 /* See if this reg overlaps range under consideration. */
2088 if (r < end_regno
2059 && r + HARD_REGNO_NREGS (r, GET_MODE (op0)) > beg_regno)
2089 && r + hard_regno_nregs[r][GET_MODE (op0)] > beg_regno)
2060 return 1;
2061 }
2062 }
2063 else if (GET_CODE (x) == PARALLEL)
2064 {
2065 int i = XVECLEN (x, 0) - 1;
2066
2067 for (; i >= 0; i--)

--- 38 unchanged lines hidden (view full) ---

2106{
2107 int i;
2108 RTX_CODE code = GET_CODE (x);
2109 const char *fmt;
2110 int success_2;
2111
2112 if (x == y)
2113 return 1;
2090 return 1;
2091 }
2092 }
2093 else if (GET_CODE (x) == PARALLEL)
2094 {
2095 int i = XVECLEN (x, 0) - 1;
2096
2097 for (; i >= 0; i--)

--- 38 unchanged lines hidden (view full) ---

2136{
2137 int i;
2138 RTX_CODE code = GET_CODE (x);
2139 const char *fmt;
2140 int success_2;
2141
2142 if (x == y)
2143 return 1;
2114 if ((code == REG || (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG))
2115 && (GET_CODE (y) == REG || (GET_CODE (y) == SUBREG
2116 && GET_CODE (SUBREG_REG (y)) == REG)))
2144 if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
2145 && (REG_P (y) || (GET_CODE (y) == SUBREG
2146 && REG_P (SUBREG_REG (y)))))
2117 {
2118 int j;
2119
2120 if (code == SUBREG)
2121 {
2122 i = REGNO (SUBREG_REG (x));
2123 if (i >= FIRST_PSEUDO_REGISTER)
2124 goto slow;

--- 20 unchanged lines hidden (view full) ---

2145
2146 /* On a WORDS_BIG_ENDIAN machine, point to the last register of a
2147 multiple hard register group of scalar integer registers, so that
2148 for example (reg:DI 0) and (reg:SI 1) will be considered the same
2149 register. */
2150 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD
2151 && SCALAR_INT_MODE_P (GET_MODE (x))
2152 && i < FIRST_PSEUDO_REGISTER)
2147 {
2148 int j;
2149
2150 if (code == SUBREG)
2151 {
2152 i = REGNO (SUBREG_REG (x));
2153 if (i >= FIRST_PSEUDO_REGISTER)
2154 goto slow;

--- 20 unchanged lines hidden (view full) ---

2175
2176 /* On a WORDS_BIG_ENDIAN machine, point to the last register of a
2177 multiple hard register group of scalar integer registers, so that
2178 for example (reg:DI 0) and (reg:SI 1) will be considered the same
2179 register. */
2180 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD
2181 && SCALAR_INT_MODE_P (GET_MODE (x))
2182 && i < FIRST_PSEUDO_REGISTER)
2153 i += HARD_REGNO_NREGS (i, GET_MODE (x)) - 1;
2183 i += hard_regno_nregs[i][GET_MODE (x)] - 1;
2154 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (y)) > UNITS_PER_WORD
2155 && SCALAR_INT_MODE_P (GET_MODE (y))
2156 && j < FIRST_PSEUDO_REGISTER)
2184 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (y)) > UNITS_PER_WORD
2185 && SCALAR_INT_MODE_P (GET_MODE (y))
2186 && j < FIRST_PSEUDO_REGISTER)
2157 j += HARD_REGNO_NREGS (j, GET_MODE (y)) - 1;
2187 j += hard_regno_nregs[j][GET_MODE (y)] - 1;
2158
2159 return i == j;
2160 }
2161 /* If two operands must match, because they are really a single
2162 operand of an assembler insn, then two postincrements are invalid
2163 because the assembler insn would increment only once.
2164 On the other hand, a postincrement matches ordinary indexing
2165 if the postincrement is the output operand. */

--- 6 unchanged lines hidden (view full) ---

2172 In this case, return 2, since some callers need to do special
2173 things when this happens. */
2174 if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC
2175 || GET_CODE (y) == PRE_MODIFY)
2176 return operands_match_p (x, XEXP (y, 0)) ? 2 : 0;
2177
2178 slow:
2179
2188
2189 return i == j;
2190 }
2191 /* If two operands must match, because they are really a single
2192 operand of an assembler insn, then two postincrements are invalid
2193 because the assembler insn would increment only once.
2194 On the other hand, a postincrement matches ordinary indexing
2195 if the postincrement is the output operand. */

--- 6 unchanged lines hidden (view full) ---

2202 In this case, return 2, since some callers need to do special
2203 things when this happens. */
2204 if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC
2205 || GET_CODE (y) == PRE_MODIFY)
2206 return operands_match_p (x, XEXP (y, 0)) ? 2 : 0;
2207
2208 slow:
2209
2180 /* Now we have disposed of all the cases
2181 in which different rtx codes can match. */
2210 /* Now we have disposed of all the cases in which different rtx codes
2211 can match. */
2182 if (code != GET_CODE (y))
2183 return 0;
2212 if (code != GET_CODE (y))
2213 return 0;
2184 if (code == LABEL_REF)
2185 return XEXP (x, 0) == XEXP (y, 0);
2186 if (code == SYMBOL_REF)
2187 return XSTR (x, 0) == XSTR (y, 0);
2188
2189 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
2214
2215 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
2190
2191 if (GET_MODE (x) != GET_MODE (y))
2192 return 0;
2193
2216 if (GET_MODE (x) != GET_MODE (y))
2217 return 0;
2218
2219 switch (code)
2220 {
2221 case CONST_INT:
2222 case CONST_DOUBLE:
2223 return 0;
2224
2225 case LABEL_REF:
2226 return XEXP (x, 0) == XEXP (y, 0);
2227 case SYMBOL_REF:
2228 return XSTR (x, 0) == XSTR (y, 0);
2229
2230 default:
2231 break;
2232 }
2233
2194 /* Compare the elements. If any pair of corresponding elements
2195 fail to match, return 0 for the whole things. */
2196
2197 success_2 = 0;
2198 fmt = GET_RTX_FORMAT (code);
2199 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2200 {
2201 int val, j;

--- 34 unchanged lines hidden (view full) ---

2236 success_2 = 1;
2237 }
2238 break;
2239
2240 /* It is believed that rtx's at this level will never
2241 contain anything but integers and other rtx's,
2242 except for within LABEL_REFs and SYMBOL_REFs. */
2243 default:
2234 /* Compare the elements. If any pair of corresponding elements
2235 fail to match, return 0 for the whole things. */
2236
2237 success_2 = 0;
2238 fmt = GET_RTX_FORMAT (code);
2239 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2240 {
2241 int val, j;

--- 34 unchanged lines hidden (view full) ---

2276 success_2 = 1;
2277 }
2278 break;
2279
2280 /* It is believed that rtx's at this level will never
2281 contain anything but integers and other rtx's,
2282 except for within LABEL_REFs and SYMBOL_REFs. */
2283 default:
2244 abort ();
2284 gcc_unreachable ();
2245 }
2246 }
2247 return 1 + success_2;
2248}
2249
2250/* Describe the range of registers or memory referenced by X.
2251 If X is a register, set REG_FLAG and put the first register
2252 number into START and the last plus one into END.
2253 If X is a memory reference, put a base address into BASE
2254 and a range of integer offsets into START and END.
2255 If X is pushing on the stack, we can assume it causes no trouble,
2256 so we set the SAFE field. */
2257
2258static struct decomposition
2259decompose (rtx x)
2260{
2261 struct decomposition val;
2262 int all_const = 0;
2263
2285 }
2286 }
2287 return 1 + success_2;
2288}
2289
2290/* Describe the range of registers or memory referenced by X.
2291 If X is a register, set REG_FLAG and put the first register
2292 number into START and the last plus one into END.
2293 If X is a memory reference, put a base address into BASE
2294 and a range of integer offsets into START and END.
2295 If X is pushing on the stack, we can assume it causes no trouble,
2296 so we set the SAFE field. */
2297
2298static struct decomposition
2299decompose (rtx x)
2300{
2301 struct decomposition val;
2302 int all_const = 0;
2303
2264 val.reg_flag = 0;
2265 val.safe = 0;
2266 val.base = 0;
2267 if (GET_CODE (x) == MEM)
2268 {
2269 rtx base = NULL_RTX, offset = 0;
2270 rtx addr = XEXP (x, 0);
2304 memset (&val, 0, sizeof (val));
2271
2305
2272 if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == PRE_INC
2273 || GET_CODE (addr) == POST_DEC || GET_CODE (addr) == POST_INC)
2274 {
2275 val.base = XEXP (addr, 0);
2276 val.start = -GET_MODE_SIZE (GET_MODE (x));
2277 val.end = GET_MODE_SIZE (GET_MODE (x));
2278 val.safe = REGNO (val.base) == STACK_POINTER_REGNUM;
2279 return val;
2280 }
2281
2282 if (GET_CODE (addr) == PRE_MODIFY || GET_CODE (addr) == POST_MODIFY)
2283 {
2284 if (GET_CODE (XEXP (addr, 1)) == PLUS
2285 && XEXP (addr, 0) == XEXP (XEXP (addr, 1), 0)
2286 && CONSTANT_P (XEXP (XEXP (addr, 1), 1)))
2287 {
2288 val.base = XEXP (addr, 0);
2289 val.start = -INTVAL (XEXP (XEXP (addr, 1), 1));
2290 val.end = INTVAL (XEXP (XEXP (addr, 1), 1));
2291 val.safe = REGNO (val.base) == STACK_POINTER_REGNUM;
2292 return val;
2293 }
2294 }
2295
2296 if (GET_CODE (addr) == CONST)
2297 {
2298 addr = XEXP (addr, 0);
2299 all_const = 1;
2300 }
2301 if (GET_CODE (addr) == PLUS)
2302 {
2303 if (CONSTANT_P (XEXP (addr, 0)))
2304 {
2305 base = XEXP (addr, 1);
2306 offset = XEXP (addr, 0);
2307 }
2308 else if (CONSTANT_P (XEXP (addr, 1)))
2309 {
2310 base = XEXP (addr, 0);
2311 offset = XEXP (addr, 1);
2312 }
2313 }
2314
2315 if (offset == 0)
2316 {
2317 base = addr;
2318 offset = const0_rtx;
2319 }
2320 if (GET_CODE (offset) == CONST)
2321 offset = XEXP (offset, 0);
2322 if (GET_CODE (offset) == PLUS)
2323 {
2324 if (GET_CODE (XEXP (offset, 0)) == CONST_INT)
2325 {
2326 base = gen_rtx_PLUS (GET_MODE (base), base, XEXP (offset, 1));
2327 offset = XEXP (offset, 0);
2328 }
2329 else if (GET_CODE (XEXP (offset, 1)) == CONST_INT)
2330 {
2331 base = gen_rtx_PLUS (GET_MODE (base), base, XEXP (offset, 0));
2332 offset = XEXP (offset, 1);
2333 }
2334 else
2335 {
2336 base = gen_rtx_PLUS (GET_MODE (base), base, offset);
2337 offset = const0_rtx;
2338 }
2339 }
2340 else if (GET_CODE (offset) != CONST_INT)
2341 {
2342 base = gen_rtx_PLUS (GET_MODE (base), base, offset);
2343 offset = const0_rtx;
2344 }
2345
2346 if (all_const && GET_CODE (base) == PLUS)
2347 base = gen_rtx_CONST (GET_MODE (base), base);
2348
2349 if (GET_CODE (offset) != CONST_INT)
2350 abort ();
2351
2352 val.start = INTVAL (offset);
2353 val.end = val.start + GET_MODE_SIZE (GET_MODE (x));
2354 val.base = base;
2355 return val;
2356 }
2357 else if (GET_CODE (x) == REG)
2306 switch (GET_CODE (x))
2358 {
2307 {
2308 case MEM:
2309 {
2310 rtx base = NULL_RTX, offset = 0;
2311 rtx addr = XEXP (x, 0);
2312
2313 if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == PRE_INC
2314 || GET_CODE (addr) == POST_DEC || GET_CODE (addr) == POST_INC)
2315 {
2316 val.base = XEXP (addr, 0);
2317 val.start = -GET_MODE_SIZE (GET_MODE (x));
2318 val.end = GET_MODE_SIZE (GET_MODE (x));
2319 val.safe = REGNO (val.base) == STACK_POINTER_REGNUM;
2320 return val;
2321 }
2322
2323 if (GET_CODE (addr) == PRE_MODIFY || GET_CODE (addr) == POST_MODIFY)
2324 {
2325 if (GET_CODE (XEXP (addr, 1)) == PLUS
2326 && XEXP (addr, 0) == XEXP (XEXP (addr, 1), 0)
2327 && CONSTANT_P (XEXP (XEXP (addr, 1), 1)))
2328 {
2329 val.base = XEXP (addr, 0);
2330 val.start = -INTVAL (XEXP (XEXP (addr, 1), 1));
2331 val.end = INTVAL (XEXP (XEXP (addr, 1), 1));
2332 val.safe = REGNO (val.base) == STACK_POINTER_REGNUM;
2333 return val;
2334 }
2335 }
2336
2337 if (GET_CODE (addr) == CONST)
2338 {
2339 addr = XEXP (addr, 0);
2340 all_const = 1;
2341 }
2342 if (GET_CODE (addr) == PLUS)
2343 {
2344 if (CONSTANT_P (XEXP (addr, 0)))
2345 {
2346 base = XEXP (addr, 1);
2347 offset = XEXP (addr, 0);
2348 }
2349 else if (CONSTANT_P (XEXP (addr, 1)))
2350 {
2351 base = XEXP (addr, 0);
2352 offset = XEXP (addr, 1);
2353 }
2354 }
2355
2356 if (offset == 0)
2357 {
2358 base = addr;
2359 offset = const0_rtx;
2360 }
2361 if (GET_CODE (offset) == CONST)
2362 offset = XEXP (offset, 0);
2363 if (GET_CODE (offset) == PLUS)
2364 {
2365 if (GET_CODE (XEXP (offset, 0)) == CONST_INT)
2366 {
2367 base = gen_rtx_PLUS (GET_MODE (base), base, XEXP (offset, 1));
2368 offset = XEXP (offset, 0);
2369 }
2370 else if (GET_CODE (XEXP (offset, 1)) == CONST_INT)
2371 {
2372 base = gen_rtx_PLUS (GET_MODE (base), base, XEXP (offset, 0));
2373 offset = XEXP (offset, 1);
2374 }
2375 else
2376 {
2377 base = gen_rtx_PLUS (GET_MODE (base), base, offset);
2378 offset = const0_rtx;
2379 }
2380 }
2381 else if (GET_CODE (offset) != CONST_INT)
2382 {
2383 base = gen_rtx_PLUS (GET_MODE (base), base, offset);
2384 offset = const0_rtx;
2385 }
2386
2387 if (all_const && GET_CODE (base) == PLUS)
2388 base = gen_rtx_CONST (GET_MODE (base), base);
2389
2390 gcc_assert (GET_CODE (offset) == CONST_INT);
2391
2392 val.start = INTVAL (offset);
2393 val.end = val.start + GET_MODE_SIZE (GET_MODE (x));
2394 val.base = base;
2395 }
2396 break;
2397
2398 case REG:
2359 val.reg_flag = 1;
2360 val.start = true_regnum (x);
2399 val.reg_flag = 1;
2400 val.start = true_regnum (x);
2361 if (val.start < 0)
2401 if (val.start < 0 || val.start >= FIRST_PSEUDO_REGISTER)
2362 {
2363 /* A pseudo with no hard reg. */
2364 val.start = REGNO (x);
2365 val.end = val.start + 1;
2366 }
2367 else
2368 /* A hard reg. */
2402 {
2403 /* A pseudo with no hard reg. */
2404 val.start = REGNO (x);
2405 val.end = val.start + 1;
2406 }
2407 else
2408 /* A hard reg. */
2369 val.end = val.start + HARD_REGNO_NREGS (val.start, GET_MODE (x));
2370 }
2371 else if (GET_CODE (x) == SUBREG)
2372 {
2373 if (GET_CODE (SUBREG_REG (x)) != REG)
2409 val.end = val.start + hard_regno_nregs[val.start][GET_MODE (x)];
2410 break;
2411
2412 case SUBREG:
2413 if (!REG_P (SUBREG_REG (x)))
2374 /* This could be more precise, but it's good enough. */
2375 return decompose (SUBREG_REG (x));
2376 val.reg_flag = 1;
2377 val.start = true_regnum (x);
2414 /* This could be more precise, but it's good enough. */
2415 return decompose (SUBREG_REG (x));
2416 val.reg_flag = 1;
2417 val.start = true_regnum (x);
2378 if (val.start < 0)
2418 if (val.start < 0 || val.start >= FIRST_PSEUDO_REGISTER)
2379 return decompose (SUBREG_REG (x));
2380 else
2381 /* A hard reg. */
2419 return decompose (SUBREG_REG (x));
2420 else
2421 /* A hard reg. */
2382 val.end = val.start + HARD_REGNO_NREGS (val.start, GET_MODE (x));
2422 val.end = val.start + hard_regno_nregs[val.start][GET_MODE (x)];
2423 break;
2424
2425 case SCRATCH:
2426 /* This hasn't been assigned yet, so it can't conflict yet. */
2427 val.safe = 1;
2428 break;
2429
2430 default:
2431 gcc_assert (CONSTANT_P (x));
2432 val.safe = 1;
2433 break;
2383 }
2434 }
2384 else if (CONSTANT_P (x)
2385 /* This hasn't been assigned yet, so it can't conflict yet. */
2386 || GET_CODE (x) == SCRATCH)
2387 val.safe = 1;
2388 else
2389 abort ();
2390 return val;
2391}
2392
2393/* Return 1 if altering Y will not modify the value of X.
2394 Y is also described by YDATA, which should be decompose (Y). */
2395
2396static int
2397immune_p (rtx x, rtx y, struct decomposition ydata)
2398{
2399 struct decomposition xdata;
2400
2401 if (ydata.reg_flag)
2402 return !refers_to_regno_for_reload_p (ydata.start, ydata.end, x, (rtx*) 0);
2403 if (ydata.safe)
2404 return 1;
2405
2435 return val;
2436}
2437
2438/* Return 1 if altering Y will not modify the value of X.
2439 Y is also described by YDATA, which should be decompose (Y). */
2440
2441static int
2442immune_p (rtx x, rtx y, struct decomposition ydata)
2443{
2444 struct decomposition xdata;
2445
2446 if (ydata.reg_flag)
2447 return !refers_to_regno_for_reload_p (ydata.start, ydata.end, x, (rtx*) 0);
2448 if (ydata.safe)
2449 return 1;
2450
2406 if (GET_CODE (y) != MEM)
2407 abort ();
2451 gcc_assert (MEM_P (y));
2408 /* If Y is memory and X is not, Y can't affect X. */
2452 /* If Y is memory and X is not, Y can't affect X. */
2409 if (GET_CODE (x) != MEM)
2453 if (!MEM_P (x))
2410 return 1;
2411
2412 xdata = decompose (x);
2413
2414 if (! rtx_equal_p (xdata.base, ydata.base))
2415 {
2416 /* If bases are distinct symbolic constants, there is no overlap. */
2417 if (CONSTANT_P (xdata.base) && CONSTANT_P (ydata.base))

--- 58 unchanged lines hidden (view full) ---

2476 int noperands;
2477 /* These start out as the constraints for the insn
2478 and they are chewed up as we consider alternatives. */
2479 char *constraints[MAX_RECOG_OPERANDS];
2480 /* These are the preferred classes for an operand, or NO_REGS if it isn't
2481 a register. */
2482 enum reg_class preferred_class[MAX_RECOG_OPERANDS];
2483 char pref_or_nothing[MAX_RECOG_OPERANDS];
2454 return 1;
2455
2456 xdata = decompose (x);
2457
2458 if (! rtx_equal_p (xdata.base, ydata.base))
2459 {
2460 /* If bases are distinct symbolic constants, there is no overlap. */
2461 if (CONSTANT_P (xdata.base) && CONSTANT_P (ydata.base))

--- 58 unchanged lines hidden (view full) ---

2520 int noperands;
2521 /* These start out as the constraints for the insn
2522 and they are chewed up as we consider alternatives. */
2523 char *constraints[MAX_RECOG_OPERANDS];
2524 /* These are the preferred classes for an operand, or NO_REGS if it isn't
2525 a register. */
2526 enum reg_class preferred_class[MAX_RECOG_OPERANDS];
2527 char pref_or_nothing[MAX_RECOG_OPERANDS];
2484 /* Nonzero for a MEM operand whose entire address needs a reload. */
2528 /* Nonzero for a MEM operand whose entire address needs a reload.
2529 May be -1 to indicate the entire address may or may not need a reload. */
2485 int address_reloaded[MAX_RECOG_OPERANDS];
2530 int address_reloaded[MAX_RECOG_OPERANDS];
2486 /* Nonzero for an address operand that needs to be completely reloaded. */
2531 /* Nonzero for an address operand that needs to be completely reloaded.
2532 May be -1 to indicate the entire operand may or may not need a reload. */
2487 int address_operand_reloaded[MAX_RECOG_OPERANDS];
2488 /* Value of enum reload_type to use for operand. */
2489 enum reload_type operand_type[MAX_RECOG_OPERANDS];
2490 /* Value of enum reload_type to use within address of operand. */
2491 enum reload_type address_type[MAX_RECOG_OPERANDS];
2492 /* Save the usage of each operand. */
2493 enum reload_usage { RELOAD_READ, RELOAD_READ_WRITE, RELOAD_WRITE } modified[MAX_RECOG_OPERANDS];
2494 int no_input_reloads = 0, no_output_reloads = 0;

--- 32 unchanged lines hidden (view full) ---

2527 n_earlyclobbers = 0;
2528 replace_reloads = replace;
2529 hard_regs_live_known = live_known;
2530 static_reload_reg_p = reload_reg_p;
2531
2532 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output reloads;
2533 neither are insns that SET cc0. Insns that use CC0 are not allowed
2534 to have any input reloads. */
2533 int address_operand_reloaded[MAX_RECOG_OPERANDS];
2534 /* Value of enum reload_type to use for operand. */
2535 enum reload_type operand_type[MAX_RECOG_OPERANDS];
2536 /* Value of enum reload_type to use within address of operand. */
2537 enum reload_type address_type[MAX_RECOG_OPERANDS];
2538 /* Save the usage of each operand. */
2539 enum reload_usage { RELOAD_READ, RELOAD_READ_WRITE, RELOAD_WRITE } modified[MAX_RECOG_OPERANDS];
2540 int no_input_reloads = 0, no_output_reloads = 0;

--- 32 unchanged lines hidden (view full) ---

2573 n_earlyclobbers = 0;
2574 replace_reloads = replace;
2575 hard_regs_live_known = live_known;
2576 static_reload_reg_p = reload_reg_p;
2577
2578 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output reloads;
2579 neither are insns that SET cc0. Insns that use CC0 are not allowed
2580 to have any input reloads. */
2535 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN)
2581 if (JUMP_P (insn) || CALL_P (insn))
2536 no_output_reloads = 1;
2537
2538#ifdef HAVE_cc0
2539 if (reg_referenced_p (cc0_rtx, PATTERN (insn)))
2540 no_input_reloads = 1;
2541 if (reg_set_p (cc0_rtx, PATTERN (insn)))
2542 no_output_reloads = 1;
2543#endif

--- 9 unchanged lines hidden (view full) ---

2553 secondary_memlocs_elim_used = 0;
2554 }
2555#endif
2556
2557 /* Dispose quickly of (set (reg..) (reg..)) if both have hard regs and it
2558 is cheap to move between them. If it is not, there may not be an insn
2559 to do the copy, so we may need a reload. */
2560 if (GET_CODE (body) == SET
2582 no_output_reloads = 1;
2583
2584#ifdef HAVE_cc0
2585 if (reg_referenced_p (cc0_rtx, PATTERN (insn)))
2586 no_input_reloads = 1;
2587 if (reg_set_p (cc0_rtx, PATTERN (insn)))
2588 no_output_reloads = 1;
2589#endif

--- 9 unchanged lines hidden (view full) ---

2599 secondary_memlocs_elim_used = 0;
2600 }
2601#endif
2602
2603 /* Dispose quickly of (set (reg..) (reg..)) if both have hard regs and it
2604 is cheap to move between them. If it is not, there may not be an insn
2605 to do the copy, so we may need a reload. */
2606 if (GET_CODE (body) == SET
2561 && GET_CODE (SET_DEST (body)) == REG
2607 && REG_P (SET_DEST (body))
2562 && REGNO (SET_DEST (body)) < FIRST_PSEUDO_REGISTER
2608 && REGNO (SET_DEST (body)) < FIRST_PSEUDO_REGISTER
2563 && GET_CODE (SET_SRC (body)) == REG
2609 && REG_P (SET_SRC (body))
2564 && REGNO (SET_SRC (body)) < FIRST_PSEUDO_REGISTER
2565 && REGISTER_MOVE_COST (GET_MODE (SET_SRC (body)),
2566 REGNO_REG_CLASS (REGNO (SET_SRC (body))),
2567 REGNO_REG_CLASS (REGNO (SET_DEST (body)))) == 2)
2568 return 0;
2569
2570 extract_insn (insn);
2571

--- 29 unchanged lines hidden (view full) ---

2601 modified[i] = RELOAD_READ;
2602
2603 /* Scan this operand's constraint to see if it is an output operand,
2604 an in-out operand, is commutative, or should match another. */
2605
2606 while ((c = *p))
2607 {
2608 p += CONSTRAINT_LEN (c, p);
2610 && REGNO (SET_SRC (body)) < FIRST_PSEUDO_REGISTER
2611 && REGISTER_MOVE_COST (GET_MODE (SET_SRC (body)),
2612 REGNO_REG_CLASS (REGNO (SET_SRC (body))),
2613 REGNO_REG_CLASS (REGNO (SET_DEST (body)))) == 2)
2614 return 0;
2615
2616 extract_insn (insn);
2617

--- 29 unchanged lines hidden (view full) ---

2647 modified[i] = RELOAD_READ;
2648
2649 /* Scan this operand's constraint to see if it is an output operand,
2650 an in-out operand, is commutative, or should match another. */
2651
2652 while ((c = *p))
2653 {
2654 p += CONSTRAINT_LEN (c, p);
2609 if (c == '=')
2610 modified[i] = RELOAD_WRITE;
2611 else if (c == '+')
2612 modified[i] = RELOAD_READ_WRITE;
2613 else if (c == '%')
2655 switch (c)
2614 {
2656 {
2615 /* The last operand should not be marked commutative. */
2616 if (i == noperands - 1)
2617 abort ();
2657 case '=':
2658 modified[i] = RELOAD_WRITE;
2659 break;
2660 case '+':
2661 modified[i] = RELOAD_READ_WRITE;
2662 break;
2663 case '%':
2664 {
2665 /* The last operand should not be marked commutative. */
2666 gcc_assert (i != noperands - 1);
2618
2667
2619 /* We currently only support one commutative pair of
2620 operands. Some existing asm code currently uses more
2621 than one pair. Previously, that would usually work,
2622 but sometimes it would crash the compiler. We
2623 continue supporting that case as well as we can by
2624 silently ignoring all but the first pair. In the
2625 future we may handle it correctly. */
2626 if (commutative < 0)
2627 commutative = i;
2628 else if (!this_insn_is_asm)
2629 abort ();
2630 }
2631 else if (ISDIGIT (c))
2632 {
2633 c = strtoul (p - 1, &p, 10);
2668 /* We currently only support one commutative pair of
2669 operands. Some existing asm code currently uses more
2670 than one pair. Previously, that would usually work,
2671 but sometimes it would crash the compiler. We
2672 continue supporting that case as well as we can by
2673 silently ignoring all but the first pair. In the
2674 future we may handle it correctly. */
2675 if (commutative < 0)
2676 commutative = i;
2677 else
2678 gcc_assert (this_insn_is_asm);
2679 }
2680 break;
2681 /* Use of ISDIGIT is tempting here, but it may get expensive because
2682 of locale support we don't want. */
2683 case '0': case '1': case '2': case '3': case '4':
2684 case '5': case '6': case '7': case '8': case '9':
2685 {
2686 c = strtoul (p - 1, &p, 10);
2634
2687
2635 operands_match[c][i]
2636 = operands_match_p (recog_data.operand[c],
2637 recog_data.operand[i]);
2688 operands_match[c][i]
2689 = operands_match_p (recog_data.operand[c],
2690 recog_data.operand[i]);
2638
2691
2639 /* An operand may not match itself. */
2640 if (c == i)
2641 abort ();
2692 /* An operand may not match itself. */
2693 gcc_assert (c != i);
2642
2694
2643 /* If C can be commuted with C+1, and C might need to match I,
2644 then C+1 might also need to match I. */
2645 if (commutative >= 0)
2646 {
2647 if (c == commutative || c == commutative + 1)
2648 {
2649 int other = c + (c == commutative ? 1 : -1);
2650 operands_match[other][i]
2651 = operands_match_p (recog_data.operand[other],
2652 recog_data.operand[i]);
2653 }
2654 if (i == commutative || i == commutative + 1)
2655 {
2656 int other = i + (i == commutative ? 1 : -1);
2657 operands_match[c][other]
2658 = operands_match_p (recog_data.operand[c],
2659 recog_data.operand[other]);
2660 }
2661 /* Note that C is supposed to be less than I.
2662 No need to consider altering both C and I because in
2663 that case we would alter one into the other. */
2664 }
2695 /* If C can be commuted with C+1, and C might need to match I,
2696 then C+1 might also need to match I. */
2697 if (commutative >= 0)
2698 {
2699 if (c == commutative || c == commutative + 1)
2700 {
2701 int other = c + (c == commutative ? 1 : -1);
2702 operands_match[other][i]
2703 = operands_match_p (recog_data.operand[other],
2704 recog_data.operand[i]);
2705 }
2706 if (i == commutative || i == commutative + 1)
2707 {
2708 int other = i + (i == commutative ? 1 : -1);
2709 operands_match[c][other]
2710 = operands_match_p (recog_data.operand[c],
2711 recog_data.operand[other]);
2712 }
2713 /* Note that C is supposed to be less than I.
2714 No need to consider altering both C and I because in
2715 that case we would alter one into the other. */
2716 }
2717 }
2665 }
2666 }
2667 }
2668
2669 /* Examine each operand that is a memory reference or memory address
2670 and reload parts of the addresses into index registers.
2671 Also here any references to pseudo regs that didn't get hard regs
2672 but are equivalent to constants get replaced in the insn itself

--- 24 unchanged lines hidden (view full) ---

2697 address_operand_reloaded[i]
2698 = find_reloads_address (recog_data.operand_mode[i], (rtx*) 0,
2699 recog_data.operand[i],
2700 recog_data.operand_loc[i],
2701 i, operand_type[i], ind_levels, insn);
2702
2703 /* If we now have a simple operand where we used to have a
2704 PLUS or MULT, re-recognize and try again. */
2718 }
2719 }
2720 }
2721
2722 /* Examine each operand that is a memory reference or memory address
2723 and reload parts of the addresses into index registers.
2724 Also here any references to pseudo regs that didn't get hard regs
2725 but are equivalent to constants get replaced in the insn itself

--- 24 unchanged lines hidden (view full) ---

2750 address_operand_reloaded[i]
2751 = find_reloads_address (recog_data.operand_mode[i], (rtx*) 0,
2752 recog_data.operand[i],
2753 recog_data.operand_loc[i],
2754 i, operand_type[i], ind_levels, insn);
2755
2756 /* If we now have a simple operand where we used to have a
2757 PLUS or MULT, re-recognize and try again. */
2705 if ((GET_RTX_CLASS (GET_CODE (*recog_data.operand_loc[i])) == 'o'
2758 if ((OBJECT_P (*recog_data.operand_loc[i])
2706 || GET_CODE (*recog_data.operand_loc[i]) == SUBREG)
2707 && (GET_CODE (recog_data.operand[i]) == MULT
2708 || GET_CODE (recog_data.operand[i]) == PLUS))
2709 {
2710 INSN_CODE (insn) = -1;
2711 retval = find_reloads (insn, replace, ind_levels, live_known,
2712 reload_reg_p);
2713 return retval;

--- 29 unchanged lines hidden (view full) ---

2743 &address_reloaded[i]);
2744
2745 /* If we made a MEM to load (a part of) the stackslot of a pseudo
2746 that didn't get a hard register, emit a USE with a REG_EQUAL
2747 note in front so that we might inherit a previous, possibly
2748 wider reload. */
2749
2750 if (replace
2759 || GET_CODE (*recog_data.operand_loc[i]) == SUBREG)
2760 && (GET_CODE (recog_data.operand[i]) == MULT
2761 || GET_CODE (recog_data.operand[i]) == PLUS))
2762 {
2763 INSN_CODE (insn) = -1;
2764 retval = find_reloads (insn, replace, ind_levels, live_known,
2765 reload_reg_p);
2766 return retval;

--- 29 unchanged lines hidden (view full) ---

2796 &address_reloaded[i]);
2797
2798 /* If we made a MEM to load (a part of) the stackslot of a pseudo
2799 that didn't get a hard register, emit a USE with a REG_EQUAL
2800 note in front so that we might inherit a previous, possibly
2801 wider reload. */
2802
2803 if (replace
2751 && GET_CODE (op) == MEM
2752 && GET_CODE (reg) == REG
2804 && MEM_P (op)
2805 && REG_P (reg)
2753 && (GET_MODE_SIZE (GET_MODE (reg))
2754 >= GET_MODE_SIZE (GET_MODE (op))))
2755 set_unique_reg_note (emit_insn_before (gen_rtx_USE (VOIDmode, reg),
2756 insn),
2757 REG_EQUAL, reg_equiv_memory_loc[REGNO (reg)]);
2758
2759 substed_operand[i] = recog_data.operand[i] = op;
2760 }
2806 && (GET_MODE_SIZE (GET_MODE (reg))
2807 >= GET_MODE_SIZE (GET_MODE (op))))
2808 set_unique_reg_note (emit_insn_before (gen_rtx_USE (VOIDmode, reg),
2809 insn),
2810 REG_EQUAL, reg_equiv_memory_loc[REGNO (reg)]);
2811
2812 substed_operand[i] = recog_data.operand[i] = op;
2813 }
2761 else if (code == PLUS || GET_RTX_CLASS (code) == '1')
2814 else if (code == PLUS || GET_RTX_CLASS (code) == RTX_UNARY)
2762 /* We can get a PLUS as an "operand" as a result of register
2763 elimination. See eliminate_regs and gen_reload. We handle
2764 a unary operator by reloading the operand. */
2765 substed_operand[i] = recog_data.operand[i]
2766 = find_reloads_toplev (recog_data.operand[i], i, address_type[i],
2767 ind_levels, 0, insn,
2768 &address_reloaded[i]);
2769 else if (code == REG)

--- 111 unchanged lines hidden (view full) ---

2881 /* Nonzero if a constant forced into memory would be OK for this
2882 operand. */
2883 int constmemok = 0;
2884 int earlyclobber = 0;
2885
2886 /* If the predicate accepts a unary operator, it means that
2887 we need to reload the operand, but do not do this for
2888 match_operator and friends. */
2815 /* We can get a PLUS as an "operand" as a result of register
2816 elimination. See eliminate_regs and gen_reload. We handle
2817 a unary operator by reloading the operand. */
2818 substed_operand[i] = recog_data.operand[i]
2819 = find_reloads_toplev (recog_data.operand[i], i, address_type[i],
2820 ind_levels, 0, insn,
2821 &address_reloaded[i]);
2822 else if (code == REG)

--- 111 unchanged lines hidden (view full) ---

2934 /* Nonzero if a constant forced into memory would be OK for this
2935 operand. */
2936 int constmemok = 0;
2937 int earlyclobber = 0;
2938
2939 /* If the predicate accepts a unary operator, it means that
2940 we need to reload the operand, but do not do this for
2941 match_operator and friends. */
2889 if (GET_RTX_CLASS (GET_CODE (operand)) == '1' && *p != 0)
2942 if (UNARY_P (operand) && *p != 0)
2890 operand = XEXP (operand, 0);
2891
2892 /* If the operand is a SUBREG, extract
2893 the REG or MEM (or maybe even a constant) within.
2894 (Constants can occur as a result of reg_equiv_constant.) */
2895
2896 while (GET_CODE (operand) == SUBREG)
2897 {
2898 /* Offset only matters when operand is a REG and
2899 it is a hard reg. This is because it is passed
2900 to reg_fits_class_p if it is a REG and all pseudos
2901 return 0 from that function. */
2943 operand = XEXP (operand, 0);
2944
2945 /* If the operand is a SUBREG, extract
2946 the REG or MEM (or maybe even a constant) within.
2947 (Constants can occur as a result of reg_equiv_constant.) */
2948
2949 while (GET_CODE (operand) == SUBREG)
2950 {
2951 /* Offset only matters when operand is a REG and
2952 it is a hard reg. This is because it is passed
2953 to reg_fits_class_p if it is a REG and all pseudos
2954 return 0 from that function. */
2902 if (GET_CODE (SUBREG_REG (operand)) == REG
2955 if (REG_P (SUBREG_REG (operand))
2903 && REGNO (SUBREG_REG (operand)) < FIRST_PSEUDO_REGISTER)
2904 {
2905 if (!subreg_offset_representable_p
2906 (REGNO (SUBREG_REG (operand)),
2907 GET_MODE (SUBREG_REG (operand)),
2908 SUBREG_BYTE (operand),
2909 GET_MODE (operand)))
2910 force_reload = 1;

--- 26 unchanged lines hidden (view full) ---

2937 This is doubly true if WORD_REGISTER_OPERATIONS. In
2938 this case eliminate_regs has left non-paradoxical
2939 subregs for push_reload to see. Make sure it does
2940 by forcing the reload.
2941
2942 ??? When is it right at this stage to have a subreg
2943 of a mem that is _not_ to be handled specially? IMO
2944 those should have been reduced to just a mem. */
2956 && REGNO (SUBREG_REG (operand)) < FIRST_PSEUDO_REGISTER)
2957 {
2958 if (!subreg_offset_representable_p
2959 (REGNO (SUBREG_REG (operand)),
2960 GET_MODE (SUBREG_REG (operand)),
2961 SUBREG_BYTE (operand),
2962 GET_MODE (operand)))
2963 force_reload = 1;

--- 26 unchanged lines hidden (view full) ---

2990 This is doubly true if WORD_REGISTER_OPERATIONS. In
2991 this case eliminate_regs has left non-paradoxical
2992 subregs for push_reload to see. Make sure it does
2993 by forcing the reload.
2994
2995 ??? When is it right at this stage to have a subreg
2996 of a mem that is _not_ to be handled specially? IMO
2997 those should have been reduced to just a mem. */
2945 || ((GET_CODE (operand) == MEM
2946 || (GET_CODE (operand)== REG
2998 || ((MEM_P (operand)
2999 || (REG_P (operand)
2947 && REGNO (operand) >= FIRST_PSEUDO_REGISTER))
2948#ifndef WORD_REGISTER_OPERATIONS
2949 && (((GET_MODE_BITSIZE (GET_MODE (operand))
2950 < BIGGEST_ALIGNMENT)
2951 && (GET_MODE_SIZE (operand_mode[i])
2952 > GET_MODE_SIZE (GET_MODE (operand))))
2953 || BYTES_BIG_ENDIAN
2954#ifdef LOAD_EXTEND_OP
2955 || (GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD
2956 && (GET_MODE_SIZE (GET_MODE (operand))
2957 <= UNITS_PER_WORD)
2958 && (GET_MODE_SIZE (operand_mode[i])
2959 > GET_MODE_SIZE (GET_MODE (operand)))
2960 && INTEGRAL_MODE_P (GET_MODE (operand))
3000 && REGNO (operand) >= FIRST_PSEUDO_REGISTER))
3001#ifndef WORD_REGISTER_OPERATIONS
3002 && (((GET_MODE_BITSIZE (GET_MODE (operand))
3003 < BIGGEST_ALIGNMENT)
3004 && (GET_MODE_SIZE (operand_mode[i])
3005 > GET_MODE_SIZE (GET_MODE (operand))))
3006 || BYTES_BIG_ENDIAN
3007#ifdef LOAD_EXTEND_OP
3008 || (GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD
3009 && (GET_MODE_SIZE (GET_MODE (operand))
3010 <= UNITS_PER_WORD)
3011 && (GET_MODE_SIZE (operand_mode[i])
3012 > GET_MODE_SIZE (GET_MODE (operand)))
3013 && INTEGRAL_MODE_P (GET_MODE (operand))
2961 && LOAD_EXTEND_OP (GET_MODE (operand)) != NIL)
3014 && LOAD_EXTEND_OP (GET_MODE (operand)) != UNKNOWN)
2962#endif
2963 )
2964#endif
2965 )
2966 )
2967 force_reload = 1;
2968 }
2969

--- 78 unchanged lines hidden (view full) ---

3048 [(i == commutative || i == commutative + 1)
3049 ? 2 * commutative + 1 - i : i])
3050 : operands_match[m][i])
3051 {
3052 /* If we are matching a non-offsettable address where an
3053 offsettable address was expected, then we must reject
3054 this combination, because we can't reload it. */
3055 if (this_alternative_offmemok[m]
3015#endif
3016 )
3017#endif
3018 )
3019 )
3020 force_reload = 1;
3021 }
3022

--- 78 unchanged lines hidden (view full) ---

3101 [(i == commutative || i == commutative + 1)
3102 ? 2 * commutative + 1 - i : i])
3103 : operands_match[m][i])
3104 {
3105 /* If we are matching a non-offsettable address where an
3106 offsettable address was expected, then we must reject
3107 this combination, because we can't reload it. */
3108 if (this_alternative_offmemok[m]
3056 && GET_CODE (recog_data.operand[m]) == MEM
3109 && MEM_P (recog_data.operand[m])
3057 && this_alternative[m] == (int) NO_REGS
3058 && ! this_alternative_win[m])
3059 bad = 1;
3060
3061 did_match = this_alternative_win[m];
3062 }
3063 else
3064 {

--- 49 unchanged lines hidden (view full) ---

3114 if (this_alternative_matches[j]
3115 == this_alternative_matches[i])
3116 badop = 1;
3117 break;
3118
3119 case 'p':
3120 /* All necessary reloads for an address_operand
3121 were handled in find_reloads_address. */
3110 && this_alternative[m] == (int) NO_REGS
3111 && ! this_alternative_win[m])
3112 bad = 1;
3113
3114 did_match = this_alternative_win[m];
3115 }
3116 else
3117 {

--- 49 unchanged lines hidden (view full) ---

3167 if (this_alternative_matches[j]
3168 == this_alternative_matches[i])
3169 badop = 1;
3170 break;
3171
3172 case 'p':
3173 /* All necessary reloads for an address_operand
3174 were handled in find_reloads_address. */
3122 this_alternative[i] = (int) MODE_BASE_REG_CLASS (VOIDmode);
3175 this_alternative[i]
3176 = (int) base_reg_class (VOIDmode, ADDRESS, SCRATCH);
3123 win = 1;
3124 badop = 0;
3125 break;
3126
3127 case 'm':
3128 if (force_reload)
3129 break;
3177 win = 1;
3178 badop = 0;
3179 break;
3180
3181 case 'm':
3182 if (force_reload)
3183 break;
3130 if (GET_CODE (operand) == MEM
3131 || (GET_CODE (operand) == REG
3184 if (MEM_P (operand)
3185 || (REG_P (operand)
3132 && REGNO (operand) >= FIRST_PSEUDO_REGISTER
3133 && reg_renumber[REGNO (operand)] < 0))
3134 win = 1;
3186 && REGNO (operand) >= FIRST_PSEUDO_REGISTER
3187 && reg_renumber[REGNO (operand)] < 0))
3188 win = 1;
3135 if (CONSTANT_P (operand)
3136 /* force_const_mem does not accept HIGH. */
3137 && GET_CODE (operand) != HIGH)
3189 if (CONST_POOL_OK_P (operand))
3138 badop = 0;
3139 constmemok = 1;
3140 break;
3141
3142 case '<':
3190 badop = 0;
3191 constmemok = 1;
3192 break;
3193
3194 case '<':
3143 if (GET_CODE (operand) == MEM
3195 if (MEM_P (operand)
3144 && ! address_reloaded[i]
3145 && (GET_CODE (XEXP (operand, 0)) == PRE_DEC
3146 || GET_CODE (XEXP (operand, 0)) == POST_DEC))
3147 win = 1;
3148 break;
3149
3150 case '>':
3196 && ! address_reloaded[i]
3197 && (GET_CODE (XEXP (operand, 0)) == PRE_DEC
3198 || GET_CODE (XEXP (operand, 0)) == POST_DEC))
3199 win = 1;
3200 break;
3201
3202 case '>':
3151 if (GET_CODE (operand) == MEM
3203 if (MEM_P (operand)
3152 && ! address_reloaded[i]
3153 && (GET_CODE (XEXP (operand, 0)) == PRE_INC
3154 || GET_CODE (XEXP (operand, 0)) == POST_INC))
3155 win = 1;
3156 break;
3157
3158 /* Memory operand whose address is not offsettable. */
3159 case 'V':
3160 if (force_reload)
3161 break;
3204 && ! address_reloaded[i]
3205 && (GET_CODE (XEXP (operand, 0)) == PRE_INC
3206 || GET_CODE (XEXP (operand, 0)) == POST_INC))
3207 win = 1;
3208 break;
3209
3210 /* Memory operand whose address is not offsettable. */
3211 case 'V':
3212 if (force_reload)
3213 break;
3162 if (GET_CODE (operand) == MEM
3214 if (MEM_P (operand)
3163 && ! (ind_levels ? offsettable_memref_p (operand)
3164 : offsettable_nonstrict_memref_p (operand))
3165 /* Certain mem addresses will become offsettable
3166 after they themselves are reloaded. This is important;
3167 we don't want our own handling of unoffsettables
3168 to override the handling of reg_equiv_address. */
3215 && ! (ind_levels ? offsettable_memref_p (operand)
3216 : offsettable_nonstrict_memref_p (operand))
3217 /* Certain mem addresses will become offsettable
3218 after they themselves are reloaded. This is important;
3219 we don't want our own handling of unoffsettables
3220 to override the handling of reg_equiv_address. */
3169 && !(GET_CODE (XEXP (operand, 0)) == REG
3221 && !(REG_P (XEXP (operand, 0))
3170 && (ind_levels == 0
3171 || reg_equiv_address[REGNO (XEXP (operand, 0))] != 0)))
3172 win = 1;
3173 break;
3174
3175 /* Memory operand whose address is offsettable. */
3176 case 'o':
3177 if (force_reload)
3178 break;
3222 && (ind_levels == 0
3223 || reg_equiv_address[REGNO (XEXP (operand, 0))] != 0)))
3224 win = 1;
3225 break;
3226
3227 /* Memory operand whose address is offsettable. */
3228 case 'o':
3229 if (force_reload)
3230 break;
3179 if ((GET_CODE (operand) == MEM
3231 if ((MEM_P (operand)
3180 /* If IND_LEVELS, find_reloads_address won't reload a
3181 pseudo that didn't get a hard reg, so we have to
3182 reject that case. */
3183 && ((ind_levels ? offsettable_memref_p (operand)
3184 : offsettable_nonstrict_memref_p (operand))
3185 /* A reloaded address is offsettable because it is now
3186 just a simple register indirect. */
3232 /* If IND_LEVELS, find_reloads_address won't reload a
3233 pseudo that didn't get a hard reg, so we have to
3234 reject that case. */
3235 && ((ind_levels ? offsettable_memref_p (operand)
3236 : offsettable_nonstrict_memref_p (operand))
3237 /* A reloaded address is offsettable because it is now
3238 just a simple register indirect. */
3187 || address_reloaded[i]))
3188 || (GET_CODE (operand) == REG
3239 || address_reloaded[i] == 1))
3240 || (REG_P (operand)
3189 && REGNO (operand) >= FIRST_PSEUDO_REGISTER
3190 && reg_renumber[REGNO (operand)] < 0
3191 /* If reg_equiv_address is nonzero, we will be
3192 loading it into a register; hence it will be
3193 offsettable, but we cannot say that reg_equiv_mem
3194 is offsettable without checking. */
3195 && ((reg_equiv_mem[REGNO (operand)] != 0
3196 && offsettable_memref_p (reg_equiv_mem[REGNO (operand)]))
3197 || (reg_equiv_address[REGNO (operand)] != 0))))
3198 win = 1;
3241 && REGNO (operand) >= FIRST_PSEUDO_REGISTER
3242 && reg_renumber[REGNO (operand)] < 0
3243 /* If reg_equiv_address is nonzero, we will be
3244 loading it into a register; hence it will be
3245 offsettable, but we cannot say that reg_equiv_mem
3246 is offsettable without checking. */
3247 && ((reg_equiv_mem[REGNO (operand)] != 0
3248 && offsettable_memref_p (reg_equiv_mem[REGNO (operand)]))
3249 || (reg_equiv_address[REGNO (operand)] != 0))))
3250 win = 1;
3199 /* force_const_mem does not accept HIGH. */
3200 if ((CONSTANT_P (operand) && GET_CODE (operand) != HIGH)
3201 || GET_CODE (operand) == MEM)
3251 if (CONST_POOL_OK_P (operand)
3252 || MEM_P (operand))
3202 badop = 0;
3203 constmemok = 1;
3204 offmemok = 1;
3205 break;
3206
3207 case '&':
3208 /* Output operand that is stored before the need for the
3209 input operands (and their index registers) is over. */

--- 18 unchanged lines hidden (view full) ---

3228
3229 case 's':
3230 if (GET_CODE (operand) == CONST_INT
3231 || (GET_CODE (operand) == CONST_DOUBLE
3232 && GET_MODE (operand) == VOIDmode))
3233 break;
3234 case 'i':
3235 if (CONSTANT_P (operand)
3253 badop = 0;
3254 constmemok = 1;
3255 offmemok = 1;
3256 break;
3257
3258 case '&':
3259 /* Output operand that is stored before the need for the
3260 input operands (and their index registers) is over. */

--- 18 unchanged lines hidden (view full) ---

3279
3280 case 's':
3281 if (GET_CODE (operand) == CONST_INT
3282 || (GET_CODE (operand) == CONST_DOUBLE
3283 && GET_MODE (operand) == VOIDmode))
3284 break;
3285 case 'i':
3286 if (CONSTANT_P (operand)
3236#ifdef LEGITIMATE_PIC_OPERAND_P
3237 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (operand))
3238#endif
3239 )
3287 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (operand)))
3240 win = 1;
3241 break;
3242
3243 case 'n':
3244 if (GET_CODE (operand) == CONST_INT
3245 || (GET_CODE (operand) == CONST_DOUBLE
3246 && GET_MODE (operand) == VOIDmode))
3247 win = 1;

--- 8 unchanged lines hidden (view full) ---

3256 case 'O':
3257 case 'P':
3258 if (GET_CODE (operand) == CONST_INT
3259 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operand), c, p))
3260 win = 1;
3261 break;
3262
3263 case 'X':
3288 win = 1;
3289 break;
3290
3291 case 'n':
3292 if (GET_CODE (operand) == CONST_INT
3293 || (GET_CODE (operand) == CONST_DOUBLE
3294 && GET_MODE (operand) == VOIDmode))
3295 win = 1;

--- 8 unchanged lines hidden (view full) ---

3304 case 'O':
3305 case 'P':
3306 if (GET_CODE (operand) == CONST_INT
3307 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operand), c, p))
3308 win = 1;
3309 break;
3310
3311 case 'X':
3312 force_reload = 0;
3264 win = 1;
3265 break;
3266
3267 case 'g':
3268 if (! force_reload
3269 /* A PLUS is never a valid operand, but reload can make
3270 it from a register when eliminating registers. */
3271 && GET_CODE (operand) != PLUS
3272 /* A SCRATCH is not a valid operand. */
3273 && GET_CODE (operand) != SCRATCH
3313 win = 1;
3314 break;
3315
3316 case 'g':
3317 if (! force_reload
3318 /* A PLUS is never a valid operand, but reload can make
3319 it from a register when eliminating registers. */
3320 && GET_CODE (operand) != PLUS
3321 /* A SCRATCH is not a valid operand. */
3322 && GET_CODE (operand) != SCRATCH
3274#ifdef LEGITIMATE_PIC_OPERAND_P
3275 && (! CONSTANT_P (operand)
3276 || ! flag_pic
3277 || LEGITIMATE_PIC_OPERAND_P (operand))
3323 && (! CONSTANT_P (operand)
3324 || ! flag_pic
3325 || LEGITIMATE_PIC_OPERAND_P (operand))
3278#endif
3279 && (GENERAL_REGS == ALL_REGS
3326 && (GENERAL_REGS == ALL_REGS
3280 || GET_CODE (operand) != REG
3327 || !REG_P (operand)
3281 || (REGNO (operand) >= FIRST_PSEUDO_REGISTER
3282 && reg_renumber[REGNO (operand)] < 0)))
3283 win = 1;
3284 /* Drop through into 'r' case. */
3285
3286 case 'r':
3287 this_alternative[i]
3288 = (int) reg_class_subunion[this_alternative[i]][(int) GENERAL_REGS];

--- 6 unchanged lines hidden (view full) ---

3295 if (EXTRA_MEMORY_CONSTRAINT (c, p))
3296 {
3297 if (force_reload)
3298 break;
3299 if (EXTRA_CONSTRAINT_STR (operand, c, p))
3300 win = 1;
3301 /* If the address was already reloaded,
3302 we win as well. */
3328 || (REGNO (operand) >= FIRST_PSEUDO_REGISTER
3329 && reg_renumber[REGNO (operand)] < 0)))
3330 win = 1;
3331 /* Drop through into 'r' case. */
3332
3333 case 'r':
3334 this_alternative[i]
3335 = (int) reg_class_subunion[this_alternative[i]][(int) GENERAL_REGS];

--- 6 unchanged lines hidden (view full) ---

3342 if (EXTRA_MEMORY_CONSTRAINT (c, p))
3343 {
3344 if (force_reload)
3345 break;
3346 if (EXTRA_CONSTRAINT_STR (operand, c, p))
3347 win = 1;
3348 /* If the address was already reloaded,
3349 we win as well. */
3303 else if (GET_CODE (operand) == MEM
3304 && address_reloaded[i])
3350 else if (MEM_P (operand)
3351 && address_reloaded[i] == 1)
3305 win = 1;
3306 /* Likewise if the address will be reloaded because
3307 reg_equiv_address is nonzero. For reg_equiv_mem
3308 we have to check. */
3352 win = 1;
3353 /* Likewise if the address will be reloaded because
3354 reg_equiv_address is nonzero. For reg_equiv_mem
3355 we have to check. */
3309 else if (GET_CODE (operand) == REG
3356 else if (REG_P (operand)
3310 && REGNO (operand) >= FIRST_PSEUDO_REGISTER
3311 && reg_renumber[REGNO (operand)] < 0
3312 && ((reg_equiv_mem[REGNO (operand)] != 0
3313 && EXTRA_CONSTRAINT_STR (reg_equiv_mem[REGNO (operand)], c, p))
3314 || (reg_equiv_address[REGNO (operand)] != 0)))
3315 win = 1;
3316
3317 /* If we didn't already win, we can reload
3318 constants via force_const_mem, and other
3319 MEMs by reloading the address like for 'o'. */
3357 && REGNO (operand) >= FIRST_PSEUDO_REGISTER
3358 && reg_renumber[REGNO (operand)] < 0
3359 && ((reg_equiv_mem[REGNO (operand)] != 0
3360 && EXTRA_CONSTRAINT_STR (reg_equiv_mem[REGNO (operand)], c, p))
3361 || (reg_equiv_address[REGNO (operand)] != 0)))
3362 win = 1;
3363
3364 /* If we didn't already win, we can reload
3365 constants via force_const_mem, and other
3366 MEMs by reloading the address like for 'o'. */
3320 if ((CONSTANT_P (operand) && GET_CODE (operand) != HIGH)
3321 || GET_CODE (operand) == MEM)
3367 if (CONST_POOL_OK_P (operand)
3368 || MEM_P (operand))
3322 badop = 0;
3323 constmemok = 1;
3324 offmemok = 1;
3325 break;
3326 }
3327 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
3328 {
3329 if (EXTRA_CONSTRAINT_STR (operand, c, p))
3330 win = 1;
3331
3332 /* If we didn't already win, we can reload
3333 the address into a base register. */
3369 badop = 0;
3370 constmemok = 1;
3371 offmemok = 1;
3372 break;
3373 }
3374 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
3375 {
3376 if (EXTRA_CONSTRAINT_STR (operand, c, p))
3377 win = 1;
3378
3379 /* If we didn't already win, we can reload
3380 the address into a base register. */
3334 this_alternative[i] = (int) MODE_BASE_REG_CLASS (VOIDmode);
3381 this_alternative[i]
3382 = (int) base_reg_class (VOIDmode, ADDRESS, SCRATCH);
3335 badop = 0;
3336 break;
3337 }
3338
3339 if (EXTRA_CONSTRAINT_STR (operand, c, p))
3340 win = 1;
3341#endif
3342 break;
3343 }
3344
3345 this_alternative[i]
3346 = (int) (reg_class_subunion
3347 [this_alternative[i]]
3348 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)]);
3349 reg:
3350 if (GET_MODE (operand) == BLKmode)
3351 break;
3352 winreg = 1;
3383 badop = 0;
3384 break;
3385 }
3386
3387 if (EXTRA_CONSTRAINT_STR (operand, c, p))
3388 win = 1;
3389#endif
3390 break;
3391 }
3392
3393 this_alternative[i]
3394 = (int) (reg_class_subunion
3395 [this_alternative[i]]
3396 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)]);
3397 reg:
3398 if (GET_MODE (operand) == BLKmode)
3399 break;
3400 winreg = 1;
3353 if (GET_CODE (operand) == REG
3401 if (REG_P (operand)
3354 && reg_fits_class_p (operand, this_alternative[i],
3355 offset, GET_MODE (recog_data.operand[i])))
3356 win = 1;
3357 break;
3358 }
3359 while ((p += len), c);
3360
3361 constraints[i] = p;

--- 13 unchanged lines hidden (view full) ---

3375 {
3376 int const_to_mem = 0;
3377
3378 this_alternative_offmemok[i] = offmemok;
3379 losers++;
3380 if (badop)
3381 bad = 1;
3382 /* Alternative loses if it has no regs for a reg operand. */
3402 && reg_fits_class_p (operand, this_alternative[i],
3403 offset, GET_MODE (recog_data.operand[i])))
3404 win = 1;
3405 break;
3406 }
3407 while ((p += len), c);
3408
3409 constraints[i] = p;

--- 13 unchanged lines hidden (view full) ---

3423 {
3424 int const_to_mem = 0;
3425
3426 this_alternative_offmemok[i] = offmemok;
3427 losers++;
3428 if (badop)
3429 bad = 1;
3430 /* Alternative loses if it has no regs for a reg operand. */
3383 if (GET_CODE (operand) == REG
3431 if (REG_P (operand)
3384 && this_alternative[i] == (int) NO_REGS
3385 && this_alternative_matches[i] < 0)
3386 bad = 1;
3387
3388 /* If this is a constant that is reloaded into the desired
3389 class by copying it to memory first, count that as another
3390 reload. This is consistent with other code and is
3391 required to avoid choosing another alternative when
3392 the constant is moved into memory by this function on
3393 an early reload pass. Note that the test here is
3394 precisely the same as in the code below that calls
3395 force_const_mem. */
3432 && this_alternative[i] == (int) NO_REGS
3433 && this_alternative_matches[i] < 0)
3434 bad = 1;
3435
3436 /* If this is a constant that is reloaded into the desired
3437 class by copying it to memory first, count that as another
3438 reload. This is consistent with other code and is
3439 required to avoid choosing another alternative when
3440 the constant is moved into memory by this function on
3441 an early reload pass. Note that the test here is
3442 precisely the same as in the code below that calls
3443 force_const_mem. */
3396 if (CONSTANT_P (operand)
3397 /* force_const_mem does not accept HIGH. */
3398 && GET_CODE (operand) != HIGH
3444 if (CONST_POOL_OK_P (operand)
3399 && ((PREFERRED_RELOAD_CLASS (operand,
3400 (enum reg_class) this_alternative[i])
3401 == NO_REGS)
3402 || no_input_reloads)
3403 && operand_mode[i] != VOIDmode)
3404 {
3405 const_to_mem = 1;
3406 if (this_alternative[i] != (int) NO_REGS)
3407 losers++;
3408 }
3409
3445 && ((PREFERRED_RELOAD_CLASS (operand,
3446 (enum reg_class) this_alternative[i])
3447 == NO_REGS)
3448 || no_input_reloads)
3449 && operand_mode[i] != VOIDmode)
3450 {
3451 const_to_mem = 1;
3452 if (this_alternative[i] != (int) NO_REGS)
3453 losers++;
3454 }
3455
3410 /* If we can't reload this value at all, reject this
3411 alternative. Note that we could also lose due to
3412 LIMIT_RELOAD_RELOAD_CLASS, but we don't check that
3413 here. */
3414
3415 if (! CONSTANT_P (operand)
3416 && (enum reg_class) this_alternative[i] != NO_REGS
3417 && (PREFERRED_RELOAD_CLASS (operand,
3418 (enum reg_class) this_alternative[i])
3419 == NO_REGS))
3420 bad = 1;
3421
3422 /* Alternative loses if it requires a type of reload not
3423 permitted for this insn. We can always reload SCRATCH
3424 and objects with a REG_UNUSED note. */
3456 /* Alternative loses if it requires a type of reload not
3457 permitted for this insn. We can always reload SCRATCH
3458 and objects with a REG_UNUSED note. */
3425 else if (GET_CODE (operand) != SCRATCH
3459 if (GET_CODE (operand) != SCRATCH
3426 && modified[i] != RELOAD_READ && no_output_reloads
3427 && ! find_reg_note (insn, REG_UNUSED, operand))
3428 bad = 1;
3429 else if (modified[i] != RELOAD_WRITE && no_input_reloads
3430 && ! const_to_mem)
3431 bad = 1;
3432
3460 && modified[i] != RELOAD_READ && no_output_reloads
3461 && ! find_reg_note (insn, REG_UNUSED, operand))
3462 bad = 1;
3463 else if (modified[i] != RELOAD_WRITE && no_input_reloads
3464 && ! const_to_mem)
3465 bad = 1;
3466
3433#ifdef DISPARAGE_RELOAD_CLASS
3434 reject
3435 += DISPARAGE_RELOAD_CLASS (operand,
3436 (enum reg_class) this_alternative[i]);
3467 /* If we can't reload this value at all, reject this
3468 alternative. Note that we could also lose due to
3469 LIMIT_RELOAD_CLASS, but we don't check that
3470 here. */
3471
3472 if (! CONSTANT_P (operand)
3473 && (enum reg_class) this_alternative[i] != NO_REGS)
3474 {
3475 if (PREFERRED_RELOAD_CLASS
3476 (operand, (enum reg_class) this_alternative[i])
3477 == NO_REGS)
3478 reject = 600;
3479
3480#ifdef PREFERRED_OUTPUT_RELOAD_CLASS
3481 if (operand_type[i] == RELOAD_FOR_OUTPUT
3482 && PREFERRED_OUTPUT_RELOAD_CLASS
3483 (operand, (enum reg_class) this_alternative[i])
3484 == NO_REGS)
3485 reject = 600;
3437#endif
3486#endif
3487 }
3438
3439 /* We prefer to reload pseudos over reloading other things,
3440 since such reloads may be able to be eliminated later.
3441 If we are reloading a SCRATCH, we won't be generating any
3442 insns, just using a register, so it is also preferred.
3443 So bump REJECT in other cases. Don't do this in the
3444 case where we are forcing a constant into memory and
3445 it will then win since we don't want to have a different
3446 alternative match then. */
3488
3489 /* We prefer to reload pseudos over reloading other things,
3490 since such reloads may be able to be eliminated later.
3491 If we are reloading a SCRATCH, we won't be generating any
3492 insns, just using a register, so it is also preferred.
3493 So bump REJECT in other cases. Don't do this in the
3494 case where we are forcing a constant into memory and
3495 it will then win since we don't want to have a different
3496 alternative match then. */
3447 if (! (GET_CODE (operand) == REG
3497 if (! (REG_P (operand)
3448 && REGNO (operand) >= FIRST_PSEUDO_REGISTER)
3449 && GET_CODE (operand) != SCRATCH
3450 && ! (const_to_mem && constmemok))
3451 reject += 2;
3452
3453 /* Input reloads can be inherited more often than output
3454 reloads can be removed, so penalize output reloads. */
3455 if (operand_type[i] != RELOAD_FOR_INPUT

--- 20 unchanged lines hidden (view full) ---

3476 which could cause a large loss.
3477
3478 Don't do this if the preferred class has only one register
3479 because we might otherwise exhaust the class. */
3480
3481 if (! win && ! did_match
3482 && this_alternative[i] != (int) NO_REGS
3483 && GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD
3498 && REGNO (operand) >= FIRST_PSEUDO_REGISTER)
3499 && GET_CODE (operand) != SCRATCH
3500 && ! (const_to_mem && constmemok))
3501 reject += 2;
3502
3503 /* Input reloads can be inherited more often than output
3504 reloads can be removed, so penalize output reloads. */
3505 if (operand_type[i] != RELOAD_FOR_INPUT

--- 20 unchanged lines hidden (view full) ---

3526 which could cause a large loss.
3527
3528 Don't do this if the preferred class has only one register
3529 because we might otherwise exhaust the class. */
3530
3531 if (! win && ! did_match
3532 && this_alternative[i] != (int) NO_REGS
3533 && GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD
3484 && reg_class_size[(int) preferred_class[i]] > 1)
3534 && reg_class_size [(int) preferred_class[i]] > 0
3535 && ! SMALL_REGISTER_CLASS_P (preferred_class[i]))
3485 {
3486 if (! reg_class_subset_p (this_alternative[i],
3487 preferred_class[i]))
3488 {
3489 /* Since we don't have a way of forming the intersection,
3490 we just do something special if the preferred class
3491 is a subset of the class we have; that's the most
3492 common case anyway. */

--- 13 unchanged lines hidden (view full) ---

3506 for (i = 0; i < noperands; i++)
3507 if (this_alternative_earlyclobber[i]
3508 && (this_alternative_win[i] || this_alternative_match_win[i]))
3509 {
3510 struct decomposition early_data;
3511
3512 early_data = decompose (recog_data.operand[i]);
3513
3536 {
3537 if (! reg_class_subset_p (this_alternative[i],
3538 preferred_class[i]))
3539 {
3540 /* Since we don't have a way of forming the intersection,
3541 we just do something special if the preferred class
3542 is a subset of the class we have; that's the most
3543 common case anyway. */

--- 13 unchanged lines hidden (view full) ---

3557 for (i = 0; i < noperands; i++)
3558 if (this_alternative_earlyclobber[i]
3559 && (this_alternative_win[i] || this_alternative_match_win[i]))
3560 {
3561 struct decomposition early_data;
3562
3563 early_data = decompose (recog_data.operand[i]);
3564
3514 if (modified[i] == RELOAD_READ)
3515 abort ();
3565 gcc_assert (modified[i] != RELOAD_READ);
3516
3517 if (this_alternative[i] == NO_REGS)
3518 {
3519 this_alternative_earlyclobber[i] = 0;
3566
3567 if (this_alternative[i] == NO_REGS)
3568 {
3569 this_alternative_earlyclobber[i] = 0;
3520 if (this_insn_is_asm)
3521 error_for_asm (this_insn,
3522 "`&' constraint used with no register class");
3523 else
3524 abort ();
3570 gcc_assert (this_insn_is_asm);
3571 error_for_asm (this_insn,
3572 "%<&%> constraint used with no register class");
3525 }
3526
3527 for (j = 0; j < noperands; j++)
3528 /* Is this an input operand or a memory ref? */
3573 }
3574
3575 for (j = 0; j < noperands; j++)
3576 /* Is this an input operand or a memory ref? */
3529 if ((GET_CODE (recog_data.operand[j]) == MEM
3577 if ((MEM_P (recog_data.operand[j])
3530 || modified[j] != RELOAD_WRITE)
3531 && j != i
3532 /* Ignore things like match_operator operands. */
3533 && *recog_data.constraints[j] != 0
3534 /* Don't count an input operand that is constrained to match
3535 the early clobber operand. */
3536 && ! (this_alternative_matches[j] == i
3537 && rtx_equal_p (recog_data.operand[i],
3538 recog_data.operand[j]))
3539 /* Is it altered by storing the earlyclobber operand? */
3540 && !immune_p (recog_data.operand[j], recog_data.operand[i],
3541 early_data))
3542 {
3578 || modified[j] != RELOAD_WRITE)
3579 && j != i
3580 /* Ignore things like match_operator operands. */
3581 && *recog_data.constraints[j] != 0
3582 /* Don't count an input operand that is constrained to match
3583 the early clobber operand. */
3584 && ! (this_alternative_matches[j] == i
3585 && rtx_equal_p (recog_data.operand[i],
3586 recog_data.operand[j]))
3587 /* Is it altered by storing the earlyclobber operand? */
3588 && !immune_p (recog_data.operand[j], recog_data.operand[i],
3589 early_data))
3590 {
3543 /* If the output is in a single-reg class,
3591 /* If the output is in a non-empty few-regs class,
3544 it's costly to reload it, so reload the input instead. */
3592 it's costly to reload it, so reload the input instead. */
3545 if (reg_class_size[this_alternative[i]] == 1
3546 && (GET_CODE (recog_data.operand[j]) == REG
3593 if (SMALL_REGISTER_CLASS_P (this_alternative[i])
3594 && (REG_P (recog_data.operand[j])
3547 || GET_CODE (recog_data.operand[j]) == SUBREG))
3548 {
3549 losers++;
3550 this_alternative_win[j] = 0;
3551 this_alternative_match_win[j] = 0;
3552 }
3553 else
3554 break;

--- 100 unchanged lines hidden (view full) ---

3655 tclass = preferred_class[commutative];
3656 preferred_class[commutative] = preferred_class[commutative + 1];
3657 preferred_class[commutative + 1] = tclass;
3658
3659 t = pref_or_nothing[commutative];
3660 pref_or_nothing[commutative] = pref_or_nothing[commutative + 1];
3661 pref_or_nothing[commutative + 1] = t;
3662
3595 || GET_CODE (recog_data.operand[j]) == SUBREG))
3596 {
3597 losers++;
3598 this_alternative_win[j] = 0;
3599 this_alternative_match_win[j] = 0;
3600 }
3601 else
3602 break;

--- 100 unchanged lines hidden (view full) ---

3703 tclass = preferred_class[commutative];
3704 preferred_class[commutative] = preferred_class[commutative + 1];
3705 preferred_class[commutative + 1] = tclass;
3706
3707 t = pref_or_nothing[commutative];
3708 pref_or_nothing[commutative] = pref_or_nothing[commutative + 1];
3709 pref_or_nothing[commutative + 1] = t;
3710
3711 t = address_reloaded[commutative];
3712 address_reloaded[commutative] = address_reloaded[commutative + 1];
3713 address_reloaded[commutative + 1] = t;
3714
3663 memcpy (constraints, recog_data.constraints,
3664 noperands * sizeof (char *));
3665 goto try_swapped;
3666 }
3667 else
3668 {
3669 recog_data.operand[commutative] = substed_operand[commutative];
3670 recog_data.operand[commutative + 1]

--- 12 unchanged lines hidden (view full) ---

3683 that we could reach by reloading the fewest operands.
3684 Reload so as to fit it. */
3685
3686 if (best == MAX_RECOG_OPERANDS * 2 + 600)
3687 {
3688 /* No alternative works with reloads?? */
3689 if (insn_code_number >= 0)
3690 fatal_insn ("unable to generate reloads for:", insn);
3715 memcpy (constraints, recog_data.constraints,
3716 noperands * sizeof (char *));
3717 goto try_swapped;
3718 }
3719 else
3720 {
3721 recog_data.operand[commutative] = substed_operand[commutative];
3722 recog_data.operand[commutative + 1]

--- 12 unchanged lines hidden (view full) ---

3735 that we could reach by reloading the fewest operands.
3736 Reload so as to fit it. */
3737
3738 if (best == MAX_RECOG_OPERANDS * 2 + 600)
3739 {
3740 /* No alternative works with reloads?? */
3741 if (insn_code_number >= 0)
3742 fatal_insn ("unable to generate reloads for:", insn);
3691 error_for_asm (insn, "inconsistent operand constraints in an `asm'");
3743 error_for_asm (insn, "inconsistent operand constraints in an %<asm%>");
3692 /* Avoid further trouble with this insn. */
3693 PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx);
3694 n_reloads = 0;
3695 return 0;
3696 }
3697
3698 /* Jump to `finish' from above if all operands are valid already.
3699 In that case, goal_alternative_win is all 1. */

--- 70 unchanged lines hidden (view full) ---

3770 = (find_reg_note (insn, REG_UNUSED, recog_data.operand[i])
3771 ? RELOAD_FOR_INSN : RELOAD_OTHER);
3772 }
3773
3774 /* Any constants that aren't allowed and can't be reloaded
3775 into registers are here changed into memory references. */
3776 for (i = 0; i < noperands; i++)
3777 if (! goal_alternative_win[i]
3744 /* Avoid further trouble with this insn. */
3745 PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx);
3746 n_reloads = 0;
3747 return 0;
3748 }
3749
3750 /* Jump to `finish' from above if all operands are valid already.
3751 In that case, goal_alternative_win is all 1. */

--- 70 unchanged lines hidden (view full) ---

3822 = (find_reg_note (insn, REG_UNUSED, recog_data.operand[i])
3823 ? RELOAD_FOR_INSN : RELOAD_OTHER);
3824 }
3825
3826 /* Any constants that aren't allowed and can't be reloaded
3827 into registers are here changed into memory references. */
3828 for (i = 0; i < noperands; i++)
3829 if (! goal_alternative_win[i]
3778 && CONSTANT_P (recog_data.operand[i])
3779 /* force_const_mem does not accept HIGH. */
3780 && GET_CODE (recog_data.operand[i]) != HIGH
3830 && CONST_POOL_OK_P (recog_data.operand[i])
3781 && ((PREFERRED_RELOAD_CLASS (recog_data.operand[i],
3782 (enum reg_class) goal_alternative[i])
3783 == NO_REGS)
3784 || no_input_reloads)
3785 && operand_mode[i] != VOIDmode)
3786 {
3787 substed_operand[i] = recog_data.operand[i]
3788 = find_reloads_toplev (force_const_mem (operand_mode[i],
3789 recog_data.operand[i]),
3790 i, address_type[i], ind_levels, 0, insn,
3791 NULL);
3792 if (alternative_allows_memconst (recog_data.constraints[i],
3793 goal_alternative_number))
3794 goal_alternative_win[i] = 1;
3795 }
3796
3831 && ((PREFERRED_RELOAD_CLASS (recog_data.operand[i],
3832 (enum reg_class) goal_alternative[i])
3833 == NO_REGS)
3834 || no_input_reloads)
3835 && operand_mode[i] != VOIDmode)
3836 {
3837 substed_operand[i] = recog_data.operand[i]
3838 = find_reloads_toplev (force_const_mem (operand_mode[i],
3839 recog_data.operand[i]),
3840 i, address_type[i], ind_levels, 0, insn,
3841 NULL);
3842 if (alternative_allows_memconst (recog_data.constraints[i],
3843 goal_alternative_number))
3844 goal_alternative_win[i] = 1;
3845 }
3846
3847 /* Likewise any invalid constants appearing as operand of a PLUS
3848 that is to be reloaded. */
3849 for (i = 0; i < noperands; i++)
3850 if (! goal_alternative_win[i]
3851 && GET_CODE (recog_data.operand[i]) == PLUS
3852 && CONST_POOL_OK_P (XEXP (recog_data.operand[i], 1))
3853 && (PREFERRED_RELOAD_CLASS (XEXP (recog_data.operand[i], 1),
3854 (enum reg_class) goal_alternative[i])
3855 == NO_REGS)
3856 && operand_mode[i] != VOIDmode)
3857 {
3858 rtx tem = force_const_mem (operand_mode[i],
3859 XEXP (recog_data.operand[i], 1));
3860 tem = gen_rtx_PLUS (operand_mode[i],
3861 XEXP (recog_data.operand[i], 0), tem);
3862
3863 substed_operand[i] = recog_data.operand[i]
3864 = find_reloads_toplev (tem, i, address_type[i],
3865 ind_levels, 0, insn, NULL);
3866 }
3867
3797 /* Record the values of the earlyclobber operands for the caller. */
3798 if (goal_earlyclobber)
3799 for (i = 0; i < noperands; i++)
3800 if (goal_alternative_earlyclobber[i])
3801 reload_earlyclobbers[n_earlyclobbers++] = recog_data.operand[i];
3802
3803 /* Now record reloads for all the operands that need them. */
3804 for (i = 0; i < noperands; i++)

--- 6 unchanged lines hidden (view full) ---

3811 appearing where an offsettable address will do
3812 by reloading the address into a base register.
3813
3814 ??? We can also do this when the operand is a register and
3815 reg_equiv_mem is not offsettable, but this is a bit tricky,
3816 so we don't bother with it. It may not be worth doing. */
3817 else if (goal_alternative_matched[i] == -1
3818 && goal_alternative_offmemok[i]
3868 /* Record the values of the earlyclobber operands for the caller. */
3869 if (goal_earlyclobber)
3870 for (i = 0; i < noperands; i++)
3871 if (goal_alternative_earlyclobber[i])
3872 reload_earlyclobbers[n_earlyclobbers++] = recog_data.operand[i];
3873
3874 /* Now record reloads for all the operands that need them. */
3875 for (i = 0; i < noperands; i++)

--- 6 unchanged lines hidden (view full) ---

3882 appearing where an offsettable address will do
3883 by reloading the address into a base register.
3884
3885 ??? We can also do this when the operand is a register and
3886 reg_equiv_mem is not offsettable, but this is a bit tricky,
3887 so we don't bother with it. It may not be worth doing. */
3888 else if (goal_alternative_matched[i] == -1
3889 && goal_alternative_offmemok[i]
3819 && GET_CODE (recog_data.operand[i]) == MEM)
3890 && MEM_P (recog_data.operand[i]))
3820 {
3891 {
3892 /* If the address to be reloaded is a VOIDmode constant,
3893 use Pmode as mode of the reload register, as would have
3894 been done by find_reloads_address. */
3895 enum machine_mode address_mode;
3896 address_mode = GET_MODE (XEXP (recog_data.operand[i], 0));
3897 if (address_mode == VOIDmode)
3898 address_mode = Pmode;
3899
3821 operand_reloadnum[i]
3822 = push_reload (XEXP (recog_data.operand[i], 0), NULL_RTX,
3823 &XEXP (recog_data.operand[i], 0), (rtx*) 0,
3900 operand_reloadnum[i]
3901 = push_reload (XEXP (recog_data.operand[i], 0), NULL_RTX,
3902 &XEXP (recog_data.operand[i], 0), (rtx*) 0,
3824 MODE_BASE_REG_CLASS (VOIDmode),
3825 GET_MODE (XEXP (recog_data.operand[i], 0)),
3903 base_reg_class (VOIDmode, MEM, SCRATCH),
3904 address_mode,
3826 VOIDmode, 0, 0, i, RELOAD_FOR_INPUT);
3827 rld[operand_reloadnum[i]].inc
3828 = GET_MODE_SIZE (GET_MODE (recog_data.operand[i]));
3829
3830 /* If this operand is an output, we will have made any
3831 reloads for its address as RELOAD_FOR_OUTPUT_ADDRESS, but
3832 now we are treating part of the operand as an input, so
3833 we must change these to RELOAD_FOR_INPUT_ADDRESS. */

--- 59 unchanged lines hidden (view full) ---

3893 recog_data.operand_loc[goal_alternative_matched[i]],
3894 recog_data.operand_loc[i],
3895 (enum reg_class) goal_alternative[i],
3896 operand_mode[goal_alternative_matched[i]],
3897 operand_mode[i],
3898 0, 0, i, RELOAD_OTHER);
3899 operand_reloadnum[i] = output_reloadnum;
3900 }
3905 VOIDmode, 0, 0, i, RELOAD_FOR_INPUT);
3906 rld[operand_reloadnum[i]].inc
3907 = GET_MODE_SIZE (GET_MODE (recog_data.operand[i]));
3908
3909 /* If this operand is an output, we will have made any
3910 reloads for its address as RELOAD_FOR_OUTPUT_ADDRESS, but
3911 now we are treating part of the operand as an input, so
3912 we must change these to RELOAD_FOR_INPUT_ADDRESS. */

--- 59 unchanged lines hidden (view full) ---

3972 recog_data.operand_loc[goal_alternative_matched[i]],
3973 recog_data.operand_loc[i],
3974 (enum reg_class) goal_alternative[i],
3975 operand_mode[goal_alternative_matched[i]],
3976 operand_mode[i],
3977 0, 0, i, RELOAD_OTHER);
3978 operand_reloadnum[i] = output_reloadnum;
3979 }
3901 else if (insn_code_number >= 0)
3902 abort ();
3903 else
3904 {
3980 else
3981 {
3905 error_for_asm (insn, "inconsistent operand constraints in an `asm'");
3982 gcc_assert (insn_code_number < 0);
3983 error_for_asm (insn, "inconsistent operand constraints "
3984 "in an %<asm%>");
3906 /* Avoid further trouble with this insn. */
3907 PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx);
3908 n_reloads = 0;
3909 return 0;
3910 }
3911 }
3912 else if (goal_alternative_matched[i] < 0
3913 && goal_alternative_matches[i] < 0
3985 /* Avoid further trouble with this insn. */
3986 PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx);
3987 n_reloads = 0;
3988 return 0;
3989 }
3990 }
3991 else if (goal_alternative_matched[i] < 0
3992 && goal_alternative_matches[i] < 0
3914 && !address_operand_reloaded[i]
3993 && address_operand_reloaded[i] != 1
3915 && optimize)
3916 {
3917 /* For each non-matching operand that's a MEM or a pseudo-register
3918 that didn't get a hard register, make an optional reload.
3919 This may get done even if the insn needs no reloads otherwise. */
3920
3921 rtx operand = recog_data.operand[i];
3922
3923 while (GET_CODE (operand) == SUBREG)
3924 operand = SUBREG_REG (operand);
3994 && optimize)
3995 {
3996 /* For each non-matching operand that's a MEM or a pseudo-register
3997 that didn't get a hard register, make an optional reload.
3998 This may get done even if the insn needs no reloads otherwise. */
3999
4000 rtx operand = recog_data.operand[i];
4001
4002 while (GET_CODE (operand) == SUBREG)
4003 operand = SUBREG_REG (operand);
3925 if ((GET_CODE (operand) == MEM
3926 || (GET_CODE (operand) == REG
4004 if ((MEM_P (operand)
4005 || (REG_P (operand)
3927 && REGNO (operand) >= FIRST_PSEUDO_REGISTER))
3928 /* If this is only for an output, the optional reload would not
3929 actually cause us to use a register now, just note that
3930 something is stored here. */
3931 && ((enum reg_class) goal_alternative[i] != NO_REGS
3932 || modified[i] == RELOAD_WRITE)
3933 && ! no_input_reloads
3934 /* An optional output reload might allow to delete INSN later.

--- 23 unchanged lines hidden (view full) ---

3958 : insn_data[insn_code_number].operand[i].strict_low),
3959 1, i, operand_type[i]);
3960 /* If a memory reference remains (either as a MEM or a pseudo that
3961 did not get a hard register), yet we can't make an optional
3962 reload, check if this is actually a pseudo register reference;
3963 we then need to emit a USE and/or a CLOBBER so that reload
3964 inheritance will do the right thing. */
3965 else if (replace
4006 && REGNO (operand) >= FIRST_PSEUDO_REGISTER))
4007 /* If this is only for an output, the optional reload would not
4008 actually cause us to use a register now, just note that
4009 something is stored here. */
4010 && ((enum reg_class) goal_alternative[i] != NO_REGS
4011 || modified[i] == RELOAD_WRITE)
4012 && ! no_input_reloads
4013 /* An optional output reload might allow to delete INSN later.

--- 23 unchanged lines hidden (view full) ---

4037 : insn_data[insn_code_number].operand[i].strict_low),
4038 1, i, operand_type[i]);
4039 /* If a memory reference remains (either as a MEM or a pseudo that
4040 did not get a hard register), yet we can't make an optional
4041 reload, check if this is actually a pseudo register reference;
4042 we then need to emit a USE and/or a CLOBBER so that reload
4043 inheritance will do the right thing. */
4044 else if (replace
3966 && (GET_CODE (operand) == MEM
3967 || (GET_CODE (operand) == REG
4045 && (MEM_P (operand)
4046 || (REG_P (operand)
3968 && REGNO (operand) >= FIRST_PSEUDO_REGISTER
3969 && reg_renumber [REGNO (operand)] < 0)))
3970 {
3971 operand = *recog_data.operand_loc[i];
3972
3973 while (GET_CODE (operand) == SUBREG)
3974 operand = SUBREG_REG (operand);
4047 && REGNO (operand) >= FIRST_PSEUDO_REGISTER
4048 && reg_renumber [REGNO (operand)] < 0)))
4049 {
4050 operand = *recog_data.operand_loc[i];
4051
4052 while (GET_CODE (operand) == SUBREG)
4053 operand = SUBREG_REG (operand);
3975 if (GET_CODE (operand) == REG)
4054 if (REG_P (operand))
3976 {
3977 if (modified[i] != RELOAD_WRITE)
3978 /* We mark the USE with QImode so that we recognize
3979 it as one that can be safely deleted at the end
3980 of reload. */
3981 PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, operand),
3982 insn), QImode);
3983 if (modified[i] != RELOAD_READ)

--- 10 unchanged lines hidden (view full) ---

3994 {
3995 /* Similarly, make an optional reload for a pair of matching
3996 objects that are in MEM or a pseudo that didn't get a hard reg. */
3997
3998 rtx operand = recog_data.operand[i];
3999
4000 while (GET_CODE (operand) == SUBREG)
4001 operand = SUBREG_REG (operand);
4055 {
4056 if (modified[i] != RELOAD_WRITE)
4057 /* We mark the USE with QImode so that we recognize
4058 it as one that can be safely deleted at the end
4059 of reload. */
4060 PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, operand),
4061 insn), QImode);
4062 if (modified[i] != RELOAD_READ)

--- 10 unchanged lines hidden (view full) ---

4073 {
4074 /* Similarly, make an optional reload for a pair of matching
4075 objects that are in MEM or a pseudo that didn't get a hard reg. */
4076
4077 rtx operand = recog_data.operand[i];
4078
4079 while (GET_CODE (operand) == SUBREG)
4080 operand = SUBREG_REG (operand);
4002 if ((GET_CODE (operand) == MEM
4003 || (GET_CODE (operand) == REG
4081 if ((MEM_P (operand)
4082 || (REG_P (operand)
4004 && REGNO (operand) >= FIRST_PSEUDO_REGISTER))
4005 && ((enum reg_class) goal_alternative[goal_alternative_matches[i]]
4006 != NO_REGS))
4007 operand_reloadnum[i] = operand_reloadnum[goal_alternative_matches[i]]
4008 = push_reload (recog_data.operand[goal_alternative_matches[i]],
4009 recog_data.operand[i],
4010 recog_data.operand_loc[goal_alternative_matches[i]],
4011 recog_data.operand_loc[i],

--- 6 unchanged lines hidden (view full) ---

4018 /* Perform whatever substitutions on the operands we are supposed
4019 to make due to commutativity or replacement of registers
4020 with equivalent constants or memory slots. */
4021
4022 for (i = 0; i < noperands; i++)
4023 {
4024 /* We only do this on the last pass through reload, because it is
4025 possible for some data (like reg_equiv_address) to be changed during
4083 && REGNO (operand) >= FIRST_PSEUDO_REGISTER))
4084 && ((enum reg_class) goal_alternative[goal_alternative_matches[i]]
4085 != NO_REGS))
4086 operand_reloadnum[i] = operand_reloadnum[goal_alternative_matches[i]]
4087 = push_reload (recog_data.operand[goal_alternative_matches[i]],
4088 recog_data.operand[i],
4089 recog_data.operand_loc[goal_alternative_matches[i]],
4090 recog_data.operand_loc[i],

--- 6 unchanged lines hidden (view full) ---

4097 /* Perform whatever substitutions on the operands we are supposed
4098 to make due to commutativity or replacement of registers
4099 with equivalent constants or memory slots. */
4100
4101 for (i = 0; i < noperands; i++)
4102 {
4103 /* We only do this on the last pass through reload, because it is
4104 possible for some data (like reg_equiv_address) to be changed during
4026 later passes. Moreover, we loose the opportunity to get a useful
4105 later passes. Moreover, we lose the opportunity to get a useful
4027 reload_{in,out}_reg when we do these replacements. */
4028
4029 if (replace)
4030 {
4031 rtx substitution = substed_operand[i];
4032
4033 *recog_data.operand_loc[i] = substitution;
4034
4035 /* If we're replacing an operand with a LABEL_REF, we need
4036 to make sure that there's a REG_LABEL note attached to
4037 this instruction. */
4106 reload_{in,out}_reg when we do these replacements. */
4107
4108 if (replace)
4109 {
4110 rtx substitution = substed_operand[i];
4111
4112 *recog_data.operand_loc[i] = substitution;
4113
4114 /* If we're replacing an operand with a LABEL_REF, we need
4115 to make sure that there's a REG_LABEL note attached to
4116 this instruction. */
4038 if (GET_CODE (insn) != JUMP_INSN
4117 if (!JUMP_P (insn)
4039 && GET_CODE (substitution) == LABEL_REF
4040 && !find_reg_note (insn, REG_LABEL, XEXP (substitution, 0)))
4041 REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL,
4042 XEXP (substitution, 0),
4043 REG_NOTES (insn));
4044 }
4045 else
4046 retval |= (substed_operand[i] != *recog_data.operand_loc[i]);

--- 23 unchanged lines hidden (view full) ---

4070 Now this optimization is done safely in choose_reload_regs. */
4071
4072 /* For each reload of a reg into some other class of reg,
4073 search for an existing equivalent reg (same value now) in the right class.
4074 We can use it as long as we don't need to change its contents. */
4075 for (i = 0; i < n_reloads; i++)
4076 if (rld[i].reg_rtx == 0
4077 && rld[i].in != 0
4118 && GET_CODE (substitution) == LABEL_REF
4119 && !find_reg_note (insn, REG_LABEL, XEXP (substitution, 0)))
4120 REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL,
4121 XEXP (substitution, 0),
4122 REG_NOTES (insn));
4123 }
4124 else
4125 retval |= (substed_operand[i] != *recog_data.operand_loc[i]);

--- 23 unchanged lines hidden (view full) ---

4149 Now this optimization is done safely in choose_reload_regs. */
4150
4151 /* For each reload of a reg into some other class of reg,
4152 search for an existing equivalent reg (same value now) in the right class.
4153 We can use it as long as we don't need to change its contents. */
4154 for (i = 0; i < n_reloads; i++)
4155 if (rld[i].reg_rtx == 0
4156 && rld[i].in != 0
4078 && GET_CODE (rld[i].in) == REG
4157 && REG_P (rld[i].in)
4079 && rld[i].out == 0)
4080 {
4081 rld[i].reg_rtx
4082 = find_equiv_reg (rld[i].in, insn, rld[i].class, -1,
4083 static_reload_reg_p, 0, rld[i].inmode);
4084 /* Prevent generation of insn to load the value
4085 because the one we found already has the value. */
4086 if (rld[i].reg_rtx)
4087 rld[i].in = rld[i].reg_rtx;
4088 }
4089#endif
4090
4158 && rld[i].out == 0)
4159 {
4160 rld[i].reg_rtx
4161 = find_equiv_reg (rld[i].in, insn, rld[i].class, -1,
4162 static_reload_reg_p, 0, rld[i].inmode);
4163 /* Prevent generation of insn to load the value
4164 because the one we found already has the value. */
4165 if (rld[i].reg_rtx)
4166 rld[i].in = rld[i].reg_rtx;
4167 }
4168#endif
4169
4170 /* If we detected error and replaced asm instruction by USE, forget about the
4171 reloads. */
4172 if (GET_CODE (PATTERN (insn)) == USE
4173 && GET_CODE (XEXP (PATTERN (insn), 0)) == CONST_INT)
4174 n_reloads = 0;
4175
4091 /* Perhaps an output reload can be combined with another
4092 to reduce needs by one. */
4093 if (!goal_earlyclobber)
4094 combine_reloads ();
4095
4096 /* If we have a pair of reloads for parts of an address, they are reloading
4097 the same object, the operands themselves were not reloaded, and they
4098 are for two operands that are supposed to match, merge the reloads and

--- 253 unchanged lines hidden (view full) ---

4352 }
4353
4354#ifdef HAVE_cc0
4355 /* If we made any reloads for addresses, see if they violate a
4356 "no input reloads" requirement for this insn. But loads that we
4357 do after the insn (such as for output addresses) are fine. */
4358 if (no_input_reloads)
4359 for (i = 0; i < n_reloads; i++)
4176 /* Perhaps an output reload can be combined with another
4177 to reduce needs by one. */
4178 if (!goal_earlyclobber)
4179 combine_reloads ();
4180
4181 /* If we have a pair of reloads for parts of an address, they are reloading
4182 the same object, the operands themselves were not reloaded, and they
4183 are for two operands that are supposed to match, merge the reloads and

--- 253 unchanged lines hidden (view full) ---

4437 }
4438
4439#ifdef HAVE_cc0
4440 /* If we made any reloads for addresses, see if they violate a
4441 "no input reloads" requirement for this insn. But loads that we
4442 do after the insn (such as for output addresses) are fine. */
4443 if (no_input_reloads)
4444 for (i = 0; i < n_reloads; i++)
4360 if (rld[i].in != 0
4361 && rld[i].when_needed != RELOAD_FOR_OUTADDR_ADDRESS
4362 && rld[i].when_needed != RELOAD_FOR_OUTPUT_ADDRESS)
4363 abort ();
4445 gcc_assert (rld[i].in == 0
4446 || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS
4447 || rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS);
4364#endif
4365
4366 /* Compute reload_mode and reload_nregs. */
4367 for (i = 0; i < n_reloads; i++)
4368 {
4369 rld[i].mode
4370 = (rld[i].inmode == VOIDmode
4371 || (GET_MODE_SIZE (rld[i].outmode)
4372 > GET_MODE_SIZE (rld[i].inmode)))
4373 ? rld[i].outmode : rld[i].inmode;
4374
4375 rld[i].nregs = CLASS_MAX_NREGS (rld[i].class, rld[i].mode);
4376 }
4377
4378 /* Special case a simple move with an input reload and a
4379 destination of a hard reg, if the hard reg is ok, use it. */
4380 for (i = 0; i < n_reloads; i++)
4381 if (rld[i].when_needed == RELOAD_FOR_INPUT
4382 && GET_CODE (PATTERN (insn)) == SET
4448#endif
4449
4450 /* Compute reload_mode and reload_nregs. */
4451 for (i = 0; i < n_reloads; i++)
4452 {
4453 rld[i].mode
4454 = (rld[i].inmode == VOIDmode
4455 || (GET_MODE_SIZE (rld[i].outmode)
4456 > GET_MODE_SIZE (rld[i].inmode)))
4457 ? rld[i].outmode : rld[i].inmode;
4458
4459 rld[i].nregs = CLASS_MAX_NREGS (rld[i].class, rld[i].mode);
4460 }
4461
4462 /* Special case a simple move with an input reload and a
4463 destination of a hard reg, if the hard reg is ok, use it. */
4464 for (i = 0; i < n_reloads; i++)
4465 if (rld[i].when_needed == RELOAD_FOR_INPUT
4466 && GET_CODE (PATTERN (insn)) == SET
4383 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
4467 && REG_P (SET_DEST (PATTERN (insn)))
4384 && SET_SRC (PATTERN (insn)) == rld[i].in)
4385 {
4386 rtx dest = SET_DEST (PATTERN (insn));
4387 unsigned int regno = REGNO (dest);
4388
4389 if (regno < FIRST_PSEUDO_REGISTER
4390 && TEST_HARD_REG_BIT (reg_class_contents[rld[i].class], regno)
4391 && HARD_REGNO_MODE_OK (regno, rld[i].mode))
4392 {
4468 && SET_SRC (PATTERN (insn)) == rld[i].in)
4469 {
4470 rtx dest = SET_DEST (PATTERN (insn));
4471 unsigned int regno = REGNO (dest);
4472
4473 if (regno < FIRST_PSEUDO_REGISTER
4474 && TEST_HARD_REG_BIT (reg_class_contents[rld[i].class], regno)
4475 && HARD_REGNO_MODE_OK (regno, rld[i].mode))
4476 {
4393 int nr = HARD_REGNO_NREGS (regno, rld[i].mode);
4477 int nr = hard_regno_nregs[regno][rld[i].mode];
4394 int ok = 1, nri;
4395
4396 for (nri = 1; nri < nr; nri ++)
4397 if (! TEST_HARD_REG_BIT (reg_class_contents[rld[i].class], regno + nri))
4398 ok = 0;
4399
4400 if (ok)
4401 rld[i].reg_rtx = dest;

--- 84 unchanged lines hidden (view full) ---

4486 /* We mark the USE with QImode so that we recognize it
4487 as one that can be safely deleted at the end of
4488 reload. */
4489 PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, x), insn),
4490 QImode);
4491 x = mem;
4492 i = find_reloads_address (GET_MODE (x), &x, XEXP (x, 0), &XEXP (x, 0),
4493 opnum, type, ind_levels, insn);
4478 int ok = 1, nri;
4479
4480 for (nri = 1; nri < nr; nri ++)
4481 if (! TEST_HARD_REG_BIT (reg_class_contents[rld[i].class], regno + nri))
4482 ok = 0;
4483
4484 if (ok)
4485 rld[i].reg_rtx = dest;

--- 84 unchanged lines hidden (view full) ---

4570 /* We mark the USE with QImode so that we recognize it
4571 as one that can be safely deleted at the end of
4572 reload. */
4573 PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode, x), insn),
4574 QImode);
4575 x = mem;
4576 i = find_reloads_address (GET_MODE (x), &x, XEXP (x, 0), &XEXP (x, 0),
4577 opnum, type, ind_levels, insn);
4578 if (x != mem)
4579 push_reg_equiv_alt_mem (regno, x);
4494 if (address_reloaded)
4495 *address_reloaded = i;
4496 }
4497 }
4498 return x;
4499 }
4500 if (code == MEM)
4501 {
4502 rtx tem = x;
4503
4504 i = find_reloads_address (GET_MODE (x), &tem, XEXP (x, 0), &XEXP (x, 0),
4505 opnum, type, ind_levels, insn);
4506 if (address_reloaded)
4507 *address_reloaded = i;
4508
4509 return tem;
4510 }
4511
4580 if (address_reloaded)
4581 *address_reloaded = i;
4582 }
4583 }
4584 return x;
4585 }
4586 if (code == MEM)
4587 {
4588 rtx tem = x;
4589
4590 i = find_reloads_address (GET_MODE (x), &tem, XEXP (x, 0), &XEXP (x, 0),
4591 opnum, type, ind_levels, insn);
4592 if (address_reloaded)
4593 *address_reloaded = i;
4594
4595 return tem;
4596 }
4597
4512 if (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG)
4598 if (code == SUBREG && REG_P (SUBREG_REG (x)))
4513 {
4599 {
4514 /* Check for SUBREG containing a REG that's equivalent to a constant.
4515 If the constant has a known value, truncate it right now.
4516 Similarly if we are extracting a single-word of a multi-word
4517 constant. If the constant is symbolic, allow it to be substituted
4518 normally. push_reload will strip the subreg later. If the
4519 constant is VOIDmode, abort because we will lose the mode of
4520 the register (this should never happen because one of the cases
4521 above should handle it). */
4600 /* Check for SUBREG containing a REG that's equivalent to a
4601 constant. If the constant has a known value, truncate it
4602 right now. Similarly if we are extracting a single-word of a
4603 multi-word constant. If the constant is symbolic, allow it
4604 to be substituted normally. push_reload will strip the
4605 subreg later. The constant must not be VOIDmode, because we
4606 will lose the mode of the register (this should never happen
4607 because one of the cases above should handle it). */
4522
4523 int regno = REGNO (SUBREG_REG (x));
4524 rtx tem;
4525
4526 if (subreg_lowpart_p (x)
4608
4609 int regno = REGNO (SUBREG_REG (x));
4610 rtx tem;
4611
4612 if (subreg_lowpart_p (x)
4527 && regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
4613 && regno >= FIRST_PSEUDO_REGISTER
4614 && reg_renumber[regno] < 0
4528 && reg_equiv_constant[regno] != 0
4529 && (tem = gen_lowpart_common (GET_MODE (x),
4530 reg_equiv_constant[regno])) != 0)
4531 return tem;
4532
4615 && reg_equiv_constant[regno] != 0
4616 && (tem = gen_lowpart_common (GET_MODE (x),
4617 reg_equiv_constant[regno])) != 0)
4618 return tem;
4619
4533 if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
4620 if (regno >= FIRST_PSEUDO_REGISTER
4621 && reg_renumber[regno] < 0
4534 && reg_equiv_constant[regno] != 0)
4535 {
4536 tem =
4537 simplify_gen_subreg (GET_MODE (x), reg_equiv_constant[regno],
4538 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
4622 && reg_equiv_constant[regno] != 0)
4623 {
4624 tem =
4625 simplify_gen_subreg (GET_MODE (x), reg_equiv_constant[regno],
4626 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
4539 if (!tem)
4540 abort ();
4627 gcc_assert (tem);
4541 return tem;
4542 }
4543
4544 /* If the subreg contains a reg that will be converted to a mem,
4545 convert the subreg to a narrower memref now.
4546 Otherwise, we would get (subreg (mem ...) ...),
4547 which would force reload of the mem.
4548
4549 We also need to do this if there is an equivalent MEM that is
4550 not offsettable. In that case, alter_subreg would produce an
4551 invalid address on big-endian machines.
4552
4553 For machines that extend byte loads, we must not reload using
4554 a wider mode if we have a paradoxical SUBREG. find_reloads will
4555 force a reload in that case. So we should not do anything here. */
4556
4628 return tem;
4629 }
4630
4631 /* If the subreg contains a reg that will be converted to a mem,
4632 convert the subreg to a narrower memref now.
4633 Otherwise, we would get (subreg (mem ...) ...),
4634 which would force reload of the mem.
4635
4636 We also need to do this if there is an equivalent MEM that is
4637 not offsettable. In that case, alter_subreg would produce an
4638 invalid address on big-endian machines.
4639
4640 For machines that extend byte loads, we must not reload using
4641 a wider mode if we have a paradoxical SUBREG. find_reloads will
4642 force a reload in that case. So we should not do anything here. */
4643
4557 else if (regno >= FIRST_PSEUDO_REGISTER
4644 if (regno >= FIRST_PSEUDO_REGISTER
4558#ifdef LOAD_EXTEND_OP
4559 && (GET_MODE_SIZE (GET_MODE (x))
4560 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
4561#endif
4562 && (reg_equiv_address[regno] != 0
4563 || (reg_equiv_mem[regno] != 0
4564 && (! strict_memory_address_p (GET_MODE (x),
4565 XEXP (reg_equiv_mem[regno], 0))

--- 80 unchanged lines hidden (view full) ---

4646
4647 IND_LEVELS says how many levels of indirect addressing this machine
4648 supports.
4649
4650 INSN, if nonzero, is the insn in which we do the reload. It is used
4651 to determine if we may generate output reloads, and where to put USEs
4652 for pseudos that we have to replace with stack slots.
4653
4645#ifdef LOAD_EXTEND_OP
4646 && (GET_MODE_SIZE (GET_MODE (x))
4647 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
4648#endif
4649 && (reg_equiv_address[regno] != 0
4650 || (reg_equiv_mem[regno] != 0
4651 && (! strict_memory_address_p (GET_MODE (x),
4652 XEXP (reg_equiv_mem[regno], 0))

--- 80 unchanged lines hidden (view full) ---

4733
4734 IND_LEVELS says how many levels of indirect addressing this machine
4735 supports.
4736
4737 INSN, if nonzero, is the insn in which we do the reload. It is used
4738 to determine if we may generate output reloads, and where to put USEs
4739 for pseudos that we have to replace with stack slots.
4740
4654 Value is nonzero if this address is reloaded or replaced as a whole.
4655 This is interesting to the caller if the address is an autoincrement.
4741 Value is one if this address is reloaded or replaced as a whole; it is
4742 zero if the top level of this address was not reloaded or replaced, and
4743 it is -1 if it may or may not have been reloaded or replaced.
4656
4657 Note that there is no verification that the address will be valid after
4658 this routine does its work. Instead, we rely on the fact that the address
4659 was valid when reload started. So we need only undo things that reload
4660 could have broken. These are wrong register types, pseudos not allocated
4661 to a hard register, and frame pointer elimination. */
4662
4663static int
4664find_reloads_address (enum machine_mode mode, rtx *memrefloc, rtx ad,
4665 rtx *loc, int opnum, enum reload_type type,
4666 int ind_levels, rtx insn)
4667{
4668 int regno;
4669 int removed_and = 0;
4744
4745 Note that there is no verification that the address will be valid after
4746 this routine does its work. Instead, we rely on the fact that the address
4747 was valid when reload started. So we need only undo things that reload
4748 could have broken. These are wrong register types, pseudos not allocated
4749 to a hard register, and frame pointer elimination. */
4750
4751static int
4752find_reloads_address (enum machine_mode mode, rtx *memrefloc, rtx ad,
4753 rtx *loc, int opnum, enum reload_type type,
4754 int ind_levels, rtx insn)
4755{
4756 int regno;
4757 int removed_and = 0;
4758 int op_index;
4670 rtx tem;
4671
4672 /* If the address is a register, see if it is a legitimate address and
4673 reload if not. We first handle the cases where we need not reload
4674 or where we must reload in a non-standard way. */
4675
4759 rtx tem;
4760
4761 /* If the address is a register, see if it is a legitimate address and
4762 reload if not. We first handle the cases where we need not reload
4763 or where we must reload in a non-standard way. */
4764
4676 if (GET_CODE (ad) == REG)
4765 if (REG_P (ad))
4677 {
4678 regno = REGNO (ad);
4679
4680 /* If the register is equivalent to an invariant expression, substitute
4681 the invariant, and eliminate any eliminable register references. */
4682 tem = reg_equiv_constant[regno];
4683 if (tem != 0
4684 && (tem = eliminate_regs (tem, mode, insn))

--- 6 unchanged lines hidden (view full) ---

4691 tem = reg_equiv_memory_loc[regno];
4692 if (tem != 0)
4693 {
4694 if (reg_equiv_address[regno] != 0 || num_not_at_initial_offset)
4695 {
4696 tem = make_memloc (ad, regno);
4697 if (! strict_memory_address_p (GET_MODE (tem), XEXP (tem, 0)))
4698 {
4766 {
4767 regno = REGNO (ad);
4768
4769 /* If the register is equivalent to an invariant expression, substitute
4770 the invariant, and eliminate any eliminable register references. */
4771 tem = reg_equiv_constant[regno];
4772 if (tem != 0
4773 && (tem = eliminate_regs (tem, mode, insn))

--- 6 unchanged lines hidden (view full) ---

4780 tem = reg_equiv_memory_loc[regno];
4781 if (tem != 0)
4782 {
4783 if (reg_equiv_address[regno] != 0 || num_not_at_initial_offset)
4784 {
4785 tem = make_memloc (ad, regno);
4786 if (! strict_memory_address_p (GET_MODE (tem), XEXP (tem, 0)))
4787 {
4788 rtx orig = tem;
4789
4699 find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0),
4700 &XEXP (tem, 0), opnum,
4701 ADDR_TYPE (type), ind_levels, insn);
4790 find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0),
4791 &XEXP (tem, 0), opnum,
4792 ADDR_TYPE (type), ind_levels, insn);
4793 if (tem != orig)
4794 push_reg_equiv_alt_mem (regno, tem);
4702 }
4703 /* We can avoid a reload if the register's equivalent memory
4704 expression is valid as an indirect memory address.
4705 But not all addresses are valid in a mem used as an indirect
4706 address: only reg or reg+constant. */
4707
4708 if (ind_levels > 0
4709 && strict_memory_address_p (mode, tem)
4795 }
4796 /* We can avoid a reload if the register's equivalent memory
4797 expression is valid as an indirect memory address.
4798 But not all addresses are valid in a mem used as an indirect
4799 address: only reg or reg+constant. */
4800
4801 if (ind_levels > 0
4802 && strict_memory_address_p (mode, tem)
4710 && (GET_CODE (XEXP (tem, 0)) == REG
4803 && (REG_P (XEXP (tem, 0))
4711 || (GET_CODE (XEXP (tem, 0)) == PLUS
4804 || (GET_CODE (XEXP (tem, 0)) == PLUS
4712 && GET_CODE (XEXP (XEXP (tem, 0), 0)) == REG
4805 && REG_P (XEXP (XEXP (tem, 0), 0))
4713 && CONSTANT_P (XEXP (XEXP (tem, 0), 1)))))
4714 {
4715 /* TEM is not the same as what we'll be replacing the
4716 pseudo with after reload, put a USE in front of INSN
4717 in the final reload pass. */
4718 if (replace_reloads
4719 && num_not_at_initial_offset
4720 && ! rtx_equal_p (tem, reg_equiv_mem[regno]))

--- 14 unchanged lines hidden (view full) ---

4735 }
4736 }
4737
4738 /* The only remaining case where we can avoid a reload is if this is a
4739 hard register that is valid as a base register and which is not the
4740 subject of a CLOBBER in this insn. */
4741
4742 else if (regno < FIRST_PSEUDO_REGISTER
4806 && CONSTANT_P (XEXP (XEXP (tem, 0), 1)))))
4807 {
4808 /* TEM is not the same as what we'll be replacing the
4809 pseudo with after reload, put a USE in front of INSN
4810 in the final reload pass. */
4811 if (replace_reloads
4812 && num_not_at_initial_offset
4813 && ! rtx_equal_p (tem, reg_equiv_mem[regno]))

--- 14 unchanged lines hidden (view full) ---

4828 }
4829 }
4830
4831 /* The only remaining case where we can avoid a reload is if this is a
4832 hard register that is valid as a base register and which is not the
4833 subject of a CLOBBER in this insn. */
4834
4835 else if (regno < FIRST_PSEUDO_REGISTER
4743 && REGNO_MODE_OK_FOR_BASE_P (regno, mode)
4836 && regno_ok_for_base_p (regno, mode, MEM, SCRATCH)
4744 && ! regno_clobbered_p (regno, this_insn, mode, 0))
4745 return 0;
4746
4747 /* If we do not have one of the cases above, we must do the reload. */
4837 && ! regno_clobbered_p (regno, this_insn, mode, 0))
4838 return 0;
4839
4840 /* If we do not have one of the cases above, we must do the reload. */
4748 push_reload (ad, NULL_RTX, loc, (rtx*) 0, MODE_BASE_REG_CLASS (mode),
4841 push_reload (ad, NULL_RTX, loc, (rtx*) 0, base_reg_class (mode, MEM, SCRATCH),
4749 GET_MODE (ad), VOIDmode, 0, 0, opnum, type);
4750 return 1;
4751 }
4752
4753 if (strict_memory_address_p (mode, ad))
4754 {
4755 /* The address appears valid, so reloads are not needed.
4756 But the address may contain an eliminable register.
4757 This can happen because a machine with indirect addressing
4758 may consider a pseudo register by itself a valid address even when
4759 it has failed to get a hard reg.
4760 So do a tree-walk to find and eliminate all such regs. */
4761
4762 /* But first quickly dispose of a common case. */
4763 if (GET_CODE (ad) == PLUS
4764 && GET_CODE (XEXP (ad, 1)) == CONST_INT
4842 GET_MODE (ad), VOIDmode, 0, 0, opnum, type);
4843 return 1;
4844 }
4845
4846 if (strict_memory_address_p (mode, ad))
4847 {
4848 /* The address appears valid, so reloads are not needed.
4849 But the address may contain an eliminable register.
4850 This can happen because a machine with indirect addressing
4851 may consider a pseudo register by itself a valid address even when
4852 it has failed to get a hard reg.
4853 So do a tree-walk to find and eliminate all such regs. */
4854
4855 /* But first quickly dispose of a common case. */
4856 if (GET_CODE (ad) == PLUS
4857 && GET_CODE (XEXP (ad, 1)) == CONST_INT
4765 && GET_CODE (XEXP (ad, 0)) == REG
4858 && REG_P (XEXP (ad, 0))
4766 && reg_equiv_constant[REGNO (XEXP (ad, 0))] == 0)
4767 return 0;
4768
4769 subst_reg_equivs_changed = 0;
4770 *loc = subst_reg_equivs (ad, insn);
4771
4772 if (! subst_reg_equivs_changed)
4773 return 0;

--- 11 unchanged lines hidden (view full) ---

4785 LEGITIMIZE_RELOAD_ADDRESS (ad, GET_MODE (*memrefloc), opnum, type,
4786 ind_levels, win);
4787 }
4788 break;
4789 win:
4790 *memrefloc = copy_rtx (*memrefloc);
4791 XEXP (*memrefloc, 0) = ad;
4792 move_replacements (&ad, &XEXP (*memrefloc, 0));
4859 && reg_equiv_constant[REGNO (XEXP (ad, 0))] == 0)
4860 return 0;
4861
4862 subst_reg_equivs_changed = 0;
4863 *loc = subst_reg_equivs (ad, insn);
4864
4865 if (! subst_reg_equivs_changed)
4866 return 0;

--- 11 unchanged lines hidden (view full) ---

4878 LEGITIMIZE_RELOAD_ADDRESS (ad, GET_MODE (*memrefloc), opnum, type,
4879 ind_levels, win);
4880 }
4881 break;
4882 win:
4883 *memrefloc = copy_rtx (*memrefloc);
4884 XEXP (*memrefloc, 0) = ad;
4885 move_replacements (&ad, &XEXP (*memrefloc, 0));
4793 return 1;
4886 return -1;
4794 }
4795 while (0);
4796#endif
4797
4798 /* The address is not valid. We have to figure out why. First see if
4799 we have an outer AND and remove it if so. Then analyze what's inside. */
4800
4801 if (GET_CODE (ad) == AND)

--- 4 unchanged lines hidden (view full) ---

4806 }
4807
4808 /* One possibility for why the address is invalid is that it is itself
4809 a MEM. This can happen when the frame pointer is being eliminated, a
4810 pseudo is not allocated to a hard register, and the offset between the
4811 frame and stack pointers is not its initial value. In that case the
4812 pseudo will have been replaced by a MEM referring to the
4813 stack pointer. */
4887 }
4888 while (0);
4889#endif
4890
4891 /* The address is not valid. We have to figure out why. First see if
4892 we have an outer AND and remove it if so. Then analyze what's inside. */
4893
4894 if (GET_CODE (ad) == AND)

--- 4 unchanged lines hidden (view full) ---

4899 }
4900
4901 /* One possibility for why the address is invalid is that it is itself
4902 a MEM. This can happen when the frame pointer is being eliminated, a
4903 pseudo is not allocated to a hard register, and the offset between the
4904 frame and stack pointers is not its initial value. In that case the
4905 pseudo will have been replaced by a MEM referring to the
4906 stack pointer. */
4814 if (GET_CODE (ad) == MEM)
4907 if (MEM_P (ad))
4815 {
4816 /* First ensure that the address in this MEM is valid. Then, unless
4817 indirect addresses are valid, reload the MEM into a register. */
4818 tem = ad;
4819 find_reloads_address (GET_MODE (ad), &tem, XEXP (ad, 0), &XEXP (ad, 0),
4820 opnum, ADDR_TYPE (type),
4821 ind_levels == 0 ? 0 : ind_levels - 1, insn);
4822

--- 9 unchanged lines hidden (view full) ---

4832 }
4833
4834 /* Check similar cases as for indirect addresses as above except
4835 that we can allow pseudos and a MEM since they should have been
4836 taken care of above. */
4837
4838 if (ind_levels == 0
4839 || (GET_CODE (XEXP (tem, 0)) == SYMBOL_REF && ! indirect_symref_ok)
4908 {
4909 /* First ensure that the address in this MEM is valid. Then, unless
4910 indirect addresses are valid, reload the MEM into a register. */
4911 tem = ad;
4912 find_reloads_address (GET_MODE (ad), &tem, XEXP (ad, 0), &XEXP (ad, 0),
4913 opnum, ADDR_TYPE (type),
4914 ind_levels == 0 ? 0 : ind_levels - 1, insn);
4915

--- 9 unchanged lines hidden (view full) ---

4925 }
4926
4927 /* Check similar cases as for indirect addresses as above except
4928 that we can allow pseudos and a MEM since they should have been
4929 taken care of above. */
4930
4931 if (ind_levels == 0
4932 || (GET_CODE (XEXP (tem, 0)) == SYMBOL_REF && ! indirect_symref_ok)
4840 || GET_CODE (XEXP (tem, 0)) == MEM
4841 || ! (GET_CODE (XEXP (tem, 0)) == REG
4933 || MEM_P (XEXP (tem, 0))
4934 || ! (REG_P (XEXP (tem, 0))
4842 || (GET_CODE (XEXP (tem, 0)) == PLUS
4935 || (GET_CODE (XEXP (tem, 0)) == PLUS
4843 && GET_CODE (XEXP (XEXP (tem, 0), 0)) == REG
4936 && REG_P (XEXP (XEXP (tem, 0), 0))
4844 && GET_CODE (XEXP (XEXP (tem, 0), 1)) == CONST_INT)))
4845 {
4846 /* Must use TEM here, not AD, since it is the one that will
4847 have any subexpressions reloaded, if needed. */
4848 push_reload (tem, NULL_RTX, loc, (rtx*) 0,
4937 && GET_CODE (XEXP (XEXP (tem, 0), 1)) == CONST_INT)))
4938 {
4939 /* Must use TEM here, not AD, since it is the one that will
4940 have any subexpressions reloaded, if needed. */
4941 push_reload (tem, NULL_RTX, loc, (rtx*) 0,
4849 MODE_BASE_REG_CLASS (mode), GET_MODE (tem),
4942 base_reg_class (mode, MEM, SCRATCH), GET_MODE (tem),
4850 VOIDmode, 0,
4851 0, opnum, type);
4852 return ! removed_and;
4853 }
4854 else
4855 return 0;
4856 }
4857
4858 /* If we have address of a stack slot but it's not valid because the
4859 displacement is too large, compute the sum in a register.
4860 Handle all base registers here, not just fp/ap/sp, because on some
4861 targets (namely SH) we can also get too large displacements from
4862 big-endian corrections. */
4863 else if (GET_CODE (ad) == PLUS
4943 VOIDmode, 0,
4944 0, opnum, type);
4945 return ! removed_and;
4946 }
4947 else
4948 return 0;
4949 }
4950
4951 /* If we have address of a stack slot but it's not valid because the
4952 displacement is too large, compute the sum in a register.
4953 Handle all base registers here, not just fp/ap/sp, because on some
4954 targets (namely SH) we can also get too large displacements from
4955 big-endian corrections. */
4956 else if (GET_CODE (ad) == PLUS
4864 && GET_CODE (XEXP (ad, 0)) == REG
4957 && REG_P (XEXP (ad, 0))
4865 && REGNO (XEXP (ad, 0)) < FIRST_PSEUDO_REGISTER
4958 && REGNO (XEXP (ad, 0)) < FIRST_PSEUDO_REGISTER
4866 && REG_MODE_OK_FOR_BASE_P (XEXP (ad, 0), mode)
4867 && GET_CODE (XEXP (ad, 1)) == CONST_INT)
4959 && GET_CODE (XEXP (ad, 1)) == CONST_INT
4960 && regno_ok_for_base_p (REGNO (XEXP (ad, 0)), mode, PLUS,
4961 CONST_INT))
4962
4868 {
4869 /* Unshare the MEM rtx so we can safely alter it. */
4870 if (memrefloc)
4871 {
4872 *memrefloc = copy_rtx (*memrefloc);
4873 loc = &XEXP (*memrefloc, 0);
4874 if (removed_and)
4875 loc = &XEXP (*loc, 0);

--- 11 unchanged lines hidden (view full) ---

4887 type, ind_levels);
4888 return 0;
4889 }
4890 else
4891 {
4892 /* If the sum of two regs is not necessarily valid,
4893 reload the sum into a base reg.
4894 That will at least work. */
4963 {
4964 /* Unshare the MEM rtx so we can safely alter it. */
4965 if (memrefloc)
4966 {
4967 *memrefloc = copy_rtx (*memrefloc);
4968 loc = &XEXP (*memrefloc, 0);
4969 if (removed_and)
4970 loc = &XEXP (*loc, 0);

--- 11 unchanged lines hidden (view full) ---

4982 type, ind_levels);
4983 return 0;
4984 }
4985 else
4986 {
4987 /* If the sum of two regs is not necessarily valid,
4988 reload the sum into a base reg.
4989 That will at least work. */
4895 find_reloads_address_part (ad, loc, MODE_BASE_REG_CLASS (mode),
4990 find_reloads_address_part (ad, loc,
4991 base_reg_class (mode, MEM, SCRATCH),
4896 Pmode, opnum, type, ind_levels);
4897 }
4898 return ! removed_and;
4899 }
4900
4901 /* If we have an indexed stack slot, there are three possible reasons why
4902 it might be invalid: The index might need to be reloaded, the address
4903 might have been made by frame pointer elimination and hence have a
4904 constant out of range, or both reasons might apply.
4905
4906 We can easily check for an index needing reload, but even if that is the
4907 case, we might also have an invalid constant. To avoid making the
4908 conservative assumption and requiring two reloads, we see if this address
4909 is valid when not interpreted strictly. If it is, the only problem is
4910 that the index needs a reload and find_reloads_address_1 will take care
4911 of it.
4912
4913 Handle all base registers here, not just fp/ap/sp, because on some
4914 targets (namely SPARC) we can also get invalid addresses from preventive
4992 Pmode, opnum, type, ind_levels);
4993 }
4994 return ! removed_and;
4995 }
4996
4997 /* If we have an indexed stack slot, there are three possible reasons why
4998 it might be invalid: The index might need to be reloaded, the address
4999 might have been made by frame pointer elimination and hence have a
5000 constant out of range, or both reasons might apply.
5001
5002 We can easily check for an index needing reload, but even if that is the
5003 case, we might also have an invalid constant. To avoid making the
5004 conservative assumption and requiring two reloads, we see if this address
5005 is valid when not interpreted strictly. If it is, the only problem is
5006 that the index needs a reload and find_reloads_address_1 will take care
5007 of it.
5008
5009 Handle all base registers here, not just fp/ap/sp, because on some
5010 targets (namely SPARC) we can also get invalid addresses from preventive
4915 subreg big-endian corrections made by find_reloads_toplev.
5011 subreg big-endian corrections made by find_reloads_toplev. We
5012 can also get expressions involving LO_SUM (rather than PLUS) from
5013 find_reloads_subreg_address.
4916
4917 If we decide to do something, it must be that `double_reg_address_ok'
4918 is true. We generate a reload of the base register + constant and
4919 rework the sum so that the reload register will be added to the index.
4920 This is safe because we know the address isn't shared.
4921
4922 We check for the base register as both the first and second operand of
5014
5015 If we decide to do something, it must be that `double_reg_address_ok'
5016 is true. We generate a reload of the base register + constant and
5017 rework the sum so that the reload register will be added to the index.
5018 This is safe because we know the address isn't shared.
5019
5020 We check for the base register as both the first and second operand of
4923 the innermost PLUS. */
5021 the innermost PLUS and/or LO_SUM. */
4924
5022
4925 else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT
4926 && GET_CODE (XEXP (ad, 0)) == PLUS
4927 && GET_CODE (XEXP (XEXP (ad, 0), 0)) == REG
4928 && REGNO (XEXP (XEXP (ad, 0), 0)) < FIRST_PSEUDO_REGISTER
4929 && (REG_MODE_OK_FOR_BASE_P (XEXP (XEXP (ad, 0), 0), mode)
4930 || XEXP (XEXP (ad, 0), 0) == frame_pointer_rtx
4931#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
4932 || XEXP (XEXP (ad, 0), 0) == hard_frame_pointer_rtx
4933#endif
4934#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
4935 || XEXP (XEXP (ad, 0), 0) == arg_pointer_rtx
4936#endif
4937 || XEXP (XEXP (ad, 0), 0) == stack_pointer_rtx)
4938 && ! maybe_memory_address_p (mode, ad, &XEXP (XEXP (ad, 0), 1)))
5023 for (op_index = 0; op_index < 2; ++op_index)
4939 {
5024 {
4940 *loc = ad = gen_rtx_PLUS (GET_MODE (ad),
4941 plus_constant (XEXP (XEXP (ad, 0), 0),
4942 INTVAL (XEXP (ad, 1))),
4943 XEXP (XEXP (ad, 0), 1));
4944 find_reloads_address_part (XEXP (ad, 0), &XEXP (ad, 0),
4945 MODE_BASE_REG_CLASS (mode),
4946 GET_MODE (ad), opnum, type, ind_levels);
4947 find_reloads_address_1 (mode, XEXP (ad, 1), 1, &XEXP (ad, 1), opnum,
4948 type, 0, insn);
5025 rtx operand, addend;
5026 enum rtx_code inner_code;
4949
5027
4950 return 0;
4951 }
5028 if (GET_CODE (ad) != PLUS)
5029 continue;
4952
5030
4953 else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT
4954 && GET_CODE (XEXP (ad, 0)) == PLUS
4955 && GET_CODE (XEXP (XEXP (ad, 0), 1)) == REG
4956 && REGNO (XEXP (XEXP (ad, 0), 1)) < FIRST_PSEUDO_REGISTER
4957 && (REG_MODE_OK_FOR_BASE_P (XEXP (XEXP (ad, 0), 1), mode)
4958 || XEXP (XEXP (ad, 0), 1) == frame_pointer_rtx
5031 inner_code = GET_CODE (XEXP (ad, 0));
5032 if (!(GET_CODE (ad) == PLUS
5033 && GET_CODE (XEXP (ad, 1)) == CONST_INT
5034 && (inner_code == PLUS || inner_code == LO_SUM)))
5035 continue;
5036
5037 operand = XEXP (XEXP (ad, 0), op_index);
5038 if (!REG_P (operand) || REGNO (operand) >= FIRST_PSEUDO_REGISTER)
5039 continue;
5040
5041 addend = XEXP (XEXP (ad, 0), 1 - op_index);
5042
5043 if ((regno_ok_for_base_p (REGNO (operand), mode, inner_code,
5044 GET_CODE (addend))
5045 || operand == frame_pointer_rtx
4959#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
5046#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
4960 || XEXP (XEXP (ad, 0), 1) == hard_frame_pointer_rtx
5047 || operand == hard_frame_pointer_rtx
4961#endif
4962#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
5048#endif
5049#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
4963 || XEXP (XEXP (ad, 0), 1) == arg_pointer_rtx
5050 || operand == arg_pointer_rtx
4964#endif
5051#endif
4965 || XEXP (XEXP (ad, 0), 1) == stack_pointer_rtx)
4966 && ! maybe_memory_address_p (mode, ad, &XEXP (XEXP (ad, 0), 0)))
4967 {
4968 *loc = ad = gen_rtx_PLUS (GET_MODE (ad),
4969 XEXP (XEXP (ad, 0), 0),
4970 plus_constant (XEXP (XEXP (ad, 0), 1),
4971 INTVAL (XEXP (ad, 1))));
4972 find_reloads_address_part (XEXP (ad, 1), &XEXP (ad, 1),
4973 MODE_BASE_REG_CLASS (mode),
4974 GET_MODE (ad), opnum, type, ind_levels);
4975 find_reloads_address_1 (mode, XEXP (ad, 0), 1, &XEXP (ad, 0), opnum,
4976 type, 0, insn);
5052 || operand == stack_pointer_rtx)
5053 && ! maybe_memory_address_p (mode, ad,
5054 &XEXP (XEXP (ad, 0), 1 - op_index)))
5055 {
5056 rtx offset_reg;
5057 enum reg_class cls;
4977
5058
4978 return 0;
5059 offset_reg = plus_constant (operand, INTVAL (XEXP (ad, 1)));
5060
5061 /* Form the adjusted address. */
5062 if (GET_CODE (XEXP (ad, 0)) == PLUS)
5063 ad = gen_rtx_PLUS (GET_MODE (ad),
5064 op_index == 0 ? offset_reg : addend,
5065 op_index == 0 ? addend : offset_reg);
5066 else
5067 ad = gen_rtx_LO_SUM (GET_MODE (ad),
5068 op_index == 0 ? offset_reg : addend,
5069 op_index == 0 ? addend : offset_reg);
5070 *loc = ad;
5071
5072 cls = base_reg_class (mode, MEM, GET_CODE (addend));
5073 find_reloads_address_part (XEXP (ad, op_index),
5074 &XEXP (ad, op_index), cls,
5075 GET_MODE (ad), opnum, type, ind_levels);
5076 find_reloads_address_1 (mode,
5077 XEXP (ad, 1 - op_index), 1, GET_CODE (ad),
5078 GET_CODE (XEXP (ad, op_index)),
5079 &XEXP (ad, 1 - op_index), opnum,
5080 type, 0, insn);
5081
5082 return 0;
5083 }
4979 }
4980
4981 /* See if address becomes valid when an eliminable register
4982 in a sum is replaced. */
4983
4984 tem = ad;
4985 if (GET_CODE (ad) == PLUS)
4986 tem = subst_indexed_address (ad);

--- 24 unchanged lines hidden (view full) ---

5011 && CONSTANT_POOL_ADDRESS_P (ad))
5012 {
5013 *memrefloc = copy_rtx (*memrefloc);
5014 loc = &XEXP (*memrefloc, 0);
5015 if (removed_and)
5016 loc = &XEXP (*loc, 0);
5017 }
5018
5084 }
5085
5086 /* See if address becomes valid when an eliminable register
5087 in a sum is replaced. */
5088
5089 tem = ad;
5090 if (GET_CODE (ad) == PLUS)
5091 tem = subst_indexed_address (ad);

--- 24 unchanged lines hidden (view full) ---

5116 && CONSTANT_POOL_ADDRESS_P (ad))
5117 {
5118 *memrefloc = copy_rtx (*memrefloc);
5119 loc = &XEXP (*memrefloc, 0);
5120 if (removed_and)
5121 loc = &XEXP (*loc, 0);
5122 }
5123
5019 find_reloads_address_part (ad, loc, MODE_BASE_REG_CLASS (mode),
5124 find_reloads_address_part (ad, loc, base_reg_class (mode, MEM, SCRATCH),
5020 Pmode, opnum, type, ind_levels);
5021 return ! removed_and;
5022 }
5023
5125 Pmode, opnum, type, ind_levels);
5126 return ! removed_and;
5127 }
5128
5024 return find_reloads_address_1 (mode, ad, 0, loc, opnum, type, ind_levels,
5025 insn);
5129 return find_reloads_address_1 (mode, ad, 0, MEM, SCRATCH, loc, opnum, type,
5130 ind_levels, insn);
5026}
5027
5028/* Find all pseudo regs appearing in AD
5029 that are eliminable in favor of equivalent values
5030 and do not have hard regs; replace them by their equivalents.
5031 INSN, if nonzero, is the insn in which we do the reload. We put USEs in
5032 front of it for pseudos that we have to replace with stack slots. */
5033

--- 128 unchanged lines hidden (view full) ---

5162 rtx op0 = 0, op1 = 0, op2 = 0;
5163 rtx tem;
5164 int regno;
5165
5166 if (GET_CODE (addr) == PLUS)
5167 {
5168 /* Try to find a register to replace. */
5169 op0 = XEXP (addr, 0), op1 = XEXP (addr, 1), op2 = 0;
5131}
5132
5133/* Find all pseudo regs appearing in AD
5134 that are eliminable in favor of equivalent values
5135 and do not have hard regs; replace them by their equivalents.
5136 INSN, if nonzero, is the insn in which we do the reload. We put USEs in
5137 front of it for pseudos that we have to replace with stack slots. */
5138

--- 128 unchanged lines hidden (view full) ---

5267 rtx op0 = 0, op1 = 0, op2 = 0;
5268 rtx tem;
5269 int regno;
5270
5271 if (GET_CODE (addr) == PLUS)
5272 {
5273 /* Try to find a register to replace. */
5274 op0 = XEXP (addr, 0), op1 = XEXP (addr, 1), op2 = 0;
5170 if (GET_CODE (op0) == REG
5275 if (REG_P (op0)
5171 && (regno = REGNO (op0)) >= FIRST_PSEUDO_REGISTER
5172 && reg_renumber[regno] < 0
5173 && reg_equiv_constant[regno] != 0)
5174 op0 = reg_equiv_constant[regno];
5276 && (regno = REGNO (op0)) >= FIRST_PSEUDO_REGISTER
5277 && reg_renumber[regno] < 0
5278 && reg_equiv_constant[regno] != 0)
5279 op0 = reg_equiv_constant[regno];
5175 else if (GET_CODE (op1) == REG
5280 else if (REG_P (op1)
5176 && (regno = REGNO (op1)) >= FIRST_PSEUDO_REGISTER
5177 && reg_renumber[regno] < 0
5178 && reg_equiv_constant[regno] != 0)
5179 op1 = reg_equiv_constant[regno];
5180 else if (GET_CODE (op0) == PLUS
5181 && (tem = subst_indexed_address (op0)) != op0)
5182 op0 = tem;
5183 else if (GET_CODE (op1) == PLUS

--- 45 unchanged lines hidden (view full) ---

5229
5230/* Record the pseudo registers we must reload into hard registers in a
5231 subexpression of a would-be memory address, X referring to a value
5232 in mode MODE. (This function is not called if the address we find
5233 is strictly valid.)
5234
5235 CONTEXT = 1 means we are considering regs as index regs,
5236 = 0 means we are considering them as base regs.
5281 && (regno = REGNO (op1)) >= FIRST_PSEUDO_REGISTER
5282 && reg_renumber[regno] < 0
5283 && reg_equiv_constant[regno] != 0)
5284 op1 = reg_equiv_constant[regno];
5285 else if (GET_CODE (op0) == PLUS
5286 && (tem = subst_indexed_address (op0)) != op0)
5287 op0 = tem;
5288 else if (GET_CODE (op1) == PLUS

--- 45 unchanged lines hidden (view full) ---

5334
5335/* Record the pseudo registers we must reload into hard registers in a
5336 subexpression of a would-be memory address, X referring to a value
5337 in mode MODE. (This function is not called if the address we find
5338 is strictly valid.)
5339
5340 CONTEXT = 1 means we are considering regs as index regs,
5341 = 0 means we are considering them as base regs.
5237
5342 OUTER_CODE is the code of the enclosing RTX, typically a MEM, a PLUS,
5343 or an autoinc code.
5344 If CONTEXT == 0 and OUTER_CODE is a PLUS or LO_SUM, then INDEX_CODE
5345 is the code of the index part of the address. Otherwise, pass SCRATCH
5346 for this argument.
5238 OPNUM and TYPE specify the purpose of any reloads made.
5239
5240 IND_LEVELS says how many levels of indirect addressing are
5241 supported at this point in the address.
5242
5243 INSN, if nonzero, is the insn in which we do the reload. It is used
5244 to determine if we may generate output reloads.
5245
5246 We return nonzero if X, as a whole, is reloaded or replaced. */
5247
5248/* Note that we take shortcuts assuming that no multi-reg machine mode
5249 occurs as part of an address.
5250 Also, this is not fully machine-customizable; it works for machines
5251 such as VAXen and 68000's and 32000's, but other possible machines
5347 OPNUM and TYPE specify the purpose of any reloads made.
5348
5349 IND_LEVELS says how many levels of indirect addressing are
5350 supported at this point in the address.
5351
5352 INSN, if nonzero, is the insn in which we do the reload. It is used
5353 to determine if we may generate output reloads.
5354
5355 We return nonzero if X, as a whole, is reloaded or replaced. */
5356
5357/* Note that we take shortcuts assuming that no multi-reg machine mode
5358 occurs as part of an address.
5359 Also, this is not fully machine-customizable; it works for machines
5360 such as VAXen and 68000's and 32000's, but other possible machines
5252 could have addressing modes that this does not handle right. */
5361 could have addressing modes that this does not handle right.
5362 If you add push_reload calls here, you need to make sure gen_reload
5363 handles those cases gracefully. */
5253
5254static int
5255find_reloads_address_1 (enum machine_mode mode, rtx x, int context,
5364
5365static int
5366find_reloads_address_1 (enum machine_mode mode, rtx x, int context,
5367 enum rtx_code outer_code, enum rtx_code index_code,
5256 rtx *loc, int opnum, enum reload_type type,
5257 int ind_levels, rtx insn)
5258{
5368 rtx *loc, int opnum, enum reload_type type,
5369 int ind_levels, rtx insn)
5370{
5371#define REG_OK_FOR_CONTEXT(CONTEXT, REGNO, MODE, OUTER, INDEX) \
5372 ((CONTEXT) == 0 \
5373 ? regno_ok_for_base_p (REGNO, MODE, OUTER, INDEX) \
5374 : REGNO_OK_FOR_INDEX_P (REGNO))
5375
5376 enum reg_class context_reg_class;
5259 RTX_CODE code = GET_CODE (x);
5260
5377 RTX_CODE code = GET_CODE (x);
5378
5379 if (context == 1)
5380 context_reg_class = INDEX_REG_CLASS;
5381 else
5382 context_reg_class = base_reg_class (mode, outer_code, index_code);
5383
5261 switch (code)
5262 {
5263 case PLUS:
5264 {
5265 rtx orig_op0 = XEXP (x, 0);
5266 rtx orig_op1 = XEXP (x, 1);
5267 RTX_CODE code0 = GET_CODE (orig_op0);
5268 RTX_CODE code1 = GET_CODE (orig_op1);

--- 23 unchanged lines hidden (view full) ---

5292 op1 = gen_rtx_REG (GET_MODE (op1),
5293 (REGNO (op1) +
5294 subreg_regno_offset (REGNO (SUBREG_REG (orig_op1)),
5295 GET_MODE (SUBREG_REG (orig_op1)),
5296 SUBREG_BYTE (orig_op1),
5297 GET_MODE (orig_op1))));
5298 }
5299 /* Plus in the index register may be created only as a result of
5384 switch (code)
5385 {
5386 case PLUS:
5387 {
5388 rtx orig_op0 = XEXP (x, 0);
5389 rtx orig_op1 = XEXP (x, 1);
5390 RTX_CODE code0 = GET_CODE (orig_op0);
5391 RTX_CODE code1 = GET_CODE (orig_op1);

--- 23 unchanged lines hidden (view full) ---

5415 op1 = gen_rtx_REG (GET_MODE (op1),
5416 (REGNO (op1) +
5417 subreg_regno_offset (REGNO (SUBREG_REG (orig_op1)),
5418 GET_MODE (SUBREG_REG (orig_op1)),
5419 SUBREG_BYTE (orig_op1),
5420 GET_MODE (orig_op1))));
5421 }
5422 /* Plus in the index register may be created only as a result of
5300 register remateralization for expression like &localvar*4. Reload it.
5423 register rematerialization for expression like &localvar*4. Reload it.
5301 It may be possible to combine the displacement on the outer level,
5302 but it is probably not worthwhile to do so. */
5424 It may be possible to combine the displacement on the outer level,
5425 but it is probably not worthwhile to do so. */
5303 if (context)
5426 if (context == 1)
5304 {
5305 find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0),
5306 opnum, ADDR_TYPE (type), ind_levels, insn);
5307 push_reload (*loc, NULL_RTX, loc, (rtx*) 0,
5427 {
5428 find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0),
5429 opnum, ADDR_TYPE (type), ind_levels, insn);
5430 push_reload (*loc, NULL_RTX, loc, (rtx*) 0,
5308 (context ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (mode)),
5431 context_reg_class,
5309 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
5310 return 1;
5311 }
5312
5313 if (code0 == MULT || code0 == SIGN_EXTEND || code0 == TRUNCATE
5314 || code0 == ZERO_EXTEND || code1 == MEM)
5315 {
5432 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
5433 return 1;
5434 }
5435
5436 if (code0 == MULT || code0 == SIGN_EXTEND || code0 == TRUNCATE
5437 || code0 == ZERO_EXTEND || code1 == MEM)
5438 {
5316 find_reloads_address_1 (mode, orig_op0, 1, &XEXP (x, 0), opnum,
5317 type, ind_levels, insn);
5318 find_reloads_address_1 (mode, orig_op1, 0, &XEXP (x, 1), opnum,
5319 type, ind_levels, insn);
5439 find_reloads_address_1 (mode, orig_op0, 1, PLUS, SCRATCH,
5440 &XEXP (x, 0), opnum, type, ind_levels,
5441 insn);
5442 find_reloads_address_1 (mode, orig_op1, 0, PLUS, code0,
5443 &XEXP (x, 1), opnum, type, ind_levels,
5444 insn);
5320 }
5321
5322 else if (code1 == MULT || code1 == SIGN_EXTEND || code1 == TRUNCATE
5323 || code1 == ZERO_EXTEND || code0 == MEM)
5324 {
5445 }
5446
5447 else if (code1 == MULT || code1 == SIGN_EXTEND || code1 == TRUNCATE
5448 || code1 == ZERO_EXTEND || code0 == MEM)
5449 {
5325 find_reloads_address_1 (mode, orig_op0, 0, &XEXP (x, 0), opnum,
5326 type, ind_levels, insn);
5327 find_reloads_address_1 (mode, orig_op1, 1, &XEXP (x, 1), opnum,
5328 type, ind_levels, insn);
5450 find_reloads_address_1 (mode, orig_op0, 0, PLUS, code1,
5451 &XEXP (x, 0), opnum, type, ind_levels,
5452 insn);
5453 find_reloads_address_1 (mode, orig_op1, 1, PLUS, SCRATCH,
5454 &XEXP (x, 1), opnum, type, ind_levels,
5455 insn);
5329 }
5330
5331 else if (code0 == CONST_INT || code0 == CONST
5332 || code0 == SYMBOL_REF || code0 == LABEL_REF)
5456 }
5457
5458 else if (code0 == CONST_INT || code0 == CONST
5459 || code0 == SYMBOL_REF || code0 == LABEL_REF)
5333 find_reloads_address_1 (mode, orig_op1, 0, &XEXP (x, 1), opnum,
5334 type, ind_levels, insn);
5460 find_reloads_address_1 (mode, orig_op1, 0, PLUS, code0,
5461 &XEXP (x, 1), opnum, type, ind_levels,
5462 insn);
5335
5336 else if (code1 == CONST_INT || code1 == CONST
5337 || code1 == SYMBOL_REF || code1 == LABEL_REF)
5463
5464 else if (code1 == CONST_INT || code1 == CONST
5465 || code1 == SYMBOL_REF || code1 == LABEL_REF)
5338 find_reloads_address_1 (mode, orig_op0, 0, &XEXP (x, 0), opnum,
5339 type, ind_levels, insn);
5466 find_reloads_address_1 (mode, orig_op0, 0, PLUS, code1,
5467 &XEXP (x, 0), opnum, type, ind_levels,
5468 insn);
5340
5341 else if (code0 == REG && code1 == REG)
5342 {
5469
5470 else if (code0 == REG && code1 == REG)
5471 {
5343 if (REG_OK_FOR_INDEX_P (op0)
5344 && REG_MODE_OK_FOR_BASE_P (op1, mode))
5472 if (REGNO_OK_FOR_INDEX_P (REGNO (op0))
5473 && regno_ok_for_base_p (REGNO (op1), mode, PLUS, REG))
5345 return 0;
5474 return 0;
5346 else if (REG_OK_FOR_INDEX_P (op1)
5347 && REG_MODE_OK_FOR_BASE_P (op0, mode))
5475 else if (REGNO_OK_FOR_INDEX_P (REGNO (op1))
5476 && regno_ok_for_base_p (REGNO (op0), mode, PLUS, REG))
5348 return 0;
5477 return 0;
5349 else if (REG_MODE_OK_FOR_BASE_P (op1, mode))
5350 find_reloads_address_1 (mode, orig_op0, 1, &XEXP (x, 0), opnum,
5351 type, ind_levels, insn);
5352 else if (REG_MODE_OK_FOR_BASE_P (op0, mode))
5353 find_reloads_address_1 (mode, orig_op1, 1, &XEXP (x, 1), opnum,
5354 type, ind_levels, insn);
5355 else if (REG_OK_FOR_INDEX_P (op1))
5356 find_reloads_address_1 (mode, orig_op0, 0, &XEXP (x, 0), opnum,
5357 type, ind_levels, insn);
5358 else if (REG_OK_FOR_INDEX_P (op0))
5359 find_reloads_address_1 (mode, orig_op1, 0, &XEXP (x, 1), opnum,
5360 type, ind_levels, insn);
5478 else if (regno_ok_for_base_p (REGNO (op1), mode, PLUS, REG))
5479 find_reloads_address_1 (mode, orig_op0, 1, PLUS, SCRATCH,
5480 &XEXP (x, 0), opnum, type, ind_levels,
5481 insn);
5482 else if (regno_ok_for_base_p (REGNO (op0), mode, PLUS, REG))
5483 find_reloads_address_1 (mode, orig_op1, 1, PLUS, SCRATCH,
5484 &XEXP (x, 1), opnum, type, ind_levels,
5485 insn);
5486 else if (REGNO_OK_FOR_INDEX_P (REGNO (op1)))
5487 find_reloads_address_1 (mode, orig_op0, 0, PLUS, REG,
5488 &XEXP (x, 0), opnum, type, ind_levels,
5489 insn);
5490 else if (REGNO_OK_FOR_INDEX_P (REGNO (op0)))
5491 find_reloads_address_1 (mode, orig_op1, 0, PLUS, REG,
5492 &XEXP (x, 1), opnum, type, ind_levels,
5493 insn);
5361 else
5362 {
5494 else
5495 {
5363 find_reloads_address_1 (mode, orig_op0, 1, &XEXP (x, 0), opnum,
5364 type, ind_levels, insn);
5365 find_reloads_address_1 (mode, orig_op1, 0, &XEXP (x, 1), opnum,
5366 type, ind_levels, insn);
5496 find_reloads_address_1 (mode, orig_op0, 1, PLUS, SCRATCH,
5497 &XEXP (x, 0), opnum, type, ind_levels,
5498 insn);
5499 find_reloads_address_1 (mode, orig_op1, 0, PLUS, REG,
5500 &XEXP (x, 1), opnum, type, ind_levels,
5501 insn);
5367 }
5368 }
5369
5370 else if (code0 == REG)
5371 {
5502 }
5503 }
5504
5505 else if (code0 == REG)
5506 {
5372 find_reloads_address_1 (mode, orig_op0, 1, &XEXP (x, 0), opnum,
5373 type, ind_levels, insn);
5374 find_reloads_address_1 (mode, orig_op1, 0, &XEXP (x, 1), opnum,
5375 type, ind_levels, insn);
5507 find_reloads_address_1 (mode, orig_op0, 1, PLUS, SCRATCH,
5508 &XEXP (x, 0), opnum, type, ind_levels,
5509 insn);
5510 find_reloads_address_1 (mode, orig_op1, 0, PLUS, REG,
5511 &XEXP (x, 1), opnum, type, ind_levels,
5512 insn);
5376 }
5377
5378 else if (code1 == REG)
5379 {
5513 }
5514
5515 else if (code1 == REG)
5516 {
5380 find_reloads_address_1 (mode, orig_op1, 1, &XEXP (x, 1), opnum,
5381 type, ind_levels, insn);
5382 find_reloads_address_1 (mode, orig_op0, 0, &XEXP (x, 0), opnum,
5383 type, ind_levels, insn);
5517 find_reloads_address_1 (mode, orig_op1, 1, PLUS, SCRATCH,
5518 &XEXP (x, 1), opnum, type, ind_levels,
5519 insn);
5520 find_reloads_address_1 (mode, orig_op0, 0, PLUS, REG,
5521 &XEXP (x, 0), opnum, type, ind_levels,
5522 insn);
5384 }
5385 }
5386
5387 return 0;
5388
5389 case POST_MODIFY:
5390 case PRE_MODIFY:
5391 {
5392 rtx op0 = XEXP (x, 0);
5393 rtx op1 = XEXP (x, 1);
5523 }
5524 }
5525
5526 return 0;
5527
5528 case POST_MODIFY:
5529 case PRE_MODIFY:
5530 {
5531 rtx op0 = XEXP (x, 0);
5532 rtx op1 = XEXP (x, 1);
5533 enum rtx_code index_code;
5534 int regno;
5535 int reloadnum;
5394
5395 if (GET_CODE (op1) != PLUS && GET_CODE (op1) != MINUS)
5396 return 0;
5397
5398 /* Currently, we only support {PRE,POST}_MODIFY constructs
5399 where a base register is {inc,dec}remented by the contents
5400 of another register or by a constant value. Thus, these
5401 operands must match. */
5536
5537 if (GET_CODE (op1) != PLUS && GET_CODE (op1) != MINUS)
5538 return 0;
5539
5540 /* Currently, we only support {PRE,POST}_MODIFY constructs
5541 where a base register is {inc,dec}remented by the contents
5542 of another register or by a constant value. Thus, these
5543 operands must match. */
5402 if (op0 != XEXP (op1, 0))
5403 abort ();
5544 gcc_assert (op0 == XEXP (op1, 0));
5404
5405 /* Require index register (or constant). Let's just handle the
5406 register case in the meantime... If the target allows
5407 auto-modify by a constant then we could try replacing a pseudo
5545
5546 /* Require index register (or constant). Let's just handle the
5547 register case in the meantime... If the target allows
5548 auto-modify by a constant then we could try replacing a pseudo
5408 register with its equivalent constant where applicable. */
5549 register with its equivalent constant where applicable.
5550
5551 If we later decide to reload the whole PRE_MODIFY or
5552 POST_MODIFY, inc_for_reload might clobber the reload register
5553 before reading the index. The index register might therefore
5554 need to live longer than a TYPE reload normally would, so be
5555 conservative and class it as RELOAD_OTHER. */
5409 if (REG_P (XEXP (op1, 1)))
5410 if (!REGNO_OK_FOR_INDEX_P (REGNO (XEXP (op1, 1))))
5556 if (REG_P (XEXP (op1, 1)))
5557 if (!REGNO_OK_FOR_INDEX_P (REGNO (XEXP (op1, 1))))
5411 find_reloads_address_1 (mode, XEXP (op1, 1), 1, &XEXP (op1, 1),
5412 opnum, type, ind_levels, insn);
5558 find_reloads_address_1 (mode, XEXP (op1, 1), 1, code, SCRATCH,
5559 &XEXP (op1, 1), opnum, RELOAD_OTHER,
5560 ind_levels, insn);
5413
5561
5414 if (REG_P (XEXP (op1, 0)))
5415 {
5416 int regno = REGNO (XEXP (op1, 0));
5417 int reloadnum;
5562 gcc_assert (REG_P (XEXP (op1, 0)));
5418
5563
5419 /* A register that is incremented cannot be constant! */
5420 if (regno >= FIRST_PSEUDO_REGISTER
5421 && reg_equiv_constant[regno] != 0)
5422 abort ();
5564 regno = REGNO (XEXP (op1, 0));
5565 index_code = GET_CODE (XEXP (op1, 1));
5423
5566
5424 /* Handle a register that is equivalent to a memory location
5425 which cannot be addressed directly. */
5426 if (reg_equiv_memory_loc[regno] != 0
5427 && (reg_equiv_address[regno] != 0
5428 || num_not_at_initial_offset))
5429 {
5430 rtx tem = make_memloc (XEXP (x, 0), regno);
5567 /* A register that is incremented cannot be constant! */
5568 gcc_assert (regno < FIRST_PSEUDO_REGISTER
5569 || reg_equiv_constant[regno] == 0);
5431
5570
5432 if (reg_equiv_address[regno]
5433 || ! rtx_equal_p (tem, reg_equiv_mem[regno]))
5434 {
5435 /* First reload the memory location's address.
5436 We can't use ADDR_TYPE (type) here, because we need to
5437 write back the value after reading it, hence we actually
5438 need two registers. */
5439 find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0),
5440 &XEXP (tem, 0), opnum,
5441 RELOAD_OTHER,
5442 ind_levels, insn);
5571 /* Handle a register that is equivalent to a memory location
5572 which cannot be addressed directly. */
5573 if (reg_equiv_memory_loc[regno] != 0
5574 && (reg_equiv_address[regno] != 0
5575 || num_not_at_initial_offset))
5576 {
5577 rtx tem = make_memloc (XEXP (x, 0), regno);
5443
5578
5444 /* Then reload the memory location into a base
5445 register. */
5446 reloadnum = push_reload (tem, tem, &XEXP (x, 0),
5447 &XEXP (op1, 0),
5448 MODE_BASE_REG_CLASS (mode),
5449 GET_MODE (x), GET_MODE (x), 0,
5450 0, opnum, RELOAD_OTHER);
5579 if (reg_equiv_address[regno]
5580 || ! rtx_equal_p (tem, reg_equiv_mem[regno]))
5581 {
5582 rtx orig = tem;
5451
5583
5452 update_auto_inc_notes (this_insn, regno, reloadnum);
5453 return 0;
5454 }
5455 }
5584 /* First reload the memory location's address.
5585 We can't use ADDR_TYPE (type) here, because we need to
5586 write back the value after reading it, hence we actually
5587 need two registers. */
5588 find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0),
5589 &XEXP (tem, 0), opnum,
5590 RELOAD_OTHER,
5591 ind_levels, insn);
5456
5592
5457 if (reg_renumber[regno] >= 0)
5458 regno = reg_renumber[regno];
5593 if (tem != orig)
5594 push_reg_equiv_alt_mem (regno, tem);
5459
5595
5460 /* We require a base register here... */
5461 if (!REGNO_MODE_OK_FOR_BASE_P (regno, GET_MODE (x)))
5462 {
5463 reloadnum = push_reload (XEXP (op1, 0), XEXP (x, 0),
5464 &XEXP (op1, 0), &XEXP (x, 0),
5465 MODE_BASE_REG_CLASS (mode),
5466 GET_MODE (x), GET_MODE (x), 0, 0,
5467 opnum, RELOAD_OTHER);
5596 /* Then reload the memory location into a base
5597 register. */
5598 reloadnum = push_reload (tem, tem, &XEXP (x, 0),
5599 &XEXP (op1, 0),
5600 base_reg_class (mode, code,
5601 index_code),
5602 GET_MODE (x), GET_MODE (x), 0,
5603 0, opnum, RELOAD_OTHER);
5468
5469 update_auto_inc_notes (this_insn, regno, reloadnum);
5470 return 0;
5471 }
5472 }
5604
5605 update_auto_inc_notes (this_insn, regno, reloadnum);
5606 return 0;
5607 }
5608 }
5473 else
5474 abort ();
5609
5610 if (reg_renumber[regno] >= 0)
5611 regno = reg_renumber[regno];
5612
5613 /* We require a base register here... */
5614 if (!regno_ok_for_base_p (regno, GET_MODE (x), code, index_code))
5615 {
5616 reloadnum = push_reload (XEXP (op1, 0), XEXP (x, 0),
5617 &XEXP (op1, 0), &XEXP (x, 0),
5618 base_reg_class (mode, code, index_code),
5619 GET_MODE (x), GET_MODE (x), 0, 0,
5620 opnum, RELOAD_OTHER);
5621
5622 update_auto_inc_notes (this_insn, regno, reloadnum);
5623 return 0;
5624 }
5475 }
5476 return 0;
5477
5478 case POST_INC:
5479 case POST_DEC:
5480 case PRE_INC:
5481 case PRE_DEC:
5625 }
5626 return 0;
5627
5628 case POST_INC:
5629 case POST_DEC:
5630 case PRE_INC:
5631 case PRE_DEC:
5482 if (GET_CODE (XEXP (x, 0)) == REG)
5632 if (REG_P (XEXP (x, 0)))
5483 {
5484 int regno = REGNO (XEXP (x, 0));
5485 int value = 0;
5486 rtx x_orig = x;
5487
5488 /* A register that is incremented cannot be constant! */
5633 {
5634 int regno = REGNO (XEXP (x, 0));
5635 int value = 0;
5636 rtx x_orig = x;
5637
5638 /* A register that is incremented cannot be constant! */
5489 if (regno >= FIRST_PSEUDO_REGISTER
5490 && reg_equiv_constant[regno] != 0)
5491 abort ();
5639 gcc_assert (regno < FIRST_PSEUDO_REGISTER
5640 || reg_equiv_constant[regno] == 0);
5492
5493 /* Handle a register that is equivalent to a memory location
5494 which cannot be addressed directly. */
5495 if (reg_equiv_memory_loc[regno] != 0
5496 && (reg_equiv_address[regno] != 0 || num_not_at_initial_offset))
5497 {
5498 rtx tem = make_memloc (XEXP (x, 0), regno);
5499 if (reg_equiv_address[regno]
5500 || ! rtx_equal_p (tem, reg_equiv_mem[regno]))
5501 {
5641
5642 /* Handle a register that is equivalent to a memory location
5643 which cannot be addressed directly. */
5644 if (reg_equiv_memory_loc[regno] != 0
5645 && (reg_equiv_address[regno] != 0 || num_not_at_initial_offset))
5646 {
5647 rtx tem = make_memloc (XEXP (x, 0), regno);
5648 if (reg_equiv_address[regno]
5649 || ! rtx_equal_p (tem, reg_equiv_mem[regno]))
5650 {
5651 rtx orig = tem;
5652
5502 /* First reload the memory location's address.
5503 We can't use ADDR_TYPE (type) here, because we need to
5504 write back the value after reading it, hence we actually
5505 need two registers. */
5506 find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0),
5507 &XEXP (tem, 0), opnum, type,
5508 ind_levels, insn);
5653 /* First reload the memory location's address.
5654 We can't use ADDR_TYPE (type) here, because we need to
5655 write back the value after reading it, hence we actually
5656 need two registers. */
5657 find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0),
5658 &XEXP (tem, 0), opnum, type,
5659 ind_levels, insn);
5660 if (tem != orig)
5661 push_reg_equiv_alt_mem (regno, tem);
5509 /* Put this inside a new increment-expression. */
5510 x = gen_rtx_fmt_e (GET_CODE (x), GET_MODE (x), tem);
5511 /* Proceed to reload that, as if it contained a register. */
5512 }
5513 }
5514
5515 /* If we have a hard register that is ok as an index,
5516 don't make a reload. If an autoincrement of a nice register
5517 isn't "valid", it must be that no autoincrement is "valid".
5518 If that is true and something made an autoincrement anyway,
5519 this must be a special context where one is allowed.
5520 (For example, a "push" instruction.)
5521 We can't improve this address, so leave it alone. */
5522
5523 /* Otherwise, reload the autoincrement into a suitable hard reg
5524 and record how much to increment by. */
5525
5526 if (reg_renumber[regno] >= 0)
5527 regno = reg_renumber[regno];
5662 /* Put this inside a new increment-expression. */
5663 x = gen_rtx_fmt_e (GET_CODE (x), GET_MODE (x), tem);
5664 /* Proceed to reload that, as if it contained a register. */
5665 }
5666 }
5667
5668 /* If we have a hard register that is ok as an index,
5669 don't make a reload. If an autoincrement of a nice register
5670 isn't "valid", it must be that no autoincrement is "valid".
5671 If that is true and something made an autoincrement anyway,
5672 this must be a special context where one is allowed.
5673 (For example, a "push" instruction.)
5674 We can't improve this address, so leave it alone. */
5675
5676 /* Otherwise, reload the autoincrement into a suitable hard reg
5677 and record how much to increment by. */
5678
5679 if (reg_renumber[regno] >= 0)
5680 regno = reg_renumber[regno];
5528 if ((regno >= FIRST_PSEUDO_REGISTER
5529 || !(context ? REGNO_OK_FOR_INDEX_P (regno)
5530 : REGNO_MODE_OK_FOR_BASE_P (regno, mode))))
5681 if (regno >= FIRST_PSEUDO_REGISTER
5682 || !REG_OK_FOR_CONTEXT (context, regno, mode, outer_code,
5683 index_code))
5531 {
5532 int reloadnum;
5533
5534 /* If we can output the register afterwards, do so, this
5535 saves the extra update.
5536 We can do so if we have an INSN - i.e. no JUMP_INSN nor
5537 CALL_INSN - and it does not set CC0.
5538 But don't do this if we cannot directly address the
5539 memory location, since this will make it harder to
5540 reuse address reloads, and increases register pressure.
5541 Also don't do this if we can probably update x directly. */
5684 {
5685 int reloadnum;
5686
5687 /* If we can output the register afterwards, do so, this
5688 saves the extra update.
5689 We can do so if we have an INSN - i.e. no JUMP_INSN nor
5690 CALL_INSN - and it does not set CC0.
5691 But don't do this if we cannot directly address the
5692 memory location, since this will make it harder to
5693 reuse address reloads, and increases register pressure.
5694 Also don't do this if we can probably update x directly. */
5542 rtx equiv = (GET_CODE (XEXP (x, 0)) == MEM
5695 rtx equiv = (MEM_P (XEXP (x, 0))
5543 ? XEXP (x, 0)
5544 : reg_equiv_mem[regno]);
5545 int icode = (int) add_optab->handlers[(int) Pmode].insn_code;
5696 ? XEXP (x, 0)
5697 : reg_equiv_mem[regno]);
5698 int icode = (int) add_optab->handlers[(int) Pmode].insn_code;
5546 if (insn && GET_CODE (insn) == INSN && equiv
5699 if (insn && NONJUMP_INSN_P (insn) && equiv
5547 && memory_operand (equiv, GET_MODE (equiv))
5548#ifdef HAVE_cc0
5549 && ! sets_cc0_p (PATTERN (insn))
5550#endif
5551 && ! (icode != CODE_FOR_nothing
5552 && ((*insn_data[icode].operand[0].predicate)
5553 (equiv, Pmode))
5554 && ((*insn_data[icode].operand[1].predicate)
5555 (equiv, Pmode))))
5556 {
5557 /* We use the original pseudo for loc, so that
5558 emit_reload_insns() knows which pseudo this
5559 reload refers to and updates the pseudo rtx, not
5560 its equivalent memory location, as well as the
5561 corresponding entry in reg_last_reload_reg. */
5562 loc = &XEXP (x_orig, 0);
5563 x = XEXP (x, 0);
5564 reloadnum
5565 = push_reload (x, x, loc, loc,
5700 && memory_operand (equiv, GET_MODE (equiv))
5701#ifdef HAVE_cc0
5702 && ! sets_cc0_p (PATTERN (insn))
5703#endif
5704 && ! (icode != CODE_FOR_nothing
5705 && ((*insn_data[icode].operand[0].predicate)
5706 (equiv, Pmode))
5707 && ((*insn_data[icode].operand[1].predicate)
5708 (equiv, Pmode))))
5709 {
5710 /* We use the original pseudo for loc, so that
5711 emit_reload_insns() knows which pseudo this
5712 reload refers to and updates the pseudo rtx, not
5713 its equivalent memory location, as well as the
5714 corresponding entry in reg_last_reload_reg. */
5715 loc = &XEXP (x_orig, 0);
5716 x = XEXP (x, 0);
5717 reloadnum
5718 = push_reload (x, x, loc, loc,
5566 (context ? INDEX_REG_CLASS :
5567 MODE_BASE_REG_CLASS (mode)),
5719 context_reg_class,
5568 GET_MODE (x), GET_MODE (x), 0, 0,
5569 opnum, RELOAD_OTHER);
5570 }
5571 else
5572 {
5573 reloadnum
5574 = push_reload (x, NULL_RTX, loc, (rtx*) 0,
5720 GET_MODE (x), GET_MODE (x), 0, 0,
5721 opnum, RELOAD_OTHER);
5722 }
5723 else
5724 {
5725 reloadnum
5726 = push_reload (x, NULL_RTX, loc, (rtx*) 0,
5575 (context ? INDEX_REG_CLASS :
5576 MODE_BASE_REG_CLASS (mode)),
5727 context_reg_class,
5577 GET_MODE (x), GET_MODE (x), 0, 0,
5578 opnum, type);
5579 rld[reloadnum].inc
5580 = find_inc_amount (PATTERN (this_insn), XEXP (x_orig, 0));
5581
5582 value = 1;
5583 }
5584
5585 update_auto_inc_notes (this_insn, REGNO (XEXP (x_orig, 0)),
5586 reloadnum);
5587 }
5588 return value;
5589 }
5590
5728 GET_MODE (x), GET_MODE (x), 0, 0,
5729 opnum, type);
5730 rld[reloadnum].inc
5731 = find_inc_amount (PATTERN (this_insn), XEXP (x_orig, 0));
5732
5733 value = 1;
5734 }
5735
5736 update_auto_inc_notes (this_insn, REGNO (XEXP (x_orig, 0)),
5737 reloadnum);
5738 }
5739 return value;
5740 }
5741
5591 else if (GET_CODE (XEXP (x, 0)) == MEM)
5742 else if (MEM_P (XEXP (x, 0)))
5592 {
5593 /* This is probably the result of a substitution, by eliminate_regs,
5594 of an equivalent address for a pseudo that was not allocated to a
5595 hard register. Verify that the specified address is valid and
5596 reload it into a register. */
5597 /* Variable `tem' might or might not be used in FIND_REG_INC_NOTE. */
5598 rtx tem ATTRIBUTE_UNUSED = XEXP (x, 0);
5599 rtx link;

--- 8 unchanged lines hidden (view full) ---

5608 /* We can't use ADDR_TYPE (type) here, because we need to
5609 write back the value after reading it, hence we actually
5610 need two registers. */
5611 find_reloads_address (GET_MODE (x), &XEXP (x, 0),
5612 XEXP (XEXP (x, 0), 0), &XEXP (XEXP (x, 0), 0),
5613 opnum, type, ind_levels, insn);
5614
5615 reloadnum = push_reload (x, NULL_RTX, loc, (rtx*) 0,
5743 {
5744 /* This is probably the result of a substitution, by eliminate_regs,
5745 of an equivalent address for a pseudo that was not allocated to a
5746 hard register. Verify that the specified address is valid and
5747 reload it into a register. */
5748 /* Variable `tem' might or might not be used in FIND_REG_INC_NOTE. */
5749 rtx tem ATTRIBUTE_UNUSED = XEXP (x, 0);
5750 rtx link;

--- 8 unchanged lines hidden (view full) ---

5759 /* We can't use ADDR_TYPE (type) here, because we need to
5760 write back the value after reading it, hence we actually
5761 need two registers. */
5762 find_reloads_address (GET_MODE (x), &XEXP (x, 0),
5763 XEXP (XEXP (x, 0), 0), &XEXP (XEXP (x, 0), 0),
5764 opnum, type, ind_levels, insn);
5765
5766 reloadnum = push_reload (x, NULL_RTX, loc, (rtx*) 0,
5616 (context ? INDEX_REG_CLASS :
5617 MODE_BASE_REG_CLASS (mode)),
5767 context_reg_class,
5618 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
5619 rld[reloadnum].inc
5620 = find_inc_amount (PATTERN (this_insn), XEXP (x, 0));
5621
5622 link = FIND_REG_INC_NOTE (this_insn, tem);
5623 if (link != 0)
5624 push_replacement (&XEXP (link, 0), reloadnum, VOIDmode);
5625
5626 return 1;
5627 }
5628 return 0;
5629
5768 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
5769 rld[reloadnum].inc
5770 = find_inc_amount (PATTERN (this_insn), XEXP (x, 0));
5771
5772 link = FIND_REG_INC_NOTE (this_insn, tem);
5773 if (link != 0)
5774 push_replacement (&XEXP (link, 0), reloadnum, VOIDmode);
5775
5776 return 1;
5777 }
5778 return 0;
5779
5780 case TRUNCATE:
5781 case SIGN_EXTEND:
5782 case ZERO_EXTEND:
5783 /* Look for parts to reload in the inner expression and reload them
5784 too, in addition to this operation. Reloading all inner parts in
5785 addition to this one shouldn't be necessary, but at this point,
5786 we don't know if we can possibly omit any part that *can* be
5787 reloaded. Targets that are better off reloading just either part
5788 (or perhaps even a different part of an outer expression), should
5789 define LEGITIMIZE_RELOAD_ADDRESS. */
5790 find_reloads_address_1 (GET_MODE (XEXP (x, 0)), XEXP (x, 0),
5791 context, code, SCRATCH, &XEXP (x, 0), opnum,
5792 type, ind_levels, insn);
5793 push_reload (x, NULL_RTX, loc, (rtx*) 0,
5794 context_reg_class,
5795 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
5796 return 1;
5797
5630 case MEM:
5631 /* This is probably the result of a substitution, by eliminate_regs, of
5632 an equivalent address for a pseudo that was not allocated to a hard
5633 register. Verify that the specified address is valid and reload it
5634 into a register.
5635
5636 Since we know we are going to reload this item, don't decrement for
5637 the indirection level.
5638
5639 Note that this is actually conservative: it would be slightly more
5640 efficient to use the value of SPILL_INDIRECT_LEVELS from
5641 reload1.c here. */
5642
5643 find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0),
5644 opnum, ADDR_TYPE (type), ind_levels, insn);
5645 push_reload (*loc, NULL_RTX, loc, (rtx*) 0,
5798 case MEM:
5799 /* This is probably the result of a substitution, by eliminate_regs, of
5800 an equivalent address for a pseudo that was not allocated to a hard
5801 register. Verify that the specified address is valid and reload it
5802 into a register.
5803
5804 Since we know we are going to reload this item, don't decrement for
5805 the indirection level.
5806
5807 Note that this is actually conservative: it would be slightly more
5808 efficient to use the value of SPILL_INDIRECT_LEVELS from
5809 reload1.c here. */
5810
5811 find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0),
5812 opnum, ADDR_TYPE (type), ind_levels, insn);
5813 push_reload (*loc, NULL_RTX, loc, (rtx*) 0,
5646 (context ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (mode)),
5814 context_reg_class,
5647 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
5648 return 1;
5649
5650 case REG:
5651 {
5652 int regno = REGNO (x);
5653
5654 if (reg_equiv_constant[regno] != 0)
5655 {
5656 find_reloads_address_part (reg_equiv_constant[regno], loc,
5815 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
5816 return 1;
5817
5818 case REG:
5819 {
5820 int regno = REGNO (x);
5821
5822 if (reg_equiv_constant[regno] != 0)
5823 {
5824 find_reloads_address_part (reg_equiv_constant[regno], loc,
5657 (context ? INDEX_REG_CLASS :
5658 MODE_BASE_REG_CLASS (mode)),
5825 context_reg_class,
5659 GET_MODE (x), opnum, type, ind_levels);
5660 return 1;
5661 }
5662
5663#if 0 /* This might screw code in reload1.c to delete prior output-reload
5664 that feeds this insn. */
5665 if (reg_equiv_mem[regno] != 0)
5666 {
5667 push_reload (reg_equiv_mem[regno], NULL_RTX, loc, (rtx*) 0,
5826 GET_MODE (x), opnum, type, ind_levels);
5827 return 1;
5828 }
5829
5830#if 0 /* This might screw code in reload1.c to delete prior output-reload
5831 that feeds this insn. */
5832 if (reg_equiv_mem[regno] != 0)
5833 {
5834 push_reload (reg_equiv_mem[regno], NULL_RTX, loc, (rtx*) 0,
5668 (context ? INDEX_REG_CLASS :
5669 MODE_BASE_REG_CLASS (mode)),
5835 context_reg_class,
5670 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
5671 return 1;
5672 }
5673#endif
5674
5675 if (reg_equiv_memory_loc[regno]
5676 && (reg_equiv_address[regno] != 0 || num_not_at_initial_offset))
5677 {
5678 rtx tem = make_memloc (x, regno);
5679 if (reg_equiv_address[regno] != 0
5680 || ! rtx_equal_p (tem, reg_equiv_mem[regno]))
5681 {
5682 x = tem;
5683 find_reloads_address (GET_MODE (x), &x, XEXP (x, 0),
5684 &XEXP (x, 0), opnum, ADDR_TYPE (type),
5685 ind_levels, insn);
5836 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
5837 return 1;
5838 }
5839#endif
5840
5841 if (reg_equiv_memory_loc[regno]
5842 && (reg_equiv_address[regno] != 0 || num_not_at_initial_offset))
5843 {
5844 rtx tem = make_memloc (x, regno);
5845 if (reg_equiv_address[regno] != 0
5846 || ! rtx_equal_p (tem, reg_equiv_mem[regno]))
5847 {
5848 x = tem;
5849 find_reloads_address (GET_MODE (x), &x, XEXP (x, 0),
5850 &XEXP (x, 0), opnum, ADDR_TYPE (type),
5851 ind_levels, insn);
5852 if (x != tem)
5853 push_reg_equiv_alt_mem (regno, x);
5686 }
5687 }
5688
5689 if (reg_renumber[regno] >= 0)
5690 regno = reg_renumber[regno];
5691
5854 }
5855 }
5856
5857 if (reg_renumber[regno] >= 0)
5858 regno = reg_renumber[regno];
5859
5692 if ((regno >= FIRST_PSEUDO_REGISTER
5693 || !(context ? REGNO_OK_FOR_INDEX_P (regno)
5694 : REGNO_MODE_OK_FOR_BASE_P (regno, mode))))
5860 if (regno >= FIRST_PSEUDO_REGISTER
5861 || !REG_OK_FOR_CONTEXT (context, regno, mode, outer_code,
5862 index_code))
5695 {
5696 push_reload (x, NULL_RTX, loc, (rtx*) 0,
5863 {
5864 push_reload (x, NULL_RTX, loc, (rtx*) 0,
5697 (context ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (mode)),
5865 context_reg_class,
5698 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
5699 return 1;
5700 }
5701
5702 /* If a register appearing in an address is the subject of a CLOBBER
5703 in this insn, reload it into some other register to be safe.
5704 The CLOBBER is supposed to make the register unavailable
5705 from before this insn to after it. */
5706 if (regno_clobbered_p (regno, this_insn, GET_MODE (x), 0))
5707 {
5708 push_reload (x, NULL_RTX, loc, (rtx*) 0,
5866 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
5867 return 1;
5868 }
5869
5870 /* If a register appearing in an address is the subject of a CLOBBER
5871 in this insn, reload it into some other register to be safe.
5872 The CLOBBER is supposed to make the register unavailable
5873 from before this insn to after it. */
5874 if (regno_clobbered_p (regno, this_insn, GET_MODE (x), 0))
5875 {
5876 push_reload (x, NULL_RTX, loc, (rtx*) 0,
5709 (context ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (mode)),
5877 context_reg_class,
5710 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
5711 return 1;
5712 }
5713 }
5714 return 0;
5715
5716 case SUBREG:
5878 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
5879 return 1;
5880 }
5881 }
5882 return 0;
5883
5884 case SUBREG:
5717 if (GET_CODE (SUBREG_REG (x)) == REG)
5885 if (REG_P (SUBREG_REG (x)))
5718 {
5719 /* If this is a SUBREG of a hard register and the resulting register
5720 is of the wrong class, reload the whole SUBREG. This avoids
5721 needless copies if SUBREG_REG is multi-word. */
5722 if (REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER)
5723 {
5724 int regno ATTRIBUTE_UNUSED = subreg_regno (x);
5725
5886 {
5887 /* If this is a SUBREG of a hard register and the resulting register
5888 is of the wrong class, reload the whole SUBREG. This avoids
5889 needless copies if SUBREG_REG is multi-word. */
5890 if (REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER)
5891 {
5892 int regno ATTRIBUTE_UNUSED = subreg_regno (x);
5893
5726 if (! (context ? REGNO_OK_FOR_INDEX_P (regno)
5727 : REGNO_MODE_OK_FOR_BASE_P (regno, mode)))
5894 if (!REG_OK_FOR_CONTEXT (context, regno, mode, outer_code,
5895 index_code))
5728 {
5729 push_reload (x, NULL_RTX, loc, (rtx*) 0,
5896 {
5897 push_reload (x, NULL_RTX, loc, (rtx*) 0,
5730 (context ? INDEX_REG_CLASS :
5731 MODE_BASE_REG_CLASS (mode)),
5898 context_reg_class,
5732 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
5733 return 1;
5734 }
5735 }
5736 /* If this is a SUBREG of a pseudo-register, and the pseudo-register
5737 is larger than the class size, then reload the whole SUBREG. */
5738 else
5739 {
5899 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
5900 return 1;
5901 }
5902 }
5903 /* If this is a SUBREG of a pseudo-register, and the pseudo-register
5904 is larger than the class size, then reload the whole SUBREG. */
5905 else
5906 {
5740 enum reg_class class = (context ? INDEX_REG_CLASS
5741 : MODE_BASE_REG_CLASS (mode));
5907 enum reg_class class = context_reg_class;
5742 if ((unsigned) CLASS_MAX_NREGS (class, GET_MODE (SUBREG_REG (x)))
5743 > reg_class_size[class])
5744 {
5908 if ((unsigned) CLASS_MAX_NREGS (class, GET_MODE (SUBREG_REG (x)))
5909 > reg_class_size[class])
5910 {
5745 x = find_reloads_subreg_address (x, 0, opnum, type,
5911 x = find_reloads_subreg_address (x, 0, opnum,
5912 ADDR_TYPE (type),
5746 ind_levels, insn);
5747 push_reload (x, NULL_RTX, loc, (rtx*) 0, class,
5748 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
5749 return 1;
5750 }
5751 }
5752 }
5753 break;

--- 4 unchanged lines hidden (view full) ---

5758
5759 {
5760 const char *fmt = GET_RTX_FORMAT (code);
5761 int i;
5762
5763 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5764 {
5765 if (fmt[i] == 'e')
5913 ind_levels, insn);
5914 push_reload (x, NULL_RTX, loc, (rtx*) 0, class,
5915 GET_MODE (x), VOIDmode, 0, 0, opnum, type);
5916 return 1;
5917 }
5918 }
5919 }
5920 break;

--- 4 unchanged lines hidden (view full) ---

5925
5926 {
5927 const char *fmt = GET_RTX_FORMAT (code);
5928 int i;
5929
5930 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5931 {
5932 if (fmt[i] == 'e')
5766 find_reloads_address_1 (mode, XEXP (x, i), context, &XEXP (x, i),
5767 opnum, type, ind_levels, insn);
5933 /* Pass SCRATCH for INDEX_CODE, since CODE can never be a PLUS once
5934 we get here. */
5935 find_reloads_address_1 (mode, XEXP (x, i), context, code, SCRATCH,
5936 &XEXP (x, i), opnum, type, ind_levels, insn);
5768 }
5769 }
5770
5937 }
5938 }
5939
5940#undef REG_OK_FOR_CONTEXT
5771 return 0;
5772}
5773
5774/* X, which is found at *LOC, is a part of an address that needs to be
5775 reloaded into a register of class CLASS. If X is a constant, or if
5776 X is a PLUS that contains a constant, check that the constant is a
5777 legitimate operand and that we are supposed to be able to load
5778 it into the register.

--- 84 unchanged lines hidden (view full) ---

5863 /* If the address changes because of register elimination, then
5864 it must be replaced. */
5865 if (force_replace
5866 || ! rtx_equal_p (tem, reg_equiv_mem[regno]))
5867 {
5868 unsigned outer_size = GET_MODE_SIZE (GET_MODE (x));
5869 unsigned inner_size = GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)));
5870 int offset;
5941 return 0;
5942}
5943
5944/* X, which is found at *LOC, is a part of an address that needs to be
5945 reloaded into a register of class CLASS. If X is a constant, or if
5946 X is a PLUS that contains a constant, check that the constant is a
5947 legitimate operand and that we are supposed to be able to load
5948 it into the register.

--- 84 unchanged lines hidden (view full) ---

6033 /* If the address changes because of register elimination, then
6034 it must be replaced. */
6035 if (force_replace
6036 || ! rtx_equal_p (tem, reg_equiv_mem[regno]))
6037 {
6038 unsigned outer_size = GET_MODE_SIZE (GET_MODE (x));
6039 unsigned inner_size = GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)));
6040 int offset;
6041 rtx orig = tem;
6042 enum machine_mode orig_mode = GET_MODE (orig);
6043 int reloaded;
5871
5872 /* For big-endian paradoxical subregs, SUBREG_BYTE does not
5873 hold the correct (negative) byte offset. */
5874 if (BYTES_BIG_ENDIAN && outer_size > inner_size)
5875 offset = inner_size - outer_size;
5876 else
5877 offset = SUBREG_BYTE (x);
5878
5879 XEXP (tem, 0) = plus_constant (XEXP (tem, 0), offset);
5880 PUT_MODE (tem, GET_MODE (x));
5881
5882 /* If this was a paradoxical subreg that we replaced, the
5883 resulting memory must be sufficiently aligned to allow
5884 us to widen the mode of the memory. */
6044
6045 /* For big-endian paradoxical subregs, SUBREG_BYTE does not
6046 hold the correct (negative) byte offset. */
6047 if (BYTES_BIG_ENDIAN && outer_size > inner_size)
6048 offset = inner_size - outer_size;
6049 else
6050 offset = SUBREG_BYTE (x);
6051
6052 XEXP (tem, 0) = plus_constant (XEXP (tem, 0), offset);
6053 PUT_MODE (tem, GET_MODE (x));
6054
6055 /* If this was a paradoxical subreg that we replaced, the
6056 resulting memory must be sufficiently aligned to allow
6057 us to widen the mode of the memory. */
5885 if (outer_size > inner_size && STRICT_ALIGNMENT)
6058 if (outer_size > inner_size)
5886 {
5887 rtx base;
5888
5889 base = XEXP (tem, 0);
5890 if (GET_CODE (base) == PLUS)
5891 {
5892 if (GET_CODE (XEXP (base, 1)) == CONST_INT
5893 && INTVAL (XEXP (base, 1)) % outer_size != 0)
5894 return x;
5895 base = XEXP (base, 0);
5896 }
6059 {
6060 rtx base;
6061
6062 base = XEXP (tem, 0);
6063 if (GET_CODE (base) == PLUS)
6064 {
6065 if (GET_CODE (XEXP (base, 1)) == CONST_INT
6066 && INTVAL (XEXP (base, 1)) % outer_size != 0)
6067 return x;
6068 base = XEXP (base, 0);
6069 }
5897 if (GET_CODE (base) != REG
6070 if (!REG_P (base)
5898 || (REGNO_POINTER_ALIGN (REGNO (base))
5899 < outer_size * BITS_PER_UNIT))
5900 return x;
5901 }
5902
6071 || (REGNO_POINTER_ALIGN (REGNO (base))
6072 < outer_size * BITS_PER_UNIT))
6073 return x;
6074 }
6075
5903 find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0),
5904 &XEXP (tem, 0), opnum, ADDR_TYPE (type),
5905 ind_levels, insn);
6076 reloaded = find_reloads_address (GET_MODE (tem), &tem,
6077 XEXP (tem, 0), &XEXP (tem, 0),
6078 opnum, type, ind_levels, insn);
6079 /* ??? Do we need to handle nonzero offsets somehow? */
6080 if (!offset && tem != orig)
6081 push_reg_equiv_alt_mem (regno, tem);
5906
6082
6083 /* For some processors an address may be valid in the
6084 original mode but not in a smaller mode. For
6085 example, ARM accepts a scaled index register in
6086 SImode but not in HImode. find_reloads_address
6087 assumes that we pass it a valid address, and doesn't
6088 force a reload. This will probably be fine if
6089 find_reloads_address finds some reloads. But if it
6090 doesn't find any, then we may have just converted a
6091 valid address into an invalid one. Check for that
6092 here. */
6093 if (reloaded != 1
6094 && strict_memory_address_p (orig_mode, XEXP (tem, 0))
6095 && !strict_memory_address_p (GET_MODE (tem),
6096 XEXP (tem, 0)))
6097 push_reload (XEXP (tem, 0), NULL_RTX, &XEXP (tem, 0), (rtx*) 0,
6098 base_reg_class (GET_MODE (tem), MEM, SCRATCH),
6099 GET_MODE (XEXP (tem, 0)), VOIDmode, 0, 0,
6100 opnum, type);
6101
5907 /* If this is not a toplevel operand, find_reloads doesn't see
5908 this substitution. We have to emit a USE of the pseudo so
5909 that delete_output_reload can see it. */
5910 if (replace_reloads && recog_data.operand[opnum] != x)
5911 /* We mark the USE with QImode so that we recognize it
5912 as one that can be safely deleted at the end of
5913 reload. */
5914 PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode,

--- 32 unchanged lines hidden (view full) ---

5947 Otherwise, if the equivalence is used after that, it will
5948 have been modified, and the thing substituted (probably a
5949 register) is likely overwritten and not a usable equivalence. */
5950 int check_regno;
5951
5952 for (check_regno = 0; check_regno < max_regno; check_regno++)
5953 {
5954#define CHECK_MODF(ARRAY) \
6102 /* If this is not a toplevel operand, find_reloads doesn't see
6103 this substitution. We have to emit a USE of the pseudo so
6104 that delete_output_reload can see it. */
6105 if (replace_reloads && recog_data.operand[opnum] != x)
6106 /* We mark the USE with QImode so that we recognize it
6107 as one that can be safely deleted at the end of
6108 reload. */
6109 PUT_MODE (emit_insn_before (gen_rtx_USE (VOIDmode,

--- 32 unchanged lines hidden (view full) ---

6142 Otherwise, if the equivalence is used after that, it will
6143 have been modified, and the thing substituted (probably a
6144 register) is likely overwritten and not a usable equivalence. */
6145 int check_regno;
6146
6147 for (check_regno = 0; check_regno < max_regno; check_regno++)
6148 {
6149#define CHECK_MODF(ARRAY) \
5955 if (ARRAY[check_regno] \
5956 && loc_mentioned_in_p (r->where, \
5957 ARRAY[check_regno])) \
5958 abort ()
6150 gcc_assert (!ARRAY[check_regno] \
6151 || !loc_mentioned_in_p (r->where, \
6152 ARRAY[check_regno]))
5959
5960 CHECK_MODF (reg_equiv_constant);
5961 CHECK_MODF (reg_equiv_memory_loc);
5962 CHECK_MODF (reg_equiv_address);
5963 CHECK_MODF (reg_equiv_mem);
5964#undef CHECK_MODF
5965 }
5966#endif /* ENABLE_CHECKING */
5967
5968 /* If we're replacing a LABEL_REF with a register, add a
5969 REG_LABEL note to indicate to flow which label this
5970 register refers to. */
5971 if (GET_CODE (*r->where) == LABEL_REF
6153
6154 CHECK_MODF (reg_equiv_constant);
6155 CHECK_MODF (reg_equiv_memory_loc);
6156 CHECK_MODF (reg_equiv_address);
6157 CHECK_MODF (reg_equiv_mem);
6158#undef CHECK_MODF
6159 }
6160#endif /* ENABLE_CHECKING */
6161
6162 /* If we're replacing a LABEL_REF with a register, add a
6163 REG_LABEL note to indicate to flow which label this
6164 register refers to. */
6165 if (GET_CODE (*r->where) == LABEL_REF
5972 && GET_CODE (insn) == JUMP_INSN)
5973 REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL,
5974 XEXP (*r->where, 0),
5975 REG_NOTES (insn));
6166 && JUMP_P (insn))
6167 {
6168 REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL,
6169 XEXP (*r->where, 0),
6170 REG_NOTES (insn));
6171 JUMP_LABEL (insn) = XEXP (*r->where, 0);
6172 }
5976
5977 /* Encapsulate RELOADREG so its machine mode matches what
5978 used to be there. Note that gen_lowpart_common will
5979 do the wrong thing if RELOADREG is multi-word. RELOADREG
5980 will always be a REG here. */
5981 if (GET_MODE (reloadreg) != r->mode && r->mode != VOIDmode)
5982 reloadreg = reload_adjust_reg_for_mode (reloadreg, r->mode);
5983

--- 21 unchanged lines hidden (view full) ---

6005 *r->where = SUBREG_REG (reloadreg);
6006 SUBREG_BYTE (*r->subreg_loc) = final_offset;
6007 }
6008 }
6009 else
6010 *r->where = reloadreg;
6011 }
6012 /* If reload got no reg and isn't optional, something's wrong. */
6173
6174 /* Encapsulate RELOADREG so its machine mode matches what
6175 used to be there. Note that gen_lowpart_common will
6176 do the wrong thing if RELOADREG is multi-word. RELOADREG
6177 will always be a REG here. */
6178 if (GET_MODE (reloadreg) != r->mode && r->mode != VOIDmode)
6179 reloadreg = reload_adjust_reg_for_mode (reloadreg, r->mode);
6180

--- 21 unchanged lines hidden (view full) ---

6202 *r->where = SUBREG_REG (reloadreg);
6203 SUBREG_BYTE (*r->subreg_loc) = final_offset;
6204 }
6205 }
6206 else
6207 *r->where = reloadreg;
6208 }
6209 /* If reload got no reg and isn't optional, something's wrong. */
6013 else if (! rld[r->what].optional)
6014 abort ();
6210 else
6211 gcc_assert (rld[r->what].optional);
6015 }
6016}
6017
6018/* Make a copy of any replacements being done into X and move those
6019 copies to locations in Y, a copy of X. */
6020
6021void
6022copy_replacements (rtx x, rtx y)
6023{
6024 /* We can't support X being a SUBREG because we might then need to know its
6025 location if something inside it was replaced. */
6212 }
6213}
6214
6215/* Make a copy of any replacements being done into X and move those
6216 copies to locations in Y, a copy of X. */
6217
6218void
6219copy_replacements (rtx x, rtx y)
6220{
6221 /* We can't support X being a SUBREG because we might then need to know its
6222 location if something inside it was replaced. */
6026 if (GET_CODE (x) == SUBREG)
6027 abort ();
6223 gcc_assert (GET_CODE (x) != SUBREG);
6028
6029 copy_replacements_1 (&x, &y, n_replacements);
6030}
6031
6032static void
6033copy_replacements_1 (rtx *px, rtx *py, int orig_replacements)
6034{
6035 int i, j;

--- 75 unchanged lines hidden (view full) ---

6111 return reloadreg;
6112 }
6113 else if (reloadreg && r->subreg_loc == loc)
6114 {
6115 /* RELOADREG must be either a REG or a SUBREG.
6116
6117 ??? Is it actually still ever a SUBREG? If so, why? */
6118
6224
6225 copy_replacements_1 (&x, &y, n_replacements);
6226}
6227
6228static void
6229copy_replacements_1 (rtx *px, rtx *py, int orig_replacements)
6230{
6231 int i, j;

--- 75 unchanged lines hidden (view full) ---

6307 return reloadreg;
6308 }
6309 else if (reloadreg && r->subreg_loc == loc)
6310 {
6311 /* RELOADREG must be either a REG or a SUBREG.
6312
6313 ??? Is it actually still ever a SUBREG? If so, why? */
6314
6119 if (GET_CODE (reloadreg) == REG)
6315 if (REG_P (reloadreg))
6120 return gen_rtx_REG (GET_MODE (*loc),
6121 (REGNO (reloadreg) +
6122 subreg_regno_offset (REGNO (SUBREG_REG (*loc)),
6123 GET_MODE (SUBREG_REG (*loc)),
6124 SUBREG_BYTE (*loc),
6125 GET_MODE (*loc))));
6126 else if (GET_MODE (reloadreg) == GET_MODE (*loc))
6127 return reloadreg;

--- 31 unchanged lines hidden (view full) ---

6159 other than being stored into (except for earlyclobber operands).
6160
6161 References contained within the substructure at LOC do not count.
6162 LOC may be zero, meaning don't ignore anything.
6163
6164 This is similar to refers_to_regno_p in rtlanal.c except that we
6165 look at equivalences for pseudos that didn't get hard registers. */
6166
6316 return gen_rtx_REG (GET_MODE (*loc),
6317 (REGNO (reloadreg) +
6318 subreg_regno_offset (REGNO (SUBREG_REG (*loc)),
6319 GET_MODE (SUBREG_REG (*loc)),
6320 SUBREG_BYTE (*loc),
6321 GET_MODE (*loc))));
6322 else if (GET_MODE (reloadreg) == GET_MODE (*loc))
6323 return reloadreg;

--- 31 unchanged lines hidden (view full) ---

6355 other than being stored into (except for earlyclobber operands).
6356
6357 References contained within the substructure at LOC do not count.
6358 LOC may be zero, meaning don't ignore anything.
6359
6360 This is similar to refers_to_regno_p in rtlanal.c except that we
6361 look at equivalences for pseudos that didn't get hard registers. */
6362
6167int
6363static int
6168refers_to_regno_for_reload_p (unsigned int regno, unsigned int endregno,
6169 rtx x, rtx *loc)
6170{
6171 int i;
6172 unsigned int r;
6173 RTX_CODE code;
6174 const char *fmt;
6175

--- 12 unchanged lines hidden (view full) ---

6188 X must therefore either be a constant or be in memory. */
6189 if (r >= FIRST_PSEUDO_REGISTER)
6190 {
6191 if (reg_equiv_memory_loc[r])
6192 return refers_to_regno_for_reload_p (regno, endregno,
6193 reg_equiv_memory_loc[r],
6194 (rtx*) 0);
6195
6364refers_to_regno_for_reload_p (unsigned int regno, unsigned int endregno,
6365 rtx x, rtx *loc)
6366{
6367 int i;
6368 unsigned int r;
6369 RTX_CODE code;
6370 const char *fmt;
6371

--- 12 unchanged lines hidden (view full) ---

6384 X must therefore either be a constant or be in memory. */
6385 if (r >= FIRST_PSEUDO_REGISTER)
6386 {
6387 if (reg_equiv_memory_loc[r])
6388 return refers_to_regno_for_reload_p (regno, endregno,
6389 reg_equiv_memory_loc[r],
6390 (rtx*) 0);
6391
6196 if (reg_equiv_constant[r])
6197 return 0;
6198
6199 abort ();
6392 gcc_assert (reg_equiv_constant[r] || reg_equiv_invariant[r]);
6393 return 0;
6200 }
6201
6202 return (endregno > r
6203 && regno < r + (r < FIRST_PSEUDO_REGISTER
6394 }
6395
6396 return (endregno > r
6397 && regno < r + (r < FIRST_PSEUDO_REGISTER
6204 ? HARD_REGNO_NREGS (r, GET_MODE (x))
6398 ? hard_regno_nregs[r][GET_MODE (x)]
6205 : 1));
6206
6207 case SUBREG:
6208 /* If this is a SUBREG of a hard reg, we can see exactly which
6209 registers are being modified. Otherwise, handle normally. */
6399 : 1));
6400
6401 case SUBREG:
6402 /* If this is a SUBREG of a hard reg, we can see exactly which
6403 registers are being modified. Otherwise, handle normally. */
6210 if (GET_CODE (SUBREG_REG (x)) == REG
6404 if (REG_P (SUBREG_REG (x))
6211 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER)
6212 {
6213 unsigned int inner_regno = subreg_regno (x);
6214 unsigned int inner_endregno
6215 = inner_regno + (inner_regno < FIRST_PSEUDO_REGISTER
6405 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER)
6406 {
6407 unsigned int inner_regno = subreg_regno (x);
6408 unsigned int inner_endregno
6409 = inner_regno + (inner_regno < FIRST_PSEUDO_REGISTER
6216 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
6410 ? hard_regno_nregs[inner_regno][GET_MODE (x)] : 1);
6217
6218 return endregno > inner_regno && regno < inner_endregno;
6219 }
6220 break;
6221
6222 case CLOBBER:
6223 case SET:
6224 if (&SET_DEST (x) != loc
6225 /* Note setting a SUBREG counts as referring to the REG it is in for
6226 a pseudo but not for hard registers since we can
6227 treat each word individually. */
6228 && ((GET_CODE (SET_DEST (x)) == SUBREG
6229 && loc != &SUBREG_REG (SET_DEST (x))
6411
6412 return endregno > inner_regno && regno < inner_endregno;
6413 }
6414 break;
6415
6416 case CLOBBER:
6417 case SET:
6418 if (&SET_DEST (x) != loc
6419 /* Note setting a SUBREG counts as referring to the REG it is in for
6420 a pseudo but not for hard registers since we can
6421 treat each word individually. */
6422 && ((GET_CODE (SET_DEST (x)) == SUBREG
6423 && loc != &SUBREG_REG (SET_DEST (x))
6230 && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG
6424 && REG_P (SUBREG_REG (SET_DEST (x)))
6231 && REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER
6232 && refers_to_regno_for_reload_p (regno, endregno,
6233 SUBREG_REG (SET_DEST (x)),
6234 loc))
6235 /* If the output is an earlyclobber operand, this is
6236 a conflict. */
6425 && REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER
6426 && refers_to_regno_for_reload_p (regno, endregno,
6427 SUBREG_REG (SET_DEST (x)),
6428 loc))
6429 /* If the output is an earlyclobber operand, this is
6430 a conflict. */
6237 || ((GET_CODE (SET_DEST (x)) != REG
6431 || ((!REG_P (SET_DEST (x))
6238 || earlyclobber_operand_p (SET_DEST (x)))
6239 && refers_to_regno_for_reload_p (regno, endregno,
6240 SET_DEST (x), loc))))
6241 return 1;
6242
6243 if (code == CLOBBER || loc == &SET_SRC (x))
6244 return 0;
6245 x = SET_SRC (x);

--- 44 unchanged lines hidden (view full) ---

6290
6291int
6292reg_overlap_mentioned_for_reload_p (rtx x, rtx in)
6293{
6294 int regno, endregno;
6295
6296 /* Overly conservative. */
6297 if (GET_CODE (x) == STRICT_LOW_PART
6432 || earlyclobber_operand_p (SET_DEST (x)))
6433 && refers_to_regno_for_reload_p (regno, endregno,
6434 SET_DEST (x), loc))))
6435 return 1;
6436
6437 if (code == CLOBBER || loc == &SET_SRC (x))
6438 return 0;
6439 x = SET_SRC (x);

--- 44 unchanged lines hidden (view full) ---

6484
6485int
6486reg_overlap_mentioned_for_reload_p (rtx x, rtx in)
6487{
6488 int regno, endregno;
6489
6490 /* Overly conservative. */
6491 if (GET_CODE (x) == STRICT_LOW_PART
6298 || GET_RTX_CLASS (GET_CODE (x)) == 'a')
6492 || GET_RTX_CLASS (GET_CODE (x)) == RTX_AUTOINC)
6299 x = XEXP (x, 0);
6300
6301 /* If either argument is a constant, then modifying X can not affect IN. */
6302 if (CONSTANT_P (x) || CONSTANT_P (in))
6303 return 0;
6493 x = XEXP (x, 0);
6494
6495 /* If either argument is a constant, then modifying X can not affect IN. */
6496 if (CONSTANT_P (x) || CONSTANT_P (in))
6497 return 0;
6498 else if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
6499 return refers_to_mem_for_reload_p (in);
6304 else if (GET_CODE (x) == SUBREG)
6305 {
6306 regno = REGNO (SUBREG_REG (x));
6307 if (regno < FIRST_PSEUDO_REGISTER)
6308 regno += subreg_regno_offset (REGNO (SUBREG_REG (x)),
6309 GET_MODE (SUBREG_REG (x)),
6310 SUBREG_BYTE (x),
6311 GET_MODE (x));
6312 }
6500 else if (GET_CODE (x) == SUBREG)
6501 {
6502 regno = REGNO (SUBREG_REG (x));
6503 if (regno < FIRST_PSEUDO_REGISTER)
6504 regno += subreg_regno_offset (REGNO (SUBREG_REG (x)),
6505 GET_MODE (SUBREG_REG (x)),
6506 SUBREG_BYTE (x),
6507 GET_MODE (x));
6508 }
6313 else if (GET_CODE (x) == REG)
6509 else if (REG_P (x))
6314 {
6315 regno = REGNO (x);
6316
6317 /* If this is a pseudo, it must not have been assigned a hard register.
6318 Therefore, it must either be in memory or be a constant. */
6319
6320 if (regno >= FIRST_PSEUDO_REGISTER)
6321 {
6322 if (reg_equiv_memory_loc[regno])
6323 return refers_to_mem_for_reload_p (in);
6510 {
6511 regno = REGNO (x);
6512
6513 /* If this is a pseudo, it must not have been assigned a hard register.
6514 Therefore, it must either be in memory or be a constant. */
6515
6516 if (regno >= FIRST_PSEUDO_REGISTER)
6517 {
6518 if (reg_equiv_memory_loc[regno])
6519 return refers_to_mem_for_reload_p (in);
6324 else if (reg_equiv_constant[regno])
6325 return 0;
6326 abort ();
6520 gcc_assert (reg_equiv_constant[regno]);
6521 return 0;
6327 }
6328 }
6522 }
6523 }
6329 else if (GET_CODE (x) == MEM)
6524 else if (MEM_P (x))
6330 return refers_to_mem_for_reload_p (in);
6331 else if (GET_CODE (x) == SCRATCH || GET_CODE (x) == PC
6332 || GET_CODE (x) == CC0)
6333 return reg_mentioned_p (x, in);
6525 return refers_to_mem_for_reload_p (in);
6526 else if (GET_CODE (x) == SCRATCH || GET_CODE (x) == PC
6527 || GET_CODE (x) == CC0)
6528 return reg_mentioned_p (x, in);
6334 else if (GET_CODE (x) == PLUS)
6529 else
6335 {
6530 {
6531 gcc_assert (GET_CODE (x) == PLUS);
6532
6336 /* We actually want to know if X is mentioned somewhere inside IN.
6337 We must not say that (plus (sp) (const_int 124)) is in
6338 (plus (sp) (const_int 64)), since that can lead to incorrect reload
6339 allocation when spuriously changing a RELOAD_FOR_OUTPUT_ADDRESS
6340 into a RELOAD_OTHER on behalf of another RELOAD_OTHER. */
6533 /* We actually want to know if X is mentioned somewhere inside IN.
6534 We must not say that (plus (sp) (const_int 124)) is in
6535 (plus (sp) (const_int 64)), since that can lead to incorrect reload
6536 allocation when spuriously changing a RELOAD_FOR_OUTPUT_ADDRESS
6537 into a RELOAD_OTHER on behalf of another RELOAD_OTHER. */
6341 while (GET_CODE (in) == MEM)
6538 while (MEM_P (in))
6342 in = XEXP (in, 0);
6539 in = XEXP (in, 0);
6343 if (GET_CODE (in) == REG)
6540 if (REG_P (in))
6344 return 0;
6345 else if (GET_CODE (in) == PLUS)
6346 return (reg_overlap_mentioned_for_reload_p (x, XEXP (in, 0))
6347 || reg_overlap_mentioned_for_reload_p (x, XEXP (in, 1)));
6348 else return (reg_overlap_mentioned_for_reload_p (XEXP (x, 0), in)
6349 || reg_overlap_mentioned_for_reload_p (XEXP (x, 1), in));
6350 }
6541 return 0;
6542 else if (GET_CODE (in) == PLUS)
6543 return (reg_overlap_mentioned_for_reload_p (x, XEXP (in, 0))
6544 || reg_overlap_mentioned_for_reload_p (x, XEXP (in, 1)));
6545 else return (reg_overlap_mentioned_for_reload_p (XEXP (x, 0), in)
6546 || reg_overlap_mentioned_for_reload_p (XEXP (x, 1), in));
6547 }
6351 else
6352 abort ();
6353
6354 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
6548
6549 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
6355 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
6550 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
6356
6357 return refers_to_regno_for_reload_p (regno, endregno, in, (rtx*) 0);
6358}
6359
6360/* Return nonzero if anything in X contains a MEM. Look also for pseudo
6361 registers. */
6362
6551
6552 return refers_to_regno_for_reload_p (regno, endregno, in, (rtx*) 0);
6553}
6554
6555/* Return nonzero if anything in X contains a MEM. Look also for pseudo
6556 registers. */
6557
6363int
6558static int
6364refers_to_mem_for_reload_p (rtx x)
6365{
6366 const char *fmt;
6367 int i;
6368
6559refers_to_mem_for_reload_p (rtx x)
6560{
6561 const char *fmt;
6562 int i;
6563
6369 if (GET_CODE (x) == MEM)
6564 if (MEM_P (x))
6370 return 1;
6371
6565 return 1;
6566
6372 if (GET_CODE (x) == REG)
6567 if (REG_P (x))
6373 return (REGNO (x) >= FIRST_PSEUDO_REGISTER
6374 && reg_equiv_memory_loc[REGNO (x)]);
6375
6376 fmt = GET_RTX_FORMAT (GET_CODE (x));
6377 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6378 if (fmt[i] == 'e'
6568 return (REGNO (x) >= FIRST_PSEUDO_REGISTER
6569 && reg_equiv_memory_loc[REGNO (x)]);
6570
6571 fmt = GET_RTX_FORMAT (GET_CODE (x));
6572 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6573 if (fmt[i] == 'e'
6379 && (GET_CODE (XEXP (x, i)) == MEM
6574 && (MEM_P (XEXP (x, i))
6380 || refers_to_mem_for_reload_p (XEXP (x, i))))
6381 return 1;
6382
6383 return 0;
6384}
6385
6386/* Check the insns before INSN to see if there is a suitable register
6387 containing the same value as GOAL.

--- 36 unchanged lines hidden (view full) ---

6424 int goal_mem_addr_varies = 0;
6425 int need_stable_sp = 0;
6426 int nregs;
6427 int valuenregs;
6428 int num = 0;
6429
6430 if (goal == 0)
6431 regno = goalreg;
6575 || refers_to_mem_for_reload_p (XEXP (x, i))))
6576 return 1;
6577
6578 return 0;
6579}
6580
6581/* Check the insns before INSN to see if there is a suitable register
6582 containing the same value as GOAL.

--- 36 unchanged lines hidden (view full) ---

6619 int goal_mem_addr_varies = 0;
6620 int need_stable_sp = 0;
6621 int nregs;
6622 int valuenregs;
6623 int num = 0;
6624
6625 if (goal == 0)
6626 regno = goalreg;
6432 else if (GET_CODE (goal) == REG)
6627 else if (REG_P (goal))
6433 regno = REGNO (goal);
6628 regno = REGNO (goal);
6434 else if (GET_CODE (goal) == MEM)
6629 else if (MEM_P (goal))
6435 {
6436 enum rtx_code code = GET_CODE (XEXP (goal, 0));
6437 if (MEM_VOLATILE_P (goal))
6438 return 0;
6630 {
6631 enum rtx_code code = GET_CODE (XEXP (goal, 0));
6632 if (MEM_VOLATILE_P (goal))
6633 return 0;
6439 if (flag_float_store && GET_MODE_CLASS (GET_MODE (goal)) == MODE_FLOAT)
6634 if (flag_float_store && SCALAR_FLOAT_MODE_P (GET_MODE (goal)))
6440 return 0;
6441 /* An address with side effects must be reexecuted. */
6442 switch (code)
6443 {
6444 case POST_INC:
6445 case PRE_INC:
6446 case POST_DEC:
6447 case PRE_DEC:

--- 22 unchanged lines hidden (view full) ---

6470 /* Scan insns back from INSN, looking for one that copies
6471 a value into or out of GOAL.
6472 Stop and give up if we reach a label. */
6473
6474 while (1)
6475 {
6476 p = PREV_INSN (p);
6477 num++;
6635 return 0;
6636 /* An address with side effects must be reexecuted. */
6637 switch (code)
6638 {
6639 case POST_INC:
6640 case PRE_INC:
6641 case POST_DEC:
6642 case PRE_DEC:

--- 22 unchanged lines hidden (view full) ---

6665 /* Scan insns back from INSN, looking for one that copies
6666 a value into or out of GOAL.
6667 Stop and give up if we reach a label. */
6668
6669 while (1)
6670 {
6671 p = PREV_INSN (p);
6672 num++;
6478 if (p == 0 || GET_CODE (p) == CODE_LABEL
6673 if (p == 0 || LABEL_P (p)
6479 || num > PARAM_VALUE (PARAM_MAX_RELOAD_SEARCH_INSNS))
6480 return 0;
6481
6674 || num > PARAM_VALUE (PARAM_MAX_RELOAD_SEARCH_INSNS))
6675 return 0;
6676
6482 if (GET_CODE (p) == INSN
6677 if (NONJUMP_INSN_P (p)
6483 /* If we don't want spill regs ... */
6484 && (! (reload_reg_p != 0
6485 && reload_reg_p != (short *) (HOST_WIDE_INT) 1)
6486 /* ... then ignore insns introduced by reload; they aren't
6487 useful and can cause results in reload_as_needed to be
6488 different from what they were when calculating the need for
6489 spills. If we notice an input-reload insn here, we will
6490 reject it below, but it might hide a usable equivalent.
6678 /* If we don't want spill regs ... */
6679 && (! (reload_reg_p != 0
6680 && reload_reg_p != (short *) (HOST_WIDE_INT) 1)
6681 /* ... then ignore insns introduced by reload; they aren't
6682 useful and can cause results in reload_as_needed to be
6683 different from what they were when calculating the need for
6684 spills. If we notice an input-reload insn here, we will
6685 reject it below, but it might hide a usable equivalent.
6491 That makes bad code. It may even abort: perhaps no reg was
6686 That makes bad code. It may even fail: perhaps no reg was
6492 spilled for this insn because it was assumed we would find
6493 that equivalent. */
6494 || INSN_UID (p) < reload_first_uid))
6495 {
6496 rtx tem;
6497 pat = single_set (p);
6498
6499 /* First check for something that sets some reg equal to GOAL. */

--- 20 unchanged lines hidden (view full) ---

6520 /* If we are looking for a constant,
6521 and something equivalent to that constant was copied
6522 into a reg, we can use that reg. */
6523 || (goal_const && REG_NOTES (p) != 0
6524 && (tem = find_reg_note (p, REG_EQUIV, NULL_RTX))
6525 && ((rtx_equal_p (XEXP (tem, 0), goal)
6526 && (valueno
6527 = true_regnum (valtry = SET_DEST (pat))) >= 0)
6687 spilled for this insn because it was assumed we would find
6688 that equivalent. */
6689 || INSN_UID (p) < reload_first_uid))
6690 {
6691 rtx tem;
6692 pat = single_set (p);
6693
6694 /* First check for something that sets some reg equal to GOAL. */

--- 20 unchanged lines hidden (view full) ---

6715 /* If we are looking for a constant,
6716 and something equivalent to that constant was copied
6717 into a reg, we can use that reg. */
6718 || (goal_const && REG_NOTES (p) != 0
6719 && (tem = find_reg_note (p, REG_EQUIV, NULL_RTX))
6720 && ((rtx_equal_p (XEXP (tem, 0), goal)
6721 && (valueno
6722 = true_regnum (valtry = SET_DEST (pat))) >= 0)
6528 || (GET_CODE (SET_DEST (pat)) == REG
6723 || (REG_P (SET_DEST (pat))
6529 && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE
6724 && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE
6530 && (GET_MODE_CLASS (GET_MODE (XEXP (tem, 0)))
6531 == MODE_FLOAT)
6725 && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (tem, 0)))
6532 && GET_CODE (goal) == CONST_INT
6533 && 0 != (goaltry
6534 = operand_subword (XEXP (tem, 0), 0, 0,
6535 VOIDmode))
6536 && rtx_equal_p (goal, goaltry)
6537 && (valtry
6538 = operand_subword (SET_DEST (pat), 0, 0,
6539 VOIDmode))
6540 && (valueno = true_regnum (valtry)) >= 0)))
6541 || (goal_const && (tem = find_reg_note (p, REG_EQUIV,
6542 NULL_RTX))
6726 && GET_CODE (goal) == CONST_INT
6727 && 0 != (goaltry
6728 = operand_subword (XEXP (tem, 0), 0, 0,
6729 VOIDmode))
6730 && rtx_equal_p (goal, goaltry)
6731 && (valtry
6732 = operand_subword (SET_DEST (pat), 0, 0,
6733 VOIDmode))
6734 && (valueno = true_regnum (valtry)) >= 0)))
6735 || (goal_const && (tem = find_reg_note (p, REG_EQUIV,
6736 NULL_RTX))
6543 && GET_CODE (SET_DEST (pat)) == REG
6737 && REG_P (SET_DEST (pat))
6544 && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE
6738 && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE
6545 && (GET_MODE_CLASS (GET_MODE (XEXP (tem, 0)))
6546 == MODE_FLOAT)
6739 && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (tem, 0)))
6547 && GET_CODE (goal) == CONST_INT
6548 && 0 != (goaltry = operand_subword (XEXP (tem, 0), 1, 0,
6549 VOIDmode))
6550 && rtx_equal_p (goal, goaltry)
6551 && (valtry
6552 = operand_subword (SET_DEST (pat), 1, 0, VOIDmode))
6553 && (valueno = true_regnum (valtry)) >= 0)))
6554 {
6555 if (other >= 0)
6556 {
6557 if (valueno != other)
6558 continue;
6559 }
6560 else if ((unsigned) valueno >= FIRST_PSEUDO_REGISTER)
6561 continue;
6562 else
6563 {
6564 int i;
6565
6740 && GET_CODE (goal) == CONST_INT
6741 && 0 != (goaltry = operand_subword (XEXP (tem, 0), 1, 0,
6742 VOIDmode))
6743 && rtx_equal_p (goal, goaltry)
6744 && (valtry
6745 = operand_subword (SET_DEST (pat), 1, 0, VOIDmode))
6746 && (valueno = true_regnum (valtry)) >= 0)))
6747 {
6748 if (other >= 0)
6749 {
6750 if (valueno != other)
6751 continue;
6752 }
6753 else if ((unsigned) valueno >= FIRST_PSEUDO_REGISTER)
6754 continue;
6755 else
6756 {
6757 int i;
6758
6566 for (i = HARD_REGNO_NREGS (valueno, mode) - 1; i >= 0; i--)
6759 for (i = hard_regno_nregs[valueno][mode] - 1; i >= 0; i--)
6567 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class],
6568 valueno + i))
6569 break;
6570 if (i >= 0)
6571 continue;
6572 }
6573 value = valtry;
6574 where = p;

--- 25 unchanged lines hidden (view full) ---

6600 return 0;
6601
6602 /* Reject VALUE if it was loaded from GOAL
6603 and is also a register that appears in the address of GOAL. */
6604
6605 if (goal_mem && value == SET_DEST (single_set (where))
6606 && refers_to_regno_for_reload_p (valueno,
6607 (valueno
6760 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class],
6761 valueno + i))
6762 break;
6763 if (i >= 0)
6764 continue;
6765 }
6766 value = valtry;
6767 where = p;

--- 25 unchanged lines hidden (view full) ---

6793 return 0;
6794
6795 /* Reject VALUE if it was loaded from GOAL
6796 and is also a register that appears in the address of GOAL. */
6797
6798 if (goal_mem && value == SET_DEST (single_set (where))
6799 && refers_to_regno_for_reload_p (valueno,
6800 (valueno
6608 + HARD_REGNO_NREGS (valueno, mode)),
6801 + hard_regno_nregs[valueno][mode]),
6609 goal, (rtx*) 0))
6610 return 0;
6611
6612 /* Reject registers that overlap GOAL. */
6613
6802 goal, (rtx*) 0))
6803 return 0;
6804
6805 /* Reject registers that overlap GOAL. */
6806
6807 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER)
6808 nregs = hard_regno_nregs[regno][mode];
6809 else
6810 nregs = 1;
6811 valuenregs = hard_regno_nregs[valueno][mode];
6812
6614 if (!goal_mem && !goal_const
6813 if (!goal_mem && !goal_const
6615 && regno + (int) HARD_REGNO_NREGS (regno, mode) > valueno
6616 && regno < valueno + (int) HARD_REGNO_NREGS (valueno, mode))
6814 && regno + nregs > valueno && regno < valueno + valuenregs)
6617 return 0;
6618
6815 return 0;
6816
6619 nregs = HARD_REGNO_NREGS (regno, mode);
6620 valuenregs = HARD_REGNO_NREGS (valueno, mode);
6621
6622 /* Reject VALUE if it is one of the regs reserved for reloads.
6623 Reload1 knows how to reuse them anyway, and it would get
6624 confused if we allocated one without its knowledge.
6625 (Now that insns introduced by reload are ignored above,
6626 this case shouldn't happen, but I'm not positive.) */
6627
6628 if (reload_reg_p != 0 && reload_reg_p != (short *) (HOST_WIDE_INT) 1)
6629 {

--- 8 unchanged lines hidden (view full) ---

6638
6639 if (reload_reg_p != 0)
6640 {
6641 int i;
6642 for (i = 0; i < n_reloads; i++)
6643 if (rld[i].reg_rtx != 0 && rld[i].in)
6644 {
6645 int regno1 = REGNO (rld[i].reg_rtx);
6817 /* Reject VALUE if it is one of the regs reserved for reloads.
6818 Reload1 knows how to reuse them anyway, and it would get
6819 confused if we allocated one without its knowledge.
6820 (Now that insns introduced by reload are ignored above,
6821 this case shouldn't happen, but I'm not positive.) */
6822
6823 if (reload_reg_p != 0 && reload_reg_p != (short *) (HOST_WIDE_INT) 1)
6824 {

--- 8 unchanged lines hidden (view full) ---

6833
6834 if (reload_reg_p != 0)
6835 {
6836 int i;
6837 for (i = 0; i < n_reloads; i++)
6838 if (rld[i].reg_rtx != 0 && rld[i].in)
6839 {
6840 int regno1 = REGNO (rld[i].reg_rtx);
6646 int nregs1 = HARD_REGNO_NREGS (regno1,
6647 GET_MODE (rld[i].reg_rtx));
6841 int nregs1 = hard_regno_nregs[regno1]
6842 [GET_MODE (rld[i].reg_rtx)];
6648 if (regno1 < valueno + valuenregs
6649 && regno1 + nregs1 > valueno)
6650 return 0;
6651 }
6652 }
6653
6654 if (goal_mem)
6655 /* We must treat frame pointer as varying here,

--- 7 unchanged lines hidden (view full) ---

6663 while (1)
6664 {
6665 p = PREV_INSN (p);
6666 if (p == where)
6667 return value;
6668
6669 /* Don't trust the conversion past a function call
6670 if either of the two is in a call-clobbered register, or memory. */
6843 if (regno1 < valueno + valuenregs
6844 && regno1 + nregs1 > valueno)
6845 return 0;
6846 }
6847 }
6848
6849 if (goal_mem)
6850 /* We must treat frame pointer as varying here,

--- 7 unchanged lines hidden (view full) ---

6858 while (1)
6859 {
6860 p = PREV_INSN (p);
6861 if (p == where)
6862 return value;
6863
6864 /* Don't trust the conversion past a function call
6865 if either of the two is in a call-clobbered register, or memory. */
6671 if (GET_CODE (p) == CALL_INSN)
6866 if (CALL_P (p))
6672 {
6673 int i;
6674
6675 if (goal_mem || need_stable_sp)
6676 return 0;
6677
6678 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER)
6679 for (i = 0; i < nregs; ++i)
6867 {
6868 int i;
6869
6870 if (goal_mem || need_stable_sp)
6871 return 0;
6872
6873 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER)
6874 for (i = 0; i < nregs; ++i)
6680 if (call_used_regs[regno + i])
6875 if (call_used_regs[regno + i]
6876 || HARD_REGNO_CALL_PART_CLOBBERED (regno + i, mode))
6681 return 0;
6682
6683 if (valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER)
6684 for (i = 0; i < valuenregs; ++i)
6877 return 0;
6878
6879 if (valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER)
6880 for (i = 0; i < valuenregs; ++i)
6685 if (call_used_regs[valueno + i])
6881 if (call_used_regs[valueno + i]
6882 || HARD_REGNO_CALL_PART_CLOBBERED (valueno + i, mode))
6686 return 0;
6883 return 0;
6687#ifdef NON_SAVING_SETJMP
6688 if (NON_SAVING_SETJMP && find_reg_note (p, REG_SETJMP, NULL))
6689 return 0;
6690#endif
6691 }
6692
6693 if (INSN_P (p))
6694 {
6695 pat = PATTERN (p);
6696
6697 /* Watch out for unspec_volatile, and volatile asms. */
6698 if (volatile_insn_p (pat))

--- 6 unchanged lines hidden (view full) ---

6705
6706 if (GET_CODE (pat) == COND_EXEC)
6707 pat = COND_EXEC_CODE (pat);
6708 if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER)
6709 {
6710 rtx dest = SET_DEST (pat);
6711 while (GET_CODE (dest) == SUBREG
6712 || GET_CODE (dest) == ZERO_EXTRACT
6884 }
6885
6886 if (INSN_P (p))
6887 {
6888 pat = PATTERN (p);
6889
6890 /* Watch out for unspec_volatile, and volatile asms. */
6891 if (volatile_insn_p (pat))

--- 6 unchanged lines hidden (view full) ---

6898
6899 if (GET_CODE (pat) == COND_EXEC)
6900 pat = COND_EXEC_CODE (pat);
6901 if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER)
6902 {
6903 rtx dest = SET_DEST (pat);
6904 while (GET_CODE (dest) == SUBREG
6905 || GET_CODE (dest) == ZERO_EXTRACT
6713 || GET_CODE (dest) == SIGN_EXTRACT
6714 || GET_CODE (dest) == STRICT_LOW_PART)
6715 dest = XEXP (dest, 0);
6906 || GET_CODE (dest) == STRICT_LOW_PART)
6907 dest = XEXP (dest, 0);
6716 if (GET_CODE (dest) == REG)
6908 if (REG_P (dest))
6717 {
6718 int xregno = REGNO (dest);
6719 int xnregs;
6720 if (REGNO (dest) < FIRST_PSEUDO_REGISTER)
6909 {
6910 int xregno = REGNO (dest);
6911 int xnregs;
6912 if (REGNO (dest) < FIRST_PSEUDO_REGISTER)
6721 xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest));
6913 xnregs = hard_regno_nregs[xregno][GET_MODE (dest)];
6722 else
6723 xnregs = 1;
6724 if (xregno < regno + nregs && xregno + xnregs > regno)
6725 return 0;
6726 if (xregno < valueno + valuenregs
6727 && xregno + xnregs > valueno)
6728 return 0;
6729 if (goal_mem_addr_varies
6730 && reg_overlap_mentioned_for_reload_p (dest, goal))
6731 return 0;
6732 if (xregno == STACK_POINTER_REGNUM && need_stable_sp)
6733 return 0;
6734 }
6914 else
6915 xnregs = 1;
6916 if (xregno < regno + nregs && xregno + xnregs > regno)
6917 return 0;
6918 if (xregno < valueno + valuenregs
6919 && xregno + xnregs > valueno)
6920 return 0;
6921 if (goal_mem_addr_varies
6922 && reg_overlap_mentioned_for_reload_p (dest, goal))
6923 return 0;
6924 if (xregno == STACK_POINTER_REGNUM && need_stable_sp)
6925 return 0;
6926 }
6735 else if (goal_mem && GET_CODE (dest) == MEM
6927 else if (goal_mem && MEM_P (dest)
6736 && ! push_operand (dest, GET_MODE (dest)))
6737 return 0;
6928 && ! push_operand (dest, GET_MODE (dest)))
6929 return 0;
6738 else if (GET_CODE (dest) == MEM && regno >= FIRST_PSEUDO_REGISTER
6930 else if (MEM_P (dest) && regno >= FIRST_PSEUDO_REGISTER
6739 && reg_equiv_memory_loc[regno] != 0)
6740 return 0;
6741 else if (need_stable_sp && push_operand (dest, GET_MODE (dest)))
6742 return 0;
6743 }
6744 else if (GET_CODE (pat) == PARALLEL)
6745 {
6746 int i;
6747 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
6748 {
6749 rtx v1 = XVECEXP (pat, 0, i);
6750 if (GET_CODE (v1) == COND_EXEC)
6751 v1 = COND_EXEC_CODE (v1);
6752 if (GET_CODE (v1) == SET || GET_CODE (v1) == CLOBBER)
6753 {
6754 rtx dest = SET_DEST (v1);
6755 while (GET_CODE (dest) == SUBREG
6756 || GET_CODE (dest) == ZERO_EXTRACT
6931 && reg_equiv_memory_loc[regno] != 0)
6932 return 0;
6933 else if (need_stable_sp && push_operand (dest, GET_MODE (dest)))
6934 return 0;
6935 }
6936 else if (GET_CODE (pat) == PARALLEL)
6937 {
6938 int i;
6939 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
6940 {
6941 rtx v1 = XVECEXP (pat, 0, i);
6942 if (GET_CODE (v1) == COND_EXEC)
6943 v1 = COND_EXEC_CODE (v1);
6944 if (GET_CODE (v1) == SET || GET_CODE (v1) == CLOBBER)
6945 {
6946 rtx dest = SET_DEST (v1);
6947 while (GET_CODE (dest) == SUBREG
6948 || GET_CODE (dest) == ZERO_EXTRACT
6757 || GET_CODE (dest) == SIGN_EXTRACT
6758 || GET_CODE (dest) == STRICT_LOW_PART)
6759 dest = XEXP (dest, 0);
6949 || GET_CODE (dest) == STRICT_LOW_PART)
6950 dest = XEXP (dest, 0);
6760 if (GET_CODE (dest) == REG)
6951 if (REG_P (dest))
6761 {
6762 int xregno = REGNO (dest);
6763 int xnregs;
6764 if (REGNO (dest) < FIRST_PSEUDO_REGISTER)
6952 {
6953 int xregno = REGNO (dest);
6954 int xnregs;
6955 if (REGNO (dest) < FIRST_PSEUDO_REGISTER)
6765 xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest));
6956 xnregs = hard_regno_nregs[xregno][GET_MODE (dest)];
6766 else
6767 xnregs = 1;
6768 if (xregno < regno + nregs
6769 && xregno + xnregs > regno)
6770 return 0;
6771 if (xregno < valueno + valuenregs
6772 && xregno + xnregs > valueno)
6773 return 0;
6774 if (goal_mem_addr_varies
6775 && reg_overlap_mentioned_for_reload_p (dest,
6776 goal))
6777 return 0;
6778 if (xregno == STACK_POINTER_REGNUM && need_stable_sp)
6779 return 0;
6780 }
6957 else
6958 xnregs = 1;
6959 if (xregno < regno + nregs
6960 && xregno + xnregs > regno)
6961 return 0;
6962 if (xregno < valueno + valuenregs
6963 && xregno + xnregs > valueno)
6964 return 0;
6965 if (goal_mem_addr_varies
6966 && reg_overlap_mentioned_for_reload_p (dest,
6967 goal))
6968 return 0;
6969 if (xregno == STACK_POINTER_REGNUM && need_stable_sp)
6970 return 0;
6971 }
6781 else if (goal_mem && GET_CODE (dest) == MEM
6972 else if (goal_mem && MEM_P (dest)
6782 && ! push_operand (dest, GET_MODE (dest)))
6783 return 0;
6973 && ! push_operand (dest, GET_MODE (dest)))
6974 return 0;
6784 else if (GET_CODE (dest) == MEM && regno >= FIRST_PSEUDO_REGISTER
6975 else if (MEM_P (dest) && regno >= FIRST_PSEUDO_REGISTER
6785 && reg_equiv_memory_loc[regno] != 0)
6786 return 0;
6787 else if (need_stable_sp
6788 && push_operand (dest, GET_MODE (dest)))
6789 return 0;
6790 }
6791 }
6792 }
6793
6976 && reg_equiv_memory_loc[regno] != 0)
6977 return 0;
6978 else if (need_stable_sp
6979 && push_operand (dest, GET_MODE (dest)))
6980 return 0;
6981 }
6982 }
6983 }
6984
6794 if (GET_CODE (p) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (p))
6985 if (CALL_P (p) && CALL_INSN_FUNCTION_USAGE (p))
6795 {
6796 rtx link;
6797
6798 for (link = CALL_INSN_FUNCTION_USAGE (p); XEXP (link, 1) != 0;
6799 link = XEXP (link, 1))
6800 {
6801 pat = XEXP (link, 0);
6802 if (GET_CODE (pat) == CLOBBER)
6803 {
6804 rtx dest = SET_DEST (pat);
6805
6986 {
6987 rtx link;
6988
6989 for (link = CALL_INSN_FUNCTION_USAGE (p); XEXP (link, 1) != 0;
6990 link = XEXP (link, 1))
6991 {
6992 pat = XEXP (link, 0);
6993 if (GET_CODE (pat) == CLOBBER)
6994 {
6995 rtx dest = SET_DEST (pat);
6996
6806 if (GET_CODE (dest) == REG)
6997 if (REG_P (dest))
6807 {
6808 int xregno = REGNO (dest);
6809 int xnregs
6998 {
6999 int xregno = REGNO (dest);
7000 int xnregs
6810 = HARD_REGNO_NREGS (xregno, GET_MODE (dest));
7001 = hard_regno_nregs[xregno][GET_MODE (dest)];
6811
6812 if (xregno < regno + nregs
6813 && xregno + xnregs > regno)
6814 return 0;
6815 else if (xregno < valueno + valuenregs
6816 && xregno + xnregs > valueno)
6817 return 0;
6818 else if (goal_mem_addr_varies
6819 && reg_overlap_mentioned_for_reload_p (dest,
6820 goal))
6821 return 0;
6822 }
6823
7002
7003 if (xregno < regno + nregs
7004 && xregno + xnregs > regno)
7005 return 0;
7006 else if (xregno < valueno + valuenregs
7007 && xregno + xnregs > valueno)
7008 return 0;
7009 else if (goal_mem_addr_varies
7010 && reg_overlap_mentioned_for_reload_p (dest,
7011 goal))
7012 return 0;
7013 }
7014
6824 else if (goal_mem && GET_CODE (dest) == MEM
7015 else if (goal_mem && MEM_P (dest)
6825 && ! push_operand (dest, GET_MODE (dest)))
6826 return 0;
6827 else if (need_stable_sp
6828 && push_operand (dest, GET_MODE (dest)))
6829 return 0;
6830 }
6831 }
6832 }
6833
6834#ifdef AUTO_INC_DEC
6835 /* If this insn auto-increments or auto-decrements
6836 either regno or valueno, return 0 now.
6837 If GOAL is a memory ref and its address is not constant,
6838 and this insn P increments a register used in GOAL, return 0. */
6839 {
6840 rtx link;
6841
6842 for (link = REG_NOTES (p); link; link = XEXP (link, 1))
6843 if (REG_NOTE_KIND (link) == REG_INC
7016 && ! push_operand (dest, GET_MODE (dest)))
7017 return 0;
7018 else if (need_stable_sp
7019 && push_operand (dest, GET_MODE (dest)))
7020 return 0;
7021 }
7022 }
7023 }
7024
7025#ifdef AUTO_INC_DEC
7026 /* If this insn auto-increments or auto-decrements
7027 either regno or valueno, return 0 now.
7028 If GOAL is a memory ref and its address is not constant,
7029 and this insn P increments a register used in GOAL, return 0. */
7030 {
7031 rtx link;
7032
7033 for (link = REG_NOTES (p); link; link = XEXP (link, 1))
7034 if (REG_NOTE_KIND (link) == REG_INC
6844 && GET_CODE (XEXP (link, 0)) == REG)
7035 && REG_P (XEXP (link, 0)))
6845 {
6846 int incno = REGNO (XEXP (link, 0));
6847 if (incno < regno + nregs && incno >= regno)
6848 return 0;
6849 if (incno < valueno + valuenregs && incno >= valueno)
6850 return 0;
6851 if (goal_mem_addr_varies
6852 && reg_overlap_mentioned_for_reload_p (XEXP (link, 0),

--- 57 unchanged lines hidden (view full) ---

6910 return tem;
6911 }
6912 }
6913 }
6914
6915 return 0;
6916}
6917
7036 {
7037 int incno = REGNO (XEXP (link, 0));
7038 if (incno < regno + nregs && incno >= regno)
7039 return 0;
7040 if (incno < valueno + valuenregs && incno >= valueno)
7041 return 0;
7042 if (goal_mem_addr_varies
7043 && reg_overlap_mentioned_for_reload_p (XEXP (link, 0),

--- 57 unchanged lines hidden (view full) ---

7101 return tem;
7102 }
7103 }
7104 }
7105
7106 return 0;
7107}
7108
7109/* Return 1 if registers from REGNO to ENDREGNO are the subjects of a
7110 REG_INC note in insn INSN. REGNO must refer to a hard register. */
7111
7112#ifdef AUTO_INC_DEC
7113static int
7114reg_inc_found_and_valid_p (unsigned int regno, unsigned int endregno,
7115 rtx insn)
7116{
7117 rtx link;
7118
7119 gcc_assert (insn);
7120
7121 if (! INSN_P (insn))
7122 return 0;
7123
7124 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
7125 if (REG_NOTE_KIND (link) == REG_INC)
7126 {
7127 unsigned int test = (int) REGNO (XEXP (link, 0));
7128 if (test >= regno && test < endregno)
7129 return 1;
7130 }
7131 return 0;
7132}
7133#else
7134
7135#define reg_inc_found_and_valid_p(regno,endregno,insn) 0
7136
7137#endif
7138
6918/* Return 1 if register REGNO is the subject of a clobber in insn INSN.
7139/* Return 1 if register REGNO is the subject of a clobber in insn INSN.
6919 If SETS is nonzero, also consider SETs. */
7140 If SETS is 1, also consider SETs. If SETS is 2, enable checking
7141 REG_INC. REGNO must refer to a hard register. */
6920
6921int
6922regno_clobbered_p (unsigned int regno, rtx insn, enum machine_mode mode,
6923 int sets)
6924{
7142
7143int
7144regno_clobbered_p (unsigned int regno, rtx insn, enum machine_mode mode,
7145 int sets)
7146{
6925 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
6926 unsigned int endregno = regno + nregs;
7147 unsigned int nregs, endregno;
6927
7148
7149 /* regno must be a hard register. */
7150 gcc_assert (regno < FIRST_PSEUDO_REGISTER);
7151
7152 nregs = hard_regno_nregs[regno][mode];
7153 endregno = regno + nregs;
7154
6928 if ((GET_CODE (PATTERN (insn)) == CLOBBER
7155 if ((GET_CODE (PATTERN (insn)) == CLOBBER
6929 || (sets && GET_CODE (PATTERN (insn)) == SET))
6930 && GET_CODE (XEXP (PATTERN (insn), 0)) == REG)
7156 || (sets == 1 && GET_CODE (PATTERN (insn)) == SET))
7157 && REG_P (XEXP (PATTERN (insn), 0)))
6931 {
6932 unsigned int test = REGNO (XEXP (PATTERN (insn), 0));
6933
6934 return test >= regno && test < endregno;
6935 }
6936
7158 {
7159 unsigned int test = REGNO (XEXP (PATTERN (insn), 0));
7160
7161 return test >= regno && test < endregno;
7162 }
7163
7164 if (sets == 2 && reg_inc_found_and_valid_p (regno, endregno, insn))
7165 return 1;
7166
6937 if (GET_CODE (PATTERN (insn)) == PARALLEL)
6938 {
6939 int i = XVECLEN (PATTERN (insn), 0) - 1;
6940
6941 for (; i >= 0; i--)
6942 {
6943 rtx elt = XVECEXP (PATTERN (insn), 0, i);
6944 if ((GET_CODE (elt) == CLOBBER
7167 if (GET_CODE (PATTERN (insn)) == PARALLEL)
7168 {
7169 int i = XVECLEN (PATTERN (insn), 0) - 1;
7170
7171 for (; i >= 0; i--)
7172 {
7173 rtx elt = XVECEXP (PATTERN (insn), 0, i);
7174 if ((GET_CODE (elt) == CLOBBER
6945 || (sets && GET_CODE (PATTERN (insn)) == SET))
6946 && GET_CODE (XEXP (elt, 0)) == REG)
7175 || (sets == 1 && GET_CODE (PATTERN (insn)) == SET))
7176 && REG_P (XEXP (elt, 0)))
6947 {
6948 unsigned int test = REGNO (XEXP (elt, 0));
6949
6950 if (test >= regno && test < endregno)
6951 return 1;
6952 }
7177 {
7178 unsigned int test = REGNO (XEXP (elt, 0));
7179
7180 if (test >= regno && test < endregno)
7181 return 1;
7182 }
7183 if (sets == 2
7184 && reg_inc_found_and_valid_p (regno, endregno, elt))
7185 return 1;
6953 }
6954 }
6955
6956 return 0;
6957}
6958
6959/* Find the low part, with mode MODE, of a hard regno RELOADREG. */
6960rtx
6961reload_adjust_reg_for_mode (rtx reloadreg, enum machine_mode mode)
6962{
6963 int regno;
6964
6965 if (GET_MODE (reloadreg) == mode)
6966 return reloadreg;
6967
6968 regno = REGNO (reloadreg);
6969
6970 if (WORDS_BIG_ENDIAN)
7186 }
7187 }
7188
7189 return 0;
7190}
7191
7192/* Find the low part, with mode MODE, of a hard regno RELOADREG. */
7193rtx
7194reload_adjust_reg_for_mode (rtx reloadreg, enum machine_mode mode)
7195{
7196 int regno;
7197
7198 if (GET_MODE (reloadreg) == mode)
7199 return reloadreg;
7200
7201 regno = REGNO (reloadreg);
7202
7203 if (WORDS_BIG_ENDIAN)
6971 regno += HARD_REGNO_NREGS (regno, GET_MODE (reloadreg))
6972 - HARD_REGNO_NREGS (regno, mode);
7204 regno += (int) hard_regno_nregs[regno][GET_MODE (reloadreg)]
7205 - (int) hard_regno_nregs[regno][mode];
6973
6974 return gen_rtx_REG (mode, regno);
6975}
6976
6977static const char *const reload_when_needed_name[] =
6978{
6979 "RELOAD_FOR_INPUT",
6980 "RELOAD_FOR_OUTPUT",
6981 "RELOAD_FOR_INSN",
6982 "RELOAD_FOR_INPUT_ADDRESS",
6983 "RELOAD_FOR_INPADDR_ADDRESS",
6984 "RELOAD_FOR_OUTPUT_ADDRESS",
6985 "RELOAD_FOR_OUTADDR_ADDRESS",
6986 "RELOAD_FOR_OPERAND_ADDRESS",
6987 "RELOAD_FOR_OPADDR_ADDR",
6988 "RELOAD_OTHER",
6989 "RELOAD_FOR_OTHER_ADDRESS"
6990};
6991
7206
7207 return gen_rtx_REG (mode, regno);
7208}
7209
7210static const char *const reload_when_needed_name[] =
7211{
7212 "RELOAD_FOR_INPUT",
7213 "RELOAD_FOR_OUTPUT",
7214 "RELOAD_FOR_INSN",
7215 "RELOAD_FOR_INPUT_ADDRESS",
7216 "RELOAD_FOR_INPADDR_ADDRESS",
7217 "RELOAD_FOR_OUTPUT_ADDRESS",
7218 "RELOAD_FOR_OUTADDR_ADDRESS",
7219 "RELOAD_FOR_OPERAND_ADDRESS",
7220 "RELOAD_FOR_OPADDR_ADDR",
7221 "RELOAD_OTHER",
7222 "RELOAD_FOR_OTHER_ADDRESS"
7223};
7224
6992static const char * const reg_class_names[] = REG_CLASS_NAMES;
6993
6994/* These functions are used to print the variables set by 'find_reloads' */
6995
6996void
6997debug_reload_to_stream (FILE *f)
6998{
6999 int r;
7000 const char *prefix;
7001

--- 94 unchanged lines hidden --- 		7225/* These functions are used to print the variables set by 'find_reloads' */
7226
7227void
7228debug_reload_to_stream (FILE *f)
7229{
7230 int r;
7231 const char *prefix;
7232

--- 94 unchanged lines hidden ---