3c3,4
< 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
---
> 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation,
> Inc.
19,20c20,21
< Software Foundation, 59 Temple Place - Suite 330, Boston, MA
< 02111-1307, USA. */
---
> Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
> 02110-1301, USA. */
29a31
> init_reload actually has to be called earlier anyway.
100a103
> #include "addresses.h"
107a111
> #include "target.h"
109,111c113,117
< #ifndef REGNO_MODE_OK_FOR_BASE_P
< #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) REGNO_OK_FOR_BASE_P (REGNO)
< #endif
---
> /* True if X is a constant that can be forced into the constant pool. */
> #define CONST_POOL_OK_P(X) \
> (CONSTANT_P (X) \
> && GET_CODE (X) != HIGH \
> && !targetm.cannot_force_const_mem (X))
113,115c119,124
< #ifndef REG_MODE_OK_FOR_BASE_P
< #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
< #endif
---
> /* True if C is a non-empty register class that has too few registers
> to be safely used as a reload target class. */
> #define SMALL_REGISTER_CLASS_P(C) \
> (reg_class_size [(C)] == 1 \
> || (reg_class_size [(C)] >= 1 && CLASS_LIKELY_SPILLED_P (C)))
>
206,207c215,216
< (x == y || (x != 0 && (GET_CODE (x) == REG \
< ? GET_CODE (y) == REG && REGNO (x) == REGNO (y) \
---
> (x == y || (x != 0 && (REG_P (x) \
> ? REG_P (y) && REGNO (x) == REGNO (y) \
238d246
< #ifdef HAVE_SECONDARY_RELOADS
241,243c249,251
< enum insn_code *);
< #endif
< static enum reg_class find_valid_class (enum machine_mode, int, unsigned int);
---
> enum insn_code *, secondary_reload_info *);
> static enum reg_class find_valid_class (enum machine_mode, enum machine_mode,
> int, unsigned int);
265c273,274
< static int find_reloads_address_1 (enum machine_mode, rtx, int, rtx *,
---
> static int find_reloads_address_1 (enum machine_mode, rtx, int,
> enum rtx_code, enum rtx_code, rtx *,
274,275c283,285
< 
< #ifdef HAVE_SECONDARY_RELOADS
---
> static int refers_to_mem_for_reload_p (rtx);
> static int refers_to_regno_for_reload_p (unsigned int, unsigned int,
> rtx, rtx *);
276a287,303
> /* Add NEW to reg_equiv_alt_mem_list[REGNO] if it's not present in the
> list yet. */
>
> static void
> push_reg_equiv_alt_mem (int regno, rtx mem)
> {
> rtx it;
>
> for (it = reg_equiv_alt_mem_list [regno]; it; it = XEXP (it, 1))
> if (rtx_equal_p (XEXP (it, 0), mem))
> return;
>
> reg_equiv_alt_mem_list [regno]
> = alloc_EXPR_LIST (REG_EQUIV, mem,
> reg_equiv_alt_mem_list [regno]);
> }
> 
290c317
< enum insn_code *picode)
---
> enum insn_code *picode, secondary_reload_info *prev_sri)
292a320
> enum reg_class scratch_class;
295,296d322
< enum reg_class t_class = NO_REGS;
< enum machine_mode t_mode = VOIDmode;
299a326,328
> const char *scratch_constraint;
> char letter;
> secondary_reload_info sri;
327c356
< if (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER
---
> if (REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER
331,334c360,363
< #ifdef SECONDARY_INPUT_RELOAD_CLASS
< if (in_p)
< class = SECONDARY_INPUT_RELOAD_CLASS (reload_class, reload_mode, x);
< #endif
---
> sri.icode = CODE_FOR_nothing;
> sri.prev_sri = prev_sri;
> class = targetm.secondary_reload (in_p, x, reload_class, reload_mode, &sri);
> icode = sri.icode;
336,340d364
< #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
< if (! in_p)
< class = SECONDARY_OUTPUT_RELOAD_CLASS (reload_class, reload_mode, x);
< #endif
<
342c366
< if (class == NO_REGS)
---
> if (class == NO_REGS && icode == CODE_FOR_nothing)
345,346c369,371
< /* Get a possible insn to use. If the predicate doesn't accept X, don't
< use the insn. */
---
> if (class != NO_REGS)
> t_reload = push_secondary_reload (in_p, x, opnum, optional, class,
> reload_mode, type, &t_icode, &sri);
348,349c373,374
< icode = (in_p ? reload_in_optab[(int) reload_mode]
< : reload_out_optab[(int) reload_mode]);
---
> /* If we will be using an insn, the secondary reload is for a
> scratch register. */
351,361d375
< if (icode != CODE_FOR_nothing
< && insn_data[(int) icode].operand[in_p].predicate
< && (! (insn_data[(int) icode].operand[in_p].predicate) (x, reload_mode)))
< icode = CODE_FOR_nothing;
<
< /* If we will be using an insn, see if it can directly handle the reload
< register we will be using. If it can, the secondary reload is for a
< scratch register. If it can't, we will use the secondary reload for
< an intermediate register and require a tertiary reload for the scratch
< register. */
<
369c383,386
< enum reg_class insn_class;
---
> /* ??? It would be useful to be able to handle only two, or more than
> three, operands, but for now we can only handle the case of having
> exactly three: output, input and one temp/scratch. */
> gcc_assert (insn_data[(int) icode].n_operands == 3);
371,381c388,392
< if (insn_data[(int) icode].operand[!in_p].constraint[0] == 0)
< insn_class = ALL_REGS;
< else
< {
< const char *insn_constraint
< = &insn_data[(int) icode].operand[!in_p].constraint[in_p];
< char insn_letter = *insn_constraint;
< insn_class
< = (insn_letter == 'r' ? GENERAL_REGS
< : REG_CLASS_FROM_CONSTRAINT ((unsigned char) insn_letter,
< insn_constraint));
---
> /* ??? We currently have no way to represent a reload that needs
> an icode to reload from an intermediate tertiary reload register.
> We should probably have a new field in struct reload to tag a
> chain of scratch operand reloads onto. */
> gcc_assert (class == NO_REGS);
383,388c394,402
< if (insn_class == NO_REGS)
< abort ();
< if (in_p
< && insn_data[(int) icode].operand[!in_p].constraint[0] != '=')
< abort ();
< }
---
> scratch_constraint = insn_data[(int) icode].operand[2].constraint;
> gcc_assert (*scratch_constraint == '=');
> scratch_constraint++;
> if (*scratch_constraint == '&')
> scratch_constraint++;
> letter = *scratch_constraint;
> scratch_class = (letter == 'r' ? GENERAL_REGS
> : REG_CLASS_FROM_CONSTRAINT ((unsigned char) letter,
> scratch_constraint));
390,409c404,405
< /* The scratch register's constraint must start with "=&". */
< if (insn_data[(int) icode].operand[2].constraint[0] != '='
< || insn_data[(int) icode].operand[2].constraint[1] != '&')
< abort ();
<
< if (reg_class_subset_p (reload_class, insn_class))
< mode = insn_data[(int) icode].operand[2].mode;
< else
< {
< const char *t_constraint
< = &insn_data[(int) icode].operand[2].constraint[2];
< char t_letter = *t_constraint;
< class = insn_class;
< t_mode = insn_data[(int) icode].operand[2].mode;
< t_class = (t_letter == 'r' ? GENERAL_REGS
< : REG_CLASS_FROM_CONSTRAINT ((unsigned char) t_letter,
< t_constraint));
< t_icode = icode;
< icode = CODE_FOR_nothing;
< }
---
> class = scratch_class;
> mode = insn_data[(int) icode].operand[2].mode;
426,428c422,423
< if (in_p && class == reload_class && icode == CODE_FOR_nothing
< && t_icode == CODE_FOR_nothing)
< abort ();
---
> gcc_assert (!in_p || class != reload_class || icode != CODE_FOR_nothing
> || t_icode != CODE_FOR_nothing);
430,491d424
< /* If we need a tertiary reload, see if we have one we can reuse or else
< make a new one. */
<
< if (t_class != NO_REGS)
< {
< for (t_reload = 0; t_reload < n_reloads; t_reload++)
< if (rld[t_reload].secondary_p
< && (reg_class_subset_p (t_class, rld[t_reload].class)
< || reg_class_subset_p (rld[t_reload].class, t_class))
< && ((in_p && rld[t_reload].inmode == t_mode)
< || (! in_p && rld[t_reload].outmode == t_mode))
< && ((in_p && (rld[t_reload].secondary_in_icode
< == CODE_FOR_nothing))
< || (! in_p &&(rld[t_reload].secondary_out_icode
< == CODE_FOR_nothing)))
< && (reg_class_size[(int) t_class] == 1 || SMALL_REGISTER_CLASSES)
< && MERGABLE_RELOADS (secondary_type,
< rld[t_reload].when_needed,
< opnum, rld[t_reload].opnum))
< {
< if (in_p)
< rld[t_reload].inmode = t_mode;
< if (! in_p)
< rld[t_reload].outmode = t_mode;
<
< if (reg_class_subset_p (t_class, rld[t_reload].class))
< rld[t_reload].class = t_class;
<
< rld[t_reload].opnum = MIN (rld[t_reload].opnum, opnum);
< rld[t_reload].optional &= optional;
< rld[t_reload].secondary_p = 1;
< if (MERGE_TO_OTHER (secondary_type, rld[t_reload].when_needed,
< opnum, rld[t_reload].opnum))
< rld[t_reload].when_needed = RELOAD_OTHER;
< }
<
< if (t_reload == n_reloads)
< {
< /* We need to make a new tertiary reload for this register class. */
< rld[t_reload].in = rld[t_reload].out = 0;
< rld[t_reload].class = t_class;
< rld[t_reload].inmode = in_p ? t_mode : VOIDmode;
< rld[t_reload].outmode = ! in_p ? t_mode : VOIDmode;
< rld[t_reload].reg_rtx = 0;
< rld[t_reload].optional = optional;
< rld[t_reload].inc = 0;
< /* Maybe we could combine these, but it seems too tricky. */
< rld[t_reload].nocombine = 1;
< rld[t_reload].in_reg = 0;
< rld[t_reload].out_reg = 0;
< rld[t_reload].opnum = opnum;
< rld[t_reload].when_needed = secondary_type;
< rld[t_reload].secondary_in_reload = -1;
< rld[t_reload].secondary_out_reload = -1;
< rld[t_reload].secondary_in_icode = CODE_FOR_nothing;
< rld[t_reload].secondary_out_icode = CODE_FOR_nothing;
< rld[t_reload].secondary_p = 1;
<
< n_reloads++;
< }
< }
<
503c436
< && (reg_class_size[(int) class] == 1 || SMALL_REGISTER_CLASSES)
---
> && (SMALL_REGISTER_CLASS_P (class) || SMALL_REGISTER_CLASSES)
576c509,560
< #endif /* HAVE_SECONDARY_RELOADS */
---
>
> /* If a secondary reload is needed, return its class. If both an intermediate
> register and a scratch register is needed, we return the class of the
> intermediate register. */
> enum reg_class
> secondary_reload_class (bool in_p, enum reg_class class,
> enum machine_mode mode, rtx x)
> {
> enum insn_code icode;
> secondary_reload_info sri;
>
> sri.icode = CODE_FOR_nothing;
> sri.prev_sri = NULL;
> class = targetm.secondary_reload (in_p, x, class, mode, &sri);
> icode = sri.icode;
>
> /* If there are no secondary reloads at all, we return NO_REGS.
> If an intermediate register is needed, we return its class. */
> if (icode == CODE_FOR_nothing || class != NO_REGS)
> return class;
>
> /* No intermediate register is needed, but we have a special reload
> pattern, which we assume for now needs a scratch register. */
> return scratch_reload_class (icode);
> }
>
> /* ICODE is the insn_code of a reload pattern. Check that it has exactly
> three operands, verify that operand 2 is an output operand, and return
> its register class.
> ??? We'd like to be able to handle any pattern with at least 2 operands,
> for zero or more scratch registers, but that needs more infrastructure. */
> enum reg_class
> scratch_reload_class (enum insn_code icode)
> {
> const char *scratch_constraint;
> char scratch_letter;
> enum reg_class class;
>
> gcc_assert (insn_data[(int) icode].n_operands == 3);
> scratch_constraint = insn_data[(int) icode].operand[2].constraint;
> gcc_assert (*scratch_constraint == '=');
> scratch_constraint++;
> if (*scratch_constraint == '&')
> scratch_constraint++;
> scratch_letter = *scratch_constraint;
> if (scratch_letter == 'r')
> return GENERAL_REGS;
> class = REG_CLASS_FROM_CONSTRAINT ((unsigned char) scratch_letter,
> scratch_constraint);
> gcc_assert (class != NO_REGS);
> return class;
> }
662,664d645
< /* Find the largest class for which every register number plus N is valid in
< M1 (if in range) and is cheap to move into REGNO.
< Abort if no such class exists. */
665a647,651
> /* Find the largest class which has at least one register valid in
> mode INNER, and which for every such register, that register number
> plus N is also valid in OUTER (if in range) and is cheap to move
> into REGNO. Such a class must exist. */
>
667c653,654
< find_valid_class (enum machine_mode m1 ATTRIBUTE_UNUSED, int n,
---
> find_valid_class (enum machine_mode outer ATTRIBUTE_UNUSED,
> enum machine_mode inner ATTRIBUTE_UNUSED, int n,
681,685c668,679
< for (regno = 0; regno < FIRST_PSEUDO_REGISTER && ! bad; regno++)
< if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
< && TEST_HARD_REG_BIT (reg_class_contents[class], regno + n)
< && ! HARD_REGNO_MODE_OK (regno + n, m1))
< bad = 1;
---
> int good = 0;
> for (regno = 0; regno < FIRST_PSEUDO_REGISTER - n && ! bad; regno++)
> if (TEST_HARD_REG_BIT (reg_class_contents[class], regno))
> {
> if (HARD_REGNO_MODE_OK (regno, inner))
> {
> good = 1;
> if (! TEST_HARD_REG_BIT (reg_class_contents[class], regno + n)
> || ! HARD_REGNO_MODE_OK (regno + n, outer))
> bad = 1;
> }
> }
687c681
< if (bad)
---
> if (bad || !good)
689c683
< cost = REGISTER_MOVE_COST (m1, class, dest_class);
---
> cost = REGISTER_MOVE_COST (outer, class, dest_class);
697c691
< best_cost = REGISTER_MOVE_COST (m1, class, dest_class);
---
> best_cost = REGISTER_MOVE_COST (outer, class, dest_class);
701,702c695
< if (best_size == 0)
< abort ();
---
> gcc_assert (best_size != 0);
748c741
< && (reg_class_size[(int) class] == 1 || SMALL_REGISTER_CLASSES)
---
> && (SMALL_REGISTER_CLASS_P (class) || SMALL_REGISTER_CLASSES)
766,767c759,760
< && ((GET_CODE (in) == REG
< && GET_RTX_CLASS (GET_CODE (rld[i].in)) == 'a'
---
> && ((REG_P (in)
> && GET_RTX_CLASS (GET_CODE (rld[i].in)) == RTX_AUTOINC
769,770c762,763
< || (GET_CODE (rld[i].in) == REG
< && GET_RTX_CLASS (GET_CODE (in)) == 'a'
---
> || (REG_P (rld[i].in)
> && GET_RTX_CLASS (GET_CODE (in)) == RTX_AUTOINC
773c766
< && (reg_class_size[(int) class] == 1 || SMALL_REGISTER_CLASSES)
---
> && (SMALL_REGISTER_CLASS_P (class) || SMALL_REGISTER_CLASSES)
779c772
< if (GET_CODE (in) == REG)
---
> if (REG_P (in))
806c799
< if (GET_CODE (inner) != REG
---
> if (!REG_P (inner)
821c814
< != (int) HARD_REGNO_NREGS (REGNO (inner), GET_MODE (inner))));
---
> != (int) hard_regno_nregs[REGNO (inner)][GET_MODE (inner)]));
850c843
< if (GET_CODE (in) == REG)
---
> if (REG_P (in))
857c850
< if (GET_CODE (in) == MEM)
---
> if (MEM_P (in))
933c926
< if (in != 0 && GET_CODE (in) == REG)
---
> if (in != 0 && REG_P (in))
945c938
< if (out != 0 && GET_CODE (out) == REG)
---
> if (out != 0 && REG_P (out))
956c949
< if (in != 0 && out != 0 && GET_CODE (in) == MEM && rtx_equal_p (in, out))
---
> if (in != 0 && out != 0 && MEM_P (in) && rtx_equal_p (in, out))
1009c1002
< || (((GET_CODE (SUBREG_REG (in)) == REG
---
> || (((REG_P (SUBREG_REG (in))
1011c1004
< || GET_CODE (SUBREG_REG (in)) == MEM)
---
> || MEM_P (SUBREG_REG (in)))
1021c1014
< && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (in))) != NIL)
---
> && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (in))) != UNKNOWN)
1031c1024
< || (GET_CODE (SUBREG_REG (in)) == REG
---
> || (REG_P (SUBREG_REG (in))
1041,1042c1034,1035
< != (int) HARD_REGNO_NREGS (REGNO (SUBREG_REG (in)),
< GET_MODE (SUBREG_REG (in)))))
---
> != (int) hard_regno_nregs[REGNO (SUBREG_REG (in))]
> [GET_MODE (SUBREG_REG (in))]))
1044,1048c1037,1039
< #ifdef SECONDARY_INPUT_RELOAD_CLASS
< || (SECONDARY_INPUT_RELOAD_CLASS (class, inmode, in) != NO_REGS
< && (SECONDARY_INPUT_RELOAD_CLASS (class,
< GET_MODE (SUBREG_REG (in)),
< SUBREG_REG (in))
---
> || (secondary_reload_class (1, class, inmode, in) != NO_REGS
> && (secondary_reload_class (1, class, GET_MODE (SUBREG_REG (in)),
> SUBREG_REG (in))
1050d1040
< #endif
1052c1042
< || (GET_CODE (SUBREG_REG (in)) == REG
---
> || (REG_P (SUBREG_REG (in))
1063c1053
< if (GET_CODE (in) == MEM)
---
> if (MEM_P (in))
1066,1067c1056
< if (GET_MODE_SIZE (GET_MODE (in)) > GET_MODE_SIZE (inmode))
< abort ();
---
> gcc_assert (GET_MODE_SIZE (GET_MODE (in)) <= GET_MODE_SIZE (inmode));
1086c1075
< if (GET_CODE (SUBREG_REG (in)) == REG)
---
> if (REG_P (SUBREG_REG (in)))
1088c1077
< = find_valid_class (inmode,
---
> = find_valid_class (inmode, GET_MODE (SUBREG_REG (in)),
1118c1107
< || (((GET_CODE (SUBREG_REG (out)) == REG
---
> || (((REG_P (SUBREG_REG (out))
1120c1109
< || GET_CODE (SUBREG_REG (out)) == MEM)
---
> || MEM_P (SUBREG_REG (out)))
1131c1120
< || (GET_CODE (SUBREG_REG (out)) == REG
---
> || (REG_P (SUBREG_REG (out))
1138,1139c1127,1128
< != (int) HARD_REGNO_NREGS (REGNO (SUBREG_REG (out)),
< GET_MODE (SUBREG_REG (out)))))
---
> != (int) hard_regno_nregs[REGNO (SUBREG_REG (out))]
> [GET_MODE (SUBREG_REG (out))]))
1141,1145c1130,1132
< #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
< || (SECONDARY_OUTPUT_RELOAD_CLASS (class, outmode, out) != NO_REGS
< && (SECONDARY_OUTPUT_RELOAD_CLASS (class,
< GET_MODE (SUBREG_REG (out)),
< SUBREG_REG (out))
---
> || (secondary_reload_class (0, class, outmode, out) != NO_REGS
> && (secondary_reload_class (0, class, GET_MODE (SUBREG_REG (out)),
> SUBREG_REG (out))
1147d1133
< #endif
1149c1135
< || (GET_CODE (SUBREG_REG (out)) == REG
---
> || (REG_P (SUBREG_REG (out))
1161,1163c1147,1149
< if (GET_CODE (out) == MEM
< && GET_MODE_SIZE (GET_MODE (out)) > GET_MODE_SIZE (outmode))
< abort ();
---
> gcc_assert (!MEM_P (out)
> || GET_MODE_SIZE (GET_MODE (out))
> <= GET_MODE_SIZE (outmode));
1185c1171
< find_valid_class (outmode,
---
> find_valid_class (outmode, GET_MODE (SUBREG_REG (out)),
1196,1197c1182,1183
< if (in != 0 && out != 0 && GET_CODE (out) == MEM
< && (GET_CODE (in) == REG || GET_CODE (in) == MEM)
---
> if (in != 0 && out != 0 && MEM_P (out)
> && (REG_P (in) || MEM_P (in))
1204c1190
< if (in != 0 && GET_CODE (in) == SUBREG && GET_CODE (SUBREG_REG (in)) == REG
---
> if (in != 0 && GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))
1211c1197
< && GET_CODE (SUBREG_REG (out)) == REG
---
> && REG_P (SUBREG_REG (out))
1218,1219c1204,1205
< if (in != 0)
< class = PREFERRED_RELOAD_CLASS (in, class);
---
> {
> enum reg_class preferred_class = class;
1220a1207,1209
> if (in != 0)
> preferred_class = PREFERRED_RELOAD_CLASS (in, class);
>
1223,1224c1212,1213
< if (out != 0)
< class = PREFERRED_OUTPUT_RELOAD_CLASS (out, class);
---
> if (out != 0)
> preferred_class = PREFERRED_OUTPUT_RELOAD_CLASS (out, preferred_class);
1226a1216,1221
> /* Discard what the target said if we cannot do it. */
> if (preferred_class != NO_REGS
> || (optional && type == RELOAD_FOR_OUTPUT))
> class = preferred_class;
> }
>
1254c1249,1250
< error_for_asm (this_insn, "cannot reload integer constant operand in `asm'");
---
> error_for_asm (this_insn, "cannot reload integer constant "
> "operand in %<asm%>");
1265c1261
< int nregs = HARD_REGNO_NREGS (i, mode);
---
> int nregs = hard_regno_nregs[i][mode];
1276,1277c1272,1286
< error_for_asm (this_insn, "impossible register constraint in `asm'");
< class = ALL_REGS;
---
> error_for_asm (this_insn, "impossible register constraint "
> "in %<asm%>");
> /* Avoid further trouble with this insn. */
> PATTERN (this_insn) = gen_rtx_USE (VOIDmode, const0_rtx);
> /* We used to continue here setting class to ALL_REGS, but it triggers
> sanity check on i386 for:
> void foo(long double d)
> {
> asm("" :: "a" (d));
> }
> Returning zero here ought to be safe as we take care in
> find_reloads to not process the reloads when instruction was
> replaced by USE. */
>
> return 0;
1284,1286c1293,1294
< if (class == NO_REGS
< && (optional == 0 || type != RELOAD_FOR_OUTPUT))
< abort ();
---
> gcc_assert (class != NO_REGS
> || (optional != 0 && type == RELOAD_FOR_OUTPUT));
1296d1303
< #ifdef SECONDARY_INPUT_RELOAD_CLASS
1300,1303c1307
< &secondary_in_icode);
< #endif
<
< #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
---
> &secondary_in_icode, NULL);
1307,1308c1311
< type, &secondary_out_icode);
< #endif
---
> type, &secondary_out_icode, NULL);
1315c1318,1320
< if (in != 0 && (GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
---
> if (in != 0
> && (REG_P (in)
> || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
1345c1350,1352
< if (out != 0 && (GET_CODE (out) == REG || GET_CODE (out) == SUBREG)
---
> if (out != 0
> && (REG_P (out)
> || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
1440,1441c1447
< if (rld[i].inc == 0)
< abort ();
---
> gcc_assert (rld[i].inc != 0);
1489c1495
< && (GET_CODE (in) == REG || CONSTANT_P (in))
---
> && (REG_P (in) || CONSTANT_P (in))
1507c1513
< if (rld[i].reg_rtx == 0 && in != 0)
---
> if (rld[i].reg_rtx == 0 && in != 0 && hard_regs_live_known)
1518c1524
< && GET_CODE (XEXP (note, 0)) == REG
---
> && REG_P (XEXP (note, 0))
1520a1527,1531
> /* Check that we don't use a hardreg for an uninitialized
> pseudo. See also find_dummy_reload(). */
> && (ORIGINAL_REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER
> || ! bitmap_bit_p (ENTRY_BLOCK_PTR->il.rtl->global_live_at_end,
> ORIGINAL_REGNO (XEXP (note, 0))))
1523,1524c1534,1535
< + HARD_REGNO_NREGS (regno,
< rel_mode)),
---
> + hard_regno_nregs[regno]
> [rel_mode]),
1532,1533c1543,1544
< + HARD_REGNO_NREGS (regno,
< rel_mode)),
---
> + hard_regno_nregs[regno]
> [rel_mode]),
1551,1552c1562,1563
< unsigned int nregs = MAX (HARD_REGNO_NREGS (regno, inmode),
< HARD_REGNO_NREGS (regno, outmode));
---
> unsigned int nregs = MAX (hard_regno_nregs[regno][inmode],
> hard_regno_nregs[regno][outmode]);
1562c1573
< (regno, (regno + HARD_REGNO_NREGS (regno, inmode)),
---
> (regno, (regno + hard_regno_nregs[regno][inmode]),
1757c1768
< && ! (GET_CODE (rld[i].in) == REG
---
> && ! (REG_P (rld[i].in)
1826c1837
< && GET_CODE (XEXP (note, 0)) == REG
---
> && REG_P (XEXP (note, 0))
1833,1834c1844,1845
< && (HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), rld[output_reload].outmode)
< <= HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), GET_MODE (XEXP (note, 0))))
---
> && (hard_regno_nregs[REGNO (XEXP (note, 0))][rld[output_reload].outmode]
> <= hard_regno_nregs[REGNO (XEXP (note, 0))][GET_MODE (XEXP (note, 0))])
1845c1856,1861
< && ! fixed_regs[REGNO (XEXP (note, 0))])
---
> && ! fixed_regs[REGNO (XEXP (note, 0))]
> /* Check that we don't use a hardreg for an uninitialized
> pseudo. See also find_dummy_reload(). */
> && (ORIGINAL_REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER
> || ! bitmap_bit_p (ENTRY_BLOCK_PTR->il.rtl->global_live_at_end,
> ORIGINAL_REGNO (XEXP (note, 0)))))
1898c1914
< if (GET_CODE (SUBREG_REG (out)) == REG
---
> if (REG_P (SUBREG_REG (out))
1908c1924
< if (GET_CODE (SUBREG_REG (in)) == REG
---
> if (REG_P (SUBREG_REG (in))
1919c1935,1939
< class = PREFERRED_RELOAD_CLASS (in, class);
---
> {
> enum reg_class preferred_class = PREFERRED_RELOAD_CLASS (in, class);
> if (preferred_class != NO_REGS)
> class = preferred_class;
> }
1922c1942
< if (GET_CODE (out) == REG
---
> if (REG_P (out)
1926c1946
< unsigned int nwords = HARD_REGNO_NREGS (regno, outmode);
---
> unsigned int nwords = hard_regno_nregs[regno][outmode];
1955c1975
< if (GET_CODE (real_out) == REG)
---
> if (REG_P (real_out))
1972c1992
< && GET_CODE (in) == REG
---
> && REG_P (in)
1984c2004,2014
< ? GET_MODE (out) : outmode)))
---
> ? GET_MODE (out) : outmode))
> /* But only do all this if we can be sure, that this input
> operand doesn't correspond with an uninitialized pseudoreg.
> global can assign some hardreg to it, which is the same as
> a different pseudo also currently live (as it can ignore the
> conflict). So we never must introduce writes to such hardregs,
> as they would clobber the other live pseudo using the same.
> See also PR20973. */
> && (ORIGINAL_REGNO (in) < FIRST_PSEUDO_REGISTER
> || ! bitmap_bit_p (ENTRY_BLOCK_PTR->il.rtl->global_live_at_end,
> ORIGINAL_REGNO (in))))
1987c2017
< unsigned int nwords = HARD_REGNO_NREGS (regno, inmode);
---
> unsigned int nwords = hard_regno_nregs[regno][inmode];
2010c2040
< if (GET_CODE (real_in) == REG)
---
> if (REG_P (real_in))
2053c2083
< if (GET_CODE (op0) == REG)
---
> if (REG_P (op0))
2059c2089
< && r + HARD_REGNO_NREGS (r, GET_MODE (op0)) > beg_regno)
---
> && r + hard_regno_nregs[r][GET_MODE (op0)] > beg_regno)
2114,2116c2144,2146
< if ((code == REG || (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG))
< && (GET_CODE (y) == REG || (GET_CODE (y) == SUBREG
< && GET_CODE (SUBREG_REG (y)) == REG)))
---
> if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
> && (REG_P (y) || (GET_CODE (y) == SUBREG
> && REG_P (SUBREG_REG (y)))))
2153c2183
< i += HARD_REGNO_NREGS (i, GET_MODE (x)) - 1;
---
> i += hard_regno_nregs[i][GET_MODE (x)] - 1;
2157c2187
< j += HARD_REGNO_NREGS (j, GET_MODE (y)) - 1;
---
> j += hard_regno_nregs[j][GET_MODE (y)] - 1;
2180,2181c2210,2211
< /* Now we have disposed of all the cases
< in which different rtx codes can match. */
---
> /* Now we have disposed of all the cases in which different rtx codes
> can match. */
2184,2187d2213
< if (code == LABEL_REF)
< return XEXP (x, 0) == XEXP (y, 0);
< if (code == SYMBOL_REF)
< return XSTR (x, 0) == XSTR (y, 0);
2190d2215
<
2193a2219,2233
> switch (code)
> {
> case CONST_INT:
> case CONST_DOUBLE:
> return 0;
>
> case LABEL_REF:
> return XEXP (x, 0) == XEXP (y, 0);
> case SYMBOL_REF:
> return XSTR (x, 0) == XSTR (y, 0);
>
> default:
> break;
> }
>
2244c2284
< abort ();
---
> gcc_unreachable ();
2264,2270c2304
< val.reg_flag = 0;
< val.safe = 0;
< val.base = 0;
< if (GET_CODE (x) == MEM)
< {
< rtx base = NULL_RTX, offset = 0;
< rtx addr = XEXP (x, 0);
---
> memset (&val, 0, sizeof (val));
2272,2357c2306
< if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == PRE_INC
< || GET_CODE (addr) == POST_DEC || GET_CODE (addr) == POST_INC)
< {
< val.base = XEXP (addr, 0);
< val.start = -GET_MODE_SIZE (GET_MODE (x));
< val.end = GET_MODE_SIZE (GET_MODE (x));
< val.safe = REGNO (val.base) == STACK_POINTER_REGNUM;
< return val;
< }
<
< if (GET_CODE (addr) == PRE_MODIFY || GET_CODE (addr) == POST_MODIFY)
< {
< if (GET_CODE (XEXP (addr, 1)) == PLUS
< && XEXP (addr, 0) == XEXP (XEXP (addr, 1), 0)
< && CONSTANT_P (XEXP (XEXP (addr, 1), 1)))
< {
< val.base = XEXP (addr, 0);
< val.start = -INTVAL (XEXP (XEXP (addr, 1), 1));
< val.end = INTVAL (XEXP (XEXP (addr, 1), 1));
< val.safe = REGNO (val.base) == STACK_POINTER_REGNUM;
< return val;
< }
< }
<
< if (GET_CODE (addr) == CONST)
< {
< addr = XEXP (addr, 0);
< all_const = 1;
< }
< if (GET_CODE (addr) == PLUS)
< {
< if (CONSTANT_P (XEXP (addr, 0)))
< {
< base = XEXP (addr, 1);
< offset = XEXP (addr, 0);
< }
< else if (CONSTANT_P (XEXP (addr, 1)))
< {
< base = XEXP (addr, 0);
< offset = XEXP (addr, 1);
< }
< }
<
< if (offset == 0)
< {
< base = addr;
< offset = const0_rtx;
< }
< if (GET_CODE (offset) == CONST)
< offset = XEXP (offset, 0);
< if (GET_CODE (offset) == PLUS)
< {
< if (GET_CODE (XEXP (offset, 0)) == CONST_INT)
< {
< base = gen_rtx_PLUS (GET_MODE (base), base, XEXP (offset, 1));
< offset = XEXP (offset, 0);
< }
< else if (GET_CODE (XEXP (offset, 1)) == CONST_INT)
< {
< base = gen_rtx_PLUS (GET_MODE (base), base, XEXP (offset, 0));
< offset = XEXP (offset, 1);
< }
< else
< {
< base = gen_rtx_PLUS (GET_MODE (base), base, offset);
< offset = const0_rtx;
< }
< }
< else if (GET_CODE (offset) != CONST_INT)
< {
< base = gen_rtx_PLUS (GET_MODE (base), base, offset);
< offset = const0_rtx;
< }
<
< if (all_const && GET_CODE (base) == PLUS)
< base = gen_rtx_CONST (GET_MODE (base), base);
<
< if (GET_CODE (offset) != CONST_INT)
< abort ();
<
< val.start = INTVAL (offset);
< val.end = val.start + GET_MODE_SIZE (GET_MODE (x));
< val.base = base;
< return val;
< }
< else if (GET_CODE (x) == REG)
---
> switch (GET_CODE (x))
2358a2308,2398
> case MEM:
> {
> rtx base = NULL_RTX, offset = 0;
> rtx addr = XEXP (x, 0);
>
> if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == PRE_INC
> || GET_CODE (addr) == POST_DEC || GET_CODE (addr) == POST_INC)
> {
> val.base = XEXP (addr, 0);
> val.start = -GET_MODE_SIZE (GET_MODE (x));
> val.end = GET_MODE_SIZE (GET_MODE (x));
> val.safe = REGNO (val.base) == STACK_POINTER_REGNUM;
> return val;
> }
>
> if (GET_CODE (addr) == PRE_MODIFY || GET_CODE (addr) == POST_MODIFY)
> {
> if (GET_CODE (XEXP (addr, 1)) == PLUS
> && XEXP (addr, 0) == XEXP (XEXP (addr, 1), 0)
> && CONSTANT_P (XEXP (XEXP (addr, 1), 1)))
> {
> val.base = XEXP (addr, 0);
> val.start = -INTVAL (XEXP (XEXP (addr, 1), 1));
> val.end = INTVAL (XEXP (XEXP (addr, 1), 1));
> val.safe = REGNO (val.base) == STACK_POINTER_REGNUM;
> return val;
> }
> }
>
> if (GET_CODE (addr) == CONST)
> {
> addr = XEXP (addr, 0);
> all_const = 1;
> }
> if (GET_CODE (addr) == PLUS)
> {
> if (CONSTANT_P (XEXP (addr, 0)))
> {
> base = XEXP (addr, 1);
> offset = XEXP (addr, 0);
> }
> else if (CONSTANT_P (XEXP (addr, 1)))
> {
> base = XEXP (addr, 0);
> offset = XEXP (addr, 1);
> }
> }
>
> if (offset == 0)
> {
> base = addr;
> offset = const0_rtx;
> }
> if (GET_CODE (offset) == CONST)
> offset = XEXP (offset, 0);
> if (GET_CODE (offset) == PLUS)
> {
> if (GET_CODE (XEXP (offset, 0)) == CONST_INT)
> {
> base = gen_rtx_PLUS (GET_MODE (base), base, XEXP (offset, 1));
> offset = XEXP (offset, 0);
> }
> else if (GET_CODE (XEXP (offset, 1)) == CONST_INT)
> {
> base = gen_rtx_PLUS (GET_MODE (base), base, XEXP (offset, 0));
> offset = XEXP (offset, 1);
> }
> else
> {
> base = gen_rtx_PLUS (GET_MODE (base), base, offset);
> offset = const0_rtx;
> }
> }
> else if (GET_CODE (offset) != CONST_INT)
> {
> base = gen_rtx_PLUS (GET_MODE (base), base, offset);
> offset = const0_rtx;
> }
>
> if (all_const && GET_CODE (base) == PLUS)
> base = gen_rtx_CONST (GET_MODE (base), base);
>
> gcc_assert (GET_CODE (offset) == CONST_INT);
>
> val.start = INTVAL (offset);
> val.end = val.start + GET_MODE_SIZE (GET_MODE (x));
> val.base = base;
> }
> break;
>
> case REG:
2361c2401
< if (val.start < 0)
---
> if (val.start < 0 || val.start >= FIRST_PSEUDO_REGISTER)
2369,2373c2409,2413
< val.end = val.start + HARD_REGNO_NREGS (val.start, GET_MODE (x));
< }
< else if (GET_CODE (x) == SUBREG)
< {
< if (GET_CODE (SUBREG_REG (x)) != REG)
---
> val.end = val.start + hard_regno_nregs[val.start][GET_MODE (x)];
> break;
>
> case SUBREG:
> if (!REG_P (SUBREG_REG (x)))
2378c2418
< if (val.start < 0)
---
> if (val.start < 0 || val.start >= FIRST_PSEUDO_REGISTER)
2382c2422,2433
< val.end = val.start + HARD_REGNO_NREGS (val.start, GET_MODE (x));
---
> val.end = val.start + hard_regno_nregs[val.start][GET_MODE (x)];
> break;
>
> case SCRATCH:
> /* This hasn't been assigned yet, so it can't conflict yet. */
> val.safe = 1;
> break;
>
> default:
> gcc_assert (CONSTANT_P (x));
> val.safe = 1;
> break;
2384,2389d2434
< else if (CONSTANT_P (x)
< /* This hasn't been assigned yet, so it can't conflict yet. */
< || GET_CODE (x) == SCRATCH)
< val.safe = 1;
< else
< abort ();
2406,2407c2451
< if (GET_CODE (y) != MEM)
< abort ();
---
> gcc_assert (MEM_P (y));
2409c2453
< if (GET_CODE (x) != MEM)
---
> if (!MEM_P (x))
2484c2528,2529
< /* Nonzero for a MEM operand whose entire address needs a reload. */
---
> /* Nonzero for a MEM operand whose entire address needs a reload.
> May be -1 to indicate the entire address may or may not need a reload. */
2486c2531,2532
< /* Nonzero for an address operand that needs to be completely reloaded. */
---
> /* Nonzero for an address operand that needs to be completely reloaded.
> May be -1 to indicate the entire operand may or may not need a reload. */
2535c2581
< if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN)
---
> if (JUMP_P (insn) || CALL_P (insn))
2561c2607
< && GET_CODE (SET_DEST (body)) == REG
---
> && REG_P (SET_DEST (body))
2563c2609
< && GET_CODE (SET_SRC (body)) == REG
---
> && REG_P (SET_SRC (body))
2609,2613c2655
< if (c == '=')
< modified[i] = RELOAD_WRITE;
< else if (c == '+')
< modified[i] = RELOAD_READ_WRITE;
< else if (c == '%')
---
> switch (c)
2615,2617c2657,2666
< /* The last operand should not be marked commutative. */
< if (i == noperands - 1)
< abort ();
---
> case '=':
> modified[i] = RELOAD_WRITE;
> break;
> case '+':
> modified[i] = RELOAD_READ_WRITE;
> break;
> case '%':
> {
> /* The last operand should not be marked commutative. */
> gcc_assert (i != noperands - 1);
2619,2633c2668,2686
< /* We currently only support one commutative pair of
< operands. Some existing asm code currently uses more
< than one pair. Previously, that would usually work,
< but sometimes it would crash the compiler. We
< continue supporting that case as well as we can by
< silently ignoring all but the first pair. In the
< future we may handle it correctly. */
< if (commutative < 0)
< commutative = i;
< else if (!this_insn_is_asm)
< abort ();
< }
< else if (ISDIGIT (c))
< {
< c = strtoul (p - 1, &p, 10);
---
> /* We currently only support one commutative pair of
> operands. Some existing asm code currently uses more
> than one pair. Previously, that would usually work,
> but sometimes it would crash the compiler. We
> continue supporting that case as well as we can by
> silently ignoring all but the first pair. In the
> future we may handle it correctly. */
> if (commutative < 0)
> commutative = i;
> else
> gcc_assert (this_insn_is_asm);
> }
> break;
> /* Use of ISDIGIT is tempting here, but it may get expensive because
> of locale support we don't want. */
> case '0': case '1': case '2': case '3': case '4':
> case '5': case '6': case '7': case '8': case '9':
> {
> c = strtoul (p - 1, &p, 10);
2635,2637c2688,2690
< operands_match[c][i]
< = operands_match_p (recog_data.operand[c],
< recog_data.operand[i]);
---
> operands_match[c][i]
> = operands_match_p (recog_data.operand[c],
> recog_data.operand[i]);
2639,2641c2692,2693
< /* An operand may not match itself. */
< if (c == i)
< abort ();
---
> /* An operand may not match itself. */
> gcc_assert (c != i);
2643,2664c2695,2717
< /* If C can be commuted with C+1, and C might need to match I,
< then C+1 might also need to match I. */
< if (commutative >= 0)
< {
< if (c == commutative || c == commutative + 1)
< {
< int other = c + (c == commutative ? 1 : -1);
< operands_match[other][i]
< = operands_match_p (recog_data.operand[other],
< recog_data.operand[i]);
< }
< if (i == commutative || i == commutative + 1)
< {
< int other = i + (i == commutative ? 1 : -1);
< operands_match[c][other]
< = operands_match_p (recog_data.operand[c],
< recog_data.operand[other]);
< }
< /* Note that C is supposed to be less than I.
< No need to consider altering both C and I because in
< that case we would alter one into the other. */
< }
---
> /* If C can be commuted with C+1, and C might need to match I,
> then C+1 might also need to match I. */
> if (commutative >= 0)
> {
> if (c == commutative || c == commutative + 1)
> {
> int other = c + (c == commutative ? 1 : -1);
> operands_match[other][i]
> = operands_match_p (recog_data.operand[other],
> recog_data.operand[i]);
> }
> if (i == commutative || i == commutative + 1)
> {
> int other = i + (i == commutative ? 1 : -1);
> operands_match[c][other]
> = operands_match_p (recog_data.operand[c],
> recog_data.operand[other]);
> }
> /* Note that C is supposed to be less than I.
> No need to consider altering both C and I because in
> that case we would alter one into the other. */
> }
> }
2705c2758
< if ((GET_RTX_CLASS (GET_CODE (*recog_data.operand_loc[i])) == 'o'
---
> if ((OBJECT_P (*recog_data.operand_loc[i])
2751,2752c2804,2805
< && GET_CODE (op) == MEM
< && GET_CODE (reg) == REG
---
> && MEM_P (op)
> && REG_P (reg)
2761c2814
< else if (code == PLUS || GET_RTX_CLASS (code) == '1')
---
> else if (code == PLUS || GET_RTX_CLASS (code) == RTX_UNARY)
2889c2942
< if (GET_RTX_CLASS (GET_CODE (operand)) == '1' && *p != 0)
---
> if (UNARY_P (operand) && *p != 0)
2902c2955
< if (GET_CODE (SUBREG_REG (operand)) == REG
---
> if (REG_P (SUBREG_REG (operand))
2945,2946c2998,2999
< || ((GET_CODE (operand) == MEM
< || (GET_CODE (operand)== REG
---
> || ((MEM_P (operand)
> || (REG_P (operand)
2961c3014
< && LOAD_EXTEND_OP (GET_MODE (operand)) != NIL)
---
> && LOAD_EXTEND_OP (GET_MODE (operand)) != UNKNOWN)
3056c3109
< && GET_CODE (recog_data.operand[m]) == MEM
---
> && MEM_P (recog_data.operand[m])
3122c3175,3176
< this_alternative[i] = (int) MODE_BASE_REG_CLASS (VOIDmode);
---
> this_alternative[i]
> = (int) base_reg_class (VOIDmode, ADDRESS, SCRATCH);
3130,3131c3184,3185
< if (GET_CODE (operand) == MEM
< || (GET_CODE (operand) == REG
---
> if (MEM_P (operand)
> || (REG_P (operand)
3135,3137c3189
< if (CONSTANT_P (operand)
< /* force_const_mem does not accept HIGH. */
< && GET_CODE (operand) != HIGH)
---
> if (CONST_POOL_OK_P (operand))
3143c3195
< if (GET_CODE (operand) == MEM
---
> if (MEM_P (operand)
3151c3203
< if (GET_CODE (operand) == MEM
---
> if (MEM_P (operand)
3162c3214
< if (GET_CODE (operand) == MEM
---
> if (MEM_P (operand)
3169c3221
< && !(GET_CODE (XEXP (operand, 0)) == REG
---
> && !(REG_P (XEXP (operand, 0))
3179c3231
< if ((GET_CODE (operand) == MEM
---
> if ((MEM_P (operand)
3187,3188c3239,3240
< || address_reloaded[i]))
< || (GET_CODE (operand) == REG
---
> || address_reloaded[i] == 1))
> || (REG_P (operand)
3199,3201c3251,3252
< /* force_const_mem does not accept HIGH. */
< if ((CONSTANT_P (operand) && GET_CODE (operand) != HIGH)
< || GET_CODE (operand) == MEM)
---
> if (CONST_POOL_OK_P (operand)
> || MEM_P (operand))
3236,3239c3287
< #ifdef LEGITIMATE_PIC_OPERAND_P
< && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (operand))
< #endif
< )
---
> && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (operand)))
3263a3312
> force_reload = 0;
3274d3322
< #ifdef LEGITIMATE_PIC_OPERAND_P
3278d3325
< #endif
3280c3327
< || GET_CODE (operand) != REG
---
> || !REG_P (operand)
3303,3304c3350,3351
< else if (GET_CODE (operand) == MEM
< && address_reloaded[i])
---
> else if (MEM_P (operand)
> && address_reloaded[i] == 1)
3309c3356
< else if (GET_CODE (operand) == REG
---
> else if (REG_P (operand)
3320,3321c3367,3368
< if ((CONSTANT_P (operand) && GET_CODE (operand) != HIGH)
< || GET_CODE (operand) == MEM)
---
> if (CONST_POOL_OK_P (operand)
> || MEM_P (operand))
3334c3381,3382
< this_alternative[i] = (int) MODE_BASE_REG_CLASS (VOIDmode);
---
> this_alternative[i]
> = (int) base_reg_class (VOIDmode, ADDRESS, SCRATCH);
3353c3401
< if (GET_CODE (operand) == REG
---
> if (REG_P (operand)
3383c3431
< if (GET_CODE (operand) == REG
---
> if (REG_P (operand)
3396,3398c3444
< if (CONSTANT_P (operand)
< /* force_const_mem does not accept HIGH. */
< && GET_CODE (operand) != HIGH
---
> if (CONST_POOL_OK_P (operand)
3410,3421d3455
< /* If we can't reload this value at all, reject this
< alternative. Note that we could also lose due to
< LIMIT_RELOAD_RELOAD_CLASS, but we don't check that
< here. */
<
< if (! CONSTANT_P (operand)
< && (enum reg_class) this_alternative[i] != NO_REGS
< && (PREFERRED_RELOAD_CLASS (operand,
< (enum reg_class) this_alternative[i])
< == NO_REGS))
< bad = 1;
<
3425c3459
< else if (GET_CODE (operand) != SCRATCH
---
> if (GET_CODE (operand) != SCRATCH
3433,3436c3467,3485
< #ifdef DISPARAGE_RELOAD_CLASS
< reject
< += DISPARAGE_RELOAD_CLASS (operand,
< (enum reg_class) this_alternative[i]);
---
> /* If we can't reload this value at all, reject this
> alternative. Note that we could also lose due to
> LIMIT_RELOAD_CLASS, but we don't check that
> here. */
>
> if (! CONSTANT_P (operand)
> && (enum reg_class) this_alternative[i] != NO_REGS)
> {
> if (PREFERRED_RELOAD_CLASS
> (operand, (enum reg_class) this_alternative[i])
> == NO_REGS)
> reject = 600;
>
> #ifdef PREFERRED_OUTPUT_RELOAD_CLASS
> if (operand_type[i] == RELOAD_FOR_OUTPUT
> && PREFERRED_OUTPUT_RELOAD_CLASS
> (operand, (enum reg_class) this_alternative[i])
> == NO_REGS)
> reject = 600;
3437a3487
> }
3447c3497
< if (! (GET_CODE (operand) == REG
---
> if (! (REG_P (operand)
3484c3534,3535
< && reg_class_size[(int) preferred_class[i]] > 1)
---
> && reg_class_size [(int) preferred_class[i]] > 0
> && ! SMALL_REGISTER_CLASS_P (preferred_class[i]))
3514,3515c3565
< if (modified[i] == RELOAD_READ)
< abort ();
---
> gcc_assert (modified[i] != RELOAD_READ);
3520,3524c3570,3572
< if (this_insn_is_asm)
< error_for_asm (this_insn,
< "`&' constraint used with no register class");
< else
< abort ();
---
> gcc_assert (this_insn_is_asm);
> error_for_asm (this_insn,
> "%<&%> constraint used with no register class");
3529c3577
< if ((GET_CODE (recog_data.operand[j]) == MEM
---
> if ((MEM_P (recog_data.operand[j])
3543c3591
< /* If the output is in a single-reg class,
---
> /* If the output is in a non-empty few-regs class,
3545,3546c3593,3594
< if (reg_class_size[this_alternative[i]] == 1
< && (GET_CODE (recog_data.operand[j]) == REG
---
> if (SMALL_REGISTER_CLASS_P (this_alternative[i])
> && (REG_P (recog_data.operand[j])
3662a3711,3714
> t = address_reloaded[commutative];
> address_reloaded[commutative] = address_reloaded[commutative + 1];
> address_reloaded[commutative + 1] = t;
>
3691c3743
< error_for_asm (insn, "inconsistent operand constraints in an `asm'");
---
> error_for_asm (insn, "inconsistent operand constraints in an %<asm%>");
3778,3780c3830
< && CONSTANT_P (recog_data.operand[i])
< /* force_const_mem does not accept HIGH. */
< && GET_CODE (recog_data.operand[i]) != HIGH
---
> && CONST_POOL_OK_P (recog_data.operand[i])
3796a3847,3867
> /* Likewise any invalid constants appearing as operand of a PLUS
> that is to be reloaded. */
> for (i = 0; i < noperands; i++)
> if (! goal_alternative_win[i]
> && GET_CODE (recog_data.operand[i]) == PLUS
> && CONST_POOL_OK_P (XEXP (recog_data.operand[i], 1))
> && (PREFERRED_RELOAD_CLASS (XEXP (recog_data.operand[i], 1),
> (enum reg_class) goal_alternative[i])
> == NO_REGS)
> && operand_mode[i] != VOIDmode)
> {
> rtx tem = force_const_mem (operand_mode[i],
> XEXP (recog_data.operand[i], 1));
> tem = gen_rtx_PLUS (operand_mode[i],
> XEXP (recog_data.operand[i], 0), tem);
>
> substed_operand[i] = recog_data.operand[i]
> = find_reloads_toplev (tem, i, address_type[i],
> ind_levels, 0, insn, NULL);
> }
>
3819c3890
< && GET_CODE (recog_data.operand[i]) == MEM)
---
> && MEM_P (recog_data.operand[i]))
3820a3892,3899
> /* If the address to be reloaded is a VOIDmode constant,
> use Pmode as mode of the reload register, as would have
> been done by find_reloads_address. */
> enum machine_mode address_mode;
> address_mode = GET_MODE (XEXP (recog_data.operand[i], 0));
> if (address_mode == VOIDmode)
> address_mode = Pmode;
>
3824,3825c3903,3904
< MODE_BASE_REG_CLASS (VOIDmode),
< GET_MODE (XEXP (recog_data.operand[i], 0)),
---
> base_reg_class (VOIDmode, MEM, SCRATCH),
> address_mode,
3901,3902d3979
< else if (insn_code_number >= 0)
< abort ();
3905c3982,3984
< error_for_asm (insn, "inconsistent operand constraints in an `asm'");
---
> gcc_assert (insn_code_number < 0);
> error_for_asm (insn, "inconsistent operand constraints "
> "in an %<asm%>");
3914c3993
< && !address_operand_reloaded[i]
---
> && address_operand_reloaded[i] != 1
3925,3926c4004,4005
< if ((GET_CODE (operand) == MEM
< || (GET_CODE (operand) == REG
---
> if ((MEM_P (operand)
> || (REG_P (operand)
3966,3967c4045,4046
< && (GET_CODE (operand) == MEM
< || (GET_CODE (operand) == REG
---
> && (MEM_P (operand)
> || (REG_P (operand)
3975c4054
< if (GET_CODE (operand) == REG)
---
> if (REG_P (operand))
4002,4003c4081,4082
< if ((GET_CODE (operand) == MEM
< || (GET_CODE (operand) == REG
---
> if ((MEM_P (operand)
> || (REG_P (operand)
4026c4105
< later passes. Moreover, we loose the opportunity to get a useful
---
> later passes. Moreover, we lose the opportunity to get a useful
4038c4117
< if (GET_CODE (insn) != JUMP_INSN
---
> if (!JUMP_P (insn)
4078c4157
< && GET_CODE (rld[i].in) == REG
---
> && REG_P (rld[i].in)
4090a4170,4175
> /* If we detected error and replaced asm instruction by USE, forget about the
> reloads. */
> if (GET_CODE (PATTERN (insn)) == USE
> && GET_CODE (XEXP (PATTERN (insn), 0)) == CONST_INT)
> n_reloads = 0;
>
4360,4363c4445,4447
< if (rld[i].in != 0
< && rld[i].when_needed != RELOAD_FOR_OUTADDR_ADDRESS
< && rld[i].when_needed != RELOAD_FOR_OUTPUT_ADDRESS)
< abort ();
---
> gcc_assert (rld[i].in == 0
> || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS
> || rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS);
4383c4467
< && GET_CODE (SET_DEST (PATTERN (insn))) == REG
---
> && REG_P (SET_DEST (PATTERN (insn)))
4393c4477
< int nr = HARD_REGNO_NREGS (regno, rld[i].mode);
---
> int nr = hard_regno_nregs[regno][rld[i].mode];
4493a4578,4579
> if (x != mem)
> push_reg_equiv_alt_mem (regno, x);
4512c4598
< if (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG)
---
> if (code == SUBREG && REG_P (SUBREG_REG (x)))
4514,4521c4600,4607
< /* Check for SUBREG containing a REG that's equivalent to a constant.
< If the constant has a known value, truncate it right now.
< Similarly if we are extracting a single-word of a multi-word
< constant. If the constant is symbolic, allow it to be substituted
< normally. push_reload will strip the subreg later. If the
< constant is VOIDmode, abort because we will lose the mode of
< the register (this should never happen because one of the cases
< above should handle it). */
---
> /* Check for SUBREG containing a REG that's equivalent to a
> constant. If the constant has a known value, truncate it
> right now. Similarly if we are extracting a single-word of a
> multi-word constant. If the constant is symbolic, allow it
> to be substituted normally. push_reload will strip the
> subreg later. The constant must not be VOIDmode, because we
> will lose the mode of the register (this should never happen
> because one of the cases above should handle it). */
4527c4613,4614
< && regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
---
> && regno >= FIRST_PSEUDO_REGISTER
> && reg_renumber[regno] < 0
4533c4620,4621
< if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0
---
> if (regno >= FIRST_PSEUDO_REGISTER
> && reg_renumber[regno] < 0
4539,4540c4627
< if (!tem)
< abort ();
---
> gcc_assert (tem);
4557c4644
< else if (regno >= FIRST_PSEUDO_REGISTER
---
> if (regno >= FIRST_PSEUDO_REGISTER
4654,4655c4741,4743
< Value is nonzero if this address is reloaded or replaced as a whole.
< This is interesting to the caller if the address is an autoincrement.
---
> Value is one if this address is reloaded or replaced as a whole; it is
> zero if the top level of this address was not reloaded or replaced, and
> it is -1 if it may or may not have been reloaded or replaced.
4669a4758
> int op_index;
4676c4765
< if (GET_CODE (ad) == REG)
---
> if (REG_P (ad))
4698a4788,4789
> rtx orig = tem;
>
4701a4793,4794
> if (tem != orig)
> push_reg_equiv_alt_mem (regno, tem);
4710c4803
< && (GET_CODE (XEXP (tem, 0)) == REG
---
> && (REG_P (XEXP (tem, 0))
4712c4805
< && GET_CODE (XEXP (XEXP (tem, 0), 0)) == REG
---
> && REG_P (XEXP (XEXP (tem, 0), 0))
4743c4836
< && REGNO_MODE_OK_FOR_BASE_P (regno, mode)
---
> && regno_ok_for_base_p (regno, mode, MEM, SCRATCH)
4748c4841
< push_reload (ad, NULL_RTX, loc, (rtx*) 0, MODE_BASE_REG_CLASS (mode),
---
> push_reload (ad, NULL_RTX, loc, (rtx*) 0, base_reg_class (mode, MEM, SCRATCH),
4765c4858
< && GET_CODE (XEXP (ad, 0)) == REG
---
> && REG_P (XEXP (ad, 0))
4793c4886
< return 1;
---
> return -1;
4814c4907
< if (GET_CODE (ad) == MEM)
---
> if (MEM_P (ad))
4840,4841c4933,4934
< || GET_CODE (XEXP (tem, 0)) == MEM
< || ! (GET_CODE (XEXP (tem, 0)) == REG
---
> || MEM_P (XEXP (tem, 0))
> || ! (REG_P (XEXP (tem, 0))
4843c4936
< && GET_CODE (XEXP (XEXP (tem, 0), 0)) == REG
---
> && REG_P (XEXP (XEXP (tem, 0), 0))
4849c4942
< MODE_BASE_REG_CLASS (mode), GET_MODE (tem),
---
> base_reg_class (mode, MEM, SCRATCH), GET_MODE (tem),
4864c4957
< && GET_CODE (XEXP (ad, 0)) == REG
---
> && REG_P (XEXP (ad, 0))
4866,4867c4959,4962
< && REG_MODE_OK_FOR_BASE_P (XEXP (ad, 0), mode)
< && GET_CODE (XEXP (ad, 1)) == CONST_INT)
---
> && GET_CODE (XEXP (ad, 1)) == CONST_INT
> && regno_ok_for_base_p (REGNO (XEXP (ad, 0)), mode, PLUS,
> CONST_INT))
>
4895c4990,4991
< find_reloads_address_part (ad, loc, MODE_BASE_REG_CLASS (mode),
---
> find_reloads_address_part (ad, loc,
> base_reg_class (mode, MEM, SCRATCH),
4915c5011,5013
< subreg big-endian corrections made by find_reloads_toplev.
---
> subreg big-endian corrections made by find_reloads_toplev. We
> can also get expressions involving LO_SUM (rather than PLUS) from
> find_reloads_subreg_address.
4923c5021
< the innermost PLUS. */
---
> the innermost PLUS and/or LO_SUM. */
4925,4938c5023
< else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT
< && GET_CODE (XEXP (ad, 0)) == PLUS
< && GET_CODE (XEXP (XEXP (ad, 0), 0)) == REG
< && REGNO (XEXP (XEXP (ad, 0), 0)) < FIRST_PSEUDO_REGISTER
< && (REG_MODE_OK_FOR_BASE_P (XEXP (XEXP (ad, 0), 0), mode)
< || XEXP (XEXP (ad, 0), 0) == frame_pointer_rtx
< #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
< || XEXP (XEXP (ad, 0), 0) == hard_frame_pointer_rtx
< #endif
< #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
< || XEXP (XEXP (ad, 0), 0) == arg_pointer_rtx
< #endif
< || XEXP (XEXP (ad, 0), 0) == stack_pointer_rtx)
< && ! maybe_memory_address_p (mode, ad, &XEXP (XEXP (ad, 0), 1)))
---
> for (op_index = 0; op_index < 2; ++op_index)
4940,4948c5025,5026
< *loc = ad = gen_rtx_PLUS (GET_MODE (ad),
< plus_constant (XEXP (XEXP (ad, 0), 0),
< INTVAL (XEXP (ad, 1))),
< XEXP (XEXP (ad, 0), 1));
< find_reloads_address_part (XEXP (ad, 0), &XEXP (ad, 0),
< MODE_BASE_REG_CLASS (mode),
< GET_MODE (ad), opnum, type, ind_levels);
< find_reloads_address_1 (mode, XEXP (ad, 1), 1, &XEXP (ad, 1), opnum,
< type, 0, insn);
---
> rtx operand, addend;
> enum rtx_code inner_code;
4950,4951c5028,5029
< return 0;
< }
---
> if (GET_CODE (ad) != PLUS)
> continue;
4953,4958c5031,5045
< else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT
< && GET_CODE (XEXP (ad, 0)) == PLUS
< && GET_CODE (XEXP (XEXP (ad, 0), 1)) == REG
< && REGNO (XEXP (XEXP (ad, 0), 1)) < FIRST_PSEUDO_REGISTER
< && (REG_MODE_OK_FOR_BASE_P (XEXP (XEXP (ad, 0), 1), mode)
< || XEXP (XEXP (ad, 0), 1) == frame_pointer_rtx
---
> inner_code = GET_CODE (XEXP (ad, 0));
> if (!(GET_CODE (ad) == PLUS
> && GET_CODE (XEXP (ad, 1)) == CONST_INT
> && (inner_code == PLUS || inner_code == LO_SUM)))
> continue;
>
> operand = XEXP (XEXP (ad, 0), op_index);
> if (!REG_P (operand) || REGNO (operand) >= FIRST_PSEUDO_REGISTER)
> continue;
>
> addend = XEXP (XEXP (ad, 0), 1 - op_index);
>
> if ((regno_ok_for_base_p (REGNO (operand), mode, inner_code,
> GET_CODE (addend))
> || operand == frame_pointer_rtx
4960c5047
< || XEXP (XEXP (ad, 0), 1) == hard_frame_pointer_rtx
---
> || operand == hard_frame_pointer_rtx
4963c5050
< || XEXP (XEXP (ad, 0), 1) == arg_pointer_rtx
---
> || operand == arg_pointer_rtx
4965,4976c5052,5057
< || XEXP (XEXP (ad, 0), 1) == stack_pointer_rtx)
< && ! maybe_memory_address_p (mode, ad, &XEXP (XEXP (ad, 0), 0)))
< {
< *loc = ad = gen_rtx_PLUS (GET_MODE (ad),
< XEXP (XEXP (ad, 0), 0),
< plus_constant (XEXP (XEXP (ad, 0), 1),
< INTVAL (XEXP (ad, 1))));
< find_reloads_address_part (XEXP (ad, 1), &XEXP (ad, 1),
< MODE_BASE_REG_CLASS (mode),
< GET_MODE (ad), opnum, type, ind_levels);
< find_reloads_address_1 (mode, XEXP (ad, 0), 1, &XEXP (ad, 0), opnum,
< type, 0, insn);
---
> || operand == stack_pointer_rtx)
> && ! maybe_memory_address_p (mode, ad,
> &XEXP (XEXP (ad, 0), 1 - op_index)))
> {
> rtx offset_reg;
> enum reg_class cls;
4978c5059,5083
< return 0;
---
> offset_reg = plus_constant (operand, INTVAL (XEXP (ad, 1)));
>
> /* Form the adjusted address. */
> if (GET_CODE (XEXP (ad, 0)) == PLUS)
> ad = gen_rtx_PLUS (GET_MODE (ad),
> op_index == 0 ? offset_reg : addend,
> op_index == 0 ? addend : offset_reg);
> else
> ad = gen_rtx_LO_SUM (GET_MODE (ad),
> op_index == 0 ? offset_reg : addend,
> op_index == 0 ? addend : offset_reg);
> *loc = ad;
>
> cls = base_reg_class (mode, MEM, GET_CODE (addend));
> find_reloads_address_part (XEXP (ad, op_index),
> &XEXP (ad, op_index), cls,
> GET_MODE (ad), opnum, type, ind_levels);
> find_reloads_address_1 (mode,
> XEXP (ad, 1 - op_index), 1, GET_CODE (ad),
> GET_CODE (XEXP (ad, op_index)),
> &XEXP (ad, 1 - op_index), opnum,
> type, 0, insn);
>
> return 0;
> }
5019c5124
< find_reloads_address_part (ad, loc, MODE_BASE_REG_CLASS (mode),
---
> find_reloads_address_part (ad, loc, base_reg_class (mode, MEM, SCRATCH),
5024,5025c5129,5130
< return find_reloads_address_1 (mode, ad, 0, loc, opnum, type, ind_levels,
< insn);
---
> return find_reloads_address_1 (mode, ad, 0, MEM, SCRATCH, loc, opnum, type,
> ind_levels, insn);
5170c5275
< if (GET_CODE (op0) == REG
---
> if (REG_P (op0)
5175c5280
< else if (GET_CODE (op1) == REG
---
> else if (REG_P (op1)
5237c5342,5346
<
---
> OUTER_CODE is the code of the enclosing RTX, typically a MEM, a PLUS,
> or an autoinc code.
> If CONTEXT == 0 and OUTER_CODE is a PLUS or LO_SUM, then INDEX_CODE
> is the code of the index part of the address. Otherwise, pass SCRATCH
> for this argument.
5252c5361,5363
< could have addressing modes that this does not handle right. */
---
> could have addressing modes that this does not handle right.
> If you add push_reload calls here, you need to make sure gen_reload
> handles those cases gracefully. */
5255a5367
> enum rtx_code outer_code, enum rtx_code index_code,
5258a5371,5376
> #define REG_OK_FOR_CONTEXT(CONTEXT, REGNO, MODE, OUTER, INDEX) \
> ((CONTEXT) == 0 \
> ? regno_ok_for_base_p (REGNO, MODE, OUTER, INDEX) \
> : REGNO_OK_FOR_INDEX_P (REGNO))
>
> enum reg_class context_reg_class;
5260a5379,5383
> if (context == 1)
> context_reg_class = INDEX_REG_CLASS;
> else
> context_reg_class = base_reg_class (mode, outer_code, index_code);
>
5300c5423
< register remateralization for expression like &localvar*4. Reload it.
---
> register rematerialization for expression like &localvar*4. Reload it.
5303c5426
< if (context)
---
> if (context == 1)
5308c5431
< (context ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (mode)),
---
> context_reg_class,
5316,5319c5439,5444
< find_reloads_address_1 (mode, orig_op0, 1, &XEXP (x, 0), opnum,
< type, ind_levels, insn);
< find_reloads_address_1 (mode, orig_op1, 0, &XEXP (x, 1), opnum,
< type, ind_levels, insn);
---
> find_reloads_address_1 (mode, orig_op0, 1, PLUS, SCRATCH,
> &XEXP (x, 0), opnum, type, ind_levels,
> insn);
> find_reloads_address_1 (mode, orig_op1, 0, PLUS, code0,
> &XEXP (x, 1), opnum, type, ind_levels,
> insn);
5325,5328c5450,5455
< find_reloads_address_1 (mode, orig_op0, 0, &XEXP (x, 0), opnum,
< type, ind_levels, insn);
< find_reloads_address_1 (mode, orig_op1, 1, &XEXP (x, 1), opnum,
< type, ind_levels, insn);
---
> find_reloads_address_1 (mode, orig_op0, 0, PLUS, code1,
> &XEXP (x, 0), opnum, type, ind_levels,
> insn);
> find_reloads_address_1 (mode, orig_op1, 1, PLUS, SCRATCH,
> &XEXP (x, 1), opnum, type, ind_levels,
> insn);
5333,5334c5460,5462
< find_reloads_address_1 (mode, orig_op1, 0, &XEXP (x, 1), opnum,
< type, ind_levels, insn);
---
> find_reloads_address_1 (mode, orig_op1, 0, PLUS, code0,
> &XEXP (x, 1), opnum, type, ind_levels,
> insn);
5338,5339c5466,5468
< find_reloads_address_1 (mode, orig_op0, 0, &XEXP (x, 0), opnum,
< type, ind_levels, insn);
---
> find_reloads_address_1 (mode, orig_op0, 0, PLUS, code1,
> &XEXP (x, 0), opnum, type, ind_levels,
> insn);
5343,5344c5472,5473
< if (REG_OK_FOR_INDEX_P (op0)
< && REG_MODE_OK_FOR_BASE_P (op1, mode))
---
> if (REGNO_OK_FOR_INDEX_P (REGNO (op0))
> && regno_ok_for_base_p (REGNO (op1), mode, PLUS, REG))
5346,5347c5475,5476
< else if (REG_OK_FOR_INDEX_P (op1)
< && REG_MODE_OK_FOR_BASE_P (op0, mode))
---
> else if (REGNO_OK_FOR_INDEX_P (REGNO (op1))
> && regno_ok_for_base_p (REGNO (op0), mode, PLUS, REG))
5349,5360c5478,5493
< else if (REG_MODE_OK_FOR_BASE_P (op1, mode))
< find_reloads_address_1 (mode, orig_op0, 1, &XEXP (x, 0), opnum,
< type, ind_levels, insn);
< else if (REG_MODE_OK_FOR_BASE_P (op0, mode))
< find_reloads_address_1 (mode, orig_op1, 1, &XEXP (x, 1), opnum,
< type, ind_levels, insn);
< else if (REG_OK_FOR_INDEX_P (op1))
< find_reloads_address_1 (mode, orig_op0, 0, &XEXP (x, 0), opnum,
< type, ind_levels, insn);
< else if (REG_OK_FOR_INDEX_P (op0))
< find_reloads_address_1 (mode, orig_op1, 0, &XEXP (x, 1), opnum,
< type, ind_levels, insn);
---
> else if (regno_ok_for_base_p (REGNO (op1), mode, PLUS, REG))
> find_reloads_address_1 (mode, orig_op0, 1, PLUS, SCRATCH,
> &XEXP (x, 0), opnum, type, ind_levels,
> insn);
> else if (regno_ok_for_base_p (REGNO (op0), mode, PLUS, REG))
> find_reloads_address_1 (mode, orig_op1, 1, PLUS, SCRATCH,
> &XEXP (x, 1), opnum, type, ind_levels,
> insn);
> else if (REGNO_OK_FOR_INDEX_P (REGNO (op1)))
> find_reloads_address_1 (mode, orig_op0, 0, PLUS, REG,
> &XEXP (x, 0), opnum, type, ind_levels,
> insn);
> else if (REGNO_OK_FOR_INDEX_P (REGNO (op0)))
> find_reloads_address_1 (mode, orig_op1, 0, PLUS, REG,
> &XEXP (x, 1), opnum, type, ind_levels,
> insn);
5363,5366c5496,5501
< find_reloads_address_1 (mode, orig_op0, 1, &XEXP (x, 0), opnum,
< type, ind_levels, insn);
< find_reloads_address_1 (mode, orig_op1, 0, &XEXP (x, 1), opnum,
< type, ind_levels, insn);
---
> find_reloads_address_1 (mode, orig_op0, 1, PLUS, SCRATCH,
> &XEXP (x, 0), opnum, type, ind_levels,
> insn);
> find_reloads_address_1 (mode, orig_op1, 0, PLUS, REG,
> &XEXP (x, 1), opnum, type, ind_levels,
> insn);
5372,5375c5507,5512
< find_reloads_address_1 (mode, orig_op0, 1, &XEXP (x, 0), opnum,
< type, ind_levels, insn);
< find_reloads_address_1 (mode, orig_op1, 0, &XEXP (x, 1), opnum,
< type, ind_levels, insn);
---
> find_reloads_address_1 (mode, orig_op0, 1, PLUS, SCRATCH,
> &XEXP (x, 0), opnum, type, ind_levels,
> insn);
> find_reloads_address_1 (mode, orig_op1, 0, PLUS, REG,
> &XEXP (x, 1), opnum, type, ind_levels,
> insn);
5380,5383c5517,5522
< find_reloads_address_1 (mode, orig_op1, 1, &XEXP (x, 1), opnum,
< type, ind_levels, insn);
< find_reloads_address_1 (mode, orig_op0, 0, &XEXP (x, 0), opnum,
< type, ind_levels, insn);
---
> find_reloads_address_1 (mode, orig_op1, 1, PLUS, SCRATCH,
> &XEXP (x, 1), opnum, type, ind_levels,
> insn);
> find_reloads_address_1 (mode, orig_op0, 0, PLUS, REG,
> &XEXP (x, 0), opnum, type, ind_levels,
> insn);
5393a5533,5535
> enum rtx_code index_code;
> int regno;
> int reloadnum;
5402,5403c5544
< if (op0 != XEXP (op1, 0))
< abort ();
---
> gcc_assert (op0 == XEXP (op1, 0));
5408c5549,5555
< register with its equivalent constant where applicable. */
---
> register with its equivalent constant where applicable.
>
> If we later decide to reload the whole PRE_MODIFY or
> POST_MODIFY, inc_for_reload might clobber the reload register
> before reading the index. The index register might therefore
> need to live longer than a TYPE reload normally would, so be
> conservative and class it as RELOAD_OTHER. */
5411,5412c5558,5560
< find_reloads_address_1 (mode, XEXP (op1, 1), 1, &XEXP (op1, 1),
< opnum, type, ind_levels, insn);
---
> find_reloads_address_1 (mode, XEXP (op1, 1), 1, code, SCRATCH,
> &XEXP (op1, 1), opnum, RELOAD_OTHER,
> ind_levels, insn);
5414,5417c5562
< if (REG_P (XEXP (op1, 0)))
< {
< int regno = REGNO (XEXP (op1, 0));
< int reloadnum;
---
> gcc_assert (REG_P (XEXP (op1, 0)));
5419,5422c5564,5565
< /* A register that is incremented cannot be constant! */
< if (regno >= FIRST_PSEUDO_REGISTER
< && reg_equiv_constant[regno] != 0)
< abort ();
---
> regno = REGNO (XEXP (op1, 0));
> index_code = GET_CODE (XEXP (op1, 1));
5424,5430c5567,5569
< /* Handle a register that is equivalent to a memory location
< which cannot be addressed directly. */
< if (reg_equiv_memory_loc[regno] != 0
< && (reg_equiv_address[regno] != 0
< || num_not_at_initial_offset))
< {
< rtx tem = make_memloc (XEXP (x, 0), regno);
---
> /* A register that is incremented cannot be constant! */
> gcc_assert (regno < FIRST_PSEUDO_REGISTER
> || reg_equiv_constant[regno] == 0);
5432,5442c5571,5577
< if (reg_equiv_address[regno]
< || ! rtx_equal_p (tem, reg_equiv_mem[regno]))
< {
< /* First reload the memory location's address.
< We can't use ADDR_TYPE (type) here, because we need to
< write back the value after reading it, hence we actually
< need two registers. */
< find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0),
< &XEXP (tem, 0), opnum,
< RELOAD_OTHER,
< ind_levels, insn);
---
> /* Handle a register that is equivalent to a memory location
> which cannot be addressed directly. */
> if (reg_equiv_memory_loc[regno] != 0
> && (reg_equiv_address[regno] != 0
> || num_not_at_initial_offset))
> {
> rtx tem = make_memloc (XEXP (x, 0), regno);
5444,5450c5579,5582
< /* Then reload the memory location into a base
< register. */
< reloadnum = push_reload (tem, tem, &XEXP (x, 0),
< &XEXP (op1, 0),
< MODE_BASE_REG_CLASS (mode),
< GET_MODE (x), GET_MODE (x), 0,
< 0, opnum, RELOAD_OTHER);
---
> if (reg_equiv_address[regno]
> || ! rtx_equal_p (tem, reg_equiv_mem[regno]))
> {
> rtx orig = tem;
5452,5455c5584,5591
< update_auto_inc_notes (this_insn, regno, reloadnum);
< return 0;
< }
< }
---
> /* First reload the memory location's address.
> We can't use ADDR_TYPE (type) here, because we need to
> write back the value after reading it, hence we actually
> need two registers. */
> find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0),
> &XEXP (tem, 0), opnum,
> RELOAD_OTHER,
> ind_levels, insn);
5457,5458c5593,5594
< if (reg_renumber[regno] >= 0)
< regno = reg_renumber[regno];
---
> if (tem != orig)
> push_reg_equiv_alt_mem (regno, tem);
5460,5467c5596,5603
< /* We require a base register here... */
< if (!REGNO_MODE_OK_FOR_BASE_P (regno, GET_MODE (x)))
< {
< reloadnum = push_reload (XEXP (op1, 0), XEXP (x, 0),
< &XEXP (op1, 0), &XEXP (x, 0),
< MODE_BASE_REG_CLASS (mode),
< GET_MODE (x), GET_MODE (x), 0, 0,
< opnum, RELOAD_OTHER);
---
> /* Then reload the memory location into a base
> register. */
> reloadnum = push_reload (tem, tem, &XEXP (x, 0),
> &XEXP (op1, 0),
> base_reg_class (mode, code,
> index_code),
> GET_MODE (x), GET_MODE (x), 0,
> 0, opnum, RELOAD_OTHER);
5473,5474c5609,5624
< else
< abort ();
---
>
> if (reg_renumber[regno] >= 0)
> regno = reg_renumber[regno];
>
> /* We require a base register here... */
> if (!regno_ok_for_base_p (regno, GET_MODE (x), code, index_code))
> {
> reloadnum = push_reload (XEXP (op1, 0), XEXP (x, 0),
> &XEXP (op1, 0), &XEXP (x, 0),
> base_reg_class (mode, code, index_code),
> GET_MODE (x), GET_MODE (x), 0, 0,
> opnum, RELOAD_OTHER);
>
> update_auto_inc_notes (this_insn, regno, reloadnum);
> return 0;
> }
5482c5632
< if (GET_CODE (XEXP (x, 0)) == REG)
---
> if (REG_P (XEXP (x, 0)))
5489,5491c5639,5640
< if (regno >= FIRST_PSEUDO_REGISTER
< && reg_equiv_constant[regno] != 0)
< abort ();
---
> gcc_assert (regno < FIRST_PSEUDO_REGISTER
> || reg_equiv_constant[regno] == 0);
5501a5651,5652
> rtx orig = tem;
>
5508a5660,5661
> if (tem != orig)
> push_reg_equiv_alt_mem (regno, tem);
5528,5530c5681,5683
< if ((regno >= FIRST_PSEUDO_REGISTER
< || !(context ? REGNO_OK_FOR_INDEX_P (regno)
< : REGNO_MODE_OK_FOR_BASE_P (regno, mode))))
---
> if (regno >= FIRST_PSEUDO_REGISTER
> || !REG_OK_FOR_CONTEXT (context, regno, mode, outer_code,
> index_code))
5542c5695
< rtx equiv = (GET_CODE (XEXP (x, 0)) == MEM
---
> rtx equiv = (MEM_P (XEXP (x, 0))
5546c5699
< if (insn && GET_CODE (insn) == INSN && equiv
---
> if (insn && NONJUMP_INSN_P (insn) && equiv
5566,5567c5719
< (context ? INDEX_REG_CLASS :
< MODE_BASE_REG_CLASS (mode)),
---
> context_reg_class,
5575,5576c5727
< (context ? INDEX_REG_CLASS :
< MODE_BASE_REG_CLASS (mode)),
---
> context_reg_class,
5591c5742
< else if (GET_CODE (XEXP (x, 0)) == MEM)
---
> else if (MEM_P (XEXP (x, 0)))
5616,5617c5767
< (context ? INDEX_REG_CLASS :
< MODE_BASE_REG_CLASS (mode)),
---
> context_reg_class,
5629a5780,5797
> case TRUNCATE:
> case SIGN_EXTEND:
> case ZERO_EXTEND:
> /* Look for parts to reload in the inner expression and reload them
> too, in addition to this operation. Reloading all inner parts in
> addition to this one shouldn't be necessary, but at this point,
> we don't know if we can possibly omit any part that *can* be
> reloaded. Targets that are better off reloading just either part
> (or perhaps even a different part of an outer expression), should
> define LEGITIMIZE_RELOAD_ADDRESS. */
> find_reloads_address_1 (GET_MODE (XEXP (x, 0)), XEXP (x, 0),
> context, code, SCRATCH, &XEXP (x, 0), opnum,
> type, ind_levels, insn);
> push_reload (x, NULL_RTX, loc, (rtx*) 0,
> context_reg_class,
> GET_MODE (x), VOIDmode, 0, 0, opnum, type);
> return 1;
>
5646c5814
< (context ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (mode)),
---
> context_reg_class,
5657,5658c5825
< (context ? INDEX_REG_CLASS :
< MODE_BASE_REG_CLASS (mode)),
---
> context_reg_class,
5668,5669c5835
< (context ? INDEX_REG_CLASS :
< MODE_BASE_REG_CLASS (mode)),
---
> context_reg_class,
5685a5852,5853
> if (x != tem)
> push_reg_equiv_alt_mem (regno, x);
5692,5694c5860,5862
< if ((regno >= FIRST_PSEUDO_REGISTER
< || !(context ? REGNO_OK_FOR_INDEX_P (regno)
< : REGNO_MODE_OK_FOR_BASE_P (regno, mode))))
---
> if (regno >= FIRST_PSEUDO_REGISTER
> || !REG_OK_FOR_CONTEXT (context, regno, mode, outer_code,
> index_code))
5697c5865
< (context ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (mode)),
---
> context_reg_class,
5709c5877
< (context ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (mode)),
---
> context_reg_class,
5717c5885
< if (GET_CODE (SUBREG_REG (x)) == REG)
---
> if (REG_P (SUBREG_REG (x)))
5726,5727c5894,5895
< if (! (context ? REGNO_OK_FOR_INDEX_P (regno)
< : REGNO_MODE_OK_FOR_BASE_P (regno, mode)))
---
> if (!REG_OK_FOR_CONTEXT (context, regno, mode, outer_code,
> index_code))
5730,5731c5898
< (context ? INDEX_REG_CLASS :
< MODE_BASE_REG_CLASS (mode)),
---
> context_reg_class,
5740,5741c5907
< enum reg_class class = (context ? INDEX_REG_CLASS
< : MODE_BASE_REG_CLASS (mode));
---
> enum reg_class class = context_reg_class;
5745c5911,5912
< x = find_reloads_subreg_address (x, 0, opnum, type,
---
> x = find_reloads_subreg_address (x, 0, opnum,
> ADDR_TYPE (type),
5766,5767c5933,5936
< find_reloads_address_1 (mode, XEXP (x, i), context, &XEXP (x, i),
< opnum, type, ind_levels, insn);
---
> /* Pass SCRATCH for INDEX_CODE, since CODE can never be a PLUS once
> we get here. */
> find_reloads_address_1 (mode, XEXP (x, i), context, code, SCRATCH,
> &XEXP (x, i), opnum, type, ind_levels, insn);
5770a5940
> #undef REG_OK_FOR_CONTEXT
5870a6041,6043
> rtx orig = tem;
> enum machine_mode orig_mode = GET_MODE (orig);
> int reloaded;
5885c6058
< if (outer_size > inner_size && STRICT_ALIGNMENT)
---
> if (outer_size > inner_size)
5897c6070
< if (GET_CODE (base) != REG
---
> if (!REG_P (base)
5903,5905c6076,6081
< find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0),
< &XEXP (tem, 0), opnum, ADDR_TYPE (type),
< ind_levels, insn);
---
> reloaded = find_reloads_address (GET_MODE (tem), &tem,
> XEXP (tem, 0), &XEXP (tem, 0),
> opnum, type, ind_levels, insn);
> /* ??? Do we need to handle nonzero offsets somehow? */
> if (!offset && tem != orig)
> push_reg_equiv_alt_mem (regno, tem);
5906a6083,6101
> /* For some processors an address may be valid in the
> original mode but not in a smaller mode. For
> example, ARM accepts a scaled index register in
> SImode but not in HImode. find_reloads_address
> assumes that we pass it a valid address, and doesn't
> force a reload. This will probably be fine if
> find_reloads_address finds some reloads. But if it
> doesn't find any, then we may have just converted a
> valid address into an invalid one. Check for that
> here. */
> if (reloaded != 1
> && strict_memory_address_p (orig_mode, XEXP (tem, 0))
> && !strict_memory_address_p (GET_MODE (tem),
> XEXP (tem, 0)))
> push_reload (XEXP (tem, 0), NULL_RTX, &XEXP (tem, 0), (rtx*) 0,
> base_reg_class (GET_MODE (tem), MEM, SCRATCH),
> GET_MODE (XEXP (tem, 0)), VOIDmode, 0, 0,
> opnum, type);
>
5955,5958c6150,6152
< if (ARRAY[check_regno] \
< && loc_mentioned_in_p (r->where, \
< ARRAY[check_regno])) \
< abort ()
---
> gcc_assert (!ARRAY[check_regno] \
> || !loc_mentioned_in_p (r->where, \
> ARRAY[check_regno]))
5972,5975c6166,6172
< && GET_CODE (insn) == JUMP_INSN)
< REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL,
< XEXP (*r->where, 0),
< REG_NOTES (insn));
---
> && JUMP_P (insn))
> {
> REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL,
> XEXP (*r->where, 0),
> REG_NOTES (insn));
> JUMP_LABEL (insn) = XEXP (*r->where, 0);
> }
6013,6014c6210,6211
< else if (! rld[r->what].optional)
< abort ();
---
> else
> gcc_assert (rld[r->what].optional);
6026,6027c6223
< if (GET_CODE (x) == SUBREG)
< abort ();
---
> gcc_assert (GET_CODE (x) != SUBREG);
6119c6315
< if (GET_CODE (reloadreg) == REG)
---
> if (REG_P (reloadreg))
6167c6363
< int
---
> static int
6196,6199c6392,6393
< if (reg_equiv_constant[r])
< return 0;
<
< abort ();
---
> gcc_assert (reg_equiv_constant[r] || reg_equiv_invariant[r]);
> return 0;
6204c6398
< ? HARD_REGNO_NREGS (r, GET_MODE (x))
---
> ? hard_regno_nregs[r][GET_MODE (x)]
6210c6404
< if (GET_CODE (SUBREG_REG (x)) == REG
---
> if (REG_P (SUBREG_REG (x))
6216c6410
< ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
---
> ? hard_regno_nregs[inner_regno][GET_MODE (x)] : 1);
6230c6424
< && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG
---
> && REG_P (SUBREG_REG (SET_DEST (x)))
6237c6431
< || ((GET_CODE (SET_DEST (x)) != REG
---
> || ((!REG_P (SET_DEST (x))
6298c6492
< || GET_RTX_CLASS (GET_CODE (x)) == 'a')
---
> || GET_RTX_CLASS (GET_CODE (x)) == RTX_AUTOINC)
6303a6498,6499
> else if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
> return refers_to_mem_for_reload_p (in);
6313c6509
< else if (GET_CODE (x) == REG)
---
> else if (REG_P (x))
6324,6326c6520,6521
< else if (reg_equiv_constant[regno])
< return 0;
< abort ();
---
> gcc_assert (reg_equiv_constant[regno]);
> return 0;
6329c6524
< else if (GET_CODE (x) == MEM)
---
> else if (MEM_P (x))
6334c6529
< else if (GET_CODE (x) == PLUS)
---
> else
6335a6531,6532
> gcc_assert (GET_CODE (x) == PLUS);
>
6341c6538
< while (GET_CODE (in) == MEM)
---
> while (MEM_P (in))
6343c6540
< if (GET_CODE (in) == REG)
---
> if (REG_P (in))
6351,6352d6547
< else
< abort ();
6355c6550
< ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
---
> ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
6363c6558
< int
---
> static int
6369c6564
< if (GET_CODE (x) == MEM)
---
> if (MEM_P (x))
6372c6567
< if (GET_CODE (x) == REG)
---
> if (REG_P (x))
6379c6574
< && (GET_CODE (XEXP (x, i)) == MEM
---
> && (MEM_P (XEXP (x, i))
6432c6627
< else if (GET_CODE (goal) == REG)
---
> else if (REG_P (goal))
6434c6629
< else if (GET_CODE (goal) == MEM)
---
> else if (MEM_P (goal))
6439c6634
< if (flag_float_store && GET_MODE_CLASS (GET_MODE (goal)) == MODE_FLOAT)
---
> if (flag_float_store && SCALAR_FLOAT_MODE_P (GET_MODE (goal)))
6478c6673
< if (p == 0 || GET_CODE (p) == CODE_LABEL
---
> if (p == 0 || LABEL_P (p)
6482c6677
< if (GET_CODE (p) == INSN
---
> if (NONJUMP_INSN_P (p)
6491c6686
< That makes bad code. It may even abort: perhaps no reg was
---
> That makes bad code. It may even fail: perhaps no reg was
6528c6723
< || (GET_CODE (SET_DEST (pat)) == REG
---
> || (REG_P (SET_DEST (pat))
6530,6531c6725
< && (GET_MODE_CLASS (GET_MODE (XEXP (tem, 0)))
< == MODE_FLOAT)
---
> && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (tem, 0)))
6543c6737
< && GET_CODE (SET_DEST (pat)) == REG
---
> && REG_P (SET_DEST (pat))
6545,6546c6739
< && (GET_MODE_CLASS (GET_MODE (XEXP (tem, 0)))
< == MODE_FLOAT)
---
> && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (tem, 0)))
6566c6759
< for (i = HARD_REGNO_NREGS (valueno, mode) - 1; i >= 0; i--)
---
> for (i = hard_regno_nregs[valueno][mode] - 1; i >= 0; i--)
6608c6801
< + HARD_REGNO_NREGS (valueno, mode)),
---
> + hard_regno_nregs[valueno][mode]),
6613a6807,6812
> if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER)
> nregs = hard_regno_nregs[regno][mode];
> else
> nregs = 1;
> valuenregs = hard_regno_nregs[valueno][mode];
>
6615,6616c6814
< && regno + (int) HARD_REGNO_NREGS (regno, mode) > valueno
< && regno < valueno + (int) HARD_REGNO_NREGS (valueno, mode))
---
> && regno + nregs > valueno && regno < valueno + valuenregs)
6619,6621d6816
< nregs = HARD_REGNO_NREGS (regno, mode);
< valuenregs = HARD_REGNO_NREGS (valueno, mode);
<
6646,6647c6841,6842
< int nregs1 = HARD_REGNO_NREGS (regno1,
< GET_MODE (rld[i].reg_rtx));
---
> int nregs1 = hard_regno_nregs[regno1]
> [GET_MODE (rld[i].reg_rtx)];
6671c6866
< if (GET_CODE (p) == CALL_INSN)
---
> if (CALL_P (p))
6680c6875,6876
< if (call_used_regs[regno + i])
---
> if (call_used_regs[regno + i]
> || HARD_REGNO_CALL_PART_CLOBBERED (regno + i, mode))
6685c6881,6882
< if (call_used_regs[valueno + i])
---
> if (call_used_regs[valueno + i]
> || HARD_REGNO_CALL_PART_CLOBBERED (valueno + i, mode))
6687,6690d6883
< #ifdef NON_SAVING_SETJMP
< if (NON_SAVING_SETJMP && find_reg_note (p, REG_SETJMP, NULL))
< return 0;
< #endif
6713d6905
< || GET_CODE (dest) == SIGN_EXTRACT
6716c6908
< if (GET_CODE (dest) == REG)
---
> if (REG_P (dest))
6721c6913
< xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest));
---
> xnregs = hard_regno_nregs[xregno][GET_MODE (dest)];
6735c6927
< else if (goal_mem && GET_CODE (dest) == MEM
---
> else if (goal_mem && MEM_P (dest)
6738c6930
< else if (GET_CODE (dest) == MEM && regno >= FIRST_PSEUDO_REGISTER
---
> else if (MEM_P (dest) && regno >= FIRST_PSEUDO_REGISTER
6757d6948
< || GET_CODE (dest) == SIGN_EXTRACT
6760c6951
< if (GET_CODE (dest) == REG)
---
> if (REG_P (dest))
6765c6956
< xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest));
---
> xnregs = hard_regno_nregs[xregno][GET_MODE (dest)];
6781c6972
< else if (goal_mem && GET_CODE (dest) == MEM
---
> else if (goal_mem && MEM_P (dest)
6784c6975
< else if (GET_CODE (dest) == MEM && regno >= FIRST_PSEUDO_REGISTER
---
> else if (MEM_P (dest) && regno >= FIRST_PSEUDO_REGISTER
6794c6985
< if (GET_CODE (p) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (p))
---
> if (CALL_P (p) && CALL_INSN_FUNCTION_USAGE (p))
6806c6997
< if (GET_CODE (dest) == REG)
---
> if (REG_P (dest))
6810c7001
< = HARD_REGNO_NREGS (xregno, GET_MODE (dest));
---
> = hard_regno_nregs[xregno][GET_MODE (dest)];
6824c7015
< else if (goal_mem && GET_CODE (dest) == MEM
---
> else if (goal_mem && MEM_P (dest)
6844c7035
< && GET_CODE (XEXP (link, 0)) == REG)
---
> && REG_P (XEXP (link, 0)))
6917a7109,7138
> /* Return 1 if registers from REGNO to ENDREGNO are the subjects of a
> REG_INC note in insn INSN. REGNO must refer to a hard register. */
>
> #ifdef AUTO_INC_DEC
> static int
> reg_inc_found_and_valid_p (unsigned int regno, unsigned int endregno,
> rtx insn)
> {
> rtx link;
>
> gcc_assert (insn);
>
> if (! INSN_P (insn))
> return 0;
>
> for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
> if (REG_NOTE_KIND (link) == REG_INC)
> {
> unsigned int test = (int) REGNO (XEXP (link, 0));
> if (test >= regno && test < endregno)
> return 1;
> }
> return 0;
> }
> #else
>
> #define reg_inc_found_and_valid_p(regno,endregno,insn) 0
>
> #endif
>
6919c7140,7141
< If SETS is nonzero, also consider SETs. */
---
> If SETS is 1, also consider SETs. If SETS is 2, enable checking
> REG_INC. REGNO must refer to a hard register. */
6925,6926c7147
< unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
< unsigned int endregno = regno + nregs;
---
> unsigned int nregs, endregno;
6927a7149,7154
> /* regno must be a hard register. */
> gcc_assert (regno < FIRST_PSEUDO_REGISTER);
>
> nregs = hard_regno_nregs[regno][mode];
> endregno = regno + nregs;
>
6929,6930c7156,7157
< || (sets && GET_CODE (PATTERN (insn)) == SET))
< && GET_CODE (XEXP (PATTERN (insn), 0)) == REG)
---
> || (sets == 1 && GET_CODE (PATTERN (insn)) == SET))
> && REG_P (XEXP (PATTERN (insn), 0)))
6936a7164,7166
> if (sets == 2 && reg_inc_found_and_valid_p (regno, endregno, insn))
> return 1;
>
6945,6946c7175,7176
< || (sets && GET_CODE (PATTERN (insn)) == SET))
< && GET_CODE (XEXP (elt, 0)) == REG)
---
> || (sets == 1 && GET_CODE (PATTERN (insn)) == SET))
> && REG_P (XEXP (elt, 0)))
6952a7183,7185
> if (sets == 2
> && reg_inc_found_and_valid_p (regno, endregno, elt))
> return 1;
6971,6972c7204,7205
< regno += HARD_REGNO_NREGS (regno, GET_MODE (reloadreg))
< - HARD_REGNO_NREGS (regno, mode);
---
> regno += (int) hard_regno_nregs[regno][GET_MODE (reloadreg)]
> - (int) hard_regno_nregs[regno][mode];
6992,6993d7224
< static const char * const reg_class_names[] = REG_CLASS_NAMES;
<