1/* Subroutines used by or related to instruction recognition. 2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998 3 1999, 2000, 2001, 2002 Free Software Foundation, Inc. 4 5This file is part of GCC. 6 7GCC is free software; you can redistribute it and/or modify it under 8the terms of the GNU General Public License as published by the Free 9Software Foundation; either version 2, or (at your option) any later 10version. 11 12GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13WARRANTY; without even the implied warranty of MERCHANTABILITY or 14FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15for more details. 16 17You should have received a copy of the GNU General Public License 18along with GCC; see the file COPYING. If not, write to the Free 19Software Foundation, 59 Temple Place - Suite 330, Boston, MA 2002111-1307, USA. */ 21 22 23#include "config.h" 24#include "system.h" 25#include "rtl.h" 26#include "tm_p.h" 27#include "insn-config.h" 28#include "insn-attr.h" 29#include "hard-reg-set.h" 30#include "recog.h" 31#include "regs.h" 32#include "expr.h" 33#include "function.h" 34#include "flags.h" 35#include "real.h" 36#include "toplev.h" 37#include "basic-block.h" 38#include "output.h" 39#include "reload.h" 40 41#ifndef STACK_PUSH_CODE 42#ifdef STACK_GROWS_DOWNWARD 43#define STACK_PUSH_CODE PRE_DEC 44#else 45#define STACK_PUSH_CODE PRE_INC 46#endif 47#endif 48 49#ifndef STACK_POP_CODE 50#ifdef STACK_GROWS_DOWNWARD 51#define STACK_POP_CODE POST_INC 52#else 53#define STACK_POP_CODE POST_DEC 54#endif 55#endif 56 57static void validate_replace_rtx_1 PARAMS ((rtx *, rtx, rtx, rtx)); 58static rtx *find_single_use_1 PARAMS ((rtx, rtx *)); 59static void validate_replace_src_1 PARAMS ((rtx *, void *)); 60static rtx split_insn PARAMS ((rtx)); 61 62/* Nonzero means allow operands to be volatile. 63 This should be 0 if you are generating rtl, such as if you are calling 64 the functions in optabs.c and expmed.c (most of the time). 65 This should be 1 if all valid insns need to be recognized, 66 such as in regclass.c and final.c and reload.c. 67 68 init_recog and init_recog_no_volatile are responsible for setting this. */ 69 70int volatile_ok; 71 72struct recog_data recog_data; 73 74/* Contains a vector of operand_alternative structures for every operand. 75 Set up by preprocess_constraints. */ 76struct operand_alternative recog_op_alt[MAX_RECOG_OPERANDS][MAX_RECOG_ALTERNATIVES]; 77 78/* On return from `constrain_operands', indicate which alternative 79 was satisfied. */ 80 81int which_alternative; 82 83/* Nonzero after end of reload pass. 84 Set to 1 or 0 by toplev.c. 85 Controls the significance of (SUBREG (MEM)). */ 86 87int reload_completed; 88 89/* Initialize data used by the function `recog'. 90 This must be called once in the compilation of a function 91 before any insn recognition may be done in the function. */ 92 93void 94init_recog_no_volatile () 95{ 96 volatile_ok = 0; 97} 98 99void 100init_recog () 101{ 102 volatile_ok = 1; 103} 104 105/* Try recognizing the instruction INSN, 106 and return the code number that results. 107 Remember the code so that repeated calls do not 108 need to spend the time for actual rerecognition. 109 110 This function is the normal interface to instruction recognition. 111 The automatically-generated function `recog' is normally called 112 through this one. (The only exception is in combine.c.) */ 113 114int 115recog_memoized_1 (insn) 116 rtx insn; 117{ 118 if (INSN_CODE (insn) < 0) 119 INSN_CODE (insn) = recog (PATTERN (insn), insn, 0); 120 return INSN_CODE (insn); 121} 122 123/* Check that X is an insn-body for an `asm' with operands 124 and that the operands mentioned in it are legitimate. */ 125 126int 127check_asm_operands (x) 128 rtx x; 129{ 130 int noperands; 131 rtx *operands; 132 const char **constraints; 133 int i; 134 135 /* Post-reload, be more strict with things. */ 136 if (reload_completed) 137 { 138 /* ??? Doh! We've not got the wrapping insn. Cook one up. */ 139 extract_insn (make_insn_raw (x)); 140 constrain_operands (1); 141 return which_alternative >= 0; 142 } 143 144 noperands = asm_noperands (x); 145 if (noperands < 0) 146 return 0; 147 if (noperands == 0) 148 return 1; 149 150 operands = (rtx *) alloca (noperands * sizeof (rtx)); 151 constraints = (const char **) alloca (noperands * sizeof (char *)); 152 153 decode_asm_operands (x, operands, NULL, constraints, NULL); 154 155 for (i = 0; i < noperands; i++) 156 { 157 const char *c = constraints[i]; 158 if (c[0] == '%') 159 c++; 160 if (ISDIGIT ((unsigned char) c[0]) && c[1] == '\0') 161 c = constraints[c[0] - '0']; 162 163 if (! asm_operand_ok (operands[i], c)) 164 return 0; 165 } 166 167 return 1; 168} 169 170/* Static data for the next two routines. */ 171 172typedef struct change_t 173{ 174 rtx object; 175 int old_code; 176 rtx *loc; 177 rtx old; 178} change_t; 179 180static change_t *changes; 181static int changes_allocated; 182 183static int num_changes = 0; 184 185/* Validate a proposed change to OBJECT. LOC is the location in the rtl 186 at which NEW will be placed. If OBJECT is zero, no validation is done, 187 the change is simply made. 188 189 Two types of objects are supported: If OBJECT is a MEM, memory_address_p 190 will be called with the address and mode as parameters. If OBJECT is 191 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with 192 the change in place. 193 194 IN_GROUP is non-zero if this is part of a group of changes that must be 195 performed as a group. In that case, the changes will be stored. The 196 function `apply_change_group' will validate and apply the changes. 197 198 If IN_GROUP is zero, this is a single change. Try to recognize the insn 199 or validate the memory reference with the change applied. If the result 200 is not valid for the machine, suppress the change and return zero. 201 Otherwise, perform the change and return 1. */ 202 203int 204validate_change (object, loc, new, in_group) 205 rtx object; 206 rtx *loc; 207 rtx new; 208 int in_group; 209{ 210 rtx old = *loc; 211 212 if (old == new || rtx_equal_p (old, new)) 213 return 1; 214 215 if (in_group == 0 && num_changes != 0) 216 abort (); 217 218 *loc = new; 219 220 /* Save the information describing this change. */ 221 if (num_changes >= changes_allocated) 222 { 223 if (changes_allocated == 0) 224 /* This value allows for repeated substitutions inside complex 225 indexed addresses, or changes in up to 5 insns. */ 226 changes_allocated = MAX_RECOG_OPERANDS * 5; 227 else 228 changes_allocated *= 2; 229 230 changes = 231 (change_t*) xrealloc (changes, 232 sizeof (change_t) * changes_allocated); 233 } 234 235 changes[num_changes].object = object; 236 changes[num_changes].loc = loc; 237 changes[num_changes].old = old; 238 239 if (object && GET_CODE (object) != MEM) 240 { 241 /* Set INSN_CODE to force rerecognition of insn. Save old code in 242 case invalid. */ 243 changes[num_changes].old_code = INSN_CODE (object); 244 INSN_CODE (object) = -1; 245 } 246 247 num_changes++; 248 249 /* If we are making a group of changes, return 1. Otherwise, validate the 250 change group we made. */ 251 252 if (in_group) 253 return 1; 254 else 255 return apply_change_group (); 256} 257 258/* This subroutine of apply_change_group verifies whether the changes to INSN 259 were valid; i.e. whether INSN can still be recognized. */ 260 261int 262insn_invalid_p (insn) 263 rtx insn; 264{ 265 rtx pat = PATTERN (insn); 266 int num_clobbers = 0; 267 /* If we are before reload and the pattern is a SET, see if we can add 268 clobbers. */ 269 int icode = recog (pat, insn, 270 (GET_CODE (pat) == SET 271 && ! reload_completed && ! reload_in_progress) 272 ? &num_clobbers : 0); 273 int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0; 274 275 276 /* If this is an asm and the operand aren't legal, then fail. Likewise if 277 this is not an asm and the insn wasn't recognized. */ 278 if ((is_asm && ! check_asm_operands (PATTERN (insn))) 279 || (!is_asm && icode < 0)) 280 return 1; 281 282 /* If we have to add CLOBBERs, fail if we have to add ones that reference 283 hard registers since our callers can't know if they are live or not. 284 Otherwise, add them. */ 285 if (num_clobbers > 0) 286 { 287 rtx newpat; 288 289 if (added_clobbers_hard_reg_p (icode)) 290 return 1; 291 292 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_clobbers + 1)); 293 XVECEXP (newpat, 0, 0) = pat; 294 add_clobbers (newpat, icode); 295 PATTERN (insn) = pat = newpat; 296 } 297 298 /* After reload, verify that all constraints are satisfied. */ 299 if (reload_completed) 300 { 301 extract_insn (insn); 302 303 if (! constrain_operands (1)) 304 return 1; 305 } 306 307 INSN_CODE (insn) = icode; 308 return 0; 309} 310 311/* Apply a group of changes previously issued with `validate_change'. 312 Return 1 if all changes are valid, zero otherwise. */ 313 314int 315apply_change_group () 316{ 317 int i; 318 rtx last_validated = NULL_RTX; 319 320 /* The changes have been applied and all INSN_CODEs have been reset to force 321 rerecognition. 322 323 The changes are valid if we aren't given an object, or if we are 324 given a MEM and it still is a valid address, or if this is in insn 325 and it is recognized. In the latter case, if reload has completed, 326 we also require that the operands meet the constraints for 327 the insn. */ 328 329 for (i = 0; i < num_changes; i++) 330 { 331 rtx object = changes[i].object; 332 333 /* if there is no object to test or if it is the same as the one we 334 already tested, ignore it. */ 335 if (object == 0 || object == last_validated) 336 continue; 337 338 if (GET_CODE (object) == MEM) 339 { 340 if (! memory_address_p (GET_MODE (object), XEXP (object, 0))) 341 break; 342 } 343 else if (insn_invalid_p (object)) 344 { 345 rtx pat = PATTERN (object); 346 347 /* Perhaps we couldn't recognize the insn because there were 348 extra CLOBBERs at the end. If so, try to re-recognize 349 without the last CLOBBER (later iterations will cause each of 350 them to be eliminated, in turn). But don't do this if we 351 have an ASM_OPERAND. */ 352 if (GET_CODE (pat) == PARALLEL 353 && GET_CODE (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1)) == CLOBBER 354 && asm_noperands (PATTERN (object)) < 0) 355 { 356 rtx newpat; 357 358 if (XVECLEN (pat, 0) == 2) 359 newpat = XVECEXP (pat, 0, 0); 360 else 361 { 362 int j; 363 364 newpat 365 = gen_rtx_PARALLEL (VOIDmode, 366 rtvec_alloc (XVECLEN (pat, 0) - 1)); 367 for (j = 0; j < XVECLEN (newpat, 0); j++) 368 XVECEXP (newpat, 0, j) = XVECEXP (pat, 0, j); 369 } 370 371 /* Add a new change to this group to replace the pattern 372 with this new pattern. Then consider this change 373 as having succeeded. The change we added will 374 cause the entire call to fail if things remain invalid. 375 376 Note that this can lose if a later change than the one 377 we are processing specified &XVECEXP (PATTERN (object), 0, X) 378 but this shouldn't occur. */ 379 380 validate_change (object, &PATTERN (object), newpat, 1); 381 continue; 382 } 383 else if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER) 384 /* If this insn is a CLOBBER or USE, it is always valid, but is 385 never recognized. */ 386 continue; 387 else 388 break; 389 } 390 last_validated = object; 391 } 392 393 if (i == num_changes) 394 { 395 num_changes = 0; 396 return 1; 397 } 398 else 399 { 400 cancel_changes (0); 401 return 0; 402 } 403} 404 405/* Return the number of changes so far in the current group. */ 406 407int 408num_validated_changes () 409{ 410 return num_changes; 411} 412 413/* Retract the changes numbered NUM and up. */ 414 415void 416cancel_changes (num) 417 int num; 418{ 419 int i; 420 421 /* Back out all the changes. Do this in the opposite order in which 422 they were made. */ 423 for (i = num_changes - 1; i >= num; i--) 424 { 425 *changes[i].loc = changes[i].old; 426 if (changes[i].object && GET_CODE (changes[i].object) != MEM) 427 INSN_CODE (changes[i].object) = changes[i].old_code; 428 } 429 num_changes = num; 430} 431 432/* Replace every occurrence of FROM in X with TO. Mark each change with 433 validate_change passing OBJECT. */ 434 435static void 436validate_replace_rtx_1 (loc, from, to, object) 437 rtx *loc; 438 rtx from, to, object; 439{ 440 int i, j; 441 const char *fmt; 442 rtx x = *loc; 443 enum rtx_code code; 444 enum machine_mode op0_mode = VOIDmode; 445 int prev_changes = num_changes; 446 rtx new; 447 448 if (!x) 449 return; 450 451 code = GET_CODE (x); 452 fmt = GET_RTX_FORMAT (code); 453 if (fmt[0] == 'e') 454 op0_mode = GET_MODE (XEXP (x, 0)); 455 456 /* X matches FROM if it is the same rtx or they are both referring to the 457 same register in the same mode. Avoid calling rtx_equal_p unless the 458 operands look similar. */ 459 460 if (x == from 461 || (GET_CODE (x) == REG && GET_CODE (from) == REG 462 && GET_MODE (x) == GET_MODE (from) 463 && REGNO (x) == REGNO (from)) 464 || (GET_CODE (x) == GET_CODE (from) && GET_MODE (x) == GET_MODE (from) 465 && rtx_equal_p (x, from))) 466 { 467 validate_change (object, loc, to, 1); 468 return; 469 } 470 471 /* Call ourself recursively to perform the replacements. */ 472 473 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 474 { 475 if (fmt[i] == 'e') 476 validate_replace_rtx_1 (&XEXP (x, i), from, to, object); 477 else if (fmt[i] == 'E') 478 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 479 validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object); 480 } 481 482 /* If we didn't substitute, there is nothing more to do. */ 483 if (num_changes == prev_changes) 484 return; 485 486 /* Allow substituted expression to have different mode. This is used by 487 regmove to change mode of pseudo register. */ 488 if (fmt[0] == 'e' && GET_MODE (XEXP (x, 0)) != VOIDmode) 489 op0_mode = GET_MODE (XEXP (x, 0)); 490 491 /* Do changes needed to keep rtx consistent. Don't do any other 492 simplifications, as it is not our job. */ 493 494 if ((GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c') 495 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))) 496 { 497 validate_change (object, loc, 498 gen_rtx_fmt_ee (GET_RTX_CLASS (code) == 'c' ? code 499 : swap_condition (code), 500 GET_MODE (x), XEXP (x, 1), 501 XEXP (x, 0)), 1); 502 x = *loc; 503 code = GET_CODE (x); 504 } 505 506 switch (code) 507 { 508 case PLUS: 509 /* If we have a PLUS whose second operand is now a CONST_INT, use
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514 validate_change (object, loc, 515 simplify_gen_binary 516 (PLUS, GET_MODE (x), XEXP (x, 0), XEXP (x, 1)), 1); 517 break; 518 case MINUS: 519 if (GET_CODE (XEXP (x, 1)) == CONST_INT 520 || GET_CODE (XEXP (x, 1)) == CONST_DOUBLE) 521 validate_change (object, loc, 522 simplify_gen_binary 523 (PLUS, GET_MODE (x), XEXP (x, 0), 524 simplify_gen_unary (NEG, 525 GET_MODE (x), XEXP (x, 1), 526 GET_MODE (x))), 1); 527 break; 528 case ZERO_EXTEND: 529 case SIGN_EXTEND: 530 if (GET_MODE (XEXP (x, 0)) == VOIDmode) 531 { 532 new = simplify_gen_unary (code, GET_MODE (x), XEXP (x, 0), 533 op0_mode); 534 /* If any of the above failed, substitute in something that 535 we know won't be recognized. */ 536 if (!new) 537 new = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 538 validate_change (object, loc, new, 1); 539 } 540 break; 541 case SUBREG: 542 /* All subregs possible to simplify should be simplified. */ 543 new = simplify_subreg (GET_MODE (x), SUBREG_REG (x), op0_mode, 544 SUBREG_BYTE (x)); 545 546 /* Subregs of VOIDmode operands are incorrect. */ 547 if (!new && GET_MODE (SUBREG_REG (x)) == VOIDmode) 548 new = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 549 if (new) 550 validate_change (object, loc, new, 1); 551 break; 552 case ZERO_EXTRACT: 553 case SIGN_EXTRACT: 554 /* If we are replacing a register with memory, try to change the memory 555 to be the mode required for memory in extract operations (this isn't 556 likely to be an insertion operation; if it was, nothing bad will 557 happen, we might just fail in some cases). */ 558 559 if (GET_CODE (XEXP (x, 0)) == MEM 560 && GET_CODE (XEXP (x, 1)) == CONST_INT 561 && GET_CODE (XEXP (x, 2)) == CONST_INT 562 && !mode_dependent_address_p (XEXP (XEXP (x, 0), 0)) 563 && !MEM_VOLATILE_P (XEXP (x, 0))) 564 { 565 enum machine_mode wanted_mode = VOIDmode; 566 enum machine_mode is_mode = GET_MODE (XEXP (x, 0)); 567 int pos = INTVAL (XEXP (x, 2)); 568 569 if (GET_CODE (x) == ZERO_EXTRACT) 570 { 571 enum machine_mode new_mode 572 = mode_for_extraction (EP_extzv, 1); 573 if (new_mode != MAX_MACHINE_MODE) 574 wanted_mode = new_mode; 575 } 576 else if (GET_CODE (x) == SIGN_EXTRACT) 577 { 578 enum machine_mode new_mode 579 = mode_for_extraction (EP_extv, 1); 580 if (new_mode != MAX_MACHINE_MODE) 581 wanted_mode = new_mode; 582 } 583 584 /* If we have a narrower mode, we can do something. */ 585 if (wanted_mode != VOIDmode 586 && GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode)) 587 { 588 int offset = pos / BITS_PER_UNIT; 589 rtx newmem; 590 591 /* If the bytes and bits are counted differently, we 592 must adjust the offset. */ 593 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN) 594 offset = 595 (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode) - 596 offset); 597 598 pos %= GET_MODE_BITSIZE (wanted_mode); 599 600 newmem = adjust_address_nv (XEXP (x, 0), wanted_mode, offset); 601 602 validate_change (object, &XEXP (x, 2), GEN_INT (pos), 1); 603 validate_change (object, &XEXP (x, 0), newmem, 1); 604 } 605 } 606 607 break; 608 609 default: 610 break; 611 } 612} 613 614/* Try replacing every occurrence of FROM in subexpression LOC of INSN 615 with TO. After all changes have been made, validate by seeing 616 if INSN is still valid. */ 617 618int 619validate_replace_rtx_subexp (from, to, insn, loc) 620 rtx from, to, insn, *loc; 621{ 622 validate_replace_rtx_1 (loc, from, to, insn); 623 return apply_change_group (); 624} 625 626/* Try replacing every occurrence of FROM in INSN with TO. After all 627 changes have been made, validate by seeing if INSN is still valid. */ 628 629int 630validate_replace_rtx (from, to, insn) 631 rtx from, to, insn; 632{ 633 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn); 634 return apply_change_group (); 635} 636 637/* Try replacing every occurrence of FROM in INSN with TO. */ 638 639void 640validate_replace_rtx_group (from, to, insn) 641 rtx from, to, insn; 642{ 643 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn); 644} 645 646/* Function called by note_uses to replace used subexpressions. */ 647struct validate_replace_src_data 648{ 649 rtx from; /* Old RTX */ 650 rtx to; /* New RTX */ 651 rtx insn; /* Insn in which substitution is occurring. */ 652}; 653 654static void 655validate_replace_src_1 (x, data) 656 rtx *x; 657 void *data; 658{ 659 struct validate_replace_src_data *d 660 = (struct validate_replace_src_data *) data; 661 662 validate_replace_rtx_1 (x, d->from, d->to, d->insn); 663} 664 665/* Try replacing every occurrence of FROM in INSN with TO, avoiding 666 SET_DESTs. After all changes have been made, validate by seeing if 667 INSN is still valid. */ 668 669int 670validate_replace_src (from, to, insn) 671 rtx from, to, insn; 672{ 673 struct validate_replace_src_data d; 674 675 d.from = from; 676 d.to = to; 677 d.insn = insn; 678 note_uses (&PATTERN (insn), validate_replace_src_1, &d); 679 return apply_change_group (); 680} 681 682#ifdef HAVE_cc0 683/* Return 1 if the insn using CC0 set by INSN does not contain 684 any ordered tests applied to the condition codes. 685 EQ and NE tests do not count. */ 686 687int 688next_insn_tests_no_inequality (insn) 689 rtx insn; 690{ 691 rtx next = next_cc0_user (insn); 692 693 /* If there is no next insn, we have to take the conservative choice. */ 694 if (next == 0) 695 return 0; 696 697 return ((GET_CODE (next) == JUMP_INSN 698 || GET_CODE (next) == INSN 699 || GET_CODE (next) == CALL_INSN) 700 && ! inequality_comparisons_p (PATTERN (next))); 701} 702 703#if 0 /* This is useless since the insn that sets the cc's 704 must be followed immediately by the use of them. */ 705/* Return 1 if the CC value set up by INSN is not used. */ 706 707int 708next_insns_test_no_inequality (insn) 709 rtx insn; 710{ 711 rtx next = NEXT_INSN (insn); 712 713 for (; next != 0; next = NEXT_INSN (next)) 714 { 715 if (GET_CODE (next) == CODE_LABEL 716 || GET_CODE (next) == BARRIER) 717 return 1; 718 if (GET_CODE (next) == NOTE) 719 continue; 720 if (inequality_comparisons_p (PATTERN (next))) 721 return 0; 722 if (sets_cc0_p (PATTERN (next)) == 1) 723 return 1; 724 if (! reg_mentioned_p (cc0_rtx, PATTERN (next))) 725 return 1; 726 } 727 return 1; 728} 729#endif 730#endif 731 732/* This is used by find_single_use to locate an rtx that contains exactly one 733 use of DEST, which is typically either a REG or CC0. It returns a 734 pointer to the innermost rtx expression containing DEST. Appearances of 735 DEST that are being used to totally replace it are not counted. */ 736 737static rtx * 738find_single_use_1 (dest, loc) 739 rtx dest; 740 rtx *loc; 741{ 742 rtx x = *loc; 743 enum rtx_code code = GET_CODE (x); 744 rtx *result = 0; 745 rtx *this_result; 746 int i; 747 const char *fmt; 748 749 switch (code) 750 { 751 case CONST_INT: 752 case CONST: 753 case LABEL_REF: 754 case SYMBOL_REF: 755 case CONST_DOUBLE: 756 case CONST_VECTOR: 757 case CLOBBER: 758 return 0; 759 760 case SET: 761 /* If the destination is anything other than CC0, PC, a REG or a SUBREG 762 of a REG that occupies all of the REG, the insn uses DEST if 763 it is mentioned in the destination or the source. Otherwise, we 764 need just check the source. */ 765 if (GET_CODE (SET_DEST (x)) != CC0 766 && GET_CODE (SET_DEST (x)) != PC 767 && GET_CODE (SET_DEST (x)) != REG 768 && ! (GET_CODE (SET_DEST (x)) == SUBREG 769 && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG 770 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x)))) 771 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) 772 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) 773 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))) 774 break; 775 776 return find_single_use_1 (dest, &SET_SRC (x)); 777 778 case MEM: 779 case SUBREG: 780 return find_single_use_1 (dest, &XEXP (x, 0)); 781 782 default: 783 break; 784 } 785 786 /* If it wasn't one of the common cases above, check each expression and 787 vector of this code. Look for a unique usage of DEST. */ 788 789 fmt = GET_RTX_FORMAT (code); 790 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 791 { 792 if (fmt[i] == 'e') 793 { 794 if (dest == XEXP (x, i) 795 || (GET_CODE (dest) == REG && GET_CODE (XEXP (x, i)) == REG 796 && REGNO (dest) == REGNO (XEXP (x, i)))) 797 this_result = loc; 798 else 799 this_result = find_single_use_1 (dest, &XEXP (x, i)); 800 801 if (result == 0) 802 result = this_result; 803 else if (this_result) 804 /* Duplicate usage. */ 805 return 0; 806 } 807 else if (fmt[i] == 'E') 808 { 809 int j; 810 811 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 812 { 813 if (XVECEXP (x, i, j) == dest 814 || (GET_CODE (dest) == REG 815 && GET_CODE (XVECEXP (x, i, j)) == REG 816 && REGNO (XVECEXP (x, i, j)) == REGNO (dest))) 817 this_result = loc; 818 else 819 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j)); 820 821 if (result == 0) 822 result = this_result; 823 else if (this_result) 824 return 0; 825 } 826 } 827 } 828 829 return result; 830} 831 832/* See if DEST, produced in INSN, is used only a single time in the 833 sequel. If so, return a pointer to the innermost rtx expression in which 834 it is used. 835 836 If PLOC is non-zero, *PLOC is set to the insn containing the single use. 837 838 This routine will return usually zero either before flow is called (because 839 there will be no LOG_LINKS notes) or after reload (because the REG_DEAD 840 note can't be trusted). 841 842 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't 843 care about REG_DEAD notes or LOG_LINKS. 844 845 Otherwise, we find the single use by finding an insn that has a 846 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is 847 only referenced once in that insn, we know that it must be the first 848 and last insn referencing DEST. */ 849 850rtx * 851find_single_use (dest, insn, ploc) 852 rtx dest; 853 rtx insn; 854 rtx *ploc; 855{ 856 rtx next; 857 rtx *result; 858 rtx link; 859 860#ifdef HAVE_cc0 861 if (dest == cc0_rtx) 862 { 863 next = NEXT_INSN (insn); 864 if (next == 0 865 || (GET_CODE (next) != INSN && GET_CODE (next) != JUMP_INSN)) 866 return 0; 867 868 result = find_single_use_1 (dest, &PATTERN (next)); 869 if (result && ploc) 870 *ploc = next; 871 return result; 872 } 873#endif 874 875 if (reload_completed || reload_in_progress || GET_CODE (dest) != REG) 876 return 0; 877 878 for (next = next_nonnote_insn (insn); 879 next != 0 && GET_CODE (next) != CODE_LABEL; 880 next = next_nonnote_insn (next)) 881 if (INSN_P (next) && dead_or_set_p (next, dest)) 882 { 883 for (link = LOG_LINKS (next); link; link = XEXP (link, 1)) 884 if (XEXP (link, 0) == insn) 885 break; 886 887 if (link) 888 { 889 result = find_single_use_1 (dest, &PATTERN (next)); 890 if (ploc) 891 *ploc = next; 892 return result; 893 } 894 } 895 896 return 0; 897} 898 899/* Return 1 if OP is a valid general operand for machine mode MODE. 900 This is either a register reference, a memory reference, 901 or a constant. In the case of a memory reference, the address 902 is checked for general validity for the target machine. 903 904 Register and memory references must have mode MODE in order to be valid, 905 but some constants have no machine mode and are valid for any mode. 906 907 If MODE is VOIDmode, OP is checked for validity for whatever mode 908 it has. 909 910 The main use of this function is as a predicate in match_operand 911 expressions in the machine description. 912 913 For an explanation of this function's behavior for registers of 914 class NO_REGS, see the comment for `register_operand'. */ 915 916int 917general_operand (op, mode) 918 rtx op; 919 enum machine_mode mode; 920{ 921 enum rtx_code code = GET_CODE (op); 922 923 if (mode == VOIDmode) 924 mode = GET_MODE (op); 925 926 /* Don't accept CONST_INT or anything similar 927 if the caller wants something floating. */ 928 if (GET_MODE (op) == VOIDmode && mode != VOIDmode 929 && GET_MODE_CLASS (mode) != MODE_INT 930 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) 931 return 0; 932 933 if (GET_CODE (op) == CONST_INT 934 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op)) 935 return 0; 936 937 if (CONSTANT_P (op)) 938 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode 939 || mode == VOIDmode) 940#ifdef LEGITIMATE_PIC_OPERAND_P 941 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) 942#endif 943 && LEGITIMATE_CONSTANT_P (op)); 944 945 /* Except for certain constants with VOIDmode, already checked for, 946 OP's mode must match MODE if MODE specifies a mode. */ 947 948 if (GET_MODE (op) != mode) 949 return 0; 950 951 if (code == SUBREG) 952 { 953 rtx sub = SUBREG_REG (op); 954 955#ifdef INSN_SCHEDULING 956 /* On machines that have insn scheduling, we want all memory 957 reference to be explicit, so outlaw paradoxical SUBREGs. */ 958 if (GET_CODE (sub) == MEM 959 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (sub))) 960 return 0; 961#endif 962 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory 963 may result in incorrect reference. We should simplify all valid 964 subregs of MEM anyway. But allow this after reload because we 965 might be called from cleanup_subreg_operands. 966 967 ??? This is a kludge. */ 968 if (!reload_completed && SUBREG_BYTE (op) != 0 969 && GET_CODE (sub) == MEM) 970 return 0; 971 972 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally 973 create such rtl, and we must reject it. */ 974 if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT 975 && GET_MODE_SIZE (GET_MODE (op)) > GET_MODE_SIZE (GET_MODE (sub))) 976 return 0; 977 978 op = sub; 979 code = GET_CODE (op); 980 } 981 982 if (code == REG) 983 /* A register whose class is NO_REGS is not a general operand. */ 984 return (REGNO (op) >= FIRST_PSEUDO_REGISTER 985 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS); 986 987 if (code == MEM) 988 { 989 rtx y = XEXP (op, 0); 990 991 if (! volatile_ok && MEM_VOLATILE_P (op)) 992 return 0; 993 994 if (GET_CODE (y) == ADDRESSOF) 995 return 1; 996 997 /* Use the mem's mode, since it will be reloaded thus. */ 998 mode = GET_MODE (op); 999 GO_IF_LEGITIMATE_ADDRESS (mode, y, win); 1000 } 1001 1002 /* Pretend this is an operand for now; we'll run force_operand 1003 on its replacement in fixup_var_refs_1. */ 1004 if (code == ADDRESSOF) 1005 return 1; 1006 1007 return 0; 1008 1009 win: 1010 return 1; 1011} 1012 1013/* Return 1 if OP is a valid memory address for a memory reference 1014 of mode MODE. 1015 1016 The main use of this function is as a predicate in match_operand 1017 expressions in the machine description. */ 1018 1019int 1020address_operand (op, mode) 1021 rtx op; 1022 enum machine_mode mode; 1023{ 1024 return memory_address_p (mode, op); 1025} 1026 1027/* Return 1 if OP is a register reference of mode MODE. 1028 If MODE is VOIDmode, accept a register in any mode. 1029 1030 The main use of this function is as a predicate in match_operand 1031 expressions in the machine description. 1032 1033 As a special exception, registers whose class is NO_REGS are 1034 not accepted by `register_operand'. The reason for this change 1035 is to allow the representation of special architecture artifacts 1036 (such as a condition code register) without extending the rtl 1037 definitions. Since registers of class NO_REGS cannot be used 1038 as registers in any case where register classes are examined, 1039 it is most consistent to keep this function from accepting them. */ 1040 1041int 1042register_operand (op, mode) 1043 rtx op; 1044 enum machine_mode mode; 1045{ 1046 if (GET_MODE (op) != mode && mode != VOIDmode) 1047 return 0; 1048 1049 if (GET_CODE (op) == SUBREG) 1050 { 1051 rtx sub = SUBREG_REG (op); 1052 1053 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand 1054 because it is guaranteed to be reloaded into one. 1055 Just make sure the MEM is valid in itself. 1056 (Ideally, (SUBREG (MEM)...) should not exist after reload, 1057 but currently it does result from (SUBREG (REG)...) where the 1058 reg went on the stack.) */ 1059 if (! reload_completed && GET_CODE (sub) == MEM) 1060 return general_operand (op, mode); 1061 1062#ifdef CLASS_CANNOT_CHANGE_MODE 1063 if (GET_CODE (sub) == REG 1064 && REGNO (sub) < FIRST_PSEUDO_REGISTER 1065 && (TEST_HARD_REG_BIT 1066 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], 1067 REGNO (sub))) 1068 && CLASS_CANNOT_CHANGE_MODE_P (mode, GET_MODE (sub)) 1069 && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_INT 1070 && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_FLOAT) 1071 return 0; 1072#endif 1073 1074 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally 1075 create such rtl, and we must reject it. */ 1076 if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT 1077 && GET_MODE_SIZE (GET_MODE (op)) > GET_MODE_SIZE (GET_MODE (sub))) 1078 return 0; 1079 1080 op = sub; 1081 } 1082 1083 /* If we have an ADDRESSOF, consider it valid since it will be 1084 converted into something that will not be a MEM. */ 1085 if (GET_CODE (op) == ADDRESSOF) 1086 return 1; 1087 1088 /* We don't consider registers whose class is NO_REGS 1089 to be a register operand. */ 1090 return (GET_CODE (op) == REG 1091 && (REGNO (op) >= FIRST_PSEUDO_REGISTER 1092 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); 1093} 1094 1095/* Return 1 for a register in Pmode; ignore the tested mode. */ 1096 1097int 1098pmode_register_operand (op, mode) 1099 rtx op; 1100 enum machine_mode mode ATTRIBUTE_UNUSED; 1101{ 1102 return register_operand (op, Pmode); 1103} 1104 1105/* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH 1106 or a hard register. */ 1107 1108int 1109scratch_operand (op, mode) 1110 rtx op; 1111 enum machine_mode mode; 1112{ 1113 if (GET_MODE (op) != mode && mode != VOIDmode) 1114 return 0; 1115 1116 return (GET_CODE (op) == SCRATCH 1117 || (GET_CODE (op) == REG 1118 && REGNO (op) < FIRST_PSEUDO_REGISTER)); 1119} 1120 1121/* Return 1 if OP is a valid immediate operand for mode MODE. 1122 1123 The main use of this function is as a predicate in match_operand 1124 expressions in the machine description. */ 1125 1126int 1127immediate_operand (op, mode) 1128 rtx op; 1129 enum machine_mode mode; 1130{ 1131 /* Don't accept CONST_INT or anything similar 1132 if the caller wants something floating. */ 1133 if (GET_MODE (op) == VOIDmode && mode != VOIDmode 1134 && GET_MODE_CLASS (mode) != MODE_INT 1135 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) 1136 return 0; 1137 1138 if (GET_CODE (op) == CONST_INT 1139 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op)) 1140 return 0; 1141 1142 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and 1143 result in 0/1. It seems a safe assumption that this is 1144 in range for everyone. */ 1145 if (GET_CODE (op) == CONSTANT_P_RTX) 1146 return 1; 1147 1148 return (CONSTANT_P (op) 1149 && (GET_MODE (op) == mode || mode == VOIDmode 1150 || GET_MODE (op) == VOIDmode) 1151#ifdef LEGITIMATE_PIC_OPERAND_P 1152 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) 1153#endif 1154 && LEGITIMATE_CONSTANT_P (op)); 1155} 1156 1157/* Returns 1 if OP is an operand that is a CONST_INT. */ 1158 1159int 1160const_int_operand (op, mode) 1161 rtx op; 1162 enum machine_mode mode; 1163{ 1164 if (GET_CODE (op) != CONST_INT) 1165 return 0; 1166 1167 if (mode != VOIDmode 1168 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op)) 1169 return 0; 1170 1171 return 1; 1172} 1173 1174/* Returns 1 if OP is an operand that is a constant integer or constant 1175 floating-point number. */ 1176 1177int 1178const_double_operand (op, mode) 1179 rtx op; 1180 enum machine_mode mode; 1181{ 1182 /* Don't accept CONST_INT or anything similar 1183 if the caller wants something floating. */ 1184 if (GET_MODE (op) == VOIDmode && mode != VOIDmode 1185 && GET_MODE_CLASS (mode) != MODE_INT 1186 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) 1187 return 0; 1188 1189 return ((GET_CODE (op) == CONST_DOUBLE || GET_CODE (op) == CONST_INT) 1190 && (mode == VOIDmode || GET_MODE (op) == mode 1191 || GET_MODE (op) == VOIDmode)); 1192} 1193 1194/* Return 1 if OP is a general operand that is not an immediate operand. */ 1195 1196int 1197nonimmediate_operand (op, mode) 1198 rtx op; 1199 enum machine_mode mode; 1200{ 1201 return (general_operand (op, mode) && ! CONSTANT_P (op)); 1202} 1203 1204/* Return 1 if OP is a register reference or immediate value of mode MODE. */ 1205 1206int 1207nonmemory_operand (op, mode) 1208 rtx op; 1209 enum machine_mode mode; 1210{ 1211 if (CONSTANT_P (op)) 1212 { 1213 /* Don't accept CONST_INT or anything similar 1214 if the caller wants something floating. */ 1215 if (GET_MODE (op) == VOIDmode && mode != VOIDmode 1216 && GET_MODE_CLASS (mode) != MODE_INT 1217 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) 1218 return 0; 1219 1220 if (GET_CODE (op) == CONST_INT 1221 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op)) 1222 return 0; 1223 1224 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode 1225 || mode == VOIDmode) 1226#ifdef LEGITIMATE_PIC_OPERAND_P 1227 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) 1228#endif 1229 && LEGITIMATE_CONSTANT_P (op)); 1230 } 1231 1232 if (GET_MODE (op) != mode && mode != VOIDmode) 1233 return 0; 1234 1235 if (GET_CODE (op) == SUBREG) 1236 { 1237 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand 1238 because it is guaranteed to be reloaded into one. 1239 Just make sure the MEM is valid in itself. 1240 (Ideally, (SUBREG (MEM)...) should not exist after reload, 1241 but currently it does result from (SUBREG (REG)...) where the 1242 reg went on the stack.) */ 1243 if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM) 1244 return general_operand (op, mode); 1245 op = SUBREG_REG (op); 1246 } 1247 1248 /* We don't consider registers whose class is NO_REGS 1249 to be a register operand. */ 1250 return (GET_CODE (op) == REG 1251 && (REGNO (op) >= FIRST_PSEUDO_REGISTER 1252 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); 1253} 1254 1255/* Return 1 if OP is a valid operand that stands for pushing a 1256 value of mode MODE onto the stack. 1257 1258 The main use of this function is as a predicate in match_operand 1259 expressions in the machine description. */ 1260 1261int 1262push_operand (op, mode) 1263 rtx op; 1264 enum machine_mode mode; 1265{ 1266 unsigned int rounded_size = GET_MODE_SIZE (mode); 1267 1268#ifdef PUSH_ROUNDING 1269 rounded_size = PUSH_ROUNDING (rounded_size); 1270#endif 1271 1272 if (GET_CODE (op) != MEM) 1273 return 0; 1274 1275 if (mode != VOIDmode && GET_MODE (op) != mode) 1276 return 0; 1277 1278 op = XEXP (op, 0); 1279 1280 if (rounded_size == GET_MODE_SIZE (mode)) 1281 { 1282 if (GET_CODE (op) != STACK_PUSH_CODE) 1283 return 0; 1284 } 1285 else 1286 { 1287 if (GET_CODE (op) != PRE_MODIFY 1288 || GET_CODE (XEXP (op, 1)) != PLUS 1289 || XEXP (XEXP (op, 1), 0) != XEXP (op, 0) 1290 || GET_CODE (XEXP (XEXP (op, 1), 1)) != CONST_INT 1291#ifdef STACK_GROWS_DOWNWARD 1292 || INTVAL (XEXP (XEXP (op, 1), 1)) != - (int) rounded_size 1293#else 1294 || INTVAL (XEXP (XEXP (op, 1), 1)) != rounded_size 1295#endif 1296 ) 1297 return 0; 1298 } 1299 1300 return XEXP (op, 0) == stack_pointer_rtx; 1301} 1302 1303/* Return 1 if OP is a valid operand that stands for popping a 1304 value of mode MODE off the stack. 1305 1306 The main use of this function is as a predicate in match_operand 1307 expressions in the machine description. */ 1308 1309int 1310pop_operand (op, mode) 1311 rtx op; 1312 enum machine_mode mode; 1313{ 1314 if (GET_CODE (op) != MEM) 1315 return 0; 1316 1317 if (mode != VOIDmode && GET_MODE (op) != mode) 1318 return 0; 1319 1320 op = XEXP (op, 0); 1321 1322 if (GET_CODE (op) != STACK_POP_CODE) 1323 return 0; 1324 1325 return XEXP (op, 0) == stack_pointer_rtx; 1326} 1327 1328/* Return 1 if ADDR is a valid memory address for mode MODE. */ 1329 1330int 1331memory_address_p (mode, addr) 1332 enum machine_mode mode ATTRIBUTE_UNUSED; 1333 rtx addr; 1334{ 1335 if (GET_CODE (addr) == ADDRESSOF) 1336 return 1; 1337 1338 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); 1339 return 0; 1340 1341 win: 1342 return 1; 1343} 1344 1345/* Return 1 if OP is a valid memory reference with mode MODE, 1346 including a valid address. 1347 1348 The main use of this function is as a predicate in match_operand 1349 expressions in the machine description. */ 1350 1351int 1352memory_operand (op, mode) 1353 rtx op; 1354 enum machine_mode mode; 1355{ 1356 rtx inner; 1357 1358 if (! reload_completed) 1359 /* Note that no SUBREG is a memory operand before end of reload pass, 1360 because (SUBREG (MEM...)) forces reloading into a register. */ 1361 return GET_CODE (op) == MEM && general_operand (op, mode); 1362 1363 if (mode != VOIDmode && GET_MODE (op) != mode) 1364 return 0; 1365 1366 inner = op; 1367 if (GET_CODE (inner) == SUBREG) 1368 inner = SUBREG_REG (inner); 1369 1370 return (GET_CODE (inner) == MEM && general_operand (op, mode)); 1371} 1372 1373/* Return 1 if OP is a valid indirect memory reference with mode MODE; 1374 that is, a memory reference whose address is a general_operand. */ 1375 1376int 1377indirect_operand (op, mode) 1378 rtx op; 1379 enum machine_mode mode; 1380{ 1381 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */ 1382 if (! reload_completed 1383 && GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == MEM) 1384 { 1385 int offset = SUBREG_BYTE (op); 1386 rtx inner = SUBREG_REG (op); 1387 1388 if (mode != VOIDmode && GET_MODE (op) != mode) 1389 return 0; 1390 1391 /* The only way that we can have a general_operand as the resulting 1392 address is if OFFSET is zero and the address already is an operand 1393 or if the address is (plus Y (const_int -OFFSET)) and Y is an 1394 operand. */ 1395 1396 return ((offset == 0 && general_operand (XEXP (inner, 0), Pmode)) 1397 || (GET_CODE (XEXP (inner, 0)) == PLUS 1398 && GET_CODE (XEXP (XEXP (inner, 0), 1)) == CONST_INT 1399 && INTVAL (XEXP (XEXP (inner, 0), 1)) == -offset 1400 && general_operand (XEXP (XEXP (inner, 0), 0), Pmode))); 1401 } 1402 1403 return (GET_CODE (op) == MEM 1404 && memory_operand (op, mode) 1405 && general_operand (XEXP (op, 0), Pmode)); 1406} 1407 1408/* Return 1 if this is a comparison operator. This allows the use of 1409 MATCH_OPERATOR to recognize all the branch insns. */ 1410 1411int 1412comparison_operator (op, mode) 1413 rtx op; 1414 enum machine_mode mode; 1415{ 1416 return ((mode == VOIDmode || GET_MODE (op) == mode) 1417 && GET_RTX_CLASS (GET_CODE (op)) == '<'); 1418} 1419 1420/* If BODY is an insn body that uses ASM_OPERANDS, 1421 return the number of operands (both input and output) in the insn. 1422 Otherwise return -1. */ 1423 1424int 1425asm_noperands (body) 1426 rtx body; 1427{ 1428 switch (GET_CODE (body)) 1429 { 1430 case ASM_OPERANDS: 1431 /* No output operands: return number of input operands. */ 1432 return ASM_OPERANDS_INPUT_LENGTH (body); 1433 case SET: 1434 if (GET_CODE (SET_SRC (body)) == ASM_OPERANDS) 1435 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */ 1436 return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body)) + 1; 1437 else 1438 return -1; 1439 case PARALLEL: 1440 if (GET_CODE (XVECEXP (body, 0, 0)) == SET 1441 && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS) 1442 { 1443 /* Multiple output operands, or 1 output plus some clobbers: 1444 body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */ 1445 int i; 1446 int n_sets; 1447 1448 /* Count backwards through CLOBBERs to determine number of SETs. */ 1449 for (i = XVECLEN (body, 0); i > 0; i--) 1450 { 1451 if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET) 1452 break; 1453 if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER) 1454 return -1; 1455 } 1456 1457 /* N_SETS is now number of output operands. */ 1458 n_sets = i; 1459 1460 /* Verify that all the SETs we have 1461 came from a single original asm_operands insn 1462 (so that invalid combinations are blocked). */ 1463 for (i = 0; i < n_sets; i++) 1464 { 1465 rtx elt = XVECEXP (body, 0, i); 1466 if (GET_CODE (elt) != SET) 1467 return -1; 1468 if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS) 1469 return -1; 1470 /* If these ASM_OPERANDS rtx's came from different original insns 1471 then they aren't allowed together. */ 1472 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt)) 1473 != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body, 0, 0)))) 1474 return -1; 1475 } 1476 return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body, 0, 0))) 1477 + n_sets); 1478 } 1479 else if (GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS) 1480 { 1481 /* 0 outputs, but some clobbers: 1482 body is [(asm_operands ...) (clobber (reg ...))...]. */ 1483 int i; 1484 1485 /* Make sure all the other parallel things really are clobbers. */ 1486 for (i = XVECLEN (body, 0) - 1; i > 0; i--) 1487 if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER) 1488 return -1; 1489 1490 return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body, 0, 0)); 1491 } 1492 else 1493 return -1; 1494 default: 1495 return -1; 1496 } 1497} 1498 1499/* Assuming BODY is an insn body that uses ASM_OPERANDS, 1500 copy its operands (both input and output) into the vector OPERANDS, 1501 the locations of the operands within the insn into the vector OPERAND_LOCS, 1502 and the constraints for the operands into CONSTRAINTS. 1503 Write the modes of the operands into MODES. 1504 Return the assembler-template. 1505 1506 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0, 1507 we don't store that info. */ 1508 1509const char * 1510decode_asm_operands (body, operands, operand_locs, constraints, modes) 1511 rtx body; 1512 rtx *operands; 1513 rtx **operand_locs; 1514 const char **constraints; 1515 enum machine_mode *modes; 1516{ 1517 int i; 1518 int noperands; 1519 const char *template = 0; 1520 1521 if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS) 1522 { 1523 rtx asmop = SET_SRC (body); 1524 /* Single output operand: BODY is (set OUTPUT (asm_operands ....)). */ 1525 1526 noperands = ASM_OPERANDS_INPUT_LENGTH (asmop) + 1; 1527 1528 for (i = 1; i < noperands; i++) 1529 { 1530 if (operand_locs) 1531 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i - 1); 1532 if (operands) 1533 operands[i] = ASM_OPERANDS_INPUT (asmop, i - 1); 1534 if (constraints) 1535 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i - 1); 1536 if (modes) 1537 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i - 1); 1538 } 1539 1540 /* The output is in the SET. 1541 Its constraint is in the ASM_OPERANDS itself. */ 1542 if (operands) 1543 operands[0] = SET_DEST (body); 1544 if (operand_locs) 1545 operand_locs[0] = &SET_DEST (body); 1546 if (constraints) 1547 constraints[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop); 1548 if (modes) 1549 modes[0] = GET_MODE (SET_DEST (body)); 1550 template = ASM_OPERANDS_TEMPLATE (asmop); 1551 } 1552 else if (GET_CODE (body) == ASM_OPERANDS) 1553 { 1554 rtx asmop = body; 1555 /* No output operands: BODY is (asm_operands ....). */ 1556 1557 noperands = ASM_OPERANDS_INPUT_LENGTH (asmop); 1558 1559 /* The input operands are found in the 1st element vector. */ 1560 /* Constraints for inputs are in the 2nd element vector. */ 1561 for (i = 0; i < noperands; i++) 1562 { 1563 if (operand_locs) 1564 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i); 1565 if (operands) 1566 operands[i] = ASM_OPERANDS_INPUT (asmop, i); 1567 if (constraints) 1568 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i); 1569 if (modes) 1570 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i); 1571 } 1572 template = ASM_OPERANDS_TEMPLATE (asmop); 1573 } 1574 else if (GET_CODE (body) == PARALLEL 1575 && GET_CODE (XVECEXP (body, 0, 0)) == SET 1576 && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS) 1577 { 1578 rtx asmop = SET_SRC (XVECEXP (body, 0, 0)); 1579 int nparallel = XVECLEN (body, 0); /* Includes CLOBBERs. */ 1580 int nin = ASM_OPERANDS_INPUT_LENGTH (asmop); 1581 int nout = 0; /* Does not include CLOBBERs. */ 1582 1583 /* At least one output, plus some CLOBBERs. */ 1584 1585 /* The outputs are in the SETs. 1586 Their constraints are in the ASM_OPERANDS itself. */ 1587 for (i = 0; i < nparallel; i++) 1588 { 1589 if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER) 1590 break; /* Past last SET */ 1591 1592 if (operands) 1593 operands[i] = SET_DEST (XVECEXP (body, 0, i)); 1594 if (operand_locs) 1595 operand_locs[i] = &SET_DEST (XVECEXP (body, 0, i)); 1596 if (constraints) 1597 constraints[i] = XSTR (SET_SRC (XVECEXP (body, 0, i)), 1); 1598 if (modes) 1599 modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i))); 1600 nout++; 1601 } 1602 1603 for (i = 0; i < nin; i++) 1604 { 1605 if (operand_locs) 1606 operand_locs[i + nout] = &ASM_OPERANDS_INPUT (asmop, i); 1607 if (operands) 1608 operands[i + nout] = ASM_OPERANDS_INPUT (asmop, i); 1609 if (constraints) 1610 constraints[i + nout] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i); 1611 if (modes) 1612 modes[i + nout] = ASM_OPERANDS_INPUT_MODE (asmop, i); 1613 } 1614 1615 template = ASM_OPERANDS_TEMPLATE (asmop); 1616 } 1617 else if (GET_CODE (body) == PARALLEL 1618 && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS) 1619 { 1620 /* No outputs, but some CLOBBERs. */ 1621 1622 rtx asmop = XVECEXP (body, 0, 0); 1623 int nin = ASM_OPERANDS_INPUT_LENGTH (asmop); 1624 1625 for (i = 0; i < nin; i++) 1626 { 1627 if (operand_locs) 1628 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i); 1629 if (operands) 1630 operands[i] = ASM_OPERANDS_INPUT (asmop, i); 1631 if (constraints) 1632 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i); 1633 if (modes) 1634 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i); 1635 } 1636 1637 template = ASM_OPERANDS_TEMPLATE (asmop); 1638 } 1639 1640 return template; 1641} 1642 1643/* Check if an asm_operand matches it's constraints. 1644 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */ 1645 1646int 1647asm_operand_ok (op, constraint) 1648 rtx op; 1649 const char *constraint; 1650{ 1651 int result = 0; 1652 1653 /* Use constrain_operands after reload. */ 1654 if (reload_completed) 1655 abort (); 1656 1657 while (*constraint) 1658 { 1659 char c = *constraint++; 1660 switch (c) 1661 { 1662 case '=': 1663 case '+': 1664 case '*': 1665 case '%': 1666 case '?': 1667 case '!': 1668 case '#': 1669 case '&': 1670 case ',': 1671 break; 1672 1673 case '0': case '1': case '2': case '3': case '4': 1674 case '5': case '6': case '7': case '8': case '9': 1675 /* For best results, our caller should have given us the 1676 proper matching constraint, but we can't actually fail 1677 the check if they didn't. Indicate that results are 1678 inconclusive. */ 1679 while (ISDIGIT (*constraint)) 1680 constraint++; 1681 result = -1; 1682 break; 1683 1684 case 'p': 1685 if (address_operand (op, VOIDmode)) 1686 return 1; 1687 break; 1688 1689 case 'm': 1690 case 'V': /* non-offsettable */ 1691 if (memory_operand (op, VOIDmode)) 1692 return 1; 1693 break; 1694 1695 case 'o': /* offsettable */ 1696 if (offsettable_nonstrict_memref_p (op)) 1697 return 1; 1698 break; 1699 1700 case '<': 1701 /* ??? Before flow, auto inc/dec insns are not supposed to exist, 1702 excepting those that expand_call created. Further, on some 1703 machines which do not have generalized auto inc/dec, an inc/dec 1704 is not a memory_operand. 1705 1706 Match any memory and hope things are resolved after reload. */ 1707 1708 if (GET_CODE (op) == MEM 1709 && (1 1710 || GET_CODE (XEXP (op, 0)) == PRE_DEC 1711 || GET_CODE (XEXP (op, 0)) == POST_DEC)) 1712 return 1; 1713 break; 1714 1715 case '>': 1716 if (GET_CODE (op) == MEM 1717 && (1 1718 || GET_CODE (XEXP (op, 0)) == PRE_INC 1719 || GET_CODE (XEXP (op, 0)) == POST_INC)) 1720 return 1; 1721 break; 1722 1723 case 'E': 1724#ifndef REAL_ARITHMETIC 1725 /* Match any floating double constant, but only if 1726 we can examine the bits of it reliably. */ 1727 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT 1728 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) 1729 && GET_MODE (op) != VOIDmode && ! flag_pretend_float) 1730 break; 1731#endif 1732 /* FALLTHRU */ 1733 1734 case 'F': 1735 if (GET_CODE (op) == CONST_DOUBLE) 1736 return 1; 1737 break; 1738 1739 case 'G': 1740 if (GET_CODE (op) == CONST_DOUBLE 1741 && CONST_DOUBLE_OK_FOR_LETTER_P (op, 'G')) 1742 return 1; 1743 break; 1744 case 'H': 1745 if (GET_CODE (op) == CONST_DOUBLE 1746 && CONST_DOUBLE_OK_FOR_LETTER_P (op, 'H')) 1747 return 1; 1748 break; 1749 1750 case 's': 1751 if (GET_CODE (op) == CONST_INT 1752 || (GET_CODE (op) == CONST_DOUBLE 1753 && GET_MODE (op) == VOIDmode)) 1754 break; 1755 /* FALLTHRU */ 1756 1757 case 'i': 1758 if (CONSTANT_P (op) 1759#ifdef LEGITIMATE_PIC_OPERAND_P 1760 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) 1761#endif 1762 ) 1763 return 1; 1764 break; 1765 1766 case 'n': 1767 if (GET_CODE (op) == CONST_INT 1768 || (GET_CODE (op) == CONST_DOUBLE 1769 && GET_MODE (op) == VOIDmode)) 1770 return 1; 1771 break; 1772 1773 case 'I': 1774 if (GET_CODE (op) == CONST_INT 1775 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')) 1776 return 1; 1777 break; 1778 case 'J': 1779 if (GET_CODE (op) == CONST_INT 1780 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'J')) 1781 return 1; 1782 break; 1783 case 'K': 1784 if (GET_CODE (op) == CONST_INT 1785 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')) 1786 return 1; 1787 break; 1788 case 'L': 1789 if (GET_CODE (op) == CONST_INT 1790 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')) 1791 return 1; 1792 break; 1793 case 'M': 1794 if (GET_CODE (op) == CONST_INT 1795 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'M')) 1796 return 1; 1797 break; 1798 case 'N': 1799 if (GET_CODE (op) == CONST_INT 1800 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'N')) 1801 return 1; 1802 break; 1803 case 'O': 1804 if (GET_CODE (op) == CONST_INT 1805 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'O')) 1806 return 1; 1807 break; 1808 case 'P': 1809 if (GET_CODE (op) == CONST_INT 1810 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'P')) 1811 return 1; 1812 break; 1813 1814 case 'X': 1815 return 1; 1816 1817 case 'g': 1818 if (general_operand (op, VOIDmode)) 1819 return 1; 1820 break; 1821 1822 default: 1823 /* For all other letters, we first check for a register class, 1824 otherwise it is an EXTRA_CONSTRAINT. */ 1825 if (REG_CLASS_FROM_LETTER (c) != NO_REGS) 1826 { 1827 case 'r': 1828 if (GET_MODE (op) == BLKmode) 1829 break; 1830 if (register_operand (op, VOIDmode)) 1831 return 1; 1832 } 1833#ifdef EXTRA_CONSTRAINT 1834 if (EXTRA_CONSTRAINT (op, c)) 1835 return 1; 1836#endif 1837 break; 1838 } 1839 } 1840 1841 return result; 1842} 1843 1844/* Given an rtx *P, if it is a sum containing an integer constant term, 1845 return the location (type rtx *) of the pointer to that constant term. 1846 Otherwise, return a null pointer. */ 1847 1848rtx * 1849find_constant_term_loc (p) 1850 rtx *p; 1851{ 1852 rtx *tem; 1853 enum rtx_code code = GET_CODE (*p); 1854 1855 /* If *P IS such a constant term, P is its location. */ 1856 1857 if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF 1858 || code == CONST) 1859 return p; 1860 1861 /* Otherwise, if not a sum, it has no constant term. */ 1862 1863 if (GET_CODE (*p) != PLUS) 1864 return 0; 1865 1866 /* If one of the summands is constant, return its location. */ 1867 1868 if (XEXP (*p, 0) && CONSTANT_P (XEXP (*p, 0)) 1869 && XEXP (*p, 1) && CONSTANT_P (XEXP (*p, 1))) 1870 return p; 1871 1872 /* Otherwise, check each summand for containing a constant term. */ 1873 1874 if (XEXP (*p, 0) != 0) 1875 { 1876 tem = find_constant_term_loc (&XEXP (*p, 0)); 1877 if (tem != 0) 1878 return tem; 1879 } 1880 1881 if (XEXP (*p, 1) != 0) 1882 { 1883 tem = find_constant_term_loc (&XEXP (*p, 1)); 1884 if (tem != 0) 1885 return tem; 1886 } 1887 1888 return 0; 1889} 1890 1891/* Return 1 if OP is a memory reference 1892 whose address contains no side effects 1893 and remains valid after the addition 1894 of a positive integer less than the 1895 size of the object being referenced. 1896 1897 We assume that the original address is valid and do not check it. 1898 1899 This uses strict_memory_address_p as a subroutine, so 1900 don't use it before reload. */ 1901 1902int 1903offsettable_memref_p (op) 1904 rtx op; 1905{ 1906 return ((GET_CODE (op) == MEM) 1907 && offsettable_address_p (1, GET_MODE (op), XEXP (op, 0))); 1908} 1909 1910/* Similar, but don't require a strictly valid mem ref: 1911 consider pseudo-regs valid as index or base regs. */ 1912 1913int 1914offsettable_nonstrict_memref_p (op) 1915 rtx op; 1916{ 1917 return ((GET_CODE (op) == MEM) 1918 && offsettable_address_p (0, GET_MODE (op), XEXP (op, 0))); 1919} 1920 1921/* Return 1 if Y is a memory address which contains no side effects 1922 and would remain valid after the addition of a positive integer 1923 less than the size of that mode. 1924 1925 We assume that the original address is valid and do not check it. 1926 We do check that it is valid for narrower modes. 1927 1928 If STRICTP is nonzero, we require a strictly valid address, 1929 for the sake of use in reload.c. */ 1930 1931int 1932offsettable_address_p (strictp, mode, y) 1933 int strictp; 1934 enum machine_mode mode; 1935 rtx y; 1936{ 1937 enum rtx_code ycode = GET_CODE (y); 1938 rtx z; 1939 rtx y1 = y; 1940 rtx *y2; 1941 int (*addressp) PARAMS ((enum machine_mode, rtx)) = 1942 (strictp ? strict_memory_address_p : memory_address_p); 1943 unsigned int mode_sz = GET_MODE_SIZE (mode); 1944 1945 if (CONSTANT_ADDRESS_P (y)) 1946 return 1; 1947 1948 /* Adjusting an offsettable address involves changing to a narrower mode. 1949 Make sure that's OK. */ 1950 1951 if (mode_dependent_address_p (y)) 1952 return 0; 1953 1954 /* ??? How much offset does an offsettable BLKmode reference need? 1955 Clearly that depends on the situation in which it's being used. 1956 However, the current situation in which we test 0xffffffff is 1957 less than ideal. Caveat user. */ 1958 if (mode_sz == 0) 1959 mode_sz = BIGGEST_ALIGNMENT / BITS_PER_UNIT; 1960 1961 /* If the expression contains a constant term, 1962 see if it remains valid when max possible offset is added. */ 1963 1964 if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1))) 1965 { 1966 int good; 1967 1968 y1 = *y2; 1969 *y2 = plus_constant (*y2, mode_sz - 1); 1970 /* Use QImode because an odd displacement may be automatically invalid 1971 for any wider mode. But it should be valid for a single byte. */ 1972 good = (*addressp) (QImode, y); 1973 1974 /* In any case, restore old contents of memory. */ 1975 *y2 = y1; 1976 return good; 1977 } 1978 1979 if (GET_RTX_CLASS (ycode) == 'a') 1980 return 0; 1981 1982 /* The offset added here is chosen as the maximum offset that 1983 any instruction could need to add when operating on something 1984 of the specified mode. We assume that if Y and Y+c are 1985 valid addresses then so is Y+d for all 0<d<c. adjust_address will 1986 go inside a LO_SUM here, so we do so as well. */ 1987 if (GET_CODE (y) == LO_SUM 1988 && mode != BLKmode 1989 && mode_sz <= GET_MODE_ALIGNMENT (mode) / BITS_PER_UNIT) 1990 z = gen_rtx_LO_SUM (GET_MODE (y), XEXP (y, 0), 1991 plus_constant (XEXP (y, 1), mode_sz - 1)); 1992 else 1993 z = plus_constant (y, mode_sz - 1); 1994 1995 /* Use QImode because an odd displacement may be automatically invalid 1996 for any wider mode. But it should be valid for a single byte. */ 1997 return (*addressp) (QImode, z); 1998} 1999 2000/* Return 1 if ADDR is an address-expression whose effect depends 2001 on the mode of the memory reference it is used in. 2002 2003 Autoincrement addressing is a typical example of mode-dependence 2004 because the amount of the increment depends on the mode. */ 2005 2006int 2007mode_dependent_address_p (addr) 2008 rtx addr ATTRIBUTE_UNUSED; /* Maybe used in GO_IF_MODE_DEPENDENT_ADDRESS. */ 2009{ 2010 GO_IF_MODE_DEPENDENT_ADDRESS (addr, win); 2011 return 0; 2012 /* Label `win' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */ 2013 win: ATTRIBUTE_UNUSED_LABEL 2014 return 1; 2015} 2016 2017/* Return 1 if OP is a general operand 2018 other than a memory ref with a mode dependent address. */ 2019 2020int 2021mode_independent_operand (op, mode) 2022 enum machine_mode mode; 2023 rtx op; 2024{ 2025 rtx addr; 2026 2027 if (! general_operand (op, mode)) 2028 return 0; 2029 2030 if (GET_CODE (op) != MEM) 2031 return 1; 2032 2033 addr = XEXP (op, 0); 2034 GO_IF_MODE_DEPENDENT_ADDRESS (addr, lose); 2035 return 1; 2036 /* Label `lose' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */ 2037 lose: ATTRIBUTE_UNUSED_LABEL 2038 return 0; 2039} 2040 2041/* Like extract_insn, but save insn extracted and don't extract again, when 2042 called again for the same insn expecting that recog_data still contain the 2043 valid information. This is used primary by gen_attr infrastructure that 2044 often does extract insn again and again. */ 2045void 2046extract_insn_cached (insn) 2047 rtx insn; 2048{ 2049 if (recog_data.insn == insn && INSN_CODE (insn) >= 0) 2050 return; 2051 extract_insn (insn); 2052 recog_data.insn = insn; 2053} 2054/* Do cached extract_insn, constrain_operand and complain about failures. 2055 Used by insn_attrtab. */ 2056void 2057extract_constrain_insn_cached (insn) 2058 rtx insn; 2059{ 2060 extract_insn_cached (insn); 2061 if (which_alternative == -1 2062 && !constrain_operands (reload_completed)) 2063 fatal_insn_not_found (insn); 2064} 2065/* Do cached constrain_operand and complain about failures. */ 2066int 2067constrain_operands_cached (strict) 2068 int strict; 2069{ 2070 if (which_alternative == -1) 2071 return constrain_operands (strict); 2072 else 2073 return 1; 2074} 2075 2076/* Analyze INSN and fill in recog_data. */ 2077 2078void 2079extract_insn (insn) 2080 rtx insn; 2081{ 2082 int i; 2083 int icode; 2084 int noperands; 2085 rtx body = PATTERN (insn); 2086 2087 recog_data.insn = NULL; 2088 recog_data.n_operands = 0; 2089 recog_data.n_alternatives = 0; 2090 recog_data.n_dups = 0; 2091 which_alternative = -1; 2092 2093 switch (GET_CODE (body)) 2094 { 2095 case USE: 2096 case CLOBBER: 2097 case ASM_INPUT: 2098 case ADDR_VEC: 2099 case ADDR_DIFF_VEC: 2100 return; 2101 2102 case SET: 2103 if (GET_CODE (SET_SRC (body)) == ASM_OPERANDS) 2104 goto asm_insn; 2105 else 2106 goto normal_insn; 2107 case PARALLEL: 2108 if ((GET_CODE (XVECEXP (body, 0, 0)) == SET 2109 && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS) 2110 || GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS) 2111 goto asm_insn; 2112 else 2113 goto normal_insn; 2114 case ASM_OPERANDS: 2115 asm_insn: 2116 recog_data.n_operands = noperands = asm_noperands (body); 2117 if (noperands >= 0) 2118 { 2119 /* This insn is an `asm' with operands. */ 2120 2121 /* expand_asm_operands makes sure there aren't too many operands. */ 2122 if (noperands > MAX_RECOG_OPERANDS) 2123 abort (); 2124 2125 /* Now get the operand values and constraints out of the insn. */ 2126 decode_asm_operands (body, recog_data.operand, 2127 recog_data.operand_loc, 2128 recog_data.constraints, 2129 recog_data.operand_mode); 2130 if (noperands > 0) 2131 { 2132 const char *p = recog_data.constraints[0]; 2133 recog_data.n_alternatives = 1; 2134 while (*p) 2135 recog_data.n_alternatives += (*p++ == ','); 2136 } 2137 break; 2138 } 2139 fatal_insn_not_found (insn); 2140 2141 default: 2142 normal_insn: 2143 /* Ordinary insn: recognize it, get the operands via insn_extract 2144 and get the constraints. */ 2145 2146 icode = recog_memoized (insn); 2147 if (icode < 0) 2148 fatal_insn_not_found (insn); 2149 2150 recog_data.n_operands = noperands = insn_data[icode].n_operands; 2151 recog_data.n_alternatives = insn_data[icode].n_alternatives; 2152 recog_data.n_dups = insn_data[icode].n_dups; 2153 2154 insn_extract (insn); 2155 2156 for (i = 0; i < noperands; i++) 2157 { 2158 recog_data.constraints[i] = insn_data[icode].operand[i].constraint; 2159 recog_data.operand_mode[i] = insn_data[icode].operand[i].mode; 2160 /* VOIDmode match_operands gets mode from their real operand. */ 2161 if (recog_data.operand_mode[i] == VOIDmode) 2162 recog_data.operand_mode[i] = GET_MODE (recog_data.operand[i]); 2163 } 2164 } 2165 for (i = 0; i < noperands; i++) 2166 recog_data.operand_type[i] 2167 = (recog_data.constraints[i][0] == '=' ? OP_OUT 2168 : recog_data.constraints[i][0] == '+' ? OP_INOUT 2169 : OP_IN); 2170 2171 if (recog_data.n_alternatives > MAX_RECOG_ALTERNATIVES) 2172 abort (); 2173} 2174 2175/* After calling extract_insn, you can use this function to extract some 2176 information from the constraint strings into a more usable form. 2177 The collected data is stored in recog_op_alt. */ 2178void 2179preprocess_constraints () 2180{ 2181 int i; 2182 2183 memset (recog_op_alt, 0, sizeof recog_op_alt); 2184 for (i = 0; i < recog_data.n_operands; i++) 2185 { 2186 int j; 2187 struct operand_alternative *op_alt; 2188 const char *p = recog_data.constraints[i]; 2189 2190 op_alt = recog_op_alt[i]; 2191 2192 for (j = 0; j < recog_data.n_alternatives; j++) 2193 { 2194 op_alt[j].class = NO_REGS; 2195 op_alt[j].constraint = p; 2196 op_alt[j].matches = -1; 2197 op_alt[j].matched = -1; 2198 2199 if (*p == '\0' || *p == ',') 2200 { 2201 op_alt[j].anything_ok = 1; 2202 continue; 2203 } 2204 2205 for (;;) 2206 { 2207 char c = *p++; 2208 if (c == '#') 2209 do 2210 c = *p++; 2211 while (c != ',' && c != '\0'); 2212 if (c == ',' || c == '\0') 2213 break; 2214 2215 switch (c) 2216 { 2217 case '=': case '+': case '*': case '%': 2218 case 'E': case 'F': case 'G': case 'H': 2219 case 's': case 'i': case 'n': 2220 case 'I': case 'J': case 'K': case 'L': 2221 case 'M': case 'N': case 'O': case 'P': 2222 /* These don't say anything we care about. */ 2223 break; 2224 2225 case '?': 2226 op_alt[j].reject += 6; 2227 break; 2228 case '!': 2229 op_alt[j].reject += 600; 2230 break; 2231 case '&': 2232 op_alt[j].earlyclobber = 1; 2233 break; 2234 2235 case '0': case '1': case '2': case '3': case '4': 2236 case '5': case '6': case '7': case '8': case '9': 2237 { 2238 char *end; 2239 op_alt[j].matches = strtoul (p - 1, &end, 10); 2240 recog_op_alt[op_alt[j].matches][j].matched = i; 2241 p = end; 2242 } 2243 break; 2244 2245 case 'm': 2246 op_alt[j].memory_ok = 1; 2247 break; 2248 case '<': 2249 op_alt[j].decmem_ok = 1; 2250 break; 2251 case '>': 2252 op_alt[j].incmem_ok = 1; 2253 break; 2254 case 'V': 2255 op_alt[j].nonoffmem_ok = 1; 2256 break; 2257 case 'o': 2258 op_alt[j].offmem_ok = 1; 2259 break; 2260 case 'X': 2261 op_alt[j].anything_ok = 1; 2262 break; 2263 2264 case 'p': 2265 op_alt[j].is_address = 1; 2266 op_alt[j].class = reg_class_subunion[(int) op_alt[j].class] 2267 [(int) MODE_BASE_REG_CLASS (VOIDmode)]; 2268 break; 2269 2270 case 'g': case 'r': 2271 op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) GENERAL_REGS]; 2272 break; 2273 2274 default: 2275 op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) REG_CLASS_FROM_LETTER ((unsigned char) c)]; 2276 break; 2277 } 2278 } 2279 } 2280 } 2281} 2282 2283/* Check the operands of an insn against the insn's operand constraints 2284 and return 1 if they are valid. 2285 The information about the insn's operands, constraints, operand modes 2286 etc. is obtained from the global variables set up by extract_insn. 2287 2288 WHICH_ALTERNATIVE is set to a number which indicates which 2289 alternative of constraints was matched: 0 for the first alternative, 2290 1 for the next, etc. 2291 2292 In addition, when two operands are match 2293 and it happens that the output operand is (reg) while the 2294 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec), 2295 make the output operand look like the input. 2296 This is because the output operand is the one the template will print. 2297 2298 This is used in final, just before printing the assembler code and by 2299 the routines that determine an insn's attribute. 2300 2301 If STRICT is a positive non-zero value, it means that we have been 2302 called after reload has been completed. In that case, we must 2303 do all checks strictly. If it is zero, it means that we have been called 2304 before reload has completed. In that case, we first try to see if we can 2305 find an alternative that matches strictly. If not, we try again, this 2306 time assuming that reload will fix up the insn. This provides a "best 2307 guess" for the alternative and is used to compute attributes of insns prior 2308 to reload. A negative value of STRICT is used for this internal call. */ 2309 2310struct funny_match 2311{ 2312 int this, other; 2313}; 2314 2315int 2316constrain_operands (strict) 2317 int strict; 2318{ 2319 const char *constraints[MAX_RECOG_OPERANDS]; 2320 int matching_operands[MAX_RECOG_OPERANDS]; 2321 int earlyclobber[MAX_RECOG_OPERANDS]; 2322 int c; 2323 2324 struct funny_match funny_match[MAX_RECOG_OPERANDS]; 2325 int funny_match_index; 2326 2327 which_alternative = 0; 2328 if (recog_data.n_operands == 0 || recog_data.n_alternatives == 0) 2329 return 1; 2330 2331 for (c = 0; c < recog_data.n_operands; c++) 2332 { 2333 constraints[c] = recog_data.constraints[c]; 2334 matching_operands[c] = -1; 2335 } 2336 2337 do 2338 { 2339 int opno; 2340 int lose = 0; 2341 funny_match_index = 0; 2342 2343 for (opno = 0; opno < recog_data.n_operands; opno++) 2344 { 2345 rtx op = recog_data.operand[opno]; 2346 enum machine_mode mode = GET_MODE (op); 2347 const char *p = constraints[opno]; 2348 int offset = 0; 2349 int win = 0; 2350 int val; 2351 2352 earlyclobber[opno] = 0; 2353 2354 /* A unary operator may be accepted by the predicate, but it 2355 is irrelevant for matching constraints. */ 2356 if (GET_RTX_CLASS (GET_CODE (op)) == '1') 2357 op = XEXP (op, 0); 2358 2359 if (GET_CODE (op) == SUBREG) 2360 { 2361 if (GET_CODE (SUBREG_REG (op)) == REG 2362 && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER) 2363 offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), 2364 GET_MODE (SUBREG_REG (op)), 2365 SUBREG_BYTE (op), 2366 GET_MODE (op)); 2367 op = SUBREG_REG (op); 2368 } 2369 2370 /* An empty constraint or empty alternative 2371 allows anything which matched the pattern. */ 2372 if (*p == 0 || *p == ',') 2373 win = 1; 2374 2375 while (*p && (c = *p++) != ',') 2376 switch (c) 2377 { 2378 case '?': case '!': case '*': case '%': 2379 case '=': case '+': 2380 break; 2381 2382 case '#': 2383 /* Ignore rest of this alternative as far as 2384 constraint checking is concerned. */ 2385 while (*p && *p != ',') 2386 p++; 2387 break; 2388 2389 case '&': 2390 earlyclobber[opno] = 1; 2391 break; 2392 2393 case '0': case '1': case '2': case '3': case '4': 2394 case '5': case '6': case '7': case '8': case '9': 2395 { 2396 /* This operand must be the same as a previous one. 2397 This kind of constraint is used for instructions such 2398 as add when they take only two operands. 2399 2400 Note that the lower-numbered operand is passed first. 2401 2402 If we are not testing strictly, assume that this 2403 constraint will be satisfied. */ 2404 2405 char *end; 2406 int match; 2407 2408 match = strtoul (p - 1, &end, 10); 2409 p = end; 2410 2411 if (strict < 0) 2412 val = 1; 2413 else 2414 { 2415 rtx op1 = recog_data.operand[match]; 2416 rtx op2 = recog_data.operand[opno]; 2417 2418 /* A unary operator may be accepted by the predicate, 2419 but it is irrelevant for matching constraints. */ 2420 if (GET_RTX_CLASS (GET_CODE (op1)) == '1') 2421 op1 = XEXP (op1, 0); 2422 if (GET_RTX_CLASS (GET_CODE (op2)) == '1') 2423 op2 = XEXP (op2, 0); 2424 2425 val = operands_match_p (op1, op2); 2426 } 2427 2428 matching_operands[opno] = match; 2429 matching_operands[match] = opno; 2430 2431 if (val != 0) 2432 win = 1; 2433 2434 /* If output is *x and input is *--x, arrange later 2435 to change the output to *--x as well, since the 2436 output op is the one that will be printed. */ 2437 if (val == 2 && strict > 0) 2438 { 2439 funny_match[funny_match_index].this = opno; 2440 funny_match[funny_match_index++].other = match; 2441 } 2442 } 2443 break; 2444 2445 case 'p': 2446 /* p is used for address_operands. When we are called by 2447 gen_reload, no one will have checked that the address is 2448 strictly valid, i.e., that all pseudos requiring hard regs 2449 have gotten them. */ 2450 if (strict <= 0 2451 || (strict_memory_address_p (recog_data.operand_mode[opno], 2452 op))) 2453 win = 1; 2454 break; 2455 2456 /* No need to check general_operand again; 2457 it was done in insn-recog.c. */ 2458 case 'g': 2459 /* Anything goes unless it is a REG and really has a hard reg 2460 but the hard reg is not in the class GENERAL_REGS. */ 2461 if (strict < 0 2462 || GENERAL_REGS == ALL_REGS 2463 || GET_CODE (op) != REG 2464 || (reload_in_progress 2465 && REGNO (op) >= FIRST_PSEUDO_REGISTER) 2466 || reg_fits_class_p (op, GENERAL_REGS, offset, mode)) 2467 win = 1; 2468 break; 2469 2470 case 'X': 2471 /* This is used for a MATCH_SCRATCH in the cases when 2472 we don't actually need anything. So anything goes 2473 any time. */ 2474 win = 1; 2475 break; 2476 2477 case 'm': 2478 if (GET_CODE (op) == MEM 2479 /* Before reload, accept what reload can turn into mem. */ 2480 || (strict < 0 && CONSTANT_P (op)) 2481 /* During reload, accept a pseudo */ 2482 || (reload_in_progress && GET_CODE (op) == REG 2483 && REGNO (op) >= FIRST_PSEUDO_REGISTER)) 2484 win = 1; 2485 break; 2486 2487 case '<': 2488 if (GET_CODE (op) == MEM 2489 && (GET_CODE (XEXP (op, 0)) == PRE_DEC 2490 || GET_CODE (XEXP (op, 0)) == POST_DEC)) 2491 win = 1; 2492 break; 2493 2494 case '>': 2495 if (GET_CODE (op) == MEM 2496 && (GET_CODE (XEXP (op, 0)) == PRE_INC 2497 || GET_CODE (XEXP (op, 0)) == POST_INC)) 2498 win = 1; 2499 break; 2500 2501 case 'E': 2502#ifndef REAL_ARITHMETIC 2503 /* Match any CONST_DOUBLE, but only if 2504 we can examine the bits of it reliably. */ 2505 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT 2506 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) 2507 && GET_MODE (op) != VOIDmode && ! flag_pretend_float) 2508 break; 2509#endif 2510 if (GET_CODE (op) == CONST_DOUBLE) 2511 win = 1; 2512 break; 2513 2514 case 'F': 2515 if (GET_CODE (op) == CONST_DOUBLE) 2516 win = 1; 2517 break; 2518 2519 case 'G': 2520 case 'H': 2521 if (GET_CODE (op) == CONST_DOUBLE 2522 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c)) 2523 win = 1; 2524 break; 2525 2526 case 's': 2527 if (GET_CODE (op) == CONST_INT 2528 || (GET_CODE (op) == CONST_DOUBLE 2529 && GET_MODE (op) == VOIDmode)) 2530 break; 2531 case 'i': 2532 if (CONSTANT_P (op)) 2533 win = 1; 2534 break; 2535 2536 case 'n': 2537 if (GET_CODE (op) == CONST_INT 2538 || (GET_CODE (op) == CONST_DOUBLE 2539 && GET_MODE (op) == VOIDmode)) 2540 win = 1; 2541 break; 2542 2543 case 'I': 2544 case 'J': 2545 case 'K': 2546 case 'L': 2547 case 'M': 2548 case 'N': 2549 case 'O': 2550 case 'P': 2551 if (GET_CODE (op) == CONST_INT 2552 && CONST_OK_FOR_LETTER_P (INTVAL (op), c)) 2553 win = 1; 2554 break; 2555 2556 case 'V': 2557 if (GET_CODE (op) == MEM 2558 && ((strict > 0 && ! offsettable_memref_p (op)) 2559 || (strict < 0 2560 && !(CONSTANT_P (op) || GET_CODE (op) == MEM)) 2561 || (reload_in_progress 2562 && !(GET_CODE (op) == REG 2563 && REGNO (op) >= FIRST_PSEUDO_REGISTER)))) 2564 win = 1; 2565 break; 2566 2567 case 'o': 2568 if ((strict > 0 && offsettable_memref_p (op)) 2569 || (strict == 0 && offsettable_nonstrict_memref_p (op)) 2570 /* Before reload, accept what reload can handle. */ 2571 || (strict < 0 2572 && (CONSTANT_P (op) || GET_CODE (op) == MEM)) 2573 /* During reload, accept a pseudo */ 2574 || (reload_in_progress && GET_CODE (op) == REG 2575 && REGNO (op) >= FIRST_PSEUDO_REGISTER)) 2576 win = 1; 2577 break; 2578 2579 default: 2580 { 2581 enum reg_class class; 2582 2583 class = (c == 'r' ? GENERAL_REGS : REG_CLASS_FROM_LETTER (c)); 2584 if (class != NO_REGS) 2585 { 2586 if (strict < 0 2587 || (strict == 0 2588 && GET_CODE (op) == REG 2589 && REGNO (op) >= FIRST_PSEUDO_REGISTER) 2590 || (strict == 0 && GET_CODE (op) == SCRATCH) 2591 || (GET_CODE (op) == REG 2592 && reg_fits_class_p (op, class, offset, mode))) 2593 win = 1; 2594 } 2595#ifdef EXTRA_CONSTRAINT 2596 else if (EXTRA_CONSTRAINT (op, c)) 2597 win = 1; 2598#endif 2599 break; 2600 } 2601 } 2602 2603 constraints[opno] = p; 2604 /* If this operand did not win somehow, 2605 this alternative loses. */ 2606 if (! win) 2607 lose = 1; 2608 } 2609 /* This alternative won; the operands are ok. 2610 Change whichever operands this alternative says to change. */ 2611 if (! lose) 2612 { 2613 int opno, eopno; 2614 2615 /* See if any earlyclobber operand conflicts with some other 2616 operand. */ 2617 2618 if (strict > 0) 2619 for (eopno = 0; eopno < recog_data.n_operands; eopno++) 2620 /* Ignore earlyclobber operands now in memory, 2621 because we would often report failure when we have 2622 two memory operands, one of which was formerly a REG. */ 2623 if (earlyclobber[eopno] 2624 && GET_CODE (recog_data.operand[eopno]) == REG) 2625 for (opno = 0; opno < recog_data.n_operands; opno++) 2626 if ((GET_CODE (recog_data.operand[opno]) == MEM 2627 || recog_data.operand_type[opno] != OP_OUT) 2628 && opno != eopno 2629 /* Ignore things like match_operator operands. */ 2630 && *recog_data.constraints[opno] != 0 2631 && ! (matching_operands[opno] == eopno 2632 && operands_match_p (recog_data.operand[opno], 2633 recog_data.operand[eopno])) 2634 && ! safe_from_earlyclobber (recog_data.operand[opno], 2635 recog_data.operand[eopno])) 2636 lose = 1; 2637 2638 if (! lose) 2639 { 2640 while (--funny_match_index >= 0) 2641 { 2642 recog_data.operand[funny_match[funny_match_index].other] 2643 = recog_data.operand[funny_match[funny_match_index].this]; 2644 } 2645 2646 return 1; 2647 } 2648 } 2649 2650 which_alternative++; 2651 } 2652 while (which_alternative < recog_data.n_alternatives); 2653 2654 which_alternative = -1; 2655 /* If we are about to reject this, but we are not to test strictly, 2656 try a very loose test. Only return failure if it fails also. */ 2657 if (strict == 0) 2658 return constrain_operands (-1); 2659 else 2660 return 0; 2661} 2662 2663/* Return 1 iff OPERAND (assumed to be a REG rtx) 2664 is a hard reg in class CLASS when its regno is offset by OFFSET 2665 and changed to mode MODE. 2666 If REG occupies multiple hard regs, all of them must be in CLASS. */ 2667 2668int 2669reg_fits_class_p (operand, class, offset, mode) 2670 rtx operand; 2671 enum reg_class class; 2672 int offset; 2673 enum machine_mode mode; 2674{ 2675 int regno = REGNO (operand); 2676 if (regno < FIRST_PSEUDO_REGISTER 2677 && TEST_HARD_REG_BIT (reg_class_contents[(int) class], 2678 regno + offset)) 2679 { 2680 int sr; 2681 regno += offset; 2682 for (sr = HARD_REGNO_NREGS (regno, mode) - 1; 2683 sr > 0; sr--) 2684 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], 2685 regno + sr)) 2686 break; 2687 return sr == 0; 2688 } 2689 2690 return 0; 2691} 2692 2693/* Split single instruction. Helper function for split_all_insns. 2694 Return last insn in the sequence if successful, or NULL if unsuccessful. */ 2695static rtx 2696split_insn (insn) 2697 rtx insn; 2698{ 2699 rtx set; 2700 if (!INSN_P (insn)) 2701 ; 2702 /* Don't split no-op move insns. These should silently 2703 disappear later in final. Splitting such insns would 2704 break the code that handles REG_NO_CONFLICT blocks. */ 2705 2706 else if ((set = single_set (insn)) != NULL && set_noop_p (set)) 2707 { 2708 /* Nops get in the way while scheduling, so delete them 2709 now if register allocation has already been done. It 2710 is too risky to try to do this before register 2711 allocation, and there are unlikely to be very many 2712 nops then anyways. */ 2713 if (reload_completed) 2714 { 2715 PUT_CODE (insn, NOTE); 2716 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; 2717 NOTE_SOURCE_FILE (insn) = 0; 2718 } 2719 } 2720 else 2721 { 2722 /* Split insns here to get max fine-grain parallelism. */ 2723 rtx first = PREV_INSN (insn); 2724 rtx last = try_split (PATTERN (insn), insn, 1); 2725 2726 if (last != insn) 2727 { 2728 /* try_split returns the NOTE that INSN became. */ 2729 PUT_CODE (insn, NOTE); 2730 NOTE_SOURCE_FILE (insn) = 0; 2731 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; 2732 2733 /* ??? Coddle to md files that generate subregs in post- 2734 reload splitters instead of computing the proper 2735 hard register. */ 2736 if (reload_completed && first != last) 2737 { 2738 first = NEXT_INSN (first); 2739 while (1) 2740 { 2741 if (INSN_P (first)) 2742 cleanup_subreg_operands (first); 2743 if (first == last) 2744 break; 2745 first = NEXT_INSN (first); 2746 } 2747 } 2748 return last; 2749 } 2750 } 2751 return NULL_RTX; 2752} 2753/* Split all insns in the function. If UPD_LIFE, update life info after. */ 2754 2755void 2756split_all_insns (upd_life) 2757 int upd_life; 2758{ 2759 sbitmap blocks; 2760 int changed; 2761 int i; 2762 2763 blocks = sbitmap_alloc (n_basic_blocks); 2764 sbitmap_zero (blocks); 2765 changed = 0; 2766 2767 for (i = n_basic_blocks - 1; i >= 0; --i) 2768 { 2769 basic_block bb = BASIC_BLOCK (i); 2770 rtx insn, next; 2771 2772 for (insn = bb->head; insn ; insn = next) 2773 { 2774 rtx last; 2775 2776 /* Can't use `next_real_insn' because that might go across 2777 CODE_LABELS and short-out basic blocks. */ 2778 next = NEXT_INSN (insn); 2779 last = split_insn (insn); 2780 if (last) 2781 { 2782 /* The split sequence may include barrier, but the 2783 BB boundary we are interested in will be set to previous 2784 one. */ 2785 2786 while (GET_CODE (last) == BARRIER) 2787 last = PREV_INSN (last); 2788 SET_BIT (blocks, i); 2789 changed = 1; 2790 insn = last; 2791 } 2792 2793 if (insn == bb->end) 2794 break; 2795 } 2796 2797 if (insn == NULL) 2798 abort (); 2799 } 2800 2801 if (changed) 2802 { 2803 find_many_sub_basic_blocks (blocks); 2804 } 2805 2806 if (changed && upd_life) 2807 { 2808 count_or_remove_death_notes (blocks, 1); 2809 update_life_info (blocks, UPDATE_LIFE_LOCAL, PROP_DEATH_NOTES); 2810 } 2811#ifdef ENABLE_CHECKING 2812 verify_flow_info (); 2813#endif 2814 2815 sbitmap_free (blocks); 2816} 2817 2818/* Same as split_all_insns, but do not expect CFG to be available. 2819 Used by machine depedent reorg passes. */ 2820 2821void 2822split_all_insns_noflow () 2823{ 2824 rtx next, insn; 2825 2826 for (insn = get_insns (); insn; insn = next) 2827 { 2828 next = NEXT_INSN (insn); 2829 split_insn (insn); 2830 } 2831 return; 2832} 2833 2834#ifdef HAVE_peephole2 2835struct peep2_insn_data 2836{ 2837 rtx insn; 2838 regset live_before; 2839}; 2840 2841static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1]; 2842static int peep2_current; 2843 2844/* A non-insn marker indicating the last insn of the block. 2845 The live_before regset for this element is correct, indicating 2846 global_live_at_end for the block. */ 2847#define PEEP2_EOB pc_rtx 2848 2849/* Return the Nth non-note insn after `current', or return NULL_RTX if it 2850 does not exist. Used by the recognizer to find the next insn to match 2851 in a multi-insn pattern. */ 2852 2853rtx 2854peep2_next_insn (n) 2855 int n; 2856{ 2857 if (n >= MAX_INSNS_PER_PEEP2 + 1) 2858 abort (); 2859 2860 n += peep2_current; 2861 if (n >= MAX_INSNS_PER_PEEP2 + 1) 2862 n -= MAX_INSNS_PER_PEEP2 + 1; 2863 2864 if (peep2_insn_data[n].insn == PEEP2_EOB) 2865 return NULL_RTX; 2866 return peep2_insn_data[n].insn; 2867} 2868 2869/* Return true if REGNO is dead before the Nth non-note insn 2870 after `current'. */ 2871 2872int 2873peep2_regno_dead_p (ofs, regno) 2874 int ofs; 2875 int regno; 2876{ 2877 if (ofs >= MAX_INSNS_PER_PEEP2 + 1) 2878 abort (); 2879 2880 ofs += peep2_current; 2881 if (ofs >= MAX_INSNS_PER_PEEP2 + 1) 2882 ofs -= MAX_INSNS_PER_PEEP2 + 1; 2883 2884 if (peep2_insn_data[ofs].insn == NULL_RTX) 2885 abort (); 2886 2887 return ! REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno); 2888} 2889 2890/* Similarly for a REG. */ 2891 2892int 2893peep2_reg_dead_p (ofs, reg) 2894 int ofs; 2895 rtx reg; 2896{ 2897 int regno, n; 2898 2899 if (ofs >= MAX_INSNS_PER_PEEP2 + 1) 2900 abort (); 2901 2902 ofs += peep2_current; 2903 if (ofs >= MAX_INSNS_PER_PEEP2 + 1) 2904 ofs -= MAX_INSNS_PER_PEEP2 + 1; 2905 2906 if (peep2_insn_data[ofs].insn == NULL_RTX) 2907 abort (); 2908 2909 regno = REGNO (reg); 2910 n = HARD_REGNO_NREGS (regno, GET_MODE (reg)); 2911 while (--n >= 0) 2912 if (REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno + n)) 2913 return 0; 2914 return 1; 2915} 2916 2917/* Try to find a hard register of mode MODE, matching the register class in 2918 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and 2919 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX, 2920 in which case the only condition is that the register must be available 2921 before CURRENT_INSN. 2922 Registers that already have bits set in REG_SET will not be considered. 2923 2924 If an appropriate register is available, it will be returned and the 2925 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is 2926 returned. */ 2927 2928rtx 2929peep2_find_free_register (from, to, class_str, mode, reg_set) 2930 int from, to; 2931 const char *class_str; 2932 enum machine_mode mode; 2933 HARD_REG_SET *reg_set; 2934{ 2935 static int search_ofs; 2936 enum reg_class class; 2937 HARD_REG_SET live; 2938 int i; 2939 2940 if (from >= MAX_INSNS_PER_PEEP2 + 1 || to >= MAX_INSNS_PER_PEEP2 + 1) 2941 abort (); 2942 2943 from += peep2_current; 2944 if (from >= MAX_INSNS_PER_PEEP2 + 1) 2945 from -= MAX_INSNS_PER_PEEP2 + 1; 2946 to += peep2_current; 2947 if (to >= MAX_INSNS_PER_PEEP2 + 1) 2948 to -= MAX_INSNS_PER_PEEP2 + 1; 2949 2950 if (peep2_insn_data[from].insn == NULL_RTX) 2951 abort (); 2952 REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before); 2953 2954 while (from != to) 2955 { 2956 HARD_REG_SET this_live; 2957 2958 if (++from >= MAX_INSNS_PER_PEEP2 + 1) 2959 from = 0; 2960 if (peep2_insn_data[from].insn == NULL_RTX) 2961 abort (); 2962 REG_SET_TO_HARD_REG_SET (this_live, peep2_insn_data[from].live_before); 2963 IOR_HARD_REG_SET (live, this_live); 2964 } 2965 2966 class = (class_str[0] == 'r' ? GENERAL_REGS 2967 : REG_CLASS_FROM_LETTER (class_str[0])); 2968 2969 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 2970 { 2971 int raw_regno, regno, success, j; 2972 2973 /* Distribute the free registers as much as possible. */ 2974 raw_regno = search_ofs + i; 2975 if (raw_regno >= FIRST_PSEUDO_REGISTER) 2976 raw_regno -= FIRST_PSEUDO_REGISTER; 2977#ifdef REG_ALLOC_ORDER 2978 regno = reg_alloc_order[raw_regno]; 2979#else 2980 regno = raw_regno; 2981#endif 2982 2983 /* Don't allocate fixed registers. */ 2984 if (fixed_regs[regno]) 2985 continue; 2986 /* Make sure the register is of the right class. */ 2987 if (! TEST_HARD_REG_BIT (reg_class_contents[class], regno)) 2988 continue; 2989 /* And can support the mode we need. */ 2990 if (! HARD_REGNO_MODE_OK (regno, mode)) 2991 continue; 2992 /* And that we don't create an extra save/restore. */ 2993 if (! call_used_regs[regno] && ! regs_ever_live[regno]) 2994 continue; 2995 /* And we don't clobber traceback for noreturn functions. */ 2996 if ((regno == FRAME_POINTER_REGNUM || regno == HARD_FRAME_POINTER_REGNUM) 2997 && (! reload_completed || frame_pointer_needed)) 2998 continue; 2999 3000 success = 1; 3001 for (j = HARD_REGNO_NREGS (regno, mode) - 1; j >= 0; j--) 3002 { 3003 if (TEST_HARD_REG_BIT (*reg_set, regno + j) 3004 || TEST_HARD_REG_BIT (live, regno + j)) 3005 { 3006 success = 0; 3007 break; 3008 } 3009 } 3010 if (success) 3011 { 3012 for (j = HARD_REGNO_NREGS (regno, mode) - 1; j >= 0; j--) 3013 SET_HARD_REG_BIT (*reg_set, regno + j); 3014 3015 /* Start the next search with the next register. */ 3016 if (++raw_regno >= FIRST_PSEUDO_REGISTER) 3017 raw_regno = 0; 3018 search_ofs = raw_regno; 3019 3020 return gen_rtx_REG (mode, regno); 3021 } 3022 } 3023 3024 search_ofs = 0; 3025 return NULL_RTX; 3026} 3027 3028/* Perform the peephole2 optimization pass. */ 3029 3030void 3031peephole2_optimize (dump_file) 3032 FILE *dump_file ATTRIBUTE_UNUSED; 3033{ 3034 regset_head rs_heads[MAX_INSNS_PER_PEEP2 + 2]; 3035 rtx insn, prev; 3036 regset live; 3037 int i, b; 3038#ifdef HAVE_conditional_execution 3039 sbitmap blocks; 3040 bool changed; 3041#endif 3042 bool do_cleanup_cfg = false; 3043 bool do_rebuild_jump_labels = false; 3044 3045 /* Initialize the regsets we're going to use. */ 3046 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i) 3047 peep2_insn_data[i].live_before = INITIALIZE_REG_SET (rs_heads[i]); 3048 live = INITIALIZE_REG_SET (rs_heads[i]); 3049 3050#ifdef HAVE_conditional_execution 3051 blocks = sbitmap_alloc (n_basic_blocks); 3052 sbitmap_zero (blocks); 3053 changed = false; 3054#else 3055 count_or_remove_death_notes (NULL, 1); 3056#endif 3057 3058 for (b = n_basic_blocks - 1; b >= 0; --b) 3059 { 3060 basic_block bb = BASIC_BLOCK (b); 3061 struct propagate_block_info *pbi; 3062 3063 /* Indicate that all slots except the last holds invalid data. */ 3064 for (i = 0; i < MAX_INSNS_PER_PEEP2; ++i) 3065 peep2_insn_data[i].insn = NULL_RTX; 3066 3067 /* Indicate that the last slot contains live_after data. */ 3068 peep2_insn_data[MAX_INSNS_PER_PEEP2].insn = PEEP2_EOB; 3069 peep2_current = MAX_INSNS_PER_PEEP2; 3070 3071 /* Start up propagation. */ 3072 COPY_REG_SET (live, bb->global_live_at_end); 3073 COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live); 3074 3075#ifdef HAVE_conditional_execution 3076 pbi = init_propagate_block_info (bb, live, NULL, NULL, 0); 3077#else 3078 pbi = init_propagate_block_info (bb, live, NULL, NULL, PROP_DEATH_NOTES); 3079#endif 3080 3081 for (insn = bb->end; ; insn = prev) 3082 { 3083 prev = PREV_INSN (insn); 3084 if (INSN_P (insn)) 3085 { 3086 rtx try, before_try, x; 3087 int match_len; 3088 rtx note; 3089 3090 /* Record this insn. */ 3091 if (--peep2_current < 0) 3092 peep2_current = MAX_INSNS_PER_PEEP2; 3093 peep2_insn_data[peep2_current].insn = insn; 3094 propagate_one_insn (pbi, insn); 3095 COPY_REG_SET (peep2_insn_data[peep2_current].live_before, live); 3096 3097 /* Match the peephole. */ 3098 try = peephole2_insns (PATTERN (insn), insn, &match_len); 3099 if (try != NULL) 3100 { 3101 /* If we are splitting a CALL_INSN, look for the CALL_INSN 3102 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other 3103 cfg-related call notes. */ 3104 for (i = 0; i <= match_len; ++i) 3105 { 3106 int j, k; 3107 rtx old_insn, new_insn, note; 3108 3109 j = i + peep2_current; 3110 if (j >= MAX_INSNS_PER_PEEP2 + 1) 3111 j -= MAX_INSNS_PER_PEEP2 + 1; 3112 old_insn = peep2_insn_data[j].insn; 3113 if (GET_CODE (old_insn) != CALL_INSN) 3114 continue; 3115 3116 new_insn = NULL_RTX; 3117 if (GET_CODE (try) == SEQUENCE) 3118 for (k = XVECLEN (try, 0) - 1; k >= 0; k--) 3119 { 3120 rtx x = XVECEXP (try, 0, k); 3121 if (GET_CODE (x) == CALL_INSN) 3122 { 3123 new_insn = x; 3124 break; 3125 } 3126 } 3127 else if (GET_CODE (try) == CALL_INSN) 3128 new_insn = try; 3129 if (! new_insn) 3130 abort (); 3131 3132 CALL_INSN_FUNCTION_USAGE (new_insn) 3133 = CALL_INSN_FUNCTION_USAGE (old_insn); 3134 3135 for (note = REG_NOTES (old_insn); 3136 note; 3137 note = XEXP (note, 1)) 3138 switch (REG_NOTE_KIND (note)) 3139 { 3140 case REG_NORETURN: 3141 case REG_SETJMP: 3142 case REG_ALWAYS_RETURN: 3143 REG_NOTES (new_insn) 3144 = gen_rtx_EXPR_LIST (REG_NOTE_KIND (note), 3145 XEXP (note, 0), 3146 REG_NOTES (new_insn)); 3147 default: 3148 /* Discard all other reg notes. */ 3149 break; 3150 } 3151 3152 /* Croak if there is another call in the sequence. */ 3153 while (++i <= match_len) 3154 { 3155 j = i + peep2_current; 3156 if (j >= MAX_INSNS_PER_PEEP2 + 1) 3157 j -= MAX_INSNS_PER_PEEP2 + 1; 3158 old_insn = peep2_insn_data[j].insn; 3159 if (GET_CODE (old_insn) == CALL_INSN) 3160 abort (); 3161 } 3162 break; 3163 } 3164 3165 i = match_len + peep2_current; 3166 if (i >= MAX_INSNS_PER_PEEP2 + 1) 3167 i -= MAX_INSNS_PER_PEEP2 + 1; 3168 3169 note = find_reg_note (peep2_insn_data[i].insn, 3170 REG_EH_REGION, NULL_RTX); 3171 3172 /* Replace the old sequence with the new. */ 3173 try = emit_insn_after (try, peep2_insn_data[i].insn); 3174 before_try = PREV_INSN (insn); 3175 delete_insn_chain (insn, peep2_insn_data[i].insn); 3176 3177 /* Re-insert the EH_REGION notes. */ 3178 if (note) 3179 { 3180 edge eh_edge; 3181 3182 for (eh_edge = bb->succ; eh_edge 3183 ; eh_edge = eh_edge->succ_next) 3184 if (eh_edge->flags & EDGE_EH) 3185 break; 3186 3187 for (x = try ; x != before_try ; x = PREV_INSN (x)) 3188 if (GET_CODE (x) == CALL_INSN 3189 || (flag_non_call_exceptions 3190 && may_trap_p (PATTERN (x)) 3191 && !find_reg_note (x, REG_EH_REGION, NULL))) 3192 { 3193 REG_NOTES (x) 3194 = gen_rtx_EXPR_LIST (REG_EH_REGION, 3195 XEXP (note, 0), 3196 REG_NOTES (x)); 3197 3198 if (x != bb->end && eh_edge) 3199 { 3200 edge nfte, nehe; 3201 int flags; 3202 3203 nfte = split_block (bb, x); 3204 flags = EDGE_EH | EDGE_ABNORMAL; 3205 if (GET_CODE (x) == CALL_INSN) 3206 flags |= EDGE_ABNORMAL_CALL; 3207 nehe = make_edge (nfte->src, eh_edge->dest, 3208 flags); 3209 3210 nehe->probability = eh_edge->probability; 3211 nfte->probability 3212 = REG_BR_PROB_BASE - nehe->probability; 3213 3214 do_cleanup_cfg |= purge_dead_edges (nfte->dest); 3215#ifdef HAVE_conditional_execution 3216 SET_BIT (blocks, nfte->dest->index); 3217 changed = true; 3218#endif 3219 bb = nfte->src; 3220 eh_edge = nehe; 3221 } 3222 } 3223 3224 /* Converting possibly trapping insn to non-trapping is 3225 possible. Zap dummy outgoing edges. */ 3226 do_cleanup_cfg |= purge_dead_edges (bb); 3227 } 3228 3229#ifdef HAVE_conditional_execution 3230 /* With conditional execution, we cannot back up the 3231 live information so easily, since the conditional 3232 death data structures are not so self-contained. 3233 So record that we've made a modification to this 3234 block and update life information at the end. */ 3235 SET_BIT (blocks, b); 3236 changed = true; 3237 3238 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i) 3239 peep2_insn_data[i].insn = NULL_RTX; 3240 peep2_insn_data[peep2_current].insn = PEEP2_EOB; 3241#else 3242 /* Back up lifetime information past the end of the 3243 newly created sequence. */ 3244 if (++i >= MAX_INSNS_PER_PEEP2 + 1) 3245 i = 0; 3246 COPY_REG_SET (live, peep2_insn_data[i].live_before); 3247 3248 /* Update life information for the new sequence. */ 3249 x = try; 3250 do 3251 { 3252 if (INSN_P (x)) 3253 { 3254 if (--i < 0) 3255 i = MAX_INSNS_PER_PEEP2; 3256 peep2_insn_data[i].insn = x; 3257 propagate_one_insn (pbi, x); 3258 COPY_REG_SET (peep2_insn_data[i].live_before, live); 3259 } 3260 x = PREV_INSN (x); 3261 } 3262 while (x != prev); 3263 3264 /* ??? Should verify that LIVE now matches what we 3265 had before the new sequence. */ 3266 3267 peep2_current = i; 3268#endif 3269 3270 /* If we generated a jump instruction, it won't have 3271 JUMP_LABEL set. Recompute after we're done. */ 3272 for (x = try; x != before_try; x = PREV_INSN (x)) 3273 if (GET_CODE (x) == JUMP_INSN) 3274 { 3275 do_rebuild_jump_labels = true; 3276 break; 3277 } 3278 } 3279 } 3280 3281 if (insn == bb->head) 3282 break; 3283 } 3284 3285 free_propagate_block_info (pbi); 3286 } 3287 3288 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i) 3289 FREE_REG_SET (peep2_insn_data[i].live_before); 3290 FREE_REG_SET (live); 3291 3292 if (do_rebuild_jump_labels) 3293 rebuild_jump_labels (get_insns ()); 3294 3295 /* If we eliminated EH edges, we may be able to merge blocks. Further, 3296 we've changed global life since exception handlers are no longer 3297 reachable. */ 3298 if (do_cleanup_cfg) 3299 { 3300 cleanup_cfg (0); 3301 update_life_info (0, UPDATE_LIFE_GLOBAL_RM_NOTES, PROP_DEATH_NOTES); 3302 } 3303#ifdef HAVE_conditional_execution 3304 else 3305 { 3306 count_or_remove_death_notes (blocks, 1); 3307 update_life_info (blocks, UPDATE_LIFE_LOCAL, PROP_DEATH_NOTES); 3308 } 3309 sbitmap_free (blocks); 3310#endif 3311} 3312#endif /* HAVE_peephole2 */
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