| gcc.1 (219374) | gcc.1 (219639) |
|---|---|
| 1.\" Automatically generated by Pod::Man v1.37, Pod::Parser v1.14 2.\" 3.\" Standard preamble: 4.\" ======================================================================== 5.de Sh \" Subsection heading 6.br 7.if t .Sp 8.ne 5 --- 527 unchanged lines hidden (view full) --- 536.Sp 537\&\fIi386 and x86\-64 Options\fR 538\&\fB\-mtune=\fR\fIcpu-type\fR \fB\-march=\fR\fIcpu-type\fR 539\&\fB\-mfpmath=\fR\fIunit\fR 540\&\fB\-masm=\fR\fIdialect\fR \fB\-mno\-fancy\-math\-387 541\&\-mno\-fp\-ret\-in\-387 \-msoft\-float \-msvr3\-shlib 542\&\-mno\-wide\-multiply \-mrtd \-malign\-double 543\&\-mpreferred\-stack\-boundary=\fR\fInum\fR | 1.\" Automatically generated by Pod::Man v1.37, Pod::Parser v1.14 2.\" 3.\" Standard preamble: 4.\" ======================================================================== 5.de Sh \" Subsection heading 6.br 7.if t .Sp 8.ne 5 --- 527 unchanged lines hidden (view full) --- 536.Sp 537\&\fIi386 and x86\-64 Options\fR 538\&\fB\-mtune=\fR\fIcpu-type\fR \fB\-march=\fR\fIcpu-type\fR 539\&\fB\-mfpmath=\fR\fIunit\fR 540\&\fB\-masm=\fR\fIdialect\fR \fB\-mno\-fancy\-math\-387 541\&\-mno\-fp\-ret\-in\-387 \-msoft\-float \-msvr3\-shlib 542\&\-mno\-wide\-multiply \-mrtd \-malign\-double 543\&\-mpreferred\-stack\-boundary=\fR\fInum\fR |
| 544\&\fB\-mmmx \-msse \-msse2 \-msse3 \-m3dnow | 544\&\fB\-mmmx \-msse \-msse2 \-msse3 \-mssse3 \-m3dnow |
| 545\&\-mthreads \-mno\-align\-stringops \-minline\-all\-stringops 546\&\-mpush\-args \-maccumulate\-outgoing\-args \-m128bit\-long\-double 547\&\-m96bit\-long\-double \-mregparm=\fR\fInum\fR \fB\-msseregparm 548\&\-mstackrealign 549\&\-momit\-leaf\-frame\-pointer \-mno\-red\-zone \-mno\-tls\-direct\-seg\-refs 550\&\-mcmodel=\fR\fIcode-model\fR 551\&\fB\-m32 \-m64 \-mlarge\-data\-threshold=\fR\fInum\fR 552.Sp --- 8177 unchanged lines hidden (view full) --- 8730Improved version of Intel Pentium4 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0 and \s-1SSE3\s0 instruction 8731set support. 8732.IP "\fInocona\fR" 4 8733.IX Item "nocona" 8734Improved version of Intel Pentium4 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, 8735\&\s-1SSE2\s0 and \s-1SSE3\s0 instruction set support. 8736.IP "\fIcore2\fR" 4 8737.IX Item "core2" | 545\&\-mthreads \-mno\-align\-stringops \-minline\-all\-stringops 546\&\-mpush\-args \-maccumulate\-outgoing\-args \-m128bit\-long\-double 547\&\-m96bit\-long\-double \-mregparm=\fR\fInum\fR \fB\-msseregparm 548\&\-mstackrealign 549\&\-momit\-leaf\-frame\-pointer \-mno\-red\-zone \-mno\-tls\-direct\-seg\-refs 550\&\-mcmodel=\fR\fIcode-model\fR 551\&\fB\-m32 \-m64 \-mlarge\-data\-threshold=\fR\fInum\fR 552.Sp --- 8177 unchanged lines hidden (view full) --- 8730Improved version of Intel Pentium4 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0 and \s-1SSE3\s0 instruction 8731set support. 8732.IP "\fInocona\fR" 4 8733.IX Item "nocona" 8734Improved version of Intel Pentium4 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, 8735\&\s-1SSE2\s0 and \s-1SSE3\s0 instruction set support. 8736.IP "\fIcore2\fR" 4 8737.IX Item "core2" |
| 8738Intel Core2 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0 and \s-1SSE3\s0 | 8738Intel Core2 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and \s-1SSSE3\s0 |
| 8739instruction set support. 8740.IP "\fIk6\fR" 4 8741.IX Item "k6" 8742\&\s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 instruction set support. 8743.IP "\fIk6\-2, k6\-3\fR" 4 8744.IX Item "k6-2, k6-3" 8745Improved versions of \s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 and 3dNOW! instruction set support. 8746.IP "\fIathlon, athlon-tbird\fR" 4 --- 305 unchanged lines hidden (view full) --- 9052.IP "\fB\-msse2\fR" 4 9053.IX Item "-msse2" 9054.IP "\fB\-mno\-sse2\fR" 4 9055.IX Item "-mno-sse2" 9056.IP "\fB\-msse3\fR" 4 9057.IX Item "-msse3" 9058.IP "\fB\-mno\-sse3\fR" 4 9059.IX Item "-mno-sse3" | 8739instruction set support. 8740.IP "\fIk6\fR" 4 8741.IX Item "k6" 8742\&\s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 instruction set support. 8743.IP "\fIk6\-2, k6\-3\fR" 4 8744.IX Item "k6-2, k6-3" 8745Improved versions of \s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 and 3dNOW! instruction set support. 8746.IP "\fIathlon, athlon-tbird\fR" 4 --- 305 unchanged lines hidden (view full) --- 9052.IP "\fB\-msse2\fR" 4 9053.IX Item "-msse2" 9054.IP "\fB\-mno\-sse2\fR" 4 9055.IX Item "-mno-sse2" 9056.IP "\fB\-msse3\fR" 4 9057.IX Item "-msse3" 9058.IP "\fB\-mno\-sse3\fR" 4 9059.IX Item "-mno-sse3" |
| 9060.IP "\fB\-mssse3\fR" 4 9061.IX Item "-mssse3" 9062.IP "\fB\-mno\-ssse3\fR" 4 9063.IX Item "-mno-ssse3" |
|
| 9060.IP "\fB\-m3dnow\fR" 4 9061.IX Item "-m3dnow" 9062.IP "\fB\-mno\-3dnow\fR" 4 9063.IX Item "-mno-3dnow" 9064.PD 9065These switches enable or disable the use of instructions in the \s-1MMX\s0, | 9064.IP "\fB\-m3dnow\fR" 4 9065.IX Item "-m3dnow" 9066.IP "\fB\-mno\-3dnow\fR" 4 9067.IX Item "-mno-3dnow" 9068.PD 9069These switches enable or disable the use of instructions in the \s-1MMX\s0, |
| 9066\&\s-1SSE\s0, \s-1SSE2\s0 or 3DNow! extended instruction sets. These extensions are 9067also available as built-in functions: see \fBX86 Built-in Functions\fR, 9068for details of the functions enabled and disabled by these switches. | 9070\&\s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0 or 3DNow! extended instruction sets. 9071These extensions are also available as built-in functions: see 9072\fBX86 Built-in Functions\fR, for details of the functions enabled and 9073disabled by these switches. |
| 9069.Sp 9070To have \s-1SSE/SSE2\s0 instructions generated automatically from floating-point 9071code (as opposed to 387 instructions), see \fB\-mfpmath=sse\fR. 9072.Sp 9073These options will enable \s-1GCC\s0 to use these extended instructions in 9074generated code, even without \fB\-mfpmath=sse\fR. Applications which 9075perform runtime \s-1CPU\s0 detection must compile separate files for each 9076supported architecture, using the appropriate flags. In particular, --- 4052 unchanged lines hidden --- | 9074.Sp 9075To have \s-1SSE/SSE2\s0 instructions generated automatically from floating-point 9076code (as opposed to 387 instructions), see \fB\-mfpmath=sse\fR. 9077.Sp 9078These options will enable \s-1GCC\s0 to use these extended instructions in 9079generated code, even without \fB\-mfpmath=sse\fR. Applications which 9080perform runtime \s-1CPU\s0 detection must compile separate files for each 9081supported architecture, using the appropriate flags. In particular, --- 4052 unchanged lines hidden --- |