| sparc.md (169690) | sparc.md (235623) |
|---|---|
| 1;; Machine description for SPARC chip for GCC 2;; Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 3;; 1999, 2000, 2001, 2002, 2003, 2004, 2005,2006 Free Software Foundation, Inc. 4;; Contributed by Michael Tiemann (tiemann@cygnus.com) 5;; 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, 6;; at Cygnus Support. 7 8;; This file is part of GCC. --- 5057 unchanged lines hidden (view full) --- 5066 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) 5067 (match_operand:DI 2 "uns_small_int_operand" "")) 5068 (const_int 32))))] 5069 "TARGET_HARD_MUL32" 5070 "umul\t%1, %s2, %%g0\n\trd\t%%y, %0" 5071 [(set_attr "type" "multi") 5072 (set_attr "length" "2")]) 5073 | 1;; Machine description for SPARC chip for GCC 2;; Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 3;; 1999, 2000, 2001, 2002, 2003, 2004, 2005,2006 Free Software Foundation, Inc. 4;; Contributed by Michael Tiemann (tiemann@cygnus.com) 5;; 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, 6;; at Cygnus Support. 7 8;; This file is part of GCC. --- 5057 unchanged lines hidden (view full) --- 5066 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) 5067 (match_operand:DI 2 "uns_small_int_operand" "")) 5068 (const_int 32))))] 5069 "TARGET_HARD_MUL32" 5070 "umul\t%1, %s2, %%g0\n\trd\t%%y, %0" 5071 [(set_attr "type" "multi") 5072 (set_attr "length" "2")]) 5073 |
| 5074;; The V8 architecture specifies that there must be 3 instructions between 5075;; a Y register write and a use of it for correct results. 5076 | |
| 5077(define_expand "divsi3" | 5074(define_expand "divsi3" |
| 5078 [(parallel [(set (match_operand:SI 0 "register_operand" "=r,r") 5079 (div:SI (match_operand:SI 1 "register_operand" "r,r") 5080 (match_operand:SI 2 "input_operand" "rI,m"))) 5081 (clobber (match_scratch:SI 3 "=&r,&r"))])] | 5075 [(parallel [(set (match_operand:SI 0 "register_operand" "") 5076 (div:SI (match_operand:SI 1 "register_operand" "") 5077 (match_operand:SI 2 "input_operand" ""))) 5078 (clobber (match_scratch:SI 3 ""))])] |
| 5082 "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS" 5083{ 5084 if (TARGET_ARCH64) 5085 { 5086 operands[3] = gen_reg_rtx(SImode); 5087 emit_insn (gen_ashrsi3 (operands[3], operands[1], GEN_INT (31))); 5088 emit_insn (gen_divsi3_sp64 (operands[0], operands[1], operands[2], 5089 operands[3])); 5090 DONE; 5091 } 5092}) 5093 | 5079 "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS" 5080{ 5081 if (TARGET_ARCH64) 5082 { 5083 operands[3] = gen_reg_rtx(SImode); 5084 emit_insn (gen_ashrsi3 (operands[3], operands[1], GEN_INT (31))); 5085 emit_insn (gen_divsi3_sp64 (operands[0], operands[1], operands[2], 5086 operands[3])); 5087 DONE; 5088 } 5089}) 5090 |
| 5091;; The V8 architecture specifies that there must be at least 3 instructions 5092;; between a write to the Y register and a use of it for correct results. 5093;; We try to fill one of them with a simple constant or a memory load. 5094 |
|
| 5094(define_insn "divsi3_sp32" | 5095(define_insn "divsi3_sp32" |
| 5095 [(set (match_operand:SI 0 "register_operand" "=r,r") 5096 (div:SI (match_operand:SI 1 "register_operand" "r,r") 5097 (match_operand:SI 2 "input_operand" "rI,m"))) 5098 (clobber (match_scratch:SI 3 "=&r,&r"))] 5099 "(TARGET_V8 || TARGET_DEPRECATED_V8_INSNS) 5100 && TARGET_ARCH32" | 5096 [(set (match_operand:SI 0 "register_operand" "=r,r,r") 5097 (div:SI (match_operand:SI 1 "register_operand" "r,r,r") 5098 (match_operand:SI 2 "input_operand" "rI,K,m"))) 5099 (clobber (match_scratch:SI 3 "=&r,&r,&r"))] 5100 "(TARGET_V8 || TARGET_DEPRECATED_V8_INSNS) && TARGET_ARCH32" |
| 5101{ | 5101{ |
| 5102 if (which_alternative == 0) 5103 if (TARGET_V9) 5104 return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tsdiv\t%1, %2, %0"; 5105 else 5106 return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tnop\n\tnop\n\tnop\n\tsdiv\t%1, %2, %0"; 5107 else 5108 if (TARGET_V9) 5109 return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tld\t%2, %3\n\tsdiv\t%1, %3, %0"; 5110 else 5111 return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tld\t%2, %3\n\tnop\n\tnop\n\tsdiv\t%1, %3, %0"; | 5102 output_asm_insn ("sra\t%1, 31, %3", operands); 5103 output_asm_insn ("wr\t%3, 0, %%y", operands); 5104 5105 switch (which_alternative) 5106 { 5107 case 0: 5108 if (TARGET_V9) 5109 return "sdiv\t%1, %2, %0"; 5110 else 5111 return "nop\n\tnop\n\tnop\n\tsdiv\t%1, %2, %0"; 5112 case 1: 5113 if (TARGET_V9) 5114 return "sethi\t%%hi(%a2), %3\n\tsdiv\t%1, %3, %0"; 5115 else 5116 return "sethi\t%%hi(%a2), %3\n\tnop\n\tnop\n\tsdiv\t%1, %3, %0"; 5117 case 2: 5118 if (TARGET_V9) 5119 return "ld\t%2, %3\n\tsdiv\t%1, %3, %0"; 5120 else 5121 return "ld\t%2, %3\n\tnop\n\tnop\n\tsdiv\t%1, %3, %0"; 5122 default: 5123 gcc_unreachable (); 5124 } |
| 5112} 5113 [(set_attr "type" "multi") 5114 (set (attr "length") 5115 (if_then_else (eq_attr "isa" "v9") 5116 (const_int 4) (const_int 6)))]) 5117 5118(define_insn "divsi3_sp64" 5119 [(set (match_operand:SI 0 "register_operand" "=r") --- 18 unchanged lines hidden (view full) --- 5138 (compare:CC (div:SI (match_operand:SI 1 "register_operand" "r") 5139 (match_operand:SI 2 "arith_operand" "rI")) 5140 (const_int 0))) 5141 (set (match_operand:SI 0 "register_operand" "=r") 5142 (div:SI (match_dup 1) (match_dup 2))) 5143 (clobber (match_scratch:SI 3 "=&r"))] 5144 "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS" 5145{ | 5125} 5126 [(set_attr "type" "multi") 5127 (set (attr "length") 5128 (if_then_else (eq_attr "isa" "v9") 5129 (const_int 4) (const_int 6)))]) 5130 5131(define_insn "divsi3_sp64" 5132 [(set (match_operand:SI 0 "register_operand" "=r") --- 18 unchanged lines hidden (view full) --- 5151 (compare:CC (div:SI (match_operand:SI 1 "register_operand" "r") 5152 (match_operand:SI 2 "arith_operand" "rI")) 5153 (const_int 0))) 5154 (set (match_operand:SI 0 "register_operand" "=r") 5155 (div:SI (match_dup 1) (match_dup 2))) 5156 (clobber (match_scratch:SI 3 "=&r"))] 5157 "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS" 5158{ |
| 5159 output_asm_insn ("sra\t%1, 31, %3", operands); 5160 output_asm_insn ("wr\t%3, 0, %%y", operands); 5161 |
|
| 5146 if (TARGET_V9) | 5162 if (TARGET_V9) |
| 5147 return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tsdivcc\t%1, %2, %0"; | 5163 return "sdivcc\t%1, %2, %0"; |
| 5148 else | 5164 else |
| 5149 return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tnop\n\tnop\n\tnop\n\tsdivcc\t%1, %2, %0"; | 5165 return "nop\n\tnop\n\tnop\n\tsdivcc\t%1, %2, %0"; |
| 5150} 5151 [(set_attr "type" "multi") 5152 (set (attr "length") 5153 (if_then_else (eq_attr "isa" "v9") 5154 (const_int 3) (const_int 6)))]) 5155 5156;; XXX 5157(define_expand "udivsi3" 5158 [(set (match_operand:SI 0 "register_operand" "") 5159 (udiv:SI (match_operand:SI 1 "nonimmediate_operand" "") 5160 (match_operand:SI 2 "input_operand" "")))] 5161 "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS" 5162 "") 5163 | 5166} 5167 [(set_attr "type" "multi") 5168 (set (attr "length") 5169 (if_then_else (eq_attr "isa" "v9") 5170 (const_int 3) (const_int 6)))]) 5171 5172;; XXX 5173(define_expand "udivsi3" 5174 [(set (match_operand:SI 0 "register_operand" "") 5175 (udiv:SI (match_operand:SI 1 "nonimmediate_operand" "") 5176 (match_operand:SI 2 "input_operand" "")))] 5177 "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS" 5178 "") 5179 |
| 5164;; The V8 architecture specifies that there must be 3 instructions between 5165;; a Y register write and a use of it for correct results. | 5180;; The V8 architecture specifies that there must be at least 3 instructions 5181;; between a write to the Y register and a use of it for correct results. 5182;; We try to fill one of them with a simple constant or a memory load. |
| 5166 5167(define_insn "udivsi3_sp32" | 5183 5184(define_insn "udivsi3_sp32" |
| 5168 [(set (match_operand:SI 0 "register_operand" "=r,&r,&r") 5169 (udiv:SI (match_operand:SI 1 "nonimmediate_operand" "r,r,m") 5170 (match_operand:SI 2 "input_operand" "rI,m,r")))] 5171 "(TARGET_V8 || TARGET_DEPRECATED_V8_INSNS) 5172 && TARGET_ARCH32" | 5185 [(set (match_operand:SI 0 "register_operand" "=r,&r,&r,&r") 5186 (udiv:SI (match_operand:SI 1 "nonimmediate_operand" "r,r,r,m") 5187 (match_operand:SI 2 "input_operand" "rI,K,m,r")))] 5188 "(TARGET_V8 || TARGET_DEPRECATED_V8_INSNS) && TARGET_ARCH32" |
| 5173{ | 5189{ |
| 5174 output_asm_insn ("wr\t%%g0, %%g0, %%y", operands); | 5190 output_asm_insn ("wr\t%%g0, 0, %%y", operands); 5191 |
| 5175 switch (which_alternative) 5176 { | 5192 switch (which_alternative) 5193 { |
| 5177 default: 5178 return "nop\n\tnop\n\tnop\n\tudiv\t%1, %2, %0"; | 5194 case 0: 5195 if (TARGET_V9) 5196 return "udiv\t%1, %2, %0"; 5197 else 5198 return "nop\n\tnop\n\tnop\n\tudiv\t%1, %2, %0"; |
| 5179 case 1: | 5199 case 1: |
| 5180 return "ld\t%2, %0\n\tnop\n\tnop\n\tudiv\t%1, %0, %0"; | 5200 if (TARGET_V9) 5201 return "sethi\t%%hi(%a2), %0\n\tudiv\t%1, %0, %0"; 5202 else 5203 return "sethi\t%%hi(%a2), %0\n\tnop\n\tnop\n\tudiv\t%1, %0, %0"; |
| 5181 case 2: | 5204 case 2: |
| 5182 return "ld\t%1, %0\n\tnop\n\tnop\n\tudiv\t%0, %2, %0"; | 5205 if (TARGET_V9) 5206 return "ld\t%2, %0\n\tudiv\t%1, %0, %0"; 5207 else 5208 return "ld\t%2, %0\n\tnop\n\tnop\n\tudiv\t%1, %0, %0"; 5209 case 3: 5210 if (TARGET_V9) 5211 return "ld\t%1, %0\n\tudiv\t%0, %2, %0"; 5212 else 5213 return "ld\t%1, %0\n\tnop\n\tnop\n\tudiv\t%0, %2, %0"; 5214 default: 5215 gcc_unreachable (); |
| 5183 } 5184} 5185 [(set_attr "type" "multi") | 5216 } 5217} 5218 [(set_attr "type" "multi") |
| 5186 (set_attr "length" "5")]) | 5219 (set (attr "length") 5220 (if_then_else (eq_attr "isa" "v9") 5221 (const_int 3) (const_int 5)))]) |
| 5187 5188(define_insn "udivsi3_sp64" 5189 [(set (match_operand:SI 0 "register_operand" "=r") 5190 (udiv:SI (match_operand:SI 1 "nonimmediate_operand" "r") 5191 (match_operand:SI 2 "input_operand" "rI")))] 5192 "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" 5193 "wr\t%%g0, 0, %%y\n\tudiv\t%1, %2, %0" 5194 [(set_attr "type" "multi") --- 9 unchanged lines hidden (view full) --- 5204 5205(define_insn "*cmp_udiv_cc_set" 5206 [(set (reg:CC 100) 5207 (compare:CC (udiv:SI (match_operand:SI 1 "register_operand" "r") 5208 (match_operand:SI 2 "arith_operand" "rI")) 5209 (const_int 0))) 5210 (set (match_operand:SI 0 "register_operand" "=r") 5211 (udiv:SI (match_dup 1) (match_dup 2)))] | 5222 5223(define_insn "udivsi3_sp64" 5224 [(set (match_operand:SI 0 "register_operand" "=r") 5225 (udiv:SI (match_operand:SI 1 "nonimmediate_operand" "r") 5226 (match_operand:SI 2 "input_operand" "rI")))] 5227 "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" 5228 "wr\t%%g0, 0, %%y\n\tudiv\t%1, %2, %0" 5229 [(set_attr "type" "multi") --- 9 unchanged lines hidden (view full) --- 5239 5240(define_insn "*cmp_udiv_cc_set" 5241 [(set (reg:CC 100) 5242 (compare:CC (udiv:SI (match_operand:SI 1 "register_operand" "r") 5243 (match_operand:SI 2 "arith_operand" "rI")) 5244 (const_int 0))) 5245 (set (match_operand:SI 0 "register_operand" "=r") 5246 (udiv:SI (match_dup 1) (match_dup 2)))] |
| 5212 "TARGET_V8 5213 || TARGET_DEPRECATED_V8_INSNS" | 5247 "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS" |
| 5214{ | 5248{ |
| 5249 output_asm_insn ("wr\t%%g0, 0, %%y", operands); 5250 |
|
| 5215 if (TARGET_V9) | 5251 if (TARGET_V9) |
| 5216 return "wr\t%%g0, %%g0, %%y\n\tudivcc\t%1, %2, %0"; | 5252 return "udivcc\t%1, %2, %0"; |
| 5217 else | 5253 else |
| 5218 return "wr\t%%g0, %%g0, %%y\n\tnop\n\tnop\n\tnop\n\tudivcc\t%1, %2, %0"; | 5254 return "nop\n\tnop\n\tnop\n\tudivcc\t%1, %2, %0"; |
| 5219} 5220 [(set_attr "type" "multi") 5221 (set (attr "length") 5222 (if_then_else (eq_attr "isa" "v9") 5223 (const_int 2) (const_int 5)))]) 5224 5225; sparclet multiply/accumulate insns 5226 --- 3260 unchanged lines hidden --- | 5255} 5256 [(set_attr "type" "multi") 5257 (set (attr "length") 5258 (if_then_else (eq_attr "isa" "v9") 5259 (const_int 2) (const_int 5)))]) 5260 5261; sparclet multiply/accumulate insns 5262 --- 3260 unchanged lines hidden --- |