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1;; GCC machine description for SSE instructions
2;; Copyright (C) 2005, 2006
3;; Free Software Foundation, Inc.
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify
8;; it under the terms of the GNU General Public License as published by

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3944 (match_operand:SI 2 "register_operand" "d")]
3945 UNSPECV_MONITOR)]
3946 "TARGET_SSE3 && TARGET_64BIT"
3947;; 64bit version is "monitor %rax,%rcx,%rdx". But only lower 32bits in
3948;; RCX and RDX are used. Since 32bit register operands are implicitly
3949;; zero extended to 64bit, we only need to set up 32bit registers.
3950 "monitor"
3951 [(set_attr "length" "3")])
1;; GCC machine description for SSE instructions
2;; Copyright (C) 2005, 2006
3;; Free Software Foundation, Inc.
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify
8;; it under the terms of the GNU General Public License as published by

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3944 (match_operand:SI 2 "register_operand" "d")]
3945 UNSPECV_MONITOR)]
3946 "TARGET_SSE3 && TARGET_64BIT"
3947;; 64bit version is "monitor %rax,%rcx,%rdx". But only lower 32bits in
3948;; RCX and RDX are used. Since 32bit register operands are implicitly
3949;; zero extended to 64bit, we only need to set up 32bit registers.
3950 "monitor"
3951 [(set_attr "length" "3")])
3952
3953;; SSSE3
3954(define_insn "ssse3_phaddwv8hi3"
3955 [(set (match_operand:V8HI 0 "register_operand" "=x")
3956 (vec_concat:V8HI
3957 (vec_concat:V4HI
3958 (vec_concat:V2HI
3959 (plus:HI
3960 (vec_select:HI
3961 (match_operand:V8HI 1 "register_operand" "0")
3962 (parallel [(const_int 0)]))
3963 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
3964 (plus:HI
3965 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
3966 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
3967 (vec_concat:V2HI
3968 (plus:HI
3969 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
3970 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
3971 (plus:HI
3972 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
3973 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
3974 (vec_concat:V4HI
3975 (vec_concat:V2HI
3976 (plus:HI
3977 (vec_select:HI
3978 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
3979 (parallel [(const_int 0)]))
3980 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
3981 (plus:HI
3982 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
3983 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
3984 (vec_concat:V2HI
3985 (plus:HI
3986 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
3987 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
3988 (plus:HI
3989 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
3990 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
3991 "TARGET_SSSE3"
3992 "phaddw\t{%2, %0|%0, %2}"
3993 [(set_attr "type" "sseiadd")
3994 (set_attr "mode" "TI")])
3995
3996(define_insn "ssse3_phaddwv4hi3"
3997 [(set (match_operand:V4HI 0 "register_operand" "=y")
3998 (vec_concat:V4HI
3999 (vec_concat:V2HI
4000 (plus:HI
4001 (vec_select:HI
4002 (match_operand:V4HI 1 "register_operand" "0")
4003 (parallel [(const_int 0)]))
4004 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
4005 (plus:HI
4006 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
4007 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
4008 (vec_concat:V2HI
4009 (plus:HI
4010 (vec_select:HI
4011 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
4012 (parallel [(const_int 0)]))
4013 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
4014 (plus:HI
4015 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
4016 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
4017 "TARGET_SSSE3"
4018 "phaddw\t{%2, %0|%0, %2}"
4019 [(set_attr "type" "sseiadd")
4020 (set_attr "mode" "DI")])
4021
4022(define_insn "ssse3_phadddv4si3"
4023 [(set (match_operand:V4SI 0 "register_operand" "=x")
4024 (vec_concat:V4SI
4025 (vec_concat:V2SI
4026 (plus:SI
4027 (vec_select:SI
4028 (match_operand:V4SI 1 "register_operand" "0")
4029 (parallel [(const_int 0)]))
4030 (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
4031 (plus:SI
4032 (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
4033 (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
4034 (vec_concat:V2SI
4035 (plus:SI
4036 (vec_select:SI
4037 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
4038 (parallel [(const_int 0)]))
4039 (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
4040 (plus:SI
4041 (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
4042 (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
4043 "TARGET_SSSE3"
4044 "phaddd\t{%2, %0|%0, %2}"
4045 [(set_attr "type" "sseiadd")
4046 (set_attr "mode" "TI")])
4047
4048(define_insn "ssse3_phadddv2si3"
4049 [(set (match_operand:V2SI 0 "register_operand" "=y")
4050 (vec_concat:V2SI
4051 (plus:SI
4052 (vec_select:SI
4053 (match_operand:V2SI 1 "register_operand" "0")
4054 (parallel [(const_int 0)]))
4055 (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
4056 (plus:SI
4057 (vec_select:SI
4058 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
4059 (parallel [(const_int 0)]))
4060 (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))))]
4061 "TARGET_SSSE3"
4062 "phaddd\t{%2, %0|%0, %2}"
4063 [(set_attr "type" "sseiadd")
4064 (set_attr "mode" "DI")])
4065
4066(define_insn "ssse3_phaddswv8hi3"
4067 [(set (match_operand:V8HI 0 "register_operand" "=x")
4068 (vec_concat:V8HI
4069 (vec_concat:V4HI
4070 (vec_concat:V2HI
4071 (ss_plus:HI
4072 (vec_select:HI
4073 (match_operand:V8HI 1 "register_operand" "0")
4074 (parallel [(const_int 0)]))
4075 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
4076 (ss_plus:HI
4077 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
4078 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
4079 (vec_concat:V2HI
4080 (ss_plus:HI
4081 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
4082 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
4083 (ss_plus:HI
4084 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
4085 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
4086 (vec_concat:V4HI
4087 (vec_concat:V2HI
4088 (ss_plus:HI
4089 (vec_select:HI
4090 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
4091 (parallel [(const_int 0)]))
4092 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
4093 (ss_plus:HI
4094 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
4095 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
4096 (vec_concat:V2HI
4097 (ss_plus:HI
4098 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
4099 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
4100 (ss_plus:HI
4101 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
4102 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
4103 "TARGET_SSSE3"
4104 "phaddsw\t{%2, %0|%0, %2}"
4105 [(set_attr "type" "sseiadd")
4106 (set_attr "mode" "TI")])
4107
4108(define_insn "ssse3_phaddswv4hi3"
4109 [(set (match_operand:V4HI 0 "register_operand" "=y")
4110 (vec_concat:V4HI
4111 (vec_concat:V2HI
4112 (ss_plus:HI
4113 (vec_select:HI
4114 (match_operand:V4HI 1 "register_operand" "0")
4115 (parallel [(const_int 0)]))
4116 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
4117 (ss_plus:HI
4118 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
4119 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
4120 (vec_concat:V2HI
4121 (ss_plus:HI
4122 (vec_select:HI
4123 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
4124 (parallel [(const_int 0)]))
4125 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
4126 (ss_plus:HI
4127 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
4128 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
4129 "TARGET_SSSE3"
4130 "phaddsw\t{%2, %0|%0, %2}"
4131 [(set_attr "type" "sseiadd")
4132 (set_attr "mode" "DI")])
4133
4134(define_insn "ssse3_phsubwv8hi3"
4135 [(set (match_operand:V8HI 0 "register_operand" "=x")
4136 (vec_concat:V8HI
4137 (vec_concat:V4HI
4138 (vec_concat:V2HI
4139 (minus:HI
4140 (vec_select:HI
4141 (match_operand:V8HI 1 "register_operand" "0")
4142 (parallel [(const_int 0)]))
4143 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
4144 (minus:HI
4145 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
4146 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
4147 (vec_concat:V2HI
4148 (minus:HI
4149 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
4150 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
4151 (minus:HI
4152 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
4153 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
4154 (vec_concat:V4HI
4155 (vec_concat:V2HI
4156 (minus:HI
4157 (vec_select:HI
4158 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
4159 (parallel [(const_int 0)]))
4160 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
4161 (minus:HI
4162 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
4163 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
4164 (vec_concat:V2HI
4165 (minus:HI
4166 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
4167 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
4168 (minus:HI
4169 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
4170 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
4171 "TARGET_SSSE3"
4172 "phsubw\t{%2, %0|%0, %2}"
4173 [(set_attr "type" "sseiadd")
4174 (set_attr "mode" "TI")])
4175
4176(define_insn "ssse3_phsubwv4hi3"
4177 [(set (match_operand:V4HI 0 "register_operand" "=y")
4178 (vec_concat:V4HI
4179 (vec_concat:V2HI
4180 (minus:HI
4181 (vec_select:HI
4182 (match_operand:V4HI 1 "register_operand" "0")
4183 (parallel [(const_int 0)]))
4184 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
4185 (minus:HI
4186 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
4187 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
4188 (vec_concat:V2HI
4189 (minus:HI
4190 (vec_select:HI
4191 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
4192 (parallel [(const_int 0)]))
4193 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
4194 (minus:HI
4195 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
4196 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
4197 "TARGET_SSSE3"
4198 "phsubw\t{%2, %0|%0, %2}"
4199 [(set_attr "type" "sseiadd")
4200 (set_attr "mode" "DI")])
4201
4202(define_insn "ssse3_phsubdv4si3"
4203 [(set (match_operand:V4SI 0 "register_operand" "=x")
4204 (vec_concat:V4SI
4205 (vec_concat:V2SI
4206 (minus:SI
4207 (vec_select:SI
4208 (match_operand:V4SI 1 "register_operand" "0")
4209 (parallel [(const_int 0)]))
4210 (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
4211 (minus:SI
4212 (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
4213 (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
4214 (vec_concat:V2SI
4215 (minus:SI
4216 (vec_select:SI
4217 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
4218 (parallel [(const_int 0)]))
4219 (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
4220 (minus:SI
4221 (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
4222 (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
4223 "TARGET_SSSE3"
4224 "phsubd\t{%2, %0|%0, %2}"
4225 [(set_attr "type" "sseiadd")
4226 (set_attr "mode" "TI")])
4227
4228(define_insn "ssse3_phsubdv2si3"
4229 [(set (match_operand:V2SI 0 "register_operand" "=y")
4230 (vec_concat:V2SI
4231 (minus:SI
4232 (vec_select:SI
4233 (match_operand:V2SI 1 "register_operand" "0")
4234 (parallel [(const_int 0)]))
4235 (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
4236 (minus:SI
4237 (vec_select:SI
4238 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
4239 (parallel [(const_int 0)]))
4240 (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))))]
4241 "TARGET_SSSE3"
4242 "phsubd\t{%2, %0|%0, %2}"
4243 [(set_attr "type" "sseiadd")
4244 (set_attr "mode" "DI")])
4245
4246(define_insn "ssse3_phsubswv8hi3"
4247 [(set (match_operand:V8HI 0 "register_operand" "=x")
4248 (vec_concat:V8HI
4249 (vec_concat:V4HI
4250 (vec_concat:V2HI
4251 (ss_minus:HI
4252 (vec_select:HI
4253 (match_operand:V8HI 1 "register_operand" "0")
4254 (parallel [(const_int 0)]))
4255 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
4256 (ss_minus:HI
4257 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
4258 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
4259 (vec_concat:V2HI
4260 (ss_minus:HI
4261 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
4262 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
4263 (ss_minus:HI
4264 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
4265 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
4266 (vec_concat:V4HI
4267 (vec_concat:V2HI
4268 (ss_minus:HI
4269 (vec_select:HI
4270 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
4271 (parallel [(const_int 0)]))
4272 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
4273 (ss_minus:HI
4274 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
4275 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
4276 (vec_concat:V2HI
4277 (ss_minus:HI
4278 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
4279 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
4280 (ss_minus:HI
4281 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
4282 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
4283 "TARGET_SSSE3"
4284 "phsubsw\t{%2, %0|%0, %2}"
4285 [(set_attr "type" "sseiadd")
4286 (set_attr "mode" "TI")])
4287
4288(define_insn "ssse3_phsubswv4hi3"
4289 [(set (match_operand:V4HI 0 "register_operand" "=y")
4290 (vec_concat:V4HI
4291 (vec_concat:V2HI
4292 (ss_minus:HI
4293 (vec_select:HI
4294 (match_operand:V4HI 1 "register_operand" "0")
4295 (parallel [(const_int 0)]))
4296 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
4297 (ss_minus:HI
4298 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
4299 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
4300 (vec_concat:V2HI
4301 (ss_minus:HI
4302 (vec_select:HI
4303 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
4304 (parallel [(const_int 0)]))
4305 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
4306 (ss_minus:HI
4307 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
4308 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
4309 "TARGET_SSSE3"
4310 "phsubsw\t{%2, %0|%0, %2}"
4311 [(set_attr "type" "sseiadd")
4312 (set_attr "mode" "DI")])
4313
4314(define_insn "ssse3_pmaddubswv8hi3"
4315 [(set (match_operand:V8HI 0 "register_operand" "=x")
4316 (ss_plus:V8HI
4317 (mult:V8HI
4318 (zero_extend:V8HI
4319 (vec_select:V4QI
4320 (match_operand:V16QI 1 "nonimmediate_operand" "%0")
4321 (parallel [(const_int 0)
4322 (const_int 2)
4323 (const_int 4)
4324 (const_int 6)
4325 (const_int 8)
4326 (const_int 10)
4327 (const_int 12)
4328 (const_int 14)])))
4329 (sign_extend:V8HI
4330 (vec_select:V8QI
4331 (match_operand:V16QI 2 "nonimmediate_operand" "xm")
4332 (parallel [(const_int 0)
4333 (const_int 2)
4334 (const_int 4)
4335 (const_int 6)
4336 (const_int 8)
4337 (const_int 10)
4338 (const_int 12)
4339 (const_int 14)]))))
4340 (mult:V8HI
4341 (zero_extend:V8HI
4342 (vec_select:V16QI (match_dup 1)
4343 (parallel [(const_int 1)
4344 (const_int 3)
4345 (const_int 5)
4346 (const_int 7)
4347 (const_int 9)
4348 (const_int 11)
4349 (const_int 13)
4350 (const_int 15)])))
4351 (sign_extend:V8HI
4352 (vec_select:V16QI (match_dup 2)
4353 (parallel [(const_int 1)
4354 (const_int 3)
4355 (const_int 5)
4356 (const_int 7)
4357 (const_int 9)
4358 (const_int 11)
4359 (const_int 13)
4360 (const_int 15)]))))))]
4361 "TARGET_SSSE3"
4362 "pmaddubsw\t{%2, %0|%0, %2}"
4363 [(set_attr "type" "sseiadd")
4364 (set_attr "mode" "TI")])
4365
4366(define_insn "ssse3_pmaddubswv4hi3"
4367 [(set (match_operand:V4HI 0 "register_operand" "=y")
4368 (ss_plus:V4HI
4369 (mult:V4HI
4370 (zero_extend:V4HI
4371 (vec_select:V4QI
4372 (match_operand:V8QI 1 "nonimmediate_operand" "%0")
4373 (parallel [(const_int 0)
4374 (const_int 2)
4375 (const_int 4)
4376 (const_int 6)])))
4377 (sign_extend:V4HI
4378 (vec_select:V4QI
4379 (match_operand:V8QI 2 "nonimmediate_operand" "ym")
4380 (parallel [(const_int 0)
4381 (const_int 2)
4382 (const_int 4)
4383 (const_int 6)]))))
4384 (mult:V4HI
4385 (zero_extend:V4HI
4386 (vec_select:V8QI (match_dup 1)
4387 (parallel [(const_int 1)
4388 (const_int 3)
4389 (const_int 5)
4390 (const_int 7)])))
4391 (sign_extend:V4HI
4392 (vec_select:V8QI (match_dup 2)
4393 (parallel [(const_int 1)
4394 (const_int 3)
4395 (const_int 5)
4396 (const_int 7)]))))))]
4397 "TARGET_SSSE3"
4398 "pmaddubsw\t{%2, %0|%0, %2}"
4399 [(set_attr "type" "sseiadd")
4400 (set_attr "mode" "DI")])
4401
4402(define_insn "ssse3_pmulhrswv8hi3"
4403 [(set (match_operand:V8HI 0 "register_operand" "=x")
4404 (truncate:V8HI
4405 (lshiftrt:V8SI
4406 (plus:V8SI
4407 (lshiftrt:V8SI
4408 (mult:V8SI
4409 (sign_extend:V8SI
4410 (match_operand:V8HI 1 "nonimmediate_operand" "%0"))
4411 (sign_extend:V8SI
4412 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
4413 (const_int 14))
4414 (const_vector:V8HI [(const_int 1) (const_int 1)
4415 (const_int 1) (const_int 1)
4416 (const_int 1) (const_int 1)
4417 (const_int 1) (const_int 1)]))
4418 (const_int 1))))]
4419 "TARGET_SSSE3 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
4420 "pmulhrsw\t{%2, %0|%0, %2}"
4421 [(set_attr "type" "sseimul")
4422 (set_attr "mode" "TI")])
4423
4424(define_insn "ssse3_pmulhrswv4hi3"
4425 [(set (match_operand:V4HI 0 "register_operand" "=y")
4426 (truncate:V4HI
4427 (lshiftrt:V4SI
4428 (plus:V4SI
4429 (lshiftrt:V4SI
4430 (mult:V4SI
4431 (sign_extend:V4SI
4432 (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
4433 (sign_extend:V4SI
4434 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
4435 (const_int 14))
4436 (const_vector:V4HI [(const_int 1) (const_int 1)
4437 (const_int 1) (const_int 1)]))
4438 (const_int 1))))]
4439 "TARGET_SSSE3 && ix86_binary_operator_ok (MULT, V4HImode, operands)"
4440 "pmulhrsw\t{%2, %0|%0, %2}"
4441 [(set_attr "type" "sseimul")
4442 (set_attr "mode" "DI")])
4443
4444(define_insn "ssse3_pshufbv16qi3"
4445 [(set (match_operand:V16QI 0 "register_operand" "=x")
4446 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0")
4447 (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
4448 UNSPEC_PSHUFB))]
4449 "TARGET_SSSE3"
4450 "pshufb\t{%2, %0|%0, %2}";
4451 [(set_attr "type" "sselog1")
4452 (set_attr "mode" "TI")])
4453
4454(define_insn "ssse3_pshufbv8qi3"
4455 [(set (match_operand:V8QI 0 "register_operand" "=y")
4456 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "0")
4457 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
4458 UNSPEC_PSHUFB))]
4459 "TARGET_SSSE3"
4460 "pshufb\t{%2, %0|%0, %2}";
4461 [(set_attr "type" "sselog1")
4462 (set_attr "mode" "DI")])
4463
4464(define_insn "ssse3_psign<mode>3"
4465 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
4466 (unspec:SSEMODE124 [(match_operand:SSEMODE124 1 "register_operand" "0")
4467 (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")]
4468 UNSPEC_PSIGN))]
4469 "TARGET_SSSE3"
4470 "psign<ssevecsize>\t{%2, %0|%0, %2}";
4471 [(set_attr "type" "sselog1")
4472 (set_attr "mode" "TI")])
4473
4474(define_insn "ssse3_psign<mode>3"
4475 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
4476 (unspec:MMXMODEI [(match_operand:MMXMODEI 1 "register_operand" "0")
4477 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")]
4478 UNSPEC_PSIGN))]
4479 "TARGET_SSSE3"
4480 "psign<mmxvecsize>\t{%2, %0|%0, %2}";
4481 [(set_attr "type" "sselog1")
4482 (set_attr "mode" "DI")])
4483
4484(define_insn "ssse3_palignrti"
4485 [(set (match_operand:TI 0 "register_operand" "=x")
4486 (unspec:TI [(match_operand:TI 1 "register_operand" "0")
4487 (match_operand:TI 2 "nonimmediate_operand" "xm")
4488 (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
4489 UNSPEC_PALIGNR))]
4490 "TARGET_SSSE3"
4491{
4492 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
4493 return "palignr\t{%3, %2, %0|%0, %2, %3}";
4494}
4495 [(set_attr "type" "sseishft")
4496 (set_attr "mode" "TI")])
4497
4498(define_insn "ssse3_palignrdi"
4499 [(set (match_operand:DI 0 "register_operand" "=y")
4500 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
4501 (match_operand:DI 2 "nonimmediate_operand" "ym")
4502 (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
4503 UNSPEC_PALIGNR))]
4504 "TARGET_SSSE3"
4505{
4506 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
4507 return "palignr\t{%3, %2, %0|%0, %2, %3}";
4508}
4509 [(set_attr "type" "sseishft")
4510 (set_attr "mode" "DI")])
4511
4512(define_insn "abs<mode>2"
4513 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
4514 (abs:SSEMODE124 (match_operand:SSEMODE124 1 "nonimmediate_operand" "xm")))]
4515 "TARGET_SSSE3"
4516 "pabs<ssevecsize>\t{%1, %0|%0, %1}";
4517 [(set_attr "type" "sselog1")
4518 (set_attr "mode" "TI")])
4519
4520(define_insn "abs<mode>2"
4521 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
4522 (abs:MMXMODEI (match_operand:MMXMODEI 1 "nonimmediate_operand" "ym")))]
4523 "TARGET_SSSE3"
4524 "pabs<mmxvecsize>\t{%1, %0|%0, %1}";
4525 [(set_attr "type" "sselog1")
4526 (set_attr "mode" "DI")])