3951a3952,4526
>
> ;; SSSE3
> (define_insn "ssse3_phaddwv8hi3"
> [(set (match_operand:V8HI 0 "register_operand" "=x")
> (vec_concat:V8HI
> (vec_concat:V4HI
> (vec_concat:V2HI
> (plus:HI
> (vec_select:HI
> (match_operand:V8HI 1 "register_operand" "0")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
> (plus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
> (vec_concat:V2HI
> (plus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
> (plus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
> (vec_concat:V4HI
> (vec_concat:V2HI
> (plus:HI
> (vec_select:HI
> (match_operand:V8HI 2 "nonimmediate_operand" "xm")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
> (plus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
> (vec_concat:V2HI
> (plus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
> (plus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
> "TARGET_SSSE3"
> "phaddw\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "TI")])
>
> (define_insn "ssse3_phaddwv4hi3"
> [(set (match_operand:V4HI 0 "register_operand" "=y")
> (vec_concat:V4HI
> (vec_concat:V2HI
> (plus:HI
> (vec_select:HI
> (match_operand:V4HI 1 "register_operand" "0")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
> (plus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
> (vec_concat:V2HI
> (plus:HI
> (vec_select:HI
> (match_operand:V4HI 2 "nonimmediate_operand" "ym")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
> (plus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
> "TARGET_SSSE3"
> "phaddw\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "DI")])
>
> (define_insn "ssse3_phadddv4si3"
> [(set (match_operand:V4SI 0 "register_operand" "=x")
> (vec_concat:V4SI
> (vec_concat:V2SI
> (plus:SI
> (vec_select:SI
> (match_operand:V4SI 1 "register_operand" "0")
> (parallel [(const_int 0)]))
> (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
> (plus:SI
> (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
> (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
> (vec_concat:V2SI
> (plus:SI
> (vec_select:SI
> (match_operand:V4SI 2 "nonimmediate_operand" "xm")
> (parallel [(const_int 0)]))
> (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
> (plus:SI
> (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
> (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
> "TARGET_SSSE3"
> "phaddd\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "TI")])
>
> (define_insn "ssse3_phadddv2si3"
> [(set (match_operand:V2SI 0 "register_operand" "=y")
> (vec_concat:V2SI
> (plus:SI
> (vec_select:SI
> (match_operand:V2SI 1 "register_operand" "0")
> (parallel [(const_int 0)]))
> (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
> (plus:SI
> (vec_select:SI
> (match_operand:V2SI 2 "nonimmediate_operand" "ym")
> (parallel [(const_int 0)]))
> (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))))]
> "TARGET_SSSE3"
> "phaddd\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "DI")])
>
> (define_insn "ssse3_phaddswv8hi3"
> [(set (match_operand:V8HI 0 "register_operand" "=x")
> (vec_concat:V8HI
> (vec_concat:V4HI
> (vec_concat:V2HI
> (ss_plus:HI
> (vec_select:HI
> (match_operand:V8HI 1 "register_operand" "0")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
> (ss_plus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
> (vec_concat:V2HI
> (ss_plus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
> (ss_plus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
> (vec_concat:V4HI
> (vec_concat:V2HI
> (ss_plus:HI
> (vec_select:HI
> (match_operand:V8HI 2 "nonimmediate_operand" "xm")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
> (ss_plus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
> (vec_concat:V2HI
> (ss_plus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
> (ss_plus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
> "TARGET_SSSE3"
> "phaddsw\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "TI")])
>
> (define_insn "ssse3_phaddswv4hi3"
> [(set (match_operand:V4HI 0 "register_operand" "=y")
> (vec_concat:V4HI
> (vec_concat:V2HI
> (ss_plus:HI
> (vec_select:HI
> (match_operand:V4HI 1 "register_operand" "0")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
> (ss_plus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
> (vec_concat:V2HI
> (ss_plus:HI
> (vec_select:HI
> (match_operand:V4HI 2 "nonimmediate_operand" "ym")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
> (ss_plus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
> "TARGET_SSSE3"
> "phaddsw\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "DI")])
>
> (define_insn "ssse3_phsubwv8hi3"
> [(set (match_operand:V8HI 0 "register_operand" "=x")
> (vec_concat:V8HI
> (vec_concat:V4HI
> (vec_concat:V2HI
> (minus:HI
> (vec_select:HI
> (match_operand:V8HI 1 "register_operand" "0")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
> (minus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
> (vec_concat:V2HI
> (minus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
> (minus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
> (vec_concat:V4HI
> (vec_concat:V2HI
> (minus:HI
> (vec_select:HI
> (match_operand:V8HI 2 "nonimmediate_operand" "xm")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
> (minus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
> (vec_concat:V2HI
> (minus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
> (minus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
> "TARGET_SSSE3"
> "phsubw\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "TI")])
>
> (define_insn "ssse3_phsubwv4hi3"
> [(set (match_operand:V4HI 0 "register_operand" "=y")
> (vec_concat:V4HI
> (vec_concat:V2HI
> (minus:HI
> (vec_select:HI
> (match_operand:V4HI 1 "register_operand" "0")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
> (minus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
> (vec_concat:V2HI
> (minus:HI
> (vec_select:HI
> (match_operand:V4HI 2 "nonimmediate_operand" "ym")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
> (minus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
> "TARGET_SSSE3"
> "phsubw\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "DI")])
>
> (define_insn "ssse3_phsubdv4si3"
> [(set (match_operand:V4SI 0 "register_operand" "=x")
> (vec_concat:V4SI
> (vec_concat:V2SI
> (minus:SI
> (vec_select:SI
> (match_operand:V4SI 1 "register_operand" "0")
> (parallel [(const_int 0)]))
> (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
> (minus:SI
> (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
> (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
> (vec_concat:V2SI
> (minus:SI
> (vec_select:SI
> (match_operand:V4SI 2 "nonimmediate_operand" "xm")
> (parallel [(const_int 0)]))
> (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
> (minus:SI
> (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
> (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
> "TARGET_SSSE3"
> "phsubd\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "TI")])
>
> (define_insn "ssse3_phsubdv2si3"
> [(set (match_operand:V2SI 0 "register_operand" "=y")
> (vec_concat:V2SI
> (minus:SI
> (vec_select:SI
> (match_operand:V2SI 1 "register_operand" "0")
> (parallel [(const_int 0)]))
> (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
> (minus:SI
> (vec_select:SI
> (match_operand:V2SI 2 "nonimmediate_operand" "ym")
> (parallel [(const_int 0)]))
> (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))))]
> "TARGET_SSSE3"
> "phsubd\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "DI")])
>
> (define_insn "ssse3_phsubswv8hi3"
> [(set (match_operand:V8HI 0 "register_operand" "=x")
> (vec_concat:V8HI
> (vec_concat:V4HI
> (vec_concat:V2HI
> (ss_minus:HI
> (vec_select:HI
> (match_operand:V8HI 1 "register_operand" "0")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
> (ss_minus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
> (vec_concat:V2HI
> (ss_minus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
> (ss_minus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
> (vec_concat:V4HI
> (vec_concat:V2HI
> (ss_minus:HI
> (vec_select:HI
> (match_operand:V8HI 2 "nonimmediate_operand" "xm")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
> (ss_minus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
> (vec_concat:V2HI
> (ss_minus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
> (ss_minus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
> "TARGET_SSSE3"
> "phsubsw\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "TI")])
>
> (define_insn "ssse3_phsubswv4hi3"
> [(set (match_operand:V4HI 0 "register_operand" "=y")
> (vec_concat:V4HI
> (vec_concat:V2HI
> (ss_minus:HI
> (vec_select:HI
> (match_operand:V4HI 1 "register_operand" "0")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
> (ss_minus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
> (vec_concat:V2HI
> (ss_minus:HI
> (vec_select:HI
> (match_operand:V4HI 2 "nonimmediate_operand" "ym")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
> (ss_minus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
> "TARGET_SSSE3"
> "phsubsw\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "DI")])
>
> (define_insn "ssse3_pmaddubswv8hi3"
> [(set (match_operand:V8HI 0 "register_operand" "=x")
> (ss_plus:V8HI
> (mult:V8HI
> (zero_extend:V8HI
> (vec_select:V4QI
> (match_operand:V16QI 1 "nonimmediate_operand" "%0")
> (parallel [(const_int 0)
> (const_int 2)
> (const_int 4)
> (const_int 6)
> (const_int 8)
> (const_int 10)
> (const_int 12)
> (const_int 14)])))
> (sign_extend:V8HI
> (vec_select:V8QI
> (match_operand:V16QI 2 "nonimmediate_operand" "xm")
> (parallel [(const_int 0)
> (const_int 2)
> (const_int 4)
> (const_int 6)
> (const_int 8)
> (const_int 10)
> (const_int 12)
> (const_int 14)]))))
> (mult:V8HI
> (zero_extend:V8HI
> (vec_select:V16QI (match_dup 1)
> (parallel [(const_int 1)
> (const_int 3)
> (const_int 5)
> (const_int 7)
> (const_int 9)
> (const_int 11)
> (const_int 13)
> (const_int 15)])))
> (sign_extend:V8HI
> (vec_select:V16QI (match_dup 2)
> (parallel [(const_int 1)
> (const_int 3)
> (const_int 5)
> (const_int 7)
> (const_int 9)
> (const_int 11)
> (const_int 13)
> (const_int 15)]))))))]
> "TARGET_SSSE3"
> "pmaddubsw\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "TI")])
>
> (define_insn "ssse3_pmaddubswv4hi3"
> [(set (match_operand:V4HI 0 "register_operand" "=y")
> (ss_plus:V4HI
> (mult:V4HI
> (zero_extend:V4HI
> (vec_select:V4QI
> (match_operand:V8QI 1 "nonimmediate_operand" "%0")
> (parallel [(const_int 0)
> (const_int 2)
> (const_int 4)
> (const_int 6)])))
> (sign_extend:V4HI
> (vec_select:V4QI
> (match_operand:V8QI 2 "nonimmediate_operand" "ym")
> (parallel [(const_int 0)
> (const_int 2)
> (const_int 4)
> (const_int 6)]))))
> (mult:V4HI
> (zero_extend:V4HI
> (vec_select:V8QI (match_dup 1)
> (parallel [(const_int 1)
> (const_int 3)
> (const_int 5)
> (const_int 7)])))
> (sign_extend:V4HI
> (vec_select:V8QI (match_dup 2)
> (parallel [(const_int 1)
> (const_int 3)
> (const_int 5)
> (const_int 7)]))))))]
> "TARGET_SSSE3"
> "pmaddubsw\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "DI")])
>
> (define_insn "ssse3_pmulhrswv8hi3"
> [(set (match_operand:V8HI 0 "register_operand" "=x")
> (truncate:V8HI
> (lshiftrt:V8SI
> (plus:V8SI
> (lshiftrt:V8SI
> (mult:V8SI
> (sign_extend:V8SI
> (match_operand:V8HI 1 "nonimmediate_operand" "%0"))
> (sign_extend:V8SI
> (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
> (const_int 14))
> (const_vector:V8HI [(const_int 1) (const_int 1)
> (const_int 1) (const_int 1)
> (const_int 1) (const_int 1)
> (const_int 1) (const_int 1)]))
> (const_int 1))))]
> "TARGET_SSSE3 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
> "pmulhrsw\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseimul")
> (set_attr "mode" "TI")])
>
> (define_insn "ssse3_pmulhrswv4hi3"
> [(set (match_operand:V4HI 0 "register_operand" "=y")
> (truncate:V4HI
> (lshiftrt:V4SI
> (plus:V4SI
> (lshiftrt:V4SI
> (mult:V4SI
> (sign_extend:V4SI
> (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
> (sign_extend:V4SI
> (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
> (const_int 14))
> (const_vector:V4HI [(const_int 1) (const_int 1)
> (const_int 1) (const_int 1)]))
> (const_int 1))))]
> "TARGET_SSSE3 && ix86_binary_operator_ok (MULT, V4HImode, operands)"
> "pmulhrsw\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseimul")
> (set_attr "mode" "DI")])
>
> (define_insn "ssse3_pshufbv16qi3"
> [(set (match_operand:V16QI 0 "register_operand" "=x")
> (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0")
> (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
> UNSPEC_PSHUFB))]
> "TARGET_SSSE3"
> "pshufb\t{%2, %0|%0, %2}";
> [(set_attr "type" "sselog1")
> (set_attr "mode" "TI")])
>
> (define_insn "ssse3_pshufbv8qi3"
> [(set (match_operand:V8QI 0 "register_operand" "=y")
> (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "0")
> (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
> UNSPEC_PSHUFB))]
> "TARGET_SSSE3"
> "pshufb\t{%2, %0|%0, %2}";
> [(set_attr "type" "sselog1")
> (set_attr "mode" "DI")])
>
> (define_insn "ssse3_psign<mode>3"
> [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
> (unspec:SSEMODE124 [(match_operand:SSEMODE124 1 "register_operand" "0")
> (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")]
> UNSPEC_PSIGN))]
> "TARGET_SSSE3"
> "psign<ssevecsize>\t{%2, %0|%0, %2}";
> [(set_attr "type" "sselog1")
> (set_attr "mode" "TI")])
>
> (define_insn "ssse3_psign<mode>3"
> [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
> (unspec:MMXMODEI [(match_operand:MMXMODEI 1 "register_operand" "0")
> (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")]
> UNSPEC_PSIGN))]
> "TARGET_SSSE3"
> "psign<mmxvecsize>\t{%2, %0|%0, %2}";
> [(set_attr "type" "sselog1")
> (set_attr "mode" "DI")])
>
> (define_insn "ssse3_palignrti"
> [(set (match_operand:TI 0 "register_operand" "=x")
> (unspec:TI [(match_operand:TI 1 "register_operand" "0")
> (match_operand:TI 2 "nonimmediate_operand" "xm")
> (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
> UNSPEC_PALIGNR))]
> "TARGET_SSSE3"
> {
> operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
> return "palignr\t{%3, %2, %0|%0, %2, %3}";
> }
> [(set_attr "type" "sseishft")
> (set_attr "mode" "TI")])
>
> (define_insn "ssse3_palignrdi"
> [(set (match_operand:DI 0 "register_operand" "=y")
> (unspec:DI [(match_operand:DI 1 "register_operand" "0")
> (match_operand:DI 2 "nonimmediate_operand" "ym")
> (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
> UNSPEC_PALIGNR))]
> "TARGET_SSSE3"
> {
> operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
> return "palignr\t{%3, %2, %0|%0, %2, %3}";
> }
> [(set_attr "type" "sseishft")
> (set_attr "mode" "DI")])
>
> (define_insn "abs<mode>2"
> [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
> (abs:SSEMODE124 (match_operand:SSEMODE124 1 "nonimmediate_operand" "xm")))]
> "TARGET_SSSE3"
> "pabs<ssevecsize>\t{%1, %0|%0, %1}";
> [(set_attr "type" "sselog1")
> (set_attr "mode" "TI")])
>
> (define_insn "abs<mode>2"
> [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
> (abs:MMXMODEI (match_operand:MMXMODEI 1 "nonimmediate_operand" "ym")))]
> "TARGET_SSSE3"
> "pabs<mmxvecsize>\t{%1, %0|%0, %1}";
> [(set_attr "type" "sselog1")
> (set_attr "mode" "DI")])
>
> ;; SSSE3
> (define_insn "ssse3_phaddwv8hi3"
> [(set (match_operand:V8HI 0 "register_operand" "=x")
> (vec_concat:V8HI
> (vec_concat:V4HI
> (vec_concat:V2HI
> (plus:HI
> (vec_select:HI
> (match_operand:V8HI 1 "register_operand" "0")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
> (plus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
> (vec_concat:V2HI
> (plus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
> (plus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
> (vec_concat:V4HI
> (vec_concat:V2HI
> (plus:HI
> (vec_select:HI
> (match_operand:V8HI 2 "nonimmediate_operand" "xm")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
> (plus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
> (vec_concat:V2HI
> (plus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
> (plus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
> "TARGET_SSSE3"
> "phaddw\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "TI")])
>
> (define_insn "ssse3_phaddwv4hi3"
> [(set (match_operand:V4HI 0 "register_operand" "=y")
> (vec_concat:V4HI
> (vec_concat:V2HI
> (plus:HI
> (vec_select:HI
> (match_operand:V4HI 1 "register_operand" "0")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
> (plus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
> (vec_concat:V2HI
> (plus:HI
> (vec_select:HI
> (match_operand:V4HI 2 "nonimmediate_operand" "ym")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
> (plus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
> "TARGET_SSSE3"
> "phaddw\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "DI")])
>
> (define_insn "ssse3_phadddv4si3"
> [(set (match_operand:V4SI 0 "register_operand" "=x")
> (vec_concat:V4SI
> (vec_concat:V2SI
> (plus:SI
> (vec_select:SI
> (match_operand:V4SI 1 "register_operand" "0")
> (parallel [(const_int 0)]))
> (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
> (plus:SI
> (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
> (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
> (vec_concat:V2SI
> (plus:SI
> (vec_select:SI
> (match_operand:V4SI 2 "nonimmediate_operand" "xm")
> (parallel [(const_int 0)]))
> (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
> (plus:SI
> (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
> (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
> "TARGET_SSSE3"
> "phaddd\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "TI")])
>
> (define_insn "ssse3_phadddv2si3"
> [(set (match_operand:V2SI 0 "register_operand" "=y")
> (vec_concat:V2SI
> (plus:SI
> (vec_select:SI
> (match_operand:V2SI 1 "register_operand" "0")
> (parallel [(const_int 0)]))
> (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
> (plus:SI
> (vec_select:SI
> (match_operand:V2SI 2 "nonimmediate_operand" "ym")
> (parallel [(const_int 0)]))
> (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))))]
> "TARGET_SSSE3"
> "phaddd\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "DI")])
>
> (define_insn "ssse3_phaddswv8hi3"
> [(set (match_operand:V8HI 0 "register_operand" "=x")
> (vec_concat:V8HI
> (vec_concat:V4HI
> (vec_concat:V2HI
> (ss_plus:HI
> (vec_select:HI
> (match_operand:V8HI 1 "register_operand" "0")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
> (ss_plus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
> (vec_concat:V2HI
> (ss_plus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
> (ss_plus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
> (vec_concat:V4HI
> (vec_concat:V2HI
> (ss_plus:HI
> (vec_select:HI
> (match_operand:V8HI 2 "nonimmediate_operand" "xm")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
> (ss_plus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
> (vec_concat:V2HI
> (ss_plus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
> (ss_plus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
> "TARGET_SSSE3"
> "phaddsw\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "TI")])
>
> (define_insn "ssse3_phaddswv4hi3"
> [(set (match_operand:V4HI 0 "register_operand" "=y")
> (vec_concat:V4HI
> (vec_concat:V2HI
> (ss_plus:HI
> (vec_select:HI
> (match_operand:V4HI 1 "register_operand" "0")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
> (ss_plus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
> (vec_concat:V2HI
> (ss_plus:HI
> (vec_select:HI
> (match_operand:V4HI 2 "nonimmediate_operand" "ym")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
> (ss_plus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
> "TARGET_SSSE3"
> "phaddsw\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "DI")])
>
> (define_insn "ssse3_phsubwv8hi3"
> [(set (match_operand:V8HI 0 "register_operand" "=x")
> (vec_concat:V8HI
> (vec_concat:V4HI
> (vec_concat:V2HI
> (minus:HI
> (vec_select:HI
> (match_operand:V8HI 1 "register_operand" "0")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
> (minus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
> (vec_concat:V2HI
> (minus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
> (minus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
> (vec_concat:V4HI
> (vec_concat:V2HI
> (minus:HI
> (vec_select:HI
> (match_operand:V8HI 2 "nonimmediate_operand" "xm")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
> (minus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
> (vec_concat:V2HI
> (minus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
> (minus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
> "TARGET_SSSE3"
> "phsubw\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "TI")])
>
> (define_insn "ssse3_phsubwv4hi3"
> [(set (match_operand:V4HI 0 "register_operand" "=y")
> (vec_concat:V4HI
> (vec_concat:V2HI
> (minus:HI
> (vec_select:HI
> (match_operand:V4HI 1 "register_operand" "0")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
> (minus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
> (vec_concat:V2HI
> (minus:HI
> (vec_select:HI
> (match_operand:V4HI 2 "nonimmediate_operand" "ym")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
> (minus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
> "TARGET_SSSE3"
> "phsubw\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "DI")])
>
> (define_insn "ssse3_phsubdv4si3"
> [(set (match_operand:V4SI 0 "register_operand" "=x")
> (vec_concat:V4SI
> (vec_concat:V2SI
> (minus:SI
> (vec_select:SI
> (match_operand:V4SI 1 "register_operand" "0")
> (parallel [(const_int 0)]))
> (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
> (minus:SI
> (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
> (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
> (vec_concat:V2SI
> (minus:SI
> (vec_select:SI
> (match_operand:V4SI 2 "nonimmediate_operand" "xm")
> (parallel [(const_int 0)]))
> (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
> (minus:SI
> (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
> (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
> "TARGET_SSSE3"
> "phsubd\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "TI")])
>
> (define_insn "ssse3_phsubdv2si3"
> [(set (match_operand:V2SI 0 "register_operand" "=y")
> (vec_concat:V2SI
> (minus:SI
> (vec_select:SI
> (match_operand:V2SI 1 "register_operand" "0")
> (parallel [(const_int 0)]))
> (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
> (minus:SI
> (vec_select:SI
> (match_operand:V2SI 2 "nonimmediate_operand" "ym")
> (parallel [(const_int 0)]))
> (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))))]
> "TARGET_SSSE3"
> "phsubd\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "DI")])
>
> (define_insn "ssse3_phsubswv8hi3"
> [(set (match_operand:V8HI 0 "register_operand" "=x")
> (vec_concat:V8HI
> (vec_concat:V4HI
> (vec_concat:V2HI
> (ss_minus:HI
> (vec_select:HI
> (match_operand:V8HI 1 "register_operand" "0")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
> (ss_minus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
> (vec_concat:V2HI
> (ss_minus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
> (ss_minus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
> (vec_concat:V4HI
> (vec_concat:V2HI
> (ss_minus:HI
> (vec_select:HI
> (match_operand:V8HI 2 "nonimmediate_operand" "xm")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
> (ss_minus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
> (vec_concat:V2HI
> (ss_minus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
> (ss_minus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
> "TARGET_SSSE3"
> "phsubsw\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "TI")])
>
> (define_insn "ssse3_phsubswv4hi3"
> [(set (match_operand:V4HI 0 "register_operand" "=y")
> (vec_concat:V4HI
> (vec_concat:V2HI
> (ss_minus:HI
> (vec_select:HI
> (match_operand:V4HI 1 "register_operand" "0")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
> (ss_minus:HI
> (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
> (vec_concat:V2HI
> (ss_minus:HI
> (vec_select:HI
> (match_operand:V4HI 2 "nonimmediate_operand" "ym")
> (parallel [(const_int 0)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
> (ss_minus:HI
> (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
> (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
> "TARGET_SSSE3"
> "phsubsw\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "DI")])
>
> (define_insn "ssse3_pmaddubswv8hi3"
> [(set (match_operand:V8HI 0 "register_operand" "=x")
> (ss_plus:V8HI
> (mult:V8HI
> (zero_extend:V8HI
> (vec_select:V4QI
> (match_operand:V16QI 1 "nonimmediate_operand" "%0")
> (parallel [(const_int 0)
> (const_int 2)
> (const_int 4)
> (const_int 6)
> (const_int 8)
> (const_int 10)
> (const_int 12)
> (const_int 14)])))
> (sign_extend:V8HI
> (vec_select:V8QI
> (match_operand:V16QI 2 "nonimmediate_operand" "xm")
> (parallel [(const_int 0)
> (const_int 2)
> (const_int 4)
> (const_int 6)
> (const_int 8)
> (const_int 10)
> (const_int 12)
> (const_int 14)]))))
> (mult:V8HI
> (zero_extend:V8HI
> (vec_select:V16QI (match_dup 1)
> (parallel [(const_int 1)
> (const_int 3)
> (const_int 5)
> (const_int 7)
> (const_int 9)
> (const_int 11)
> (const_int 13)
> (const_int 15)])))
> (sign_extend:V8HI
> (vec_select:V16QI (match_dup 2)
> (parallel [(const_int 1)
> (const_int 3)
> (const_int 5)
> (const_int 7)
> (const_int 9)
> (const_int 11)
> (const_int 13)
> (const_int 15)]))))))]
> "TARGET_SSSE3"
> "pmaddubsw\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "TI")])
>
> (define_insn "ssse3_pmaddubswv4hi3"
> [(set (match_operand:V4HI 0 "register_operand" "=y")
> (ss_plus:V4HI
> (mult:V4HI
> (zero_extend:V4HI
> (vec_select:V4QI
> (match_operand:V8QI 1 "nonimmediate_operand" "%0")
> (parallel [(const_int 0)
> (const_int 2)
> (const_int 4)
> (const_int 6)])))
> (sign_extend:V4HI
> (vec_select:V4QI
> (match_operand:V8QI 2 "nonimmediate_operand" "ym")
> (parallel [(const_int 0)
> (const_int 2)
> (const_int 4)
> (const_int 6)]))))
> (mult:V4HI
> (zero_extend:V4HI
> (vec_select:V8QI (match_dup 1)
> (parallel [(const_int 1)
> (const_int 3)
> (const_int 5)
> (const_int 7)])))
> (sign_extend:V4HI
> (vec_select:V8QI (match_dup 2)
> (parallel [(const_int 1)
> (const_int 3)
> (const_int 5)
> (const_int 7)]))))))]
> "TARGET_SSSE3"
> "pmaddubsw\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "mode" "DI")])
>
> (define_insn "ssse3_pmulhrswv8hi3"
> [(set (match_operand:V8HI 0 "register_operand" "=x")
> (truncate:V8HI
> (lshiftrt:V8SI
> (plus:V8SI
> (lshiftrt:V8SI
> (mult:V8SI
> (sign_extend:V8SI
> (match_operand:V8HI 1 "nonimmediate_operand" "%0"))
> (sign_extend:V8SI
> (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
> (const_int 14))
> (const_vector:V8HI [(const_int 1) (const_int 1)
> (const_int 1) (const_int 1)
> (const_int 1) (const_int 1)
> (const_int 1) (const_int 1)]))
> (const_int 1))))]
> "TARGET_SSSE3 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
> "pmulhrsw\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseimul")
> (set_attr "mode" "TI")])
>
> (define_insn "ssse3_pmulhrswv4hi3"
> [(set (match_operand:V4HI 0 "register_operand" "=y")
> (truncate:V4HI
> (lshiftrt:V4SI
> (plus:V4SI
> (lshiftrt:V4SI
> (mult:V4SI
> (sign_extend:V4SI
> (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
> (sign_extend:V4SI
> (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
> (const_int 14))
> (const_vector:V4HI [(const_int 1) (const_int 1)
> (const_int 1) (const_int 1)]))
> (const_int 1))))]
> "TARGET_SSSE3 && ix86_binary_operator_ok (MULT, V4HImode, operands)"
> "pmulhrsw\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseimul")
> (set_attr "mode" "DI")])
>
> (define_insn "ssse3_pshufbv16qi3"
> [(set (match_operand:V16QI 0 "register_operand" "=x")
> (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0")
> (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
> UNSPEC_PSHUFB))]
> "TARGET_SSSE3"
> "pshufb\t{%2, %0|%0, %2}";
> [(set_attr "type" "sselog1")
> (set_attr "mode" "TI")])
>
> (define_insn "ssse3_pshufbv8qi3"
> [(set (match_operand:V8QI 0 "register_operand" "=y")
> (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "0")
> (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
> UNSPEC_PSHUFB))]
> "TARGET_SSSE3"
> "pshufb\t{%2, %0|%0, %2}";
> [(set_attr "type" "sselog1")
> (set_attr "mode" "DI")])
>
> (define_insn "ssse3_psign<mode>3"
> [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
> (unspec:SSEMODE124 [(match_operand:SSEMODE124 1 "register_operand" "0")
> (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")]
> UNSPEC_PSIGN))]
> "TARGET_SSSE3"
> "psign<ssevecsize>\t{%2, %0|%0, %2}";
> [(set_attr "type" "sselog1")
> (set_attr "mode" "TI")])
>
> (define_insn "ssse3_psign<mode>3"
> [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
> (unspec:MMXMODEI [(match_operand:MMXMODEI 1 "register_operand" "0")
> (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")]
> UNSPEC_PSIGN))]
> "TARGET_SSSE3"
> "psign<mmxvecsize>\t{%2, %0|%0, %2}";
> [(set_attr "type" "sselog1")
> (set_attr "mode" "DI")])
>
> (define_insn "ssse3_palignrti"
> [(set (match_operand:TI 0 "register_operand" "=x")
> (unspec:TI [(match_operand:TI 1 "register_operand" "0")
> (match_operand:TI 2 "nonimmediate_operand" "xm")
> (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
> UNSPEC_PALIGNR))]
> "TARGET_SSSE3"
> {
> operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
> return "palignr\t{%3, %2, %0|%0, %2, %3}";
> }
> [(set_attr "type" "sseishft")
> (set_attr "mode" "TI")])
>
> (define_insn "ssse3_palignrdi"
> [(set (match_operand:DI 0 "register_operand" "=y")
> (unspec:DI [(match_operand:DI 1 "register_operand" "0")
> (match_operand:DI 2 "nonimmediate_operand" "ym")
> (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
> UNSPEC_PALIGNR))]
> "TARGET_SSSE3"
> {
> operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
> return "palignr\t{%3, %2, %0|%0, %2, %3}";
> }
> [(set_attr "type" "sseishft")
> (set_attr "mode" "DI")])
>
> (define_insn "abs<mode>2"
> [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
> (abs:SSEMODE124 (match_operand:SSEMODE124 1 "nonimmediate_operand" "xm")))]
> "TARGET_SSSE3"
> "pabs<ssevecsize>\t{%1, %0|%0, %1}";
> [(set_attr "type" "sselog1")
> (set_attr "mode" "TI")])
>
> (define_insn "abs<mode>2"
> [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
> (abs:MMXMODEI (match_operand:MMXMODEI 1 "nonimmediate_operand" "ym")))]
> "TARGET_SSSE3"
> "pabs<mmxvecsize>\t{%1, %0|%0, %1}";
> [(set_attr "type" "sselog1")
> (set_attr "mode" "DI")])