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i386.c (219374) i386.c (219639)
1/* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4
5This file is part of GCC.
6
7GCC is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by

--- 5 unchanged lines hidden (view full) ---

14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with GCC; see the file COPYING. If not, write to
19the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20Boston, MA 02110-1301, USA. */
21
1/* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4
5This file is part of GCC.
6
7GCC is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by

--- 5 unchanged lines hidden (view full) ---

14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with GCC; see the file COPYING. If not, write to
19the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20Boston, MA 02110-1301, USA. */
21
22/* $FreeBSD: head/contrib/gcc/config/i386/i386.c 219374 2011-03-07 14:48:22Z mm $ */
22/* $FreeBSD: head/contrib/gcc/config/i386/i386.c 219639 2011-03-14 13:31:34Z mm $ */
23
24#include "config.h"
25#include "system.h"
26#include "coretypes.h"
27#include "tm.h"
28#include "rtl.h"
29#include "tree.h"
30#include "tm_p.h"

--- 1475 unchanged lines hidden (view full) ---

1506 target_flags &= ~(MASK_3DNOW | MASK_3DNOW_A);
1507 target_flags_explicit |= MASK_3DNOW | MASK_3DNOW_A;
1508 }
1509 return true;
1510
1511 case OPT_msse:
1512 if (!value)
1513 {
23
24#include "config.h"
25#include "system.h"
26#include "coretypes.h"
27#include "tm.h"
28#include "rtl.h"
29#include "tree.h"
30#include "tm_p.h"

--- 1475 unchanged lines hidden (view full) ---

1506 target_flags &= ~(MASK_3DNOW | MASK_3DNOW_A);
1507 target_flags_explicit |= MASK_3DNOW | MASK_3DNOW_A;
1508 }
1509 return true;
1510
1511 case OPT_msse:
1512 if (!value)
1513 {
1514 target_flags &= ~(MASK_SSE2 | MASK_SSE3);
1515 target_flags_explicit |= MASK_SSE2 | MASK_SSE3;
1514 target_flags &= ~(MASK_SSE2 | MASK_SSE3 | MASK_SSSE3);
1515 target_flags_explicit |= MASK_SSE2 | MASK_SSE3 | MASK_SSSE3;
1516 }
1517 return true;
1518
1519 case OPT_msse2:
1520 if (!value)
1521 {
1516 }
1517 return true;
1518
1519 case OPT_msse2:
1520 if (!value)
1521 {
1522 target_flags &= ~MASK_SSE3;
1523 target_flags_explicit |= MASK_SSE3;
1522 target_flags &= ~(MASK_SSE3 | MASK_SSSE3);
1523 target_flags_explicit |= MASK_SSE3 | MASK_SSSE3;
1524 }
1525 return true;
1526
1524 }
1525 return true;
1526
1527 case OPT_msse3:
1528 if (!value)
1529 {
1530 target_flags &= ~MASK_SSSE3;
1531 target_flags_explicit |= MASK_SSSE3;
1532 }
1533 return true;
1534
1527 default:
1528 return true;
1529 }
1530}
1531
1532/* Sometimes certain combinations of command options do not make
1533 sense on a particular target machine. You can define a macro
1534 `OVERRIDE_OPTIONS' to take account of this. This macro, if

--- 49 unchanged lines hidden (view full) ---

1584 {
1585 PTA_SSE = 1,
1586 PTA_SSE2 = 2,
1587 PTA_SSE3 = 4,
1588 PTA_MMX = 8,
1589 PTA_PREFETCH_SSE = 16,
1590 PTA_3DNOW = 32,
1591 PTA_3DNOW_A = 64,
1535 default:
1536 return true;
1537 }
1538}
1539
1540/* Sometimes certain combinations of command options do not make
1541 sense on a particular target machine. You can define a macro
1542 `OVERRIDE_OPTIONS' to take account of this. This macro, if

--- 49 unchanged lines hidden (view full) ---

1592 {
1593 PTA_SSE = 1,
1594 PTA_SSE2 = 2,
1595 PTA_SSE3 = 4,
1596 PTA_MMX = 8,
1597 PTA_PREFETCH_SSE = 16,
1598 PTA_3DNOW = 32,
1599 PTA_3DNOW_A = 64,
1592 PTA_64BIT = 128
1600 PTA_64BIT = 128,
1601 PTA_SSSE3 = 256
1593 } flags;
1594 }
1595 const processor_alias_table[] =
1596 {
1597 {"i386", PROCESSOR_I386, 0},
1598 {"i486", PROCESSOR_I486, 0},
1599 {"i586", PROCESSOR_PENTIUM, 0},
1600 {"pentium", PROCESSOR_PENTIUM, 0},

--- 11 unchanged lines hidden (view full) ---

1612 {"pentium4", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1613 | PTA_MMX | PTA_PREFETCH_SSE},
1614 {"pentium4m", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1615 | PTA_MMX | PTA_PREFETCH_SSE},
1616 {"prescott", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3
1617 | PTA_MMX | PTA_PREFETCH_SSE},
1618 {"nocona", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT
1619 | PTA_MMX | PTA_PREFETCH_SSE},
1602 } flags;
1603 }
1604 const processor_alias_table[] =
1605 {
1606 {"i386", PROCESSOR_I386, 0},
1607 {"i486", PROCESSOR_I486, 0},
1608 {"i586", PROCESSOR_PENTIUM, 0},
1609 {"pentium", PROCESSOR_PENTIUM, 0},

--- 11 unchanged lines hidden (view full) ---

1621 {"pentium4", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1622 | PTA_MMX | PTA_PREFETCH_SSE},
1623 {"pentium4m", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1624 | PTA_MMX | PTA_PREFETCH_SSE},
1625 {"prescott", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3
1626 | PTA_MMX | PTA_PREFETCH_SSE},
1627 {"nocona", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT
1628 | PTA_MMX | PTA_PREFETCH_SSE},
1620 {"core2", PROCESSOR_CORE2, PTA_SSE | PTA_SSE2 | PTA_SSE3
1629 {"core2", PROCESSOR_CORE2, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
1621 | PTA_64BIT | PTA_MMX
1622 | PTA_PREFETCH_SSE},
1623 {"geode", PROCESSOR_GEODE, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1624 | PTA_3DNOW_A},
1625 {"k6", PROCESSOR_K6, PTA_MMX},
1626 {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1627 {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1628 {"athlon", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW

--- 177 unchanged lines hidden (view full) ---

1806 && !(target_flags_explicit & MASK_SSE))
1807 target_flags |= MASK_SSE;
1808 if (processor_alias_table[i].flags & PTA_SSE2
1809 && !(target_flags_explicit & MASK_SSE2))
1810 target_flags |= MASK_SSE2;
1811 if (processor_alias_table[i].flags & PTA_SSE3
1812 && !(target_flags_explicit & MASK_SSE3))
1813 target_flags |= MASK_SSE3;
1630 | PTA_64BIT | PTA_MMX
1631 | PTA_PREFETCH_SSE},
1632 {"geode", PROCESSOR_GEODE, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1633 | PTA_3DNOW_A},
1634 {"k6", PROCESSOR_K6, PTA_MMX},
1635 {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1636 {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1637 {"athlon", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW

--- 177 unchanged lines hidden (view full) ---

1815 && !(target_flags_explicit & MASK_SSE))
1816 target_flags |= MASK_SSE;
1817 if (processor_alias_table[i].flags & PTA_SSE2
1818 && !(target_flags_explicit & MASK_SSE2))
1819 target_flags |= MASK_SSE2;
1820 if (processor_alias_table[i].flags & PTA_SSE3
1821 && !(target_flags_explicit & MASK_SSE3))
1822 target_flags |= MASK_SSE3;
1823 if (processor_alias_table[i].flags & PTA_SSSE3
1824 && !(target_flags_explicit & MASK_SSSE3))
1825 target_flags |= MASK_SSSE3;
1814 if (processor_alias_table[i].flags & PTA_PREFETCH_SSE)
1815 x86_prefetch_sse = true;
1816 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
1817 error ("CPU you selected does not support x86-64 "
1818 "instruction set");
1819 break;
1820 }
1821

--- 160 unchanged lines hidden (view full) ---

1982 if (x86_arch_always_fancy_math_387 & (1 << ix86_arch))
1983 target_flags &= ~MASK_NO_FANCY_MATH_387;
1984
1985 /* Likewise, if the target doesn't have a 387, or we've specified
1986 software floating point, don't use 387 inline intrinsics. */
1987 if (!TARGET_80387)
1988 target_flags |= MASK_NO_FANCY_MATH_387;
1989
1826 if (processor_alias_table[i].flags & PTA_PREFETCH_SSE)
1827 x86_prefetch_sse = true;
1828 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
1829 error ("CPU you selected does not support x86-64 "
1830 "instruction set");
1831 break;
1832 }
1833

--- 160 unchanged lines hidden (view full) ---

1994 if (x86_arch_always_fancy_math_387 & (1 << ix86_arch))
1995 target_flags &= ~MASK_NO_FANCY_MATH_387;
1996
1997 /* Likewise, if the target doesn't have a 387, or we've specified
1998 software floating point, don't use 387 inline intrinsics. */
1999 if (!TARGET_80387)
2000 target_flags |= MASK_NO_FANCY_MATH_387;
2001
2002 /* Turn on SSE3 builtins for -mssse3. */
2003 if (TARGET_SSSE3)
2004 target_flags |= MASK_SSE3;
2005
1990 /* Turn on SSE2 builtins for -msse3. */
1991 if (TARGET_SSE3)
1992 target_flags |= MASK_SSE2;
1993
1994 /* Turn on SSE builtins for -msse2. */
1995 if (TARGET_SSE2)
1996 target_flags |= MASK_SSE;
1997

--- 12690 unchanged lines hidden (view full) ---

14688 IX86_BUILTIN_ADDSUBPD,
14689 IX86_BUILTIN_HADDPD,
14690 IX86_BUILTIN_HSUBPD,
14691 IX86_BUILTIN_LDDQU,
14692
14693 IX86_BUILTIN_MONITOR,
14694 IX86_BUILTIN_MWAIT,
14695
2006 /* Turn on SSE2 builtins for -msse3. */
2007 if (TARGET_SSE3)
2008 target_flags |= MASK_SSE2;
2009
2010 /* Turn on SSE builtins for -msse2. */
2011 if (TARGET_SSE2)
2012 target_flags |= MASK_SSE;
2013

--- 12690 unchanged lines hidden (view full) ---

14704 IX86_BUILTIN_ADDSUBPD,
14705 IX86_BUILTIN_HADDPD,
14706 IX86_BUILTIN_HSUBPD,
14707 IX86_BUILTIN_LDDQU,
14708
14709 IX86_BUILTIN_MONITOR,
14710 IX86_BUILTIN_MWAIT,
14711
14712 /* SSSE3. */
14713 IX86_BUILTIN_PHADDW,
14714 IX86_BUILTIN_PHADDD,
14715 IX86_BUILTIN_PHADDSW,
14716 IX86_BUILTIN_PHSUBW,
14717 IX86_BUILTIN_PHSUBD,
14718 IX86_BUILTIN_PHSUBSW,
14719 IX86_BUILTIN_PMADDUBSW,
14720 IX86_BUILTIN_PMULHRSW,
14721 IX86_BUILTIN_PSHUFB,
14722 IX86_BUILTIN_PSIGNB,
14723 IX86_BUILTIN_PSIGNW,
14724 IX86_BUILTIN_PSIGND,
14725 IX86_BUILTIN_PALIGNR,
14726 IX86_BUILTIN_PABSB,
14727 IX86_BUILTIN_PABSW,
14728 IX86_BUILTIN_PABSD,
14729
14730 IX86_BUILTIN_PHADDW128,
14731 IX86_BUILTIN_PHADDD128,
14732 IX86_BUILTIN_PHADDSW128,
14733 IX86_BUILTIN_PHSUBW128,
14734 IX86_BUILTIN_PHSUBD128,
14735 IX86_BUILTIN_PHSUBSW128,
14736 IX86_BUILTIN_PMADDUBSW128,
14737 IX86_BUILTIN_PMULHRSW128,
14738 IX86_BUILTIN_PSHUFB128,
14739 IX86_BUILTIN_PSIGNB128,
14740 IX86_BUILTIN_PSIGNW128,
14741 IX86_BUILTIN_PSIGND128,
14742 IX86_BUILTIN_PALIGNR128,
14743 IX86_BUILTIN_PABSB128,
14744 IX86_BUILTIN_PABSW128,
14745 IX86_BUILTIN_PABSD128,
14746
14696 IX86_BUILTIN_VEC_INIT_V2SI,
14697 IX86_BUILTIN_VEC_INIT_V4HI,
14698 IX86_BUILTIN_VEC_INIT_V8QI,
14699 IX86_BUILTIN_VEC_EXT_V2DF,
14700 IX86_BUILTIN_VEC_EXT_V2DI,
14701 IX86_BUILTIN_VEC_EXT_V4SF,
14702 IX86_BUILTIN_VEC_EXT_V4SI,
14703 IX86_BUILTIN_VEC_EXT_V8HI,

--- 325 unchanged lines hidden (view full) ---

15029 { MASK_SSE2, CODE_FOR_sse2_cvtss2sd, 0, IX86_BUILTIN_CVTSS2SD, 0, 0 },
15030
15031 /* SSE3 MMX */
15032 { MASK_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, 0, 0 },
15033 { MASK_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, 0, 0 },
15034 { MASK_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, 0, 0 },
15035 { MASK_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, 0, 0 },
15036 { MASK_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, 0, 0 },
14747 IX86_BUILTIN_VEC_INIT_V2SI,
14748 IX86_BUILTIN_VEC_INIT_V4HI,
14749 IX86_BUILTIN_VEC_INIT_V8QI,
14750 IX86_BUILTIN_VEC_EXT_V2DF,
14751 IX86_BUILTIN_VEC_EXT_V2DI,
14752 IX86_BUILTIN_VEC_EXT_V4SF,
14753 IX86_BUILTIN_VEC_EXT_V4SI,
14754 IX86_BUILTIN_VEC_EXT_V8HI,

--- 325 unchanged lines hidden (view full) ---

15080 { MASK_SSE2, CODE_FOR_sse2_cvtss2sd, 0, IX86_BUILTIN_CVTSS2SD, 0, 0 },
15081
15082 /* SSE3 MMX */
15083 { MASK_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, 0, 0 },
15084 { MASK_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, 0, 0 },
15085 { MASK_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, 0, 0 },
15086 { MASK_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, 0, 0 },
15087 { MASK_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, 0, 0 },
15037 { MASK_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, 0, 0 }
15088 { MASK_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, 0, 0 },
15089
15090 /* SSSE3 */
15091 { MASK_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, 0, 0 },
15092 { MASK_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, 0, 0 },
15093 { MASK_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, 0, 0 },
15094 { MASK_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, 0, 0 },
15095 { MASK_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, 0, 0 },
15096 { MASK_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, 0, 0 },
15097 { MASK_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, 0, 0 },
15098 { MASK_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, 0, 0 },
15099 { MASK_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, 0, 0 },
15100 { MASK_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, 0, 0 },
15101 { MASK_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, 0, 0 },
15102 { MASK_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, 0, 0 },
15103 { MASK_SSSE3, CODE_FOR_ssse3_pmaddubswv8hi3, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, 0, 0 },
15104 { MASK_SSSE3, CODE_FOR_ssse3_pmaddubswv4hi3, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, 0, 0 },
15105 { MASK_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, 0, 0 },
15106 { MASK_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, 0, 0 },
15107 { MASK_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, 0, 0 },
15108 { MASK_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, 0, 0 },
15109 { MASK_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, 0, 0 },
15110 { MASK_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, 0, 0 },
15111 { MASK_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, 0, 0 },
15112 { MASK_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, 0, 0 },
15113 { MASK_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, 0, 0 },
15114 { MASK_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, 0, 0 }
15038};
15039
15040static const struct builtin_description bdesc_1arg[] =
15041{
15042 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB, 0, 0 },
15043 { MASK_SSE, CODE_FOR_sse_movmskps, 0, IX86_BUILTIN_MOVMSKPS, 0, 0 },
15044
15045 { MASK_SSE, CODE_FOR_sqrtv4sf2, 0, IX86_BUILTIN_SQRTPS, 0, 0 },

--- 30 unchanged lines hidden (view full) ---

15076
15077 { MASK_SSE2, CODE_FOR_sse2_cvtps2dq, 0, IX86_BUILTIN_CVTPS2DQ, 0, 0 },
15078 { MASK_SSE2, CODE_FOR_sse2_cvtps2pd, 0, IX86_BUILTIN_CVTPS2PD, 0, 0 },
15079 { MASK_SSE2, CODE_FOR_sse2_cvttps2dq, 0, IX86_BUILTIN_CVTTPS2DQ, 0, 0 },
15080
15081 /* SSE3 */
15082 { MASK_SSE3, CODE_FOR_sse3_movshdup, 0, IX86_BUILTIN_MOVSHDUP, 0, 0 },
15083 { MASK_SSE3, CODE_FOR_sse3_movsldup, 0, IX86_BUILTIN_MOVSLDUP, 0, 0 },
15115};
15116
15117static const struct builtin_description bdesc_1arg[] =
15118{
15119 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB, 0, 0 },
15120 { MASK_SSE, CODE_FOR_sse_movmskps, 0, IX86_BUILTIN_MOVMSKPS, 0, 0 },
15121
15122 { MASK_SSE, CODE_FOR_sqrtv4sf2, 0, IX86_BUILTIN_SQRTPS, 0, 0 },

--- 30 unchanged lines hidden (view full) ---

15153
15154 { MASK_SSE2, CODE_FOR_sse2_cvtps2dq, 0, IX86_BUILTIN_CVTPS2DQ, 0, 0 },
15155 { MASK_SSE2, CODE_FOR_sse2_cvtps2pd, 0, IX86_BUILTIN_CVTPS2PD, 0, 0 },
15156 { MASK_SSE2, CODE_FOR_sse2_cvttps2dq, 0, IX86_BUILTIN_CVTTPS2DQ, 0, 0 },
15157
15158 /* SSE3 */
15159 { MASK_SSE3, CODE_FOR_sse3_movshdup, 0, IX86_BUILTIN_MOVSHDUP, 0, 0 },
15160 { MASK_SSE3, CODE_FOR_sse3_movsldup, 0, IX86_BUILTIN_MOVSLDUP, 0, 0 },
15161
15162 /* SSSE3 */
15163 { MASK_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, 0, 0 },
15164 { MASK_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, 0, 0 },
15165 { MASK_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, 0, 0 },
15166 { MASK_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, 0, 0 },
15167 { MASK_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, 0, 0 },
15168 { MASK_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, 0, 0 },
15084};
15085
15086static void
15087ix86_init_builtins (void)
15088{
15089 if (TARGET_MMX)
15090 ix86_init_mmx_sse_builtins ();
15091}

--- 118 unchanged lines hidden (view full) ---

15210 pdi_type_node, long_long_unsigned_type_node,
15211 NULL_TREE);
15212 tree void_ftype_pv2di_v2di
15213 = build_function_type_list (void_type_node,
15214 pv2di_type_node, V2DI_type_node, NULL_TREE);
15215 /* Normal vector unops. */
15216 tree v4sf_ftype_v4sf
15217 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
15169};
15170
15171static void
15172ix86_init_builtins (void)
15173{
15174 if (TARGET_MMX)
15175 ix86_init_mmx_sse_builtins ();
15176}

--- 118 unchanged lines hidden (view full) ---

15295 pdi_type_node, long_long_unsigned_type_node,
15296 NULL_TREE);
15297 tree void_ftype_pv2di_v2di
15298 = build_function_type_list (void_type_node,
15299 pv2di_type_node, V2DI_type_node, NULL_TREE);
15300 /* Normal vector unops. */
15301 tree v4sf_ftype_v4sf
15302 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
15303 tree v16qi_ftype_v16qi
15304 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
15305 tree v8hi_ftype_v8hi
15306 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
15307 tree v4si_ftype_v4si
15308 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
15309 tree v8qi_ftype_v8qi
15310 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
15311 tree v4hi_ftype_v4hi
15312 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
15218
15219 /* Normal vector binops. */
15220 tree v4sf_ftype_v4sf_v4sf
15221 = build_function_type_list (V4SF_type_node,
15222 V4SF_type_node, V4SF_type_node, NULL_TREE);
15223 tree v8qi_ftype_v8qi_v8qi
15224 = build_function_type_list (V8QI_type_node,
15225 V8QI_type_node, V8QI_type_node, NULL_TREE);
15226 tree v4hi_ftype_v4hi_v4hi
15227 = build_function_type_list (V4HI_type_node,
15228 V4HI_type_node, V4HI_type_node, NULL_TREE);
15229 tree v2si_ftype_v2si_v2si
15230 = build_function_type_list (V2SI_type_node,
15231 V2SI_type_node, V2SI_type_node, NULL_TREE);
15232 tree di_ftype_di_di
15233 = build_function_type_list (long_long_unsigned_type_node,
15234 long_long_unsigned_type_node,
15235 long_long_unsigned_type_node, NULL_TREE);
15236
15313
15314 /* Normal vector binops. */
15315 tree v4sf_ftype_v4sf_v4sf
15316 = build_function_type_list (V4SF_type_node,
15317 V4SF_type_node, V4SF_type_node, NULL_TREE);
15318 tree v8qi_ftype_v8qi_v8qi
15319 = build_function_type_list (V8QI_type_node,
15320 V8QI_type_node, V8QI_type_node, NULL_TREE);
15321 tree v4hi_ftype_v4hi_v4hi
15322 = build_function_type_list (V4HI_type_node,
15323 V4HI_type_node, V4HI_type_node, NULL_TREE);
15324 tree v2si_ftype_v2si_v2si
15325 = build_function_type_list (V2SI_type_node,
15326 V2SI_type_node, V2SI_type_node, NULL_TREE);
15327 tree di_ftype_di_di
15328 = build_function_type_list (long_long_unsigned_type_node,
15329 long_long_unsigned_type_node,
15330 long_long_unsigned_type_node, NULL_TREE);
15331
15332 tree di_ftype_di_di_int
15333 = build_function_type_list (long_long_unsigned_type_node,
15334 long_long_unsigned_type_node,
15335 long_long_unsigned_type_node,
15336 integer_type_node, NULL_TREE);
15337
15237 tree v2si_ftype_v2sf
15238 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
15239 tree v2sf_ftype_v2si
15240 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
15241 tree v2si_ftype_v2si
15242 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
15243 tree v2sf_ftype_v2sf
15244 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);

--- 85 unchanged lines hidden (view full) ---

15330 tree v2di_ftype_v2df_v2df
15331 = build_function_type_list (V2DI_type_node,
15332 V2DF_type_node, V2DF_type_node, NULL_TREE);
15333 tree v2df_ftype_v2df
15334 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
15335 tree v2di_ftype_v2di_int
15336 = build_function_type_list (V2DI_type_node,
15337 V2DI_type_node, integer_type_node, NULL_TREE);
15338 tree v2si_ftype_v2sf
15339 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
15340 tree v2sf_ftype_v2si
15341 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
15342 tree v2si_ftype_v2si
15343 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
15344 tree v2sf_ftype_v2sf
15345 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);

--- 85 unchanged lines hidden (view full) ---

15431 tree v2di_ftype_v2df_v2df
15432 = build_function_type_list (V2DI_type_node,
15433 V2DF_type_node, V2DF_type_node, NULL_TREE);
15434 tree v2df_ftype_v2df
15435 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
15436 tree v2di_ftype_v2di_int
15437 = build_function_type_list (V2DI_type_node,
15438 V2DI_type_node, integer_type_node, NULL_TREE);
15439 tree v2di_ftype_v2di_v2di_int
15440 = build_function_type_list (V2DI_type_node, V2DI_type_node,
15441 V2DI_type_node, integer_type_node, NULL_TREE);
15338 tree v4si_ftype_v4si_int
15339 = build_function_type_list (V4SI_type_node,
15340 V4SI_type_node, integer_type_node, NULL_TREE);
15341 tree v8hi_ftype_v8hi_int
15342 = build_function_type_list (V8HI_type_node,
15343 V8HI_type_node, integer_type_node, NULL_TREE);
15344 tree v4si_ftype_v8hi_v8hi
15345 = build_function_type_list (V4SI_type_node,

--- 100 unchanged lines hidden (view full) ---

15446
15447 if (d->icode == CODE_FOR_sse2_maskcmpv2df3
15448 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
15449 type = v2di_ftype_v2df_v2df;
15450
15451 def_builtin (d->mask, d->name, type, d->code);
15452 }
15453
15442 tree v4si_ftype_v4si_int
15443 = build_function_type_list (V4SI_type_node,
15444 V4SI_type_node, integer_type_node, NULL_TREE);
15445 tree v8hi_ftype_v8hi_int
15446 = build_function_type_list (V8HI_type_node,
15447 V8HI_type_node, integer_type_node, NULL_TREE);
15448 tree v4si_ftype_v8hi_v8hi
15449 = build_function_type_list (V4SI_type_node,

--- 100 unchanged lines hidden (view full) ---

15550
15551 if (d->icode == CODE_FOR_sse2_maskcmpv2df3
15552 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
15553 type = v2di_ftype_v2df_v2df;
15554
15555 def_builtin (d->mask, d->name, type, d->code);
15556 }
15557
15558 /* Add all builtins that are more or less simple operations on 1 operand. */
15559 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
15560 {
15561 enum machine_mode mode;
15562 tree type;
15563
15564 if (d->name == 0)
15565 continue;
15566 mode = insn_data[d->icode].operand[1].mode;
15567
15568 switch (mode)
15569 {
15570 case V16QImode:
15571 type = v16qi_ftype_v16qi;
15572 break;
15573 case V8HImode:
15574 type = v8hi_ftype_v8hi;
15575 break;
15576 case V4SImode:
15577 type = v4si_ftype_v4si;
15578 break;
15579 case V2DFmode:
15580 type = v2df_ftype_v2df;
15581 break;
15582 case V4SFmode:
15583 type = v4sf_ftype_v4sf;
15584 break;
15585 case V8QImode:
15586 type = v8qi_ftype_v8qi;
15587 break;
15588 case V4HImode:
15589 type = v4hi_ftype_v4hi;
15590 break;
15591 case V2SImode:
15592 type = v2si_ftype_v2si;
15593 break;
15594
15595 default:
15596 abort ();
15597 }
15598
15599 def_builtin (d->mask, d->name, type, d->code);
15600 }
15601
15454 /* Add the remaining MMX insns with somewhat more complicated types. */
15455 def_builtin (MASK_MMX, "__builtin_ia32_emms", void_ftype_void, IX86_BUILTIN_EMMS);
15456 def_builtin (MASK_MMX, "__builtin_ia32_psllw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSLLW);
15457 def_builtin (MASK_MMX, "__builtin_ia32_pslld", v2si_ftype_v2si_di, IX86_BUILTIN_PSLLD);
15458 def_builtin (MASK_MMX, "__builtin_ia32_psllq", di_ftype_di_di, IX86_BUILTIN_PSLLQ);
15459
15460 def_builtin (MASK_MMX, "__builtin_ia32_psrlw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSRLW);
15461 def_builtin (MASK_MMX, "__builtin_ia32_psrld", v2si_ftype_v2si_di, IX86_BUILTIN_PSRLD);

--- 183 unchanged lines hidden (view full) ---

15645 v4sf_ftype_v4sf,
15646 IX86_BUILTIN_MOVSHDUP);
15647 def_builtin (MASK_SSE3, "__builtin_ia32_movsldup",
15648 v4sf_ftype_v4sf,
15649 IX86_BUILTIN_MOVSLDUP);
15650 def_builtin (MASK_SSE3, "__builtin_ia32_lddqu",
15651 v16qi_ftype_pcchar, IX86_BUILTIN_LDDQU);
15652
15602 /* Add the remaining MMX insns with somewhat more complicated types. */
15603 def_builtin (MASK_MMX, "__builtin_ia32_emms", void_ftype_void, IX86_BUILTIN_EMMS);
15604 def_builtin (MASK_MMX, "__builtin_ia32_psllw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSLLW);
15605 def_builtin (MASK_MMX, "__builtin_ia32_pslld", v2si_ftype_v2si_di, IX86_BUILTIN_PSLLD);
15606 def_builtin (MASK_MMX, "__builtin_ia32_psllq", di_ftype_di_di, IX86_BUILTIN_PSLLQ);
15607
15608 def_builtin (MASK_MMX, "__builtin_ia32_psrlw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSRLW);
15609 def_builtin (MASK_MMX, "__builtin_ia32_psrld", v2si_ftype_v2si_di, IX86_BUILTIN_PSRLD);

--- 183 unchanged lines hidden (view full) ---

15793 v4sf_ftype_v4sf,
15794 IX86_BUILTIN_MOVSHDUP);
15795 def_builtin (MASK_SSE3, "__builtin_ia32_movsldup",
15796 v4sf_ftype_v4sf,
15797 IX86_BUILTIN_MOVSLDUP);
15798 def_builtin (MASK_SSE3, "__builtin_ia32_lddqu",
15799 v16qi_ftype_pcchar, IX86_BUILTIN_LDDQU);
15800
15801 /* SSSE3. */
15802 def_builtin (MASK_SSSE3, "__builtin_ia32_palignr128",
15803 v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PALIGNR128);
15804 def_builtin (MASK_SSSE3, "__builtin_ia32_palignr", di_ftype_di_di_int,
15805 IX86_BUILTIN_PALIGNR);
15806
15653 /* Access to the vec_init patterns. */
15654 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
15655 integer_type_node, NULL_TREE);
15656 def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v2si",
15657 ftype, IX86_BUILTIN_VEC_INIT_V2SI);
15658
15659 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
15660 short_integer_type_node,

--- 482 unchanged lines hidden (view full) ---

16143{
16144 const struct builtin_description *d;
16145 size_t i;
16146 enum insn_code icode;
16147 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
16148 tree arglist = TREE_OPERAND (exp, 1);
16149 tree arg0, arg1, arg2;
16150 rtx op0, op1, op2, pat;
15807 /* Access to the vec_init patterns. */
15808 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
15809 integer_type_node, NULL_TREE);
15810 def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v2si",
15811 ftype, IX86_BUILTIN_VEC_INIT_V2SI);
15812
15813 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
15814 short_integer_type_node,

--- 482 unchanged lines hidden (view full) ---

16297{
16298 const struct builtin_description *d;
16299 size_t i;
16300 enum insn_code icode;
16301 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
16302 tree arglist = TREE_OPERAND (exp, 1);
16303 tree arg0, arg1, arg2;
16304 rtx op0, op1, op2, pat;
16151 enum machine_mode tmode, mode0, mode1, mode2;
16305 enum machine_mode tmode, mode0, mode1, mode2, mode3;
16152 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
16153
16154 switch (fcode)
16155 {
16156 case IX86_BUILTIN_EMMS:
16157 emit_insn (gen_mmx_emms ());
16158 return 0;
16159

--- 453 unchanged lines hidden (view full) ---

16613 op1 = copy_to_mode_reg (SImode, op1);
16614 emit_insn (gen_sse3_mwait (op0, op1));
16615 return 0;
16616
16617 case IX86_BUILTIN_LDDQU:
16618 return ix86_expand_unop_builtin (CODE_FOR_sse3_lddqu, arglist,
16619 target, 1);
16620
16306 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
16307
16308 switch (fcode)
16309 {
16310 case IX86_BUILTIN_EMMS:
16311 emit_insn (gen_mmx_emms ());
16312 return 0;
16313

--- 453 unchanged lines hidden (view full) ---

16767 op1 = copy_to_mode_reg (SImode, op1);
16768 emit_insn (gen_sse3_mwait (op0, op1));
16769 return 0;
16770
16771 case IX86_BUILTIN_LDDQU:
16772 return ix86_expand_unop_builtin (CODE_FOR_sse3_lddqu, arglist,
16773 target, 1);
16774
16775 case IX86_BUILTIN_PALIGNR:
16776 case IX86_BUILTIN_PALIGNR128:
16777 if (fcode == IX86_BUILTIN_PALIGNR)
16778 {
16779 icode = CODE_FOR_ssse3_palignrdi;
16780 mode = DImode;
16781 }
16782 else
16783 {
16784 icode = CODE_FOR_ssse3_palignrti;
16785 mode = V2DImode;
16786 }
16787 arg0 = TREE_VALUE (arglist);
16788 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
16789 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
16790 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
16791 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
16792 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
16793 tmode = insn_data[icode].operand[0].mode;
16794 mode1 = insn_data[icode].operand[1].mode;
16795 mode2 = insn_data[icode].operand[2].mode;
16796 mode3 = insn_data[icode].operand[3].mode;
16797
16798 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
16799 {
16800 op0 = copy_to_reg (op0);
16801 op0 = simplify_gen_subreg (mode1, op0, GET_MODE (op0), 0);
16802 }
16803 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
16804 {
16805 op1 = copy_to_reg (op1);
16806 op1 = simplify_gen_subreg (mode2, op1, GET_MODE (op1), 0);
16807 }
16808 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
16809 {
16810 error ("shift must be an immediate");
16811 return const0_rtx;
16812 }
16813 target = gen_reg_rtx (mode);
16814 pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target, mode, 0),
16815 op0, op1, op2);
16816 if (! pat)
16817 return 0;
16818 emit_insn (pat);
16819 return target;
16820
16621 case IX86_BUILTIN_VEC_INIT_V2SI:
16622 case IX86_BUILTIN_VEC_INIT_V4HI:
16623 case IX86_BUILTIN_VEC_INIT_V8QI:
16624 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), arglist, target);
16625
16626 case IX86_BUILTIN_VEC_EXT_V2DF:
16627 case IX86_BUILTIN_VEC_EXT_V2DI:
16628 case IX86_BUILTIN_VEC_EXT_V4SF:

--- 2671 unchanged lines hidden --- 		16821 case IX86_BUILTIN_VEC_INIT_V2SI:
16822 case IX86_BUILTIN_VEC_INIT_V4HI:
16823 case IX86_BUILTIN_VEC_INIT_V8QI:
16824 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), arglist, target);
16825
16826 case IX86_BUILTIN_VEC_EXT_V2DF:
16827 case IX86_BUILTIN_VEC_EXT_V2DI:
16828 case IX86_BUILTIN_VEC_EXT_V4SF:

--- 2671 unchanged lines hidden ---