522007-03-11 Ian Lance Taylor <iant@google.com> (r122831 - partial) 53 54 * tree-vrp.c (vrp_int_const_binop): Handle PLUS_EXPR and 55 the *_DIV_EXPR codes correctly with overflow infinities. 56 572007-02-09 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r121763) 58 59 * config/i386/driver-i386.c: Turn on -mtune=native for AMDFAM10. 60 (bit_SSE4a): New. 61 622007-02-08 Harsha Jagasia <harsha.jagasia@amd.com> (r121726) 63 64 * config/i386/xmmintrin.h: Make inclusion of emmintrin.h 65 conditional to __SSE2__. 66 (Entries below should have been added to first ChangeLog 67 entry for amdfam10 dated 2007-02-05) 68 * config/i386/emmintrin.h: Generate #error if __SSE2__ is not 69 defined. 70 * config/i386/pmmintrin.h: Generate #error if __SSE3__ is not 71 defined. 72 * config/i386/tmmintrin.h: Generate #error if __SSSE3__ is not 73 defined. 74 752007-02-07 Jakub Jelinek <jakub@redhat.com> (r121687) 76 77 * config/i386/i386.c (override_options): Set PTA_SSSE3 for core2. 78 792007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 80 81 * config/i386/athlon.md (athlon_fldxf_k8, athlon_fld_k8, 82 athlon_fstxf_k8, athlon_fst_k8, athlon_fist, athlon_fmov, 83 athlon_fadd_load, athlon_fadd_load_k8, athlon_fadd, athlon_fmul, 84 athlon_fmul_load, athlon_fmul_load_k8, athlon_fsgn, 85 athlon_fdiv_load, athlon_fdiv_load_k8, athlon_fdiv_k8, 86 athlon_fpspc_load, athlon_fpspc, athlon_fcmov_load, 87 athlon_fcmov_load_k8, athlon_fcmov_k8, athlon_fcomi_load_k8, 88 athlon_fcomi, athlon_fcom_load_k8, athlon_fcom): Added amdfam10. 89 902007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 91 92 * config/i386/i386.md (x86_sahf_1, cmpfp_i_mixed, cmpfp_i_sse, 93 cmpfp_i_i387, cmpfp_iu_mixed, cmpfp_iu_sse, cmpfp_iu_387, 94 swapsi, swaphi_1, swapqi_1, swapdi_rex64, fix_truncsfdi_sse, 95 fix_truncdfdi_sse, fix_truncsfsi_sse, fix_truncdfsi_sse, 96 x86_fldcw_1, floatsisf2_mixed, floatsisf2_sse, floatdisf2_mixed, 97 floatdisf2_sse, floatsidf2_mixed, floatsidf2_sse, 98 floatdidf2_mixed, floatdidf2_sse, muldi3_1_rex64, mulsi3_1, 99 mulsi3_1_zext, mulhi3_1, mulqi3_1, umulqihi3_1, mulqihi3_insn, 100 umulditi3_insn, umulsidi3_insn, mulditi3_insn, mulsidi3_insn, 101 umuldi3_highpart_rex64, umulsi3_highpart_insn, 102 umulsi3_highpart_zext, smuldi3_highpart_rex64, 103 smulsi3_highpart_insn, smulsi3_highpart_zext, x86_64_shld, 104 x86_shld_1, x86_64_shrd, sqrtsf2_mixed, sqrtsf2_sse, 105 sqrtsf2_i387, sqrtdf2_mixed, sqrtdf2_sse, sqrtdf2_i387, 106 sqrtextendsfdf2_i387, sqrtxf2, sqrtextendsfxf2_i387, 107 sqrtextenddfxf2_i387): Added amdfam10_decode. 108 109 * config/i386/athlon.md (athlon_idirect_amdfam10, 110 athlon_ivector_amdfam10, athlon_idirect_load_amdfam10, 111 athlon_ivector_load_amdfam10, athlon_idirect_both_amdfam10, 112 athlon_ivector_both_amdfam10, athlon_idirect_store_amdfam10, 113 athlon_ivector_store_amdfam10): New define_insn_reservation. 114 (athlon_idirect_loadmov, athlon_idirect_movstore): Added 115 amdfam10. 116 1172007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 118 119 * config/i386/athlon.md (athlon_call_amdfam10, 120 athlon_pop_amdfam10, athlon_lea_amdfam10): New 121 define_insn_reservation. 122 (athlon_branch, athlon_push, athlon_leave_k8, athlon_imul_k8, 123 athlon_imul_k8_DI, athlon_imul_mem_k8, athlon_imul_mem_k8_DI, 124 athlon_idiv, athlon_idiv_mem, athlon_str): Added amdfam10. 125 1262007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 127 128 * config/i386/athlon.md (athlon_sseld_amdfam10, 129 athlon_mmxld_amdfam10, athlon_ssest_amdfam10, 130 athlon_mmxssest_short_amdfam10): New define_insn_reservation. 131 1322007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 133 134 * config/i386/athlon.md (athlon_sseins_amdfam10): New 135 define_insn_reservation. 136 * config/i386/i386.md (sseins): Added sseins to define_attr type 137 and define_attr unit. 138 * config/i386/sse.md: Set type attribute to sseins for insertq 139 and insertqi. 140 1412007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 142 143 * config/i386/athlon.md (sselog_load_amdfam10, sselog_amdfam10, 144 ssecmpvector_load_amdfam10, ssecmpvector_amdfam10, 145 ssecomi_load_amdfam10, ssecomi_amdfam10, 146 sseaddvector_load_amdfam10, sseaddvector_amdfam10): New 147 define_insn_reservation. 148 (ssecmp_load_k8, ssecmp, sseadd_load_k8, seadd): Added amdfam10. 149 1502007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 151 152 * config/i386/athlon.md (cvtss2sd_load_amdfam10, 153 cvtss2sd_amdfam10, cvtps2pd_load_amdfam10, cvtps2pd_amdfam10, 154 cvtsi2sd_load_amdfam10, cvtsi2ss_load_amdfam10, 155 cvtsi2sd_amdfam10, cvtsi2ss_amdfam10, cvtsd2ss_load_amdfam10, 156 cvtsd2ss_amdfam10, cvtpd2ps_load_amdfam10, cvtpd2ps_amdfam10, 157 cvtsX2si_load_amdfam10, cvtsX2si_amdfam10): New 158 define_insn_reservation. 159 160 * config/i386/sse.md (cvtsi2ss, cvtsi2ssq, cvtss2si, 161 cvtss2siq, cvttss2si, cvttss2siq, cvtsi2sd, cvtsi2sdq, 162 cvtsd2si, cvtsd2siq, cvttsd2si, cvttsd2siq, 163 cvtpd2dq, cvttpd2dq, cvtsd2ss, cvtss2sd, 164 cvtpd2ps, cvtps2pd): Added amdfam10_decode attribute. 165 1662007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 167 168 * config/i386/athlon.md (athlon_ssedivvector_amdfam10, 169 athlon_ssedivvector_load_amdfam10, athlon_ssemulvector_amdfam10, 170 athlon_ssemulvector_load_amdfam10): New define_insn_reservation. 171 (athlon_ssediv, athlon_ssediv_load_k8, athlon_ssemul, 172 athlon_ssemul_load_k8): Added amdfam10. 173 1742007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 175 176 * config/i386/i386.h (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL): New macro. 177 (x86_sse_unaligned_move_optimal): New variable. 178 179 * config/i386/i386.c (x86_sse_unaligned_move_optimal): Enable for 180 m_AMDFAM10. 181 (ix86_expand_vector_move_misalign): Add code to generate movupd/movups 182 for unaligned vector SSE double/single precision loads for AMDFAM10. 183 1842007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 185 186 * config/i386/i386.h (TARGET_AMDFAM10): New macro. 187 (TARGET_CPU_CPP_BUILTINS): Add code for amdfam10. 188 Define TARGET_CPU_DEFAULT_amdfam10. 189 (TARGET_CPU_DEFAULT_NAMES): Add amdfam10. 190 (processor_type): Add PROCESSOR_AMDFAM10. 191 192 * config/i386/i386.md: Add amdfam10 as a new cpu attribute to match 193 processor_type in config/i386/i386.h. 194 Enable imul peepholes for TARGET_AMDFAM10. 195 196 * config.gcc: Add support for --with-cpu option for amdfam10. 197 198 * config/i386/i386.c (amdfam10_cost): New variable. 199 (m_AMDFAM10): New macro. 200 (m_ATHLON_K8_AMDFAM10): New macro. 201 (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen, 202 x86_cmove, x86_3dnow_a, x86_deep_branch, x86_use_simode_fiop, 203 x86_promote_QImode, x86_integer_DFmode_moves, 204 x86_partial_reg_dependency, x86_memory_mismatch_stall, 205 x86_accumulate_outgoing_args, x86_arch_always_fancy_math_387, 206 x86_sse_partial_reg_dependency, x86_sse_typeless_stores, 207 x86_use_ffreep, x86_use_incdec, x86_four_jump_limit, 208 x86_schedule, x86_use_bt, x86_cmpxchg16b, x86_pad_returns): 209 Enable/disable for amdfam10. 210 (override_options): Add amdfam10_cost to processor_target_table. 211 Set up PROCESSOR_AMDFAM10 for amdfam10 entry in 212 processor_alias_table. 213 (ix86_issue_rate): Add PROCESSOR_AMDFAM10. 214 (ix86_adjust_cost): Add code for amdfam10. 215 2162007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 217 218 * config/i386/i386.opt: Add new Advanced Bit Manipulation (-mabm) 219 instruction set feature flag. Add new (-mpopcnt) flag for popcnt 220 instruction. Add new SSE4A (-msse4a) instruction set feature flag. 221 * config/i386/i386.h: Add builtin definition for SSE4A. 222 * config/i386/i386.md: Add support for ABM instructions 223 (popcnt and lzcnt). 224 * config/i386/sse.md: Add support for SSE4A instructions 225 (movntss, movntsd, extrq, insertq). 226 * config/i386/i386.c: Add support for ABM and SSE4A builtins. 227 Add -march=amdfam10 flag. 228 * config/i386/ammintrin.h: Add support for SSE4A intrinsics. 229 * doc/invoke.texi: Add documentation on flags for sse4a, abm, popcnt 230 and amdfam10. 231 * doc/extend.texi: Add documentation for SSE4A builtins. 232 2332007-01-24 Jakub Jelinek <jakub@redhat.com> (r121140) 234 235 * config/i386/i386.h (x86_cmpxchg16b): Remove const. 236 (TARGET_CMPXCHG16B): Define to x86_cmpxchg16b. 237 * config/i386/i386.c (x86_cmpxchg16b): Remove const. 238 (override_options): Add PTA_CX16 flag. Set x86_cmpxchg16b 239 for CPUs that have PTA_CX16 set. 240 2412007-01-17 Eric Christopher <echristo@apple.com> (r120846) 242 243 * config.gcc: Support core2 processor. 244 2452006-12-13 Ian Lance Taylor <iant@google.com> (r119855) 246 247 PR c++/19564 248 PR c++/19756 249 * c-typeck.c (parser_build_binary_op): Move parentheses warnings 250 to warn_about_parentheses in c-common.c. 251 * c-common.c (warn_about_parentheses): New function. 252 * c-common.h (warn_about_parentheses): Declare. 253 * doc/invoke.texi (Warning Options): Update -Wparentheses 254 description. 255 2562006-12-02 H.J. Lu <hongjiu.lu@intel.com> (r119454 - partial) 257 258 PR target/30040 259 * config/i386/driver-i386.c (bit_SSSE3): New. 260 2612006-11-27 Uros Bizjak <ubizjak@gmail.com> (r119260) 262 263 * config/i386/i386.c (x86_ext_80387_constants): Add m_K8, m_CORE2 264 and m_GENERIC64. 265 2662006-11-18 Vladimir Makarov <vmakarov@redhat.com> (r118973) 267 268 * doc/invoke.texi (core2): Add item. 269 270 * config/i386/i386.h (TARGET_CORE2, TARGET_CPU_DEFAULT_core2): New 271 macros. 272 (TARGET_CPU_CPP_BUILTINS): Add code for core2. 273 (TARGET_CPU_DEFAULT_generic): Change value. 274 (TARGET_CPU_DEFAULT_NAMES): Add core2. 275 (processor_type): Add new constant PROCESSOR_CORE2. 276 277 * config/i386/i386.md (cpu): Add core2. 278 279 * config/i386/i386.c (core2_cost): New initialized variable. 280 (m_CORE2): New macro. 281 (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen, 282 x86_deep_branch, x86_partial_reg_stall, x86_use_simode_fiop, 283 x86_use_cltd, x86_promote_QImode, x86_sub_esp_4, x86_sub_esp_8, 284 x86_add_esp_4, x86_add_esp_8, x86_integer_DFmode_moves, 285 x86_partial_reg_dependency, x86_memory_mismatch_stall, 286 x86_accumulate_outgoing_args, x86_prologue_using_move, 287 x86_epilogue_using_move, x86_arch_always_fancy_math_387, 288 x86_sse_partial_reg_dependency, x86_rep_movl_optimal, 289 x86_use_incdec, x86_four_jump_limit, x86_schedule, 290 x86_pad_returns): Add m_CORE2. 291 (override_options): Add entries for Core2. 292 (ix86_issue_rate): Add case for Core2. 293 2942006-10-27 Vladimir Makarov <vmakarov@redhat.com> (r118090) 295 296 * config/i386/i386.h (TARGET_GEODE): 297 (TARGET_CPU_CPP_BUILTINS): Add code for geode. 298 (TARGET_CPU_DEFAULT_geode): New macro. 299 (TARGET_CPU_DEFAULT_k6, TARGET_CPU_DEFAULT_k6_2, 300 TARGET_CPU_DEFAULT_k6_3, TARGET_CPU_DEFAULT_athlon, 301 TARGET_CPU_DEFAULT_athlon_sse, TARGET_CPU_DEFAULT_k8, 302 TARGET_CPU_DEFAULT_pentium_m, TARGET_CPU_DEFAULT_prescott, 303 TARGET_CPU_DEFAULT_nocona, TARGET_CPU_DEFAULT_generic): Increase 304 the macro values. 305 (TARGET_CPU_DEFAULT_NAMES): Add geode. 306 (processor_type): Add PROCESSOR_GEODE. 307 308 * config/i386/i386.md: Include geode.md. 309 (cpu): Add geode. 310 311 * config/i386/i386.c (geode_cost): New initialized global 312 variable. 313 (m_GEODE, m_K6_GEODE): New macros. 314 (x86_use_leave, x86_push_memory, x86_deep_branch, x86_use_sahf, 315 x86_use_himode_fiop, x86_promote_QImode, x86_add_esp_4, 316 x86_add_esp_8, x86_rep_movl_optimal, x86_ext_80387_constants, 317 x86_schedule): Use m_K6_GEODE instead of m_K6. 318 (x86_movx, x86_cmove): Set up m_GEODE. 319 (x86_integer_DFmode_moves): Clear m_GEODE. 320 (processor_target_table): Add entry for geode. 321 (processor_alias_table): Ditto. 322 323 * config/i386/geode.md: New file. 324 325 * doc/invoke.texi: Add entry about geode processor. 326 3272006-10-24 Richard Guenther <rguenther@suse.de> (r118001) 328 329 PR middle-end/28796 330 * builtins.c (fold_builtin_classify): Use HONOR_INFINITIES 331 and HONOR_NANS instead of MODE_HAS_INFINITIES and MODE_HAS_NANS 332 for deciding optimizations in consistency with fold-const.c 333 (fold_builtin_unordered_cmp): Likewise. 334 3352006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117958) 336 337 * config.gcc (i[34567]86-*-*): Add tmmintrin.h to extra_headers. 338 (x86_64-*-*): Likewise. 339 340 * config/i386/i386.c (pta_flags): Add PTA_SSSE3. 341 (override_options): Check SSSE3. 342 (ix86_builtins): Add IX86_BUILTIN_PHADDW, IX86_BUILTIN_PHADDD, 343 IX86_BUILTIN_PHADDSW, IX86_BUILTIN_PHSUBW, IX86_BUILTIN_PHSUBD, 344 IX86_BUILTIN_PHSUBSW, IX86_BUILTIN_PMADDUBSW, 345 IX86_BUILTIN_PMULHRSW, IX86_BUILTIN_PSHUFB, 346 IX86_BUILTIN_PSIGNB, IX86_BUILTIN_PSIGNW, IX86_BUILTIN_PSIGND, 347 IX86_BUILTIN_PALIGNR, IX86_BUILTIN_PABSB, IX86_BUILTIN_PABSW, 348 IX86_BUILTIN_PABSD, IX86_BUILTIN_PHADDW128, 349 IX86_BUILTIN_PHADDD128, IX86_BUILTIN_PHADDSW128, 350 IX86_BUILTIN_PHSUBW128, IX86_BUILTIN_PHSUBD128, 351 IX86_BUILTIN_PHSUBSW128, IX86_BUILTIN_PMADDUBSW128, 352 IX86_BUILTIN_PMULHRSW128, IX86_BUILTIN_PSHUFB128, 353 IX86_BUILTIN_PSIGNB128, IX86_BUILTIN_PSIGNW128, 354 IX86_BUILTIN_PSIGND128, IX86_BUILTIN_PALIGNR128, 355 IX86_BUILTIN_PABSB128, IX86_BUILTIN_PABSW128 and 356 IX86_BUILTIN_PABSD128. 357 (bdesc_2arg): Add SSSE3. 358 (bdesc_1arg): Likewise. 359 (ix86_init_mmx_sse_builtins): Support SSSE3. 360 (ix86_expand_builtin): Likewise. 361 * config/i386/i386.h (TARGET_CPU_CPP_BUILTINS): Likewise. 362 363 * config/i386/i386.md (UNSPEC_PSHUFB): New. 364 (UNSPEC_PSIGN): Likewise. 365 (UNSPEC_PALIGNR): Likewise. 366 Include mmx.md before sse.md. 367 368 * config/i386/i386.opt: Add -mssse3. 369 370 * config/i386/sse.md (ssse3_phaddwv8hi3): New pattern for SSSE3. 371 (ssse3_phaddwv4hi3): Likewise. 372 (ssse3_phadddv4si3): Likewise. 373 (ssse3_phadddv2si3): Likewise. 374 (ssse3_phaddswv8hi3): Likewise. 375 (ssse3_phaddswv4hi3): Likewise. 376 (ssse3_phsubwv8hi3): Likewise. 377 (ssse3_phsubwv4hi3): Likewise. 378 (ssse3_phsubdv4si3): Likewise. 379 (ssse3_phsubdv2si3): Likewise. 380 (ssse3_phsubswv8hi3): Likewise. 381 (ssse3_phsubswv4hi3): Likewise. 382 (ssse3_pmaddubswv8hi3): Likewise. 383 (ssse3_pmaddubswv4hi3): Likewise. 384 (ssse3_pmulhrswv8hi3): Likewise. 385 (ssse3_pmulhrswv4hi3): Likewise. 386 (ssse3_pshufbv16qi3): Likewise. 387 (ssse3_pshufbv8qi3): Likewise. 388 (ssse3_psign<mode>3): Likewise. 389 (ssse3_psign<mode>3): Likewise. 390 (ssse3_palignrti): Likewise. 391 (ssse3_palignrdi): Likewise. 392 (abs<mode>2): Likewise. 393 (abs<mode>2): Likewise. 394 395 * config/i386/tmmintrin.h: New file. 396 397 * doc/extend.texi: Document SSSE3 built-in functions. 398 399 * doc/invoke.texi: Document -mssse3/-mno-ssse3 switches. 400 4012006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117959) 402 403 * config/i386/tmmintrin.h: Remove the duplicated content. 404 4052006-10-21 Richard Guenther <rguenther@suse.de> (r117932) 406 407 PR tree-optimization/3511 408 * tree-ssa-pre.c (phi_translate): Fold CALL_EXPRs that 409 got new invariant arguments during PHI translation. 410 4112006-10-21 Richard Guenther <rguenther@suse.de> (r117929) 412 413 * builtins.c (fold_builtin_classify): Fix typo. 414
| 602007-03-11 Ian Lance Taylor <iant@google.com> (r122831 - partial) 61 62 * tree-vrp.c (vrp_int_const_binop): Handle PLUS_EXPR and 63 the *_DIV_EXPR codes correctly with overflow infinities. 64 652007-02-09 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r121763) 66 67 * config/i386/driver-i386.c: Turn on -mtune=native for AMDFAM10. 68 (bit_SSE4a): New. 69 702007-02-08 Harsha Jagasia <harsha.jagasia@amd.com> (r121726) 71 72 * config/i386/xmmintrin.h: Make inclusion of emmintrin.h 73 conditional to __SSE2__. 74 (Entries below should have been added to first ChangeLog 75 entry for amdfam10 dated 2007-02-05) 76 * config/i386/emmintrin.h: Generate #error if __SSE2__ is not 77 defined. 78 * config/i386/pmmintrin.h: Generate #error if __SSE3__ is not 79 defined. 80 * config/i386/tmmintrin.h: Generate #error if __SSSE3__ is not 81 defined. 82 832007-02-07 Jakub Jelinek <jakub@redhat.com> (r121687) 84 85 * config/i386/i386.c (override_options): Set PTA_SSSE3 for core2. 86 872007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 88 89 * config/i386/athlon.md (athlon_fldxf_k8, athlon_fld_k8, 90 athlon_fstxf_k8, athlon_fst_k8, athlon_fist, athlon_fmov, 91 athlon_fadd_load, athlon_fadd_load_k8, athlon_fadd, athlon_fmul, 92 athlon_fmul_load, athlon_fmul_load_k8, athlon_fsgn, 93 athlon_fdiv_load, athlon_fdiv_load_k8, athlon_fdiv_k8, 94 athlon_fpspc_load, athlon_fpspc, athlon_fcmov_load, 95 athlon_fcmov_load_k8, athlon_fcmov_k8, athlon_fcomi_load_k8, 96 athlon_fcomi, athlon_fcom_load_k8, athlon_fcom): Added amdfam10. 97 982007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 99 100 * config/i386/i386.md (x86_sahf_1, cmpfp_i_mixed, cmpfp_i_sse, 101 cmpfp_i_i387, cmpfp_iu_mixed, cmpfp_iu_sse, cmpfp_iu_387, 102 swapsi, swaphi_1, swapqi_1, swapdi_rex64, fix_truncsfdi_sse, 103 fix_truncdfdi_sse, fix_truncsfsi_sse, fix_truncdfsi_sse, 104 x86_fldcw_1, floatsisf2_mixed, floatsisf2_sse, floatdisf2_mixed, 105 floatdisf2_sse, floatsidf2_mixed, floatsidf2_sse, 106 floatdidf2_mixed, floatdidf2_sse, muldi3_1_rex64, mulsi3_1, 107 mulsi3_1_zext, mulhi3_1, mulqi3_1, umulqihi3_1, mulqihi3_insn, 108 umulditi3_insn, umulsidi3_insn, mulditi3_insn, mulsidi3_insn, 109 umuldi3_highpart_rex64, umulsi3_highpart_insn, 110 umulsi3_highpart_zext, smuldi3_highpart_rex64, 111 smulsi3_highpart_insn, smulsi3_highpart_zext, x86_64_shld, 112 x86_shld_1, x86_64_shrd, sqrtsf2_mixed, sqrtsf2_sse, 113 sqrtsf2_i387, sqrtdf2_mixed, sqrtdf2_sse, sqrtdf2_i387, 114 sqrtextendsfdf2_i387, sqrtxf2, sqrtextendsfxf2_i387, 115 sqrtextenddfxf2_i387): Added amdfam10_decode. 116 117 * config/i386/athlon.md (athlon_idirect_amdfam10, 118 athlon_ivector_amdfam10, athlon_idirect_load_amdfam10, 119 athlon_ivector_load_amdfam10, athlon_idirect_both_amdfam10, 120 athlon_ivector_both_amdfam10, athlon_idirect_store_amdfam10, 121 athlon_ivector_store_amdfam10): New define_insn_reservation. 122 (athlon_idirect_loadmov, athlon_idirect_movstore): Added 123 amdfam10. 124 1252007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 126 127 * config/i386/athlon.md (athlon_call_amdfam10, 128 athlon_pop_amdfam10, athlon_lea_amdfam10): New 129 define_insn_reservation. 130 (athlon_branch, athlon_push, athlon_leave_k8, athlon_imul_k8, 131 athlon_imul_k8_DI, athlon_imul_mem_k8, athlon_imul_mem_k8_DI, 132 athlon_idiv, athlon_idiv_mem, athlon_str): Added amdfam10. 133 1342007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 135 136 * config/i386/athlon.md (athlon_sseld_amdfam10, 137 athlon_mmxld_amdfam10, athlon_ssest_amdfam10, 138 athlon_mmxssest_short_amdfam10): New define_insn_reservation. 139 1402007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 141 142 * config/i386/athlon.md (athlon_sseins_amdfam10): New 143 define_insn_reservation. 144 * config/i386/i386.md (sseins): Added sseins to define_attr type 145 and define_attr unit. 146 * config/i386/sse.md: Set type attribute to sseins for insertq 147 and insertqi. 148 1492007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 150 151 * config/i386/athlon.md (sselog_load_amdfam10, sselog_amdfam10, 152 ssecmpvector_load_amdfam10, ssecmpvector_amdfam10, 153 ssecomi_load_amdfam10, ssecomi_amdfam10, 154 sseaddvector_load_amdfam10, sseaddvector_amdfam10): New 155 define_insn_reservation. 156 (ssecmp_load_k8, ssecmp, sseadd_load_k8, seadd): Added amdfam10. 157 1582007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 159 160 * config/i386/athlon.md (cvtss2sd_load_amdfam10, 161 cvtss2sd_amdfam10, cvtps2pd_load_amdfam10, cvtps2pd_amdfam10, 162 cvtsi2sd_load_amdfam10, cvtsi2ss_load_amdfam10, 163 cvtsi2sd_amdfam10, cvtsi2ss_amdfam10, cvtsd2ss_load_amdfam10, 164 cvtsd2ss_amdfam10, cvtpd2ps_load_amdfam10, cvtpd2ps_amdfam10, 165 cvtsX2si_load_amdfam10, cvtsX2si_amdfam10): New 166 define_insn_reservation. 167 168 * config/i386/sse.md (cvtsi2ss, cvtsi2ssq, cvtss2si, 169 cvtss2siq, cvttss2si, cvttss2siq, cvtsi2sd, cvtsi2sdq, 170 cvtsd2si, cvtsd2siq, cvttsd2si, cvttsd2siq, 171 cvtpd2dq, cvttpd2dq, cvtsd2ss, cvtss2sd, 172 cvtpd2ps, cvtps2pd): Added amdfam10_decode attribute. 173 1742007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 175 176 * config/i386/athlon.md (athlon_ssedivvector_amdfam10, 177 athlon_ssedivvector_load_amdfam10, athlon_ssemulvector_amdfam10, 178 athlon_ssemulvector_load_amdfam10): New define_insn_reservation. 179 (athlon_ssediv, athlon_ssediv_load_k8, athlon_ssemul, 180 athlon_ssemul_load_k8): Added amdfam10. 181 1822007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 183 184 * config/i386/i386.h (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL): New macro. 185 (x86_sse_unaligned_move_optimal): New variable. 186 187 * config/i386/i386.c (x86_sse_unaligned_move_optimal): Enable for 188 m_AMDFAM10. 189 (ix86_expand_vector_move_misalign): Add code to generate movupd/movups 190 for unaligned vector SSE double/single precision loads for AMDFAM10. 191 1922007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 193 194 * config/i386/i386.h (TARGET_AMDFAM10): New macro. 195 (TARGET_CPU_CPP_BUILTINS): Add code for amdfam10. 196 Define TARGET_CPU_DEFAULT_amdfam10. 197 (TARGET_CPU_DEFAULT_NAMES): Add amdfam10. 198 (processor_type): Add PROCESSOR_AMDFAM10. 199 200 * config/i386/i386.md: Add amdfam10 as a new cpu attribute to match 201 processor_type in config/i386/i386.h. 202 Enable imul peepholes for TARGET_AMDFAM10. 203 204 * config.gcc: Add support for --with-cpu option for amdfam10. 205 206 * config/i386/i386.c (amdfam10_cost): New variable. 207 (m_AMDFAM10): New macro. 208 (m_ATHLON_K8_AMDFAM10): New macro. 209 (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen, 210 x86_cmove, x86_3dnow_a, x86_deep_branch, x86_use_simode_fiop, 211 x86_promote_QImode, x86_integer_DFmode_moves, 212 x86_partial_reg_dependency, x86_memory_mismatch_stall, 213 x86_accumulate_outgoing_args, x86_arch_always_fancy_math_387, 214 x86_sse_partial_reg_dependency, x86_sse_typeless_stores, 215 x86_use_ffreep, x86_use_incdec, x86_four_jump_limit, 216 x86_schedule, x86_use_bt, x86_cmpxchg16b, x86_pad_returns): 217 Enable/disable for amdfam10. 218 (override_options): Add amdfam10_cost to processor_target_table. 219 Set up PROCESSOR_AMDFAM10 for amdfam10 entry in 220 processor_alias_table. 221 (ix86_issue_rate): Add PROCESSOR_AMDFAM10. 222 (ix86_adjust_cost): Add code for amdfam10. 223 2242007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 225 226 * config/i386/i386.opt: Add new Advanced Bit Manipulation (-mabm) 227 instruction set feature flag. Add new (-mpopcnt) flag for popcnt 228 instruction. Add new SSE4A (-msse4a) instruction set feature flag. 229 * config/i386/i386.h: Add builtin definition for SSE4A. 230 * config/i386/i386.md: Add support for ABM instructions 231 (popcnt and lzcnt). 232 * config/i386/sse.md: Add support for SSE4A instructions 233 (movntss, movntsd, extrq, insertq). 234 * config/i386/i386.c: Add support for ABM and SSE4A builtins. 235 Add -march=amdfam10 flag. 236 * config/i386/ammintrin.h: Add support for SSE4A intrinsics. 237 * doc/invoke.texi: Add documentation on flags for sse4a, abm, popcnt 238 and amdfam10. 239 * doc/extend.texi: Add documentation for SSE4A builtins. 240 2412007-01-24 Jakub Jelinek <jakub@redhat.com> (r121140) 242 243 * config/i386/i386.h (x86_cmpxchg16b): Remove const. 244 (TARGET_CMPXCHG16B): Define to x86_cmpxchg16b. 245 * config/i386/i386.c (x86_cmpxchg16b): Remove const. 246 (override_options): Add PTA_CX16 flag. Set x86_cmpxchg16b 247 for CPUs that have PTA_CX16 set. 248 2492007-01-17 Eric Christopher <echristo@apple.com> (r120846) 250 251 * config.gcc: Support core2 processor. 252 2532006-12-13 Ian Lance Taylor <iant@google.com> (r119855) 254 255 PR c++/19564 256 PR c++/19756 257 * c-typeck.c (parser_build_binary_op): Move parentheses warnings 258 to warn_about_parentheses in c-common.c. 259 * c-common.c (warn_about_parentheses): New function. 260 * c-common.h (warn_about_parentheses): Declare. 261 * doc/invoke.texi (Warning Options): Update -Wparentheses 262 description. 263 2642006-12-02 H.J. Lu <hongjiu.lu@intel.com> (r119454 - partial) 265 266 PR target/30040 267 * config/i386/driver-i386.c (bit_SSSE3): New. 268 2692006-11-27 Uros Bizjak <ubizjak@gmail.com> (r119260) 270 271 * config/i386/i386.c (x86_ext_80387_constants): Add m_K8, m_CORE2 272 and m_GENERIC64. 273 2742006-11-18 Vladimir Makarov <vmakarov@redhat.com> (r118973) 275 276 * doc/invoke.texi (core2): Add item. 277 278 * config/i386/i386.h (TARGET_CORE2, TARGET_CPU_DEFAULT_core2): New 279 macros. 280 (TARGET_CPU_CPP_BUILTINS): Add code for core2. 281 (TARGET_CPU_DEFAULT_generic): Change value. 282 (TARGET_CPU_DEFAULT_NAMES): Add core2. 283 (processor_type): Add new constant PROCESSOR_CORE2. 284 285 * config/i386/i386.md (cpu): Add core2. 286 287 * config/i386/i386.c (core2_cost): New initialized variable. 288 (m_CORE2): New macro. 289 (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen, 290 x86_deep_branch, x86_partial_reg_stall, x86_use_simode_fiop, 291 x86_use_cltd, x86_promote_QImode, x86_sub_esp_4, x86_sub_esp_8, 292 x86_add_esp_4, x86_add_esp_8, x86_integer_DFmode_moves, 293 x86_partial_reg_dependency, x86_memory_mismatch_stall, 294 x86_accumulate_outgoing_args, x86_prologue_using_move, 295 x86_epilogue_using_move, x86_arch_always_fancy_math_387, 296 x86_sse_partial_reg_dependency, x86_rep_movl_optimal, 297 x86_use_incdec, x86_four_jump_limit, x86_schedule, 298 x86_pad_returns): Add m_CORE2. 299 (override_options): Add entries for Core2. 300 (ix86_issue_rate): Add case for Core2. 301 3022006-10-27 Vladimir Makarov <vmakarov@redhat.com> (r118090) 303 304 * config/i386/i386.h (TARGET_GEODE): 305 (TARGET_CPU_CPP_BUILTINS): Add code for geode. 306 (TARGET_CPU_DEFAULT_geode): New macro. 307 (TARGET_CPU_DEFAULT_k6, TARGET_CPU_DEFAULT_k6_2, 308 TARGET_CPU_DEFAULT_k6_3, TARGET_CPU_DEFAULT_athlon, 309 TARGET_CPU_DEFAULT_athlon_sse, TARGET_CPU_DEFAULT_k8, 310 TARGET_CPU_DEFAULT_pentium_m, TARGET_CPU_DEFAULT_prescott, 311 TARGET_CPU_DEFAULT_nocona, TARGET_CPU_DEFAULT_generic): Increase 312 the macro values. 313 (TARGET_CPU_DEFAULT_NAMES): Add geode. 314 (processor_type): Add PROCESSOR_GEODE. 315 316 * config/i386/i386.md: Include geode.md. 317 (cpu): Add geode. 318 319 * config/i386/i386.c (geode_cost): New initialized global 320 variable. 321 (m_GEODE, m_K6_GEODE): New macros. 322 (x86_use_leave, x86_push_memory, x86_deep_branch, x86_use_sahf, 323 x86_use_himode_fiop, x86_promote_QImode, x86_add_esp_4, 324 x86_add_esp_8, x86_rep_movl_optimal, x86_ext_80387_constants, 325 x86_schedule): Use m_K6_GEODE instead of m_K6. 326 (x86_movx, x86_cmove): Set up m_GEODE. 327 (x86_integer_DFmode_moves): Clear m_GEODE. 328 (processor_target_table): Add entry for geode. 329 (processor_alias_table): Ditto. 330 331 * config/i386/geode.md: New file. 332 333 * doc/invoke.texi: Add entry about geode processor. 334 3352006-10-24 Richard Guenther <rguenther@suse.de> (r118001) 336 337 PR middle-end/28796 338 * builtins.c (fold_builtin_classify): Use HONOR_INFINITIES 339 and HONOR_NANS instead of MODE_HAS_INFINITIES and MODE_HAS_NANS 340 for deciding optimizations in consistency with fold-const.c 341 (fold_builtin_unordered_cmp): Likewise. 342 3432006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117958) 344 345 * config.gcc (i[34567]86-*-*): Add tmmintrin.h to extra_headers. 346 (x86_64-*-*): Likewise. 347 348 * config/i386/i386.c (pta_flags): Add PTA_SSSE3. 349 (override_options): Check SSSE3. 350 (ix86_builtins): Add IX86_BUILTIN_PHADDW, IX86_BUILTIN_PHADDD, 351 IX86_BUILTIN_PHADDSW, IX86_BUILTIN_PHSUBW, IX86_BUILTIN_PHSUBD, 352 IX86_BUILTIN_PHSUBSW, IX86_BUILTIN_PMADDUBSW, 353 IX86_BUILTIN_PMULHRSW, IX86_BUILTIN_PSHUFB, 354 IX86_BUILTIN_PSIGNB, IX86_BUILTIN_PSIGNW, IX86_BUILTIN_PSIGND, 355 IX86_BUILTIN_PALIGNR, IX86_BUILTIN_PABSB, IX86_BUILTIN_PABSW, 356 IX86_BUILTIN_PABSD, IX86_BUILTIN_PHADDW128, 357 IX86_BUILTIN_PHADDD128, IX86_BUILTIN_PHADDSW128, 358 IX86_BUILTIN_PHSUBW128, IX86_BUILTIN_PHSUBD128, 359 IX86_BUILTIN_PHSUBSW128, IX86_BUILTIN_PMADDUBSW128, 360 IX86_BUILTIN_PMULHRSW128, IX86_BUILTIN_PSHUFB128, 361 IX86_BUILTIN_PSIGNB128, IX86_BUILTIN_PSIGNW128, 362 IX86_BUILTIN_PSIGND128, IX86_BUILTIN_PALIGNR128, 363 IX86_BUILTIN_PABSB128, IX86_BUILTIN_PABSW128 and 364 IX86_BUILTIN_PABSD128. 365 (bdesc_2arg): Add SSSE3. 366 (bdesc_1arg): Likewise. 367 (ix86_init_mmx_sse_builtins): Support SSSE3. 368 (ix86_expand_builtin): Likewise. 369 * config/i386/i386.h (TARGET_CPU_CPP_BUILTINS): Likewise. 370 371 * config/i386/i386.md (UNSPEC_PSHUFB): New. 372 (UNSPEC_PSIGN): Likewise. 373 (UNSPEC_PALIGNR): Likewise. 374 Include mmx.md before sse.md. 375 376 * config/i386/i386.opt: Add -mssse3. 377 378 * config/i386/sse.md (ssse3_phaddwv8hi3): New pattern for SSSE3. 379 (ssse3_phaddwv4hi3): Likewise. 380 (ssse3_phadddv4si3): Likewise. 381 (ssse3_phadddv2si3): Likewise. 382 (ssse3_phaddswv8hi3): Likewise. 383 (ssse3_phaddswv4hi3): Likewise. 384 (ssse3_phsubwv8hi3): Likewise. 385 (ssse3_phsubwv4hi3): Likewise. 386 (ssse3_phsubdv4si3): Likewise. 387 (ssse3_phsubdv2si3): Likewise. 388 (ssse3_phsubswv8hi3): Likewise. 389 (ssse3_phsubswv4hi3): Likewise. 390 (ssse3_pmaddubswv8hi3): Likewise. 391 (ssse3_pmaddubswv4hi3): Likewise. 392 (ssse3_pmulhrswv8hi3): Likewise. 393 (ssse3_pmulhrswv4hi3): Likewise. 394 (ssse3_pshufbv16qi3): Likewise. 395 (ssse3_pshufbv8qi3): Likewise. 396 (ssse3_psign<mode>3): Likewise. 397 (ssse3_psign<mode>3): Likewise. 398 (ssse3_palignrti): Likewise. 399 (ssse3_palignrdi): Likewise. 400 (abs<mode>2): Likewise. 401 (abs<mode>2): Likewise. 402 403 * config/i386/tmmintrin.h: New file. 404 405 * doc/extend.texi: Document SSSE3 built-in functions. 406 407 * doc/invoke.texi: Document -mssse3/-mno-ssse3 switches. 408 4092006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117959) 410 411 * config/i386/tmmintrin.h: Remove the duplicated content. 412 4132006-10-21 Richard Guenther <rguenther@suse.de> (r117932) 414 415 PR tree-optimization/3511 416 * tree-ssa-pre.c (phi_translate): Fold CALL_EXPRs that 417 got new invariant arguments during PHI translation. 418 4192006-10-21 Richard Guenther <rguenther@suse.de> (r117929) 420 421 * builtins.c (fold_builtin_classify): Fix typo. 422
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