2c2,3
< Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
---
> Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
> 2003, 2004, 2005
21c22
< Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
---
> Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
91a93,94
> #define OP_MASK_BITIND OP_MASK_RT
> #define OP_SH_BITIND OP_SH_RT
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> /* MIPS DSP ASE */
> #define OP_SH_DSPACC 11
> #define OP_MASK_DSPACC 0x3
> #define OP_SH_DSPACC_S 21
> #define OP_MASK_DSPACC_S 0x3
> #define OP_SH_DSPSFT 20
> #define OP_MASK_DSPSFT 0x3f
> #define OP_SH_DSPSFT_7 19
> #define OP_MASK_DSPSFT_7 0x7f
> #define OP_SH_SA3 21
> #define OP_MASK_SA3 0x7
> #define OP_SH_SA4 21
> #define OP_MASK_SA4 0xf
> #define OP_SH_IMM8 16
> #define OP_MASK_IMM8 0xff
> #define OP_SH_IMM10 16
> #define OP_MASK_IMM10 0x3ff
> #define OP_SH_WRDSP 11
> #define OP_MASK_WRDSP 0x3f
> #define OP_SH_RDDSP 16
> #define OP_MASK_RDDSP 0x3f
>
> /* MIPS MT ASE */
> #define OP_SH_MT_U 5
> #define OP_MASK_MT_U 0x1
> #define OP_SH_MT_H 4
> #define OP_MASK_MT_H 0x1
> #define OP_SH_MTACC_T 18
> #define OP_MASK_MTACC_T 0x3
> #define OP_SH_MTACC_D 13
> #define OP_MASK_MTACC_D 0x3
>
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> /* A collection of additional bits describing the instruction. */
> unsigned long pinfo2;
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> "^" 5 bit bit index amount (OP_*_BITIND)
> "~" bit index between 32 and 63, stored after subtracting 32 (OP_*_BITIND)
233a273
> "y" 10 bit signed const (OP_*_CODE2)
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> DSP ASE usage:
> "3" 3 bit unsigned immediate (OP_*_SA3)
> "4" 4 bit unsigned immediate (OP_*_SA4)
> "5" 8 bit unsigned immediate (OP_*_IMM8)
> "6" 5 bit unsigned immediate (OP_*_RS)
> "7" 2 bit dsp accumulator register (OP_*_DSPACC)
> "8" 6 bit unsigned immediate (OP_*_WRDSP)
> "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
> "0" 6 bit signed immediate (OP_*_DSPSFT)
> ":" 7 bit signed immediate (OP_*_DSPSFT_7)
> "'" 6 bit unsigned immediate (OP_*_RDDSP)
> "@" 10 bit signed immediate (OP_*_IMM10)
>
> MT ASE usage:
> "!" 1 bit immediate at bit 5
> "$" 1 bit immediate at bit 4
> "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
> "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
> "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
> "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
> "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
>
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< "%[]<>(),+"
---
> "34567890"
> "%[]<>(),+:'@!$*&^~"
305c368
< "abcdefhijklopqrstuvwxz"
---
> "abcdefghijklopqrstuvwxyz"
309c372,373
< "ABCDEFGHI"
---
> "ABCDEFGHIT"
> "t"
379,382d442
< /* Instruction reads MDMX accumulator. XXX FIXME: No bits left! */
< #define INSN_READ_MDMX_ACC 0
< /* Instruction writes MDMX accumulator. XXX FIXME: No bits left! */
< #define INSN_WRITE_MDMX_ACC 0
383a444,453
> /* These are the bits which may be set in the pinfo2 field of an
> instruction. */
>
> /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
> #define INSN2_ALIAS 0x00000001
> /* Instruction reads MDMX accumulator. */
> #define INSN2_READ_MDMX_ACC 0x00000002
> /* Instruction writes MDMX accumulator. */
> #define INSN2_WRITE_MDMX_ACC 0x00000004
>
405c475
< #define INSN_ASE_MASK 0x0000f000
---
> #define INSN_ASE_MASK 0x0400f000
406a477,478
> /* DSP ASE */
> #define INSN_DSP 0x00001000
435a508,511
> /* MT ASE */
> #define INSN_MT 0x04000000
> /* Cavium Networks Octeon instruction. */
> #define INSN_OCTEON 0x08000000
472a549
> #define CPU_RM9000 9000
481a559
> #define CPU_OCTEON 6502
491a570
> || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
497a577
> || (cpu == CPU_OCTEON && ((insn)->membership & INSN_OCTEON) != 0) \
656a737,738
> M_SAA_AB,
> M_SAAD_AB,
860c942,944
< */
---
> "m" 7 bit register list for save instruction (18 bit extended)
> "M" 7 bit register list for restore instruction (18 bit extended)
> */
861a946,950
> /* Save/restore encoding for the args field when all 4 registers are
> either saved as arguments or saved/restored as statics. */
> #define MIPS16_ALL_ARGS 0xe
> #define MIPS16_ALL_STATICS 0xb
>