1/* mips.h. Mips opcode list for GDB, the GNU debugger.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by Ralph Campbell and OSF
5 Commented and modified by Ian Lance Taylor, Cygnus Support
6
7This file is part of GDB, GAS, and the GNU binutils.
8
9GDB, GAS, and the GNU binutils are free software; you can redistribute
10them and/or modify them under the terms of the GNU General Public
11License as published by the Free Software Foundation; either version
121, or (at your option) any later version.
13
14GDB, GAS, and the GNU binutils are distributed in the hope that they
15will be useful, but WITHOUT ANY WARRANTY; without even the implied
16warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
17the GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License
20along with this file; see the file COPYING. If not, write to the Free
21Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22
23#ifndef _MIPS_H_
24#define _MIPS_H_
25
26/* These are bit masks and shift counts to use to access the various
27 fields of an instruction. To retrieve the X field of an
28 instruction, use the expression
29 (i >> OP_SH_X) & OP_MASK_X
--- 54 unchanged lines hidden (view full) ---
84#define OP_MASK_PREFX 0x1f
85#define OP_SH_PREFX 11
86#define OP_MASK_CCC 0x7
87#define OP_SH_CCC 8
88#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
89#define OP_SH_CODE20 6
90#define OP_MASK_SHAMT 0x1f
91#define OP_SH_SHAMT 6
92#define OP_MASK_FD 0x1f
93#define OP_SH_FD 6
94#define OP_MASK_TARGET 0x3ffffff
95#define OP_SH_TARGET 0
96#define OP_MASK_COPZ 0x1ffffff
97#define OP_SH_COPZ 0
98#define OP_MASK_IMMEDIATE 0xffff
99#define OP_SH_IMMEDIATE 0
--- 42 unchanged lines hidden (view full) ---
142#define OP_SH_VECBYTE 22
143#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
144#define OP_SH_VECALIGN 21
145#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
146#define OP_SH_INSMSB 11
147#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
148#define OP_SH_EXTMSBD 11
149
150#define OP_OP_COP0 0x10
151#define OP_OP_COP1 0x11
152#define OP_OP_COP2 0x12
153#define OP_OP_COP3 0x13
154#define OP_OP_LWC1 0x31
155#define OP_OP_LWC2 0x32
156#define OP_OP_LWC3 0x33 /* a.k.a. pref */
157#define OP_OP_LDC1 0x35
--- 29 unchanged lines hidden (view full) ---
187 actual opcode anded with the match field equals the opcode field,
188 then we have found the correct instruction. If pinfo is
189 INSN_MACRO, then this field is the macro identifier. */
190 unsigned long mask;
191 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
192 of bits describing the instruction, notably any relevant hazard
193 information. */
194 unsigned long pinfo;
195 /* A collection of bits describing the instruction sets of which this
196 instruction or macro is a member. */
197 unsigned long membership;
198};
199
200/* These are the characters which may appear in the args field of an
201 instruction. They appear in the order in which the fields appear
202 when the instruction is used. Commas and parentheses in the args
203 string are ignored when assembling, and written into the output
204 when disassembling.
205
206 Each of these characters corresponds to a mask field defined above.
207
208 "<" 5 bit shift amount (OP_*_SHAMT)
209 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
210 "a" 26 bit target address (OP_*_TARGET)
211 "b" 5 bit base register (OP_*_RS)
212 "c" 10 bit breakpoint code (OP_*_CODE)
213 "d" 5 bit destination register specifier (OP_*_RD)
214 "h" 5 bit prefx hint (OP_*_PREFX)
215 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
216 "j" 16 bit signed immediate (OP_*_DELTA)
217 "k" 5 bit cache opcode in target register position (OP_*_CACHE)
--- 8 unchanged lines hidden (view full) ---
226 "v" 5 bit same register used as both source and destination (OP_*_RS)
227 "w" 5 bit same register used as both target and destination (OP_*_RT)
228 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
229 (used by clo and clz)
230 "C" 25 bit coprocessor function code (OP_*_COPZ)
231 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
232 "J" 19 bit wait function code (OP_*_CODE19)
233 "x" accept and ignore register name
234 "z" must be zero register
235 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
236 "+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT).
237 Enforces: 0 <= pos < 32.
238 "+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB).
239 Requires that "+A" or "+E" occur first to set position.
240 Enforces: 0 < (pos+size) <= 32.
241 "+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD).
--- 46 unchanged lines hidden (view full) ---
288 MDMX instruction operands (note that while these use the FP register
289 fields, they accept both $fN and $vN names for the registers):
290 "O" MDMX alignment offset (OP_*_ALN)
291 "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
292 "X" MDMX destination register (OP_*_FD)
293 "Y" MDMX source register (OP_*_FS)
294 "Z" MDMX source register (OP_*_FT)
295
296 Other:
297 "()" parens surrounding optional value
298 "," separates operands
299 "[]" brackets around index for vector-op scalar operand specifier (vr5400)
300 "+" Start of extension sequence.
301
302 Characters used so far, for quick reference when adding more:
303 "%[]<>(),+"
304 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
305 "abcdefhijklopqrstuvwxz"
306
307 Extension character sequences used so far ("+" followed by the
308 following), for quick reference when adding more:
309 "ABCDEFGHI"
310*/
311
312/* These are the bits which may be set in the pinfo field of an
313 instructions, if it is not equal to INSN_MACRO. */
314
315/* Modifies the general purpose register in OP_*_RD. */
316#define INSN_WRITE_GPR_D 0x00000001
317/* Modifies the general purpose register in OP_*_RT. */
--- 53 unchanged lines hidden (view full) ---
371/* Instruction uses single precision floating point. */
372#define FP_S 0x10000000
373/* Instruction uses double precision floating point. */
374#define FP_D 0x20000000
375/* Instruction is part of the tx39's integer multiply family. */
376#define INSN_MULT 0x40000000
377/* Instruction synchronize shared memory. */
378#define INSN_SYNC 0x80000000
379/* Instruction reads MDMX accumulator. XXX FIXME: No bits left! */
380#define INSN_READ_MDMX_ACC 0
381/* Instruction writes MDMX accumulator. XXX FIXME: No bits left! */
382#define INSN_WRITE_MDMX_ACC 0
383
384/* Instruction is actually a macro. It should be ignored by the
385 disassembler, and requires special treatment by the assembler. */
386#define INSN_MACRO 0xffffffff
387
388/* Masks used to mark instructions to indicate which MIPS ISA level
389 they were introduced in. ISAs, as defined below, are logical
390 ORs of these bits, indicating that they support the instructions
391 defined at the given level. */
--- 5 unchanged lines hidden (view full) ---
397#define INSN_ISA4 0x00000008
398#define INSN_ISA5 0x00000010
399#define INSN_ISA32 0x00000020
400#define INSN_ISA64 0x00000040
401#define INSN_ISA32R2 0x00000080
402#define INSN_ISA64R2 0x00000100
403
404/* Masks used for MIPS-defined ASEs. */
405#define INSN_ASE_MASK 0x0000f000
406
407/* MIPS 16 ASE */
408#define INSN_MIPS16 0x00002000
409/* MIPS-3D ASE */
410#define INSN_MIPS3D 0x00004000
411/* MDMX ASE */
412#define INSN_MDMX 0x00008000
413
414/* Chip specific instructions. These are bitmasks. */
--- 13 unchanged lines hidden (view full) ---
428/* NEC VR4111/VR4181 instruction. */
429#define INSN_4111 0x00400000
430/* NEC VR4120 instruction. */
431#define INSN_4120 0x00800000
432/* NEC VR5400 instruction. */
433#define INSN_5400 0x01000000
434/* NEC VR5500 instruction. */
435#define INSN_5500 0x02000000
436
437/* MIPS ISA defines, use instead of hardcoding ISA level. */
438
439#define ISA_UNKNOWN 0 /* Gas internal use. */
440#define ISA_MIPS1 (INSN_ISA1)
441#define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
442#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
443#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
--- 21 unchanged lines hidden (view full) ---
465#define CPU_R4600 4600
466#define CPU_R4650 4650
467#define CPU_R5000 5000
468#define CPU_VR5400 5400
469#define CPU_VR5500 5500
470#define CPU_R6000 6000
471#define CPU_RM7000 7000
472#define CPU_R8000 8000
473#define CPU_R10000 10000
474#define CPU_R12000 12000
475#define CPU_MIPS16 16
476#define CPU_MIPS32 32
477#define CPU_MIPS32R2 33
478#define CPU_MIPS5 5
479#define CPU_MIPS64 64
480#define CPU_MIPS64R2 65
481#define CPU_SB1 12310201 /* octal 'SB', 01. */
482
483/* Test for membership in an ISA including chip specific ISAs. INSN
484 is pointer to an element of the opcode table; ISA is the specified
485 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
486 test, or zero if no CPU specific ISA test is desired. */
487
488#define OPCODE_IS_MEMBER(insn, isa, cpu) \
489 (((insn)->membership & isa) != 0 \
490 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
491 || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
492 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
493 || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
494 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
495 || ((cpu == CPU_R10000 || cpu == CPU_R12000) \
496 && ((insn)->membership & INSN_10000) != 0) \
497 || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
498 || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
499 || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
500 || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
501 || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
502 || 0) /* Please keep this term for easier source merging. */
503
504/* This is a list of macro expanded instructions.
505
--- 143 unchanged lines hidden (view full) ---
649 M_DROR,
650 M_ROR,
651 M_DROR_I,
652 M_ROR_I,
653 M_S_DA,
654 M_S_DOB,
655 M_S_DAB,
656 M_S_S,
657 M_SC_AB,
658 M_SCD_AB,
659 M_SD_A,
660 M_SD_OB,
661 M_SD_AB,
662 M_SDC1_AB,
663 M_SDC2_AB,
664 M_SDC3_AB,
--- 187 unchanged lines hidden (view full) ---
852 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
853 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
854 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
855 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
856 "q" 11 bit branch address (MIPS16OP_*_IMM11)
857 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
858 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
859 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
860 */
861
862/* For the mips16, we use the same opcode table format and a few of
863 the same flags. However, most of the flags are different. */
864
865/* Modifies the register in MIPS16OP_*_RX. */
866#define MIPS16_INSN_WRITE_X 0x00000001
867/* Modifies the register in MIPS16OP_*_RY. */
868#define MIPS16_INSN_WRITE_Y 0x00000002
869/* Modifies the register in MIPS16OP_*_RZ. */
--- 45 unchanged lines hidden ---
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by Ralph Campbell and OSF
5 Commented and modified by Ian Lance Taylor, Cygnus Support
6
7This file is part of GDB, GAS, and the GNU binutils.
8
9GDB, GAS, and the GNU binutils are free software; you can redistribute
10them and/or modify them under the terms of the GNU General Public
11License as published by the Free Software Foundation; either version
121, or (at your option) any later version.
13
14GDB, GAS, and the GNU binutils are distributed in the hope that they
15will be useful, but WITHOUT ANY WARRANTY; without even the implied
16warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
17the GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License
20along with this file; see the file COPYING. If not, write to the Free
21Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22
23#ifndef _MIPS_H_
24#define _MIPS_H_
25
26/* These are bit masks and shift counts to use to access the various
27 fields of an instruction. To retrieve the X field of an
28 instruction, use the expression
29 (i >> OP_SH_X) & OP_MASK_X
--- 54 unchanged lines hidden (view full) ---
84#define OP_MASK_PREFX 0x1f
85#define OP_SH_PREFX 11
86#define OP_MASK_CCC 0x7
87#define OP_SH_CCC 8
88#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
89#define OP_SH_CODE20 6
90#define OP_MASK_SHAMT 0x1f
91#define OP_SH_SHAMT 6
92#define OP_MASK_FD 0x1f
93#define OP_SH_FD 6
94#define OP_MASK_TARGET 0x3ffffff
95#define OP_SH_TARGET 0
96#define OP_MASK_COPZ 0x1ffffff
97#define OP_SH_COPZ 0
98#define OP_MASK_IMMEDIATE 0xffff
99#define OP_SH_IMMEDIATE 0
--- 42 unchanged lines hidden (view full) ---
142#define OP_SH_VECBYTE 22
143#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
144#define OP_SH_VECALIGN 21
145#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
146#define OP_SH_INSMSB 11
147#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
148#define OP_SH_EXTMSBD 11
149
150#define OP_OP_COP0 0x10
151#define OP_OP_COP1 0x11
152#define OP_OP_COP2 0x12
153#define OP_OP_COP3 0x13
154#define OP_OP_LWC1 0x31
155#define OP_OP_LWC2 0x32
156#define OP_OP_LWC3 0x33 /* a.k.a. pref */
157#define OP_OP_LDC1 0x35
--- 29 unchanged lines hidden (view full) ---
187 actual opcode anded with the match field equals the opcode field,
188 then we have found the correct instruction. If pinfo is
189 INSN_MACRO, then this field is the macro identifier. */
190 unsigned long mask;
191 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
192 of bits describing the instruction, notably any relevant hazard
193 information. */
194 unsigned long pinfo;
195 /* A collection of bits describing the instruction sets of which this
196 instruction or macro is a member. */
197 unsigned long membership;
198};
199
200/* These are the characters which may appear in the args field of an
201 instruction. They appear in the order in which the fields appear
202 when the instruction is used. Commas and parentheses in the args
203 string are ignored when assembling, and written into the output
204 when disassembling.
205
206 Each of these characters corresponds to a mask field defined above.
207
208 "<" 5 bit shift amount (OP_*_SHAMT)
209 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
210 "a" 26 bit target address (OP_*_TARGET)
211 "b" 5 bit base register (OP_*_RS)
212 "c" 10 bit breakpoint code (OP_*_CODE)
213 "d" 5 bit destination register specifier (OP_*_RD)
214 "h" 5 bit prefx hint (OP_*_PREFX)
215 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
216 "j" 16 bit signed immediate (OP_*_DELTA)
217 "k" 5 bit cache opcode in target register position (OP_*_CACHE)
--- 8 unchanged lines hidden (view full) ---
226 "v" 5 bit same register used as both source and destination (OP_*_RS)
227 "w" 5 bit same register used as both target and destination (OP_*_RT)
228 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
229 (used by clo and clz)
230 "C" 25 bit coprocessor function code (OP_*_COPZ)
231 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
232 "J" 19 bit wait function code (OP_*_CODE19)
233 "x" accept and ignore register name
234 "z" must be zero register
235 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
236 "+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT).
237 Enforces: 0 <= pos < 32.
238 "+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB).
239 Requires that "+A" or "+E" occur first to set position.
240 Enforces: 0 < (pos+size) <= 32.
241 "+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD).
--- 46 unchanged lines hidden (view full) ---
288 MDMX instruction operands (note that while these use the FP register
289 fields, they accept both $fN and $vN names for the registers):
290 "O" MDMX alignment offset (OP_*_ALN)
291 "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
292 "X" MDMX destination register (OP_*_FD)
293 "Y" MDMX source register (OP_*_FS)
294 "Z" MDMX source register (OP_*_FT)
295
296 Other:
297 "()" parens surrounding optional value
298 "," separates operands
299 "[]" brackets around index for vector-op scalar operand specifier (vr5400)
300 "+" Start of extension sequence.
301
302 Characters used so far, for quick reference when adding more:
303 "%[]<>(),+"
304 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
305 "abcdefhijklopqrstuvwxz"
306
307 Extension character sequences used so far ("+" followed by the
308 following), for quick reference when adding more:
309 "ABCDEFGHI"
310*/
311
312/* These are the bits which may be set in the pinfo field of an
313 instructions, if it is not equal to INSN_MACRO. */
314
315/* Modifies the general purpose register in OP_*_RD. */
316#define INSN_WRITE_GPR_D 0x00000001
317/* Modifies the general purpose register in OP_*_RT. */
--- 53 unchanged lines hidden (view full) ---
371/* Instruction uses single precision floating point. */
372#define FP_S 0x10000000
373/* Instruction uses double precision floating point. */
374#define FP_D 0x20000000
375/* Instruction is part of the tx39's integer multiply family. */
376#define INSN_MULT 0x40000000
377/* Instruction synchronize shared memory. */
378#define INSN_SYNC 0x80000000
379/* Instruction reads MDMX accumulator. XXX FIXME: No bits left! */
380#define INSN_READ_MDMX_ACC 0
381/* Instruction writes MDMX accumulator. XXX FIXME: No bits left! */
382#define INSN_WRITE_MDMX_ACC 0
383
384/* Instruction is actually a macro. It should be ignored by the
385 disassembler, and requires special treatment by the assembler. */
386#define INSN_MACRO 0xffffffff
387
388/* Masks used to mark instructions to indicate which MIPS ISA level
389 they were introduced in. ISAs, as defined below, are logical
390 ORs of these bits, indicating that they support the instructions
391 defined at the given level. */
--- 5 unchanged lines hidden (view full) ---
397#define INSN_ISA4 0x00000008
398#define INSN_ISA5 0x00000010
399#define INSN_ISA32 0x00000020
400#define INSN_ISA64 0x00000040
401#define INSN_ISA32R2 0x00000080
402#define INSN_ISA64R2 0x00000100
403
404/* Masks used for MIPS-defined ASEs. */
405#define INSN_ASE_MASK 0x0000f000
406
407/* MIPS 16 ASE */
408#define INSN_MIPS16 0x00002000
409/* MIPS-3D ASE */
410#define INSN_MIPS3D 0x00004000
411/* MDMX ASE */
412#define INSN_MDMX 0x00008000
413
414/* Chip specific instructions. These are bitmasks. */
--- 13 unchanged lines hidden (view full) ---
428/* NEC VR4111/VR4181 instruction. */
429#define INSN_4111 0x00400000
430/* NEC VR4120 instruction. */
431#define INSN_4120 0x00800000
432/* NEC VR5400 instruction. */
433#define INSN_5400 0x01000000
434/* NEC VR5500 instruction. */
435#define INSN_5500 0x02000000
436
437/* MIPS ISA defines, use instead of hardcoding ISA level. */
438
439#define ISA_UNKNOWN 0 /* Gas internal use. */
440#define ISA_MIPS1 (INSN_ISA1)
441#define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
442#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
443#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
--- 21 unchanged lines hidden (view full) ---
465#define CPU_R4600 4600
466#define CPU_R4650 4650
467#define CPU_R5000 5000
468#define CPU_VR5400 5400
469#define CPU_VR5500 5500
470#define CPU_R6000 6000
471#define CPU_RM7000 7000
472#define CPU_R8000 8000
473#define CPU_R10000 10000
474#define CPU_R12000 12000
475#define CPU_MIPS16 16
476#define CPU_MIPS32 32
477#define CPU_MIPS32R2 33
478#define CPU_MIPS5 5
479#define CPU_MIPS64 64
480#define CPU_MIPS64R2 65
481#define CPU_SB1 12310201 /* octal 'SB', 01. */
482
483/* Test for membership in an ISA including chip specific ISAs. INSN
484 is pointer to an element of the opcode table; ISA is the specified
485 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
486 test, or zero if no CPU specific ISA test is desired. */
487
488#define OPCODE_IS_MEMBER(insn, isa, cpu) \
489 (((insn)->membership & isa) != 0 \
490 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
491 || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
492 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
493 || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
494 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
495 || ((cpu == CPU_R10000 || cpu == CPU_R12000) \
496 && ((insn)->membership & INSN_10000) != 0) \
497 || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
498 || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
499 || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
500 || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
501 || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
502 || 0) /* Please keep this term for easier source merging. */
503
504/* This is a list of macro expanded instructions.
505
--- 143 unchanged lines hidden (view full) ---
649 M_DROR,
650 M_ROR,
651 M_DROR_I,
652 M_ROR_I,
653 M_S_DA,
654 M_S_DOB,
655 M_S_DAB,
656 M_S_S,
657 M_SC_AB,
658 M_SCD_AB,
659 M_SD_A,
660 M_SD_OB,
661 M_SD_AB,
662 M_SDC1_AB,
663 M_SDC2_AB,
664 M_SDC3_AB,
--- 187 unchanged lines hidden (view full) ---
852 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
853 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
854 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
855 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
856 "q" 11 bit branch address (MIPS16OP_*_IMM11)
857 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
858 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
859 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
860 */
861
862/* For the mips16, we use the same opcode table format and a few of
863 the same flags. However, most of the flags are different. */
864
865/* Modifies the register in MIPS16OP_*_RX. */
866#define MIPS16_INSN_WRITE_X 0x00000001
867/* Modifies the register in MIPS16OP_*_RY. */
868#define MIPS16_INSN_WRITE_Y 0x00000002
869/* Modifies the register in MIPS16OP_*_RZ. */
--- 45 unchanged lines hidden ---