25
26
27/* Intel 80386 machine specific gas.
28 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
29 x86_64 support by Jan Hubicka (jh@suse.cz)
30 Bugs & suggestions are completely welcome. This is free software.
31 Please help us make it better. */
32
33#include <ctype.h>
34
35#include "as.h"
36#include "subsegs.h"
37#include "dwarf2dbg.h"
38#include "opcode/i386.h"
39
40#ifndef REGISTER_WARNINGS
41#define REGISTER_WARNINGS 1
42#endif
43
44#ifndef INFER_ADDR_PREFIX
45#define INFER_ADDR_PREFIX 1
46#endif
47
48#ifndef SCALE1_WHEN_NO_INDEX
49/* Specifying a scale factor besides 1 when there is no index is
50 futile. eg. `mov (%ebx,2),%al' does exactly the same as
51 `mov (%ebx),%al'. To slavishly follow what the programmer
52 specified, set SCALE1_WHEN_NO_INDEX to 0. */
53#define SCALE1_WHEN_NO_INDEX 1
54#endif
55
56#define true 1
57#define false 0
58
59static unsigned int mode_from_disp_size PARAMS ((unsigned int));
60static int fits_in_signed_byte PARAMS ((offsetT));
61static int fits_in_unsigned_byte PARAMS ((offsetT));
62static int fits_in_unsigned_word PARAMS ((offsetT));
63static int fits_in_signed_word PARAMS ((offsetT));
64static int fits_in_unsigned_long PARAMS ((offsetT));
65static int fits_in_signed_long PARAMS ((offsetT));
66static int smallest_imm_type PARAMS ((offsetT));
67static offsetT offset_in_range PARAMS ((offsetT, int));
68static int add_prefix PARAMS ((unsigned int));
69static void set_code_flag PARAMS ((int));
70static void set_16bit_gcc_code_flag PARAMS ((int));
71static void set_intel_syntax PARAMS ((int));
72static void set_cpu_arch PARAMS ((int));
73
74#ifdef BFD_ASSEMBLER
75static bfd_reloc_code_real_type reloc
76 PARAMS ((int, int, int, bfd_reloc_code_real_type));
77#define RELOC_ENUM enum bfd_reloc_code_real
78#else
79#define RELOC_ENUM int
80#endif
81
82#ifndef DEFAULT_ARCH
83#define DEFAULT_ARCH "i386"
84#endif
85static char *default_arch = DEFAULT_ARCH;
86
87/* 'md_assemble ()' gathers together information and puts it into a
88 i386_insn. */
89
90union i386_op
91 {
92 expressionS *disps;
93 expressionS *imms;
94 const reg_entry *regs;
95 };
96
97struct _i386_insn
98 {
99 /* TM holds the template for the insn were currently assembling. */
100 template tm;
101
102 /* SUFFIX holds the instruction mnemonic suffix if given.
103 (e.g. 'l' for 'movl') */
104 char suffix;
105
106 /* OPERANDS gives the number of given operands. */
107 unsigned int operands;
108
109 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
110 of given register, displacement, memory operands and immediate
111 operands. */
112 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
113
114 /* TYPES [i] is the type (see above #defines) which tells us how to
115 use OP[i] for the corresponding operand. */
116 unsigned int types[MAX_OPERANDS];
117
118 /* Displacement expression, immediate expression, or register for each
119 operand. */
120 union i386_op op[MAX_OPERANDS];
121
122 /* Flags for operands. */
123 unsigned int flags[MAX_OPERANDS];
124#define Operand_PCrel 1
125
126 /* Relocation type for operand */
127 RELOC_ENUM reloc[MAX_OPERANDS];
128
129 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
130 the base index byte below. */
131 const reg_entry *base_reg;
132 const reg_entry *index_reg;
133 unsigned int log2_scale_factor;
134
135 /* SEG gives the seg_entries of this insn. They are zero unless
136 explicit segment overrides are given. */
137 const seg_entry *seg[2];
138
139 /* PREFIX holds all the given prefix opcodes (usually null).
140 PREFIXES is the number of prefix opcodes. */
141 unsigned int prefixes;
142 unsigned char prefix[MAX_PREFIXES];
143
144 /* RM and SIB are the modrm byte and the sib byte where the
145 addressing modes of this insn are encoded. */
146
147 modrm_byte rm;
148 rex_byte rex;
149 sib_byte sib;
150 };
151
152typedef struct _i386_insn i386_insn;
153
154/* List of chars besides those in app.c:symbol_chars that can start an
155 operand. Used to prevent the scrubber eating vital white-space. */
156#ifdef LEX_AT
157const char extra_symbol_chars[] = "*%-(@";
158#else
159const char extra_symbol_chars[] = "*%-(";
160#endif
161
162/* This array holds the chars that always start a comment. If the
163 pre-processor is disabled, these aren't very useful. */
164#if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
165/* Putting '/' here makes it impossible to use the divide operator.
166 However, we need it for compatibility with SVR4 systems. */
167const char comment_chars[] = "#/";
168#define PREFIX_SEPARATOR '\\'
169#else
170const char comment_chars[] = "#";
171#define PREFIX_SEPARATOR '/'
172#endif
173
174/* This array holds the chars that only start a comment at the beginning of
175 a line. If the line seems to have the form '# 123 filename'
176 .line and .file directives will appear in the pre-processed output.
177 Note that input_file.c hand checks for '#' at the beginning of the
178 first line of the input file. This is because the compiler outputs
179 #NO_APP at the beginning of its output.
180 Also note that comments started like this one will always work if
181 '/' isn't otherwise defined. */
182#if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
183const char line_comment_chars[] = "";
184#else
185const char line_comment_chars[] = "/";
186#endif
187
188const char line_separator_chars[] = ";";
189
190/* Chars that can be used to separate mant from exp in floating point
191 nums. */
192const char EXP_CHARS[] = "eE";
193
194/* Chars that mean this number is a floating point constant
195 As in 0f12.456
196 or 0d1.2345e12. */
197const char FLT_CHARS[] = "fFdDxX";
198
199/* Tables for lexical analysis. */
200static char mnemonic_chars[256];
201static char register_chars[256];
202static char operand_chars[256];
203static char identifier_chars[256];
204static char digit_chars[256];
205
206/* Lexical macros. */
207#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
208#define is_operand_char(x) (operand_chars[(unsigned char) x])
209#define is_register_char(x) (register_chars[(unsigned char) x])
210#define is_space_char(x) ((x) == ' ')
211#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
212#define is_digit_char(x) (digit_chars[(unsigned char) x])
213
214/* All non-digit non-letter charcters that may occur in an operand. */
215static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
216
217/* md_assemble() always leaves the strings it's passed unaltered. To
218 effect this we maintain a stack of saved characters that we've smashed
219 with '\0's (indicating end of strings for various sub-fields of the
220 assembler instruction). */
221static char save_stack[32];
222static char *save_stack_p;
223#define END_STRING_AND_SAVE(s) \
224 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
225#define RESTORE_END_STRING(s) \
226 do { *(s) = *--save_stack_p; } while (0)
227
228/* The instruction we're assembling. */
229static i386_insn i;
230
231/* Possible templates for current insn. */
232static const templates *current_templates;
233
234/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
235static expressionS disp_expressions[2], im_expressions[2];
236
237/* Current operand we are working on. */
238static int this_operand;
239
240/* We support four different modes. FLAG_CODE variable is used to distinguish
241 these. */
242
243enum flag_code {
244 CODE_32BIT,
245 CODE_16BIT,
246 CODE_64BIT };
247#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
248
249static enum flag_code flag_code;
250static int use_rela_relocations = 0;
251
252/* The names used to print error messages. */
253static const char *flag_code_names[] =
254 {
255 "32",
256 "16",
257 "64"
258 };
259
260/* 1 for intel syntax,
261 0 if att syntax. */
262static int intel_syntax = 0;
263
264/* 1 if register prefix % not required. */
265static int allow_naked_reg = 0;
266
267/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
268 leave, push, and pop instructions so that gcc has the same stack
269 frame as in 32 bit mode. */
270static char stackop_size = '\0';
271
272/* Non-zero to quieten some warnings. */
273static int quiet_warnings = 0;
274
275/* CPU name. */
276static const char *cpu_arch_name = NULL;
277
278/* CPU feature flags. */
279static unsigned int cpu_arch_flags = CpuUnknownFlags|CpuNo64;
280
281/* If set, conditional jumps are not automatically promoted to handle
282 larger than a byte offset. */
283static unsigned int no_cond_jump_promotion = 0;
284
285/* Interface to relax_segment.
286 There are 3 major relax states for 386 jump insns because the
287 different types of jumps add different sizes to frags when we're
288 figuring out what sort of jump to choose to reach a given label. */
289
290/* Types. */
291#define UNCOND_JUMP 0
292#define COND_JUMP 1
293#define COND_JUMP86 2
294
295/* Sizes. */
296#define CODE16 1
297#define SMALL 0
298#define SMALL16 (SMALL|CODE16)
299#define BIG 2
300#define BIG16 (BIG|CODE16)
301
302#ifndef INLINE
303#ifdef __GNUC__
304#define INLINE __inline__
305#else
306#define INLINE
307#endif
308#endif
309
310#define ENCODE_RELAX_STATE(type, size) \
311 ((relax_substateT) (((type) << 2) | (size)))
312#define TYPE_FROM_RELAX_STATE(s) \
313 ((s) >> 2)
314#define DISP_SIZE_FROM_RELAX_STATE(s) \
315 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
316
317/* This table is used by relax_frag to promote short jumps to long
318 ones where necessary. SMALL (short) jumps may be promoted to BIG
319 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
320 don't allow a short jump in a 32 bit code segment to be promoted to
321 a 16 bit offset jump because it's slower (requires data size
322 prefix), and doesn't work, unless the destination is in the bottom
323 64k of the code segment (The top 16 bits of eip are zeroed). */
324
325const relax_typeS md_relax_table[] =
326{
327 /* The fields are:
328 1) most positive reach of this state,
329 2) most negative reach of this state,
330 3) how many bytes this mode will have in the variable part of the frag
331 4) which index into the table to try if we can't fit into this one. */
332
333 /* UNCOND_JUMP states. */
334 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
335 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
336 /* dword jmp adds 4 bytes to frag:
337 0 extra opcode bytes, 4 displacement bytes. */
338 {0, 0, 4, 0},
339 /* word jmp adds 2 byte2 to frag:
340 0 extra opcode bytes, 2 displacement bytes. */
341 {0, 0, 2, 0},
342
343 /* COND_JUMP states. */
344 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
345 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
346 /* dword conditionals adds 5 bytes to frag:
347 1 extra opcode byte, 4 displacement bytes. */
348 {0, 0, 5, 0},
349 /* word conditionals add 3 bytes to frag:
350 1 extra opcode byte, 2 displacement bytes. */
351 {0, 0, 3, 0},
352
353 /* COND_JUMP86 states. */
354 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
355 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
356 /* dword conditionals adds 5 bytes to frag:
357 1 extra opcode byte, 4 displacement bytes. */
358 {0, 0, 5, 0},
359 /* word conditionals add 4 bytes to frag:
360 1 displacement byte and a 3 byte long branch insn. */
361 {0, 0, 4, 0}
362};
363
364static const arch_entry cpu_arch[] = {
365 {"i8086", Cpu086 },
366 {"i186", Cpu086|Cpu186 },
367 {"i286", Cpu086|Cpu186|Cpu286 },
368 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
369 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
370 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
371 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
372 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
373 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
374 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
375 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
376 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
377 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
378 {NULL, 0 }
379};
380
381void
382i386_align_code (fragP, count)
383 fragS *fragP;
384 int count;
385{
386 /* Various efficient no-op patterns for aligning code labels.
387 Note: Don't try to assemble the instructions in the comments.
388 0L and 0w are not legal. */
389 static const char f32_1[] =
390 {0x90}; /* nop */
391 static const char f32_2[] =
392 {0x89,0xf6}; /* movl %esi,%esi */
393 static const char f32_3[] =
394 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
395 static const char f32_4[] =
396 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
397 static const char f32_5[] =
398 {0x90, /* nop */
399 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
400 static const char f32_6[] =
401 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
402 static const char f32_7[] =
403 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
404 static const char f32_8[] =
405 {0x90, /* nop */
406 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
407 static const char f32_9[] =
408 {0x89,0xf6, /* movl %esi,%esi */
409 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
410 static const char f32_10[] =
411 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
412 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
413 static const char f32_11[] =
414 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
415 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
416 static const char f32_12[] =
417 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
418 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
419 static const char f32_13[] =
420 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
421 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
422 static const char f32_14[] =
423 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
424 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
425 static const char f32_15[] =
426 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
427 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
428 static const char f16_3[] =
429 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
430 static const char f16_4[] =
431 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
432 static const char f16_5[] =
433 {0x90, /* nop */
434 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
435 static const char f16_6[] =
436 {0x89,0xf6, /* mov %si,%si */
437 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
438 static const char f16_7[] =
439 {0x8d,0x74,0x00, /* lea 0(%si),%si */
440 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
441 static const char f16_8[] =
442 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
443 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
444 static const char *const f32_patt[] = {
445 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
446 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
447 };
448 static const char *const f16_patt[] = {
449 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
450 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
451 };
452
453 /* ??? We can't use these fillers for x86_64, since they often kills the
454 upper halves. Solve later. */
455 if (flag_code == CODE_64BIT)
456 count = 1;
457
458 if (count > 0 && count <= 15)
459 {
460 if (flag_code == CODE_16BIT)
461 {
462 memcpy (fragP->fr_literal + fragP->fr_fix,
463 f16_patt[count - 1], count);
464 if (count > 8)
465 /* Adjust jump offset. */
466 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
467 }
468 else
469 memcpy (fragP->fr_literal + fragP->fr_fix,
470 f32_patt[count - 1], count);
471 fragP->fr_var = count;
472 }
473}
474
475static char *output_invalid PARAMS ((int c));
476static int i386_operand PARAMS ((char *operand_string));
477static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
478static const reg_entry *parse_register PARAMS ((char *reg_string,
479 char **end_op));
480
481#ifndef I386COFF
482static void s_bss PARAMS ((int));
483#endif
484
485symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
486
487static INLINE unsigned int
488mode_from_disp_size (t)
489 unsigned int t;
490{
491 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
492}
493
494static INLINE int
495fits_in_signed_byte (num)
496 offsetT num;
497{
498 return (num >= -128) && (num <= 127);
499}
500
501static INLINE int
502fits_in_unsigned_byte (num)
503 offsetT num;
504{
505 return (num & 0xff) == num;
506}
507
508static INLINE int
509fits_in_unsigned_word (num)
510 offsetT num;
511{
512 return (num & 0xffff) == num;
513}
514
515static INLINE int
516fits_in_signed_word (num)
517 offsetT num;
518{
519 return (-32768 <= num) && (num <= 32767);
520}
521static INLINE int
522fits_in_signed_long (num)
523 offsetT num ATTRIBUTE_UNUSED;
524{
525#ifndef BFD64
526 return 1;
527#else
528 return (!(((offsetT) -1 << 31) & num)
529 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
530#endif
531} /* fits_in_signed_long() */
532static INLINE int
533fits_in_unsigned_long (num)
534 offsetT num ATTRIBUTE_UNUSED;
535{
536#ifndef BFD64
537 return 1;
538#else
539 return (num & (((offsetT) 2 << 31) - 1)) == num;
540#endif
541} /* fits_in_unsigned_long() */
542
543static int
544smallest_imm_type (num)
545 offsetT num;
546{
547 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64)
548 && !(cpu_arch_flags & (CpuUnknown)))
549 {
550 /* This code is disabled on the 486 because all the Imm1 forms
551 in the opcode table are slower on the i486. They're the
552 versions with the implicitly specified single-position
553 displacement, which has another syntax if you really want to
554 use that form. */
555 if (num == 1)
556 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
557 }
558 return (fits_in_signed_byte (num)
559 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
560 : fits_in_unsigned_byte (num)
561 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
562 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
563 ? (Imm16 | Imm32 | Imm32S | Imm64)
564 : fits_in_signed_long (num)
565 ? (Imm32 | Imm32S | Imm64)
566 : fits_in_unsigned_long (num)
567 ? (Imm32 | Imm64)
568 : Imm64);
569}
570
571static offsetT
572offset_in_range (val, size)
573 offsetT val;
574 int size;
575{
576 addressT mask;
577
578 switch (size)
579 {
580 case 1: mask = ((addressT) 1 << 8) - 1; break;
581 case 2: mask = ((addressT) 1 << 16) - 1; break;
582 case 4: mask = ((addressT) 2 << 31) - 1; break;
583#ifdef BFD64
584 case 8: mask = ((addressT) 2 << 63) - 1; break;
585#endif
586 default: abort ();
587 }
588
589 /* If BFD64, sign extend val. */
590 if (!use_rela_relocations)
591 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
592 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
593
594 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
595 {
596 char buf1[40], buf2[40];
597
598 sprint_value (buf1, val);
599 sprint_value (buf2, val & mask);
600 as_warn (_("%s shortened to %s"), buf1, buf2);
601 }
602 return val & mask;
603}
604
605/* Returns 0 if attempting to add a prefix where one from the same
606 class already exists, 1 if non rep/repne added, 2 if rep/repne
607 added. */
608static int
609add_prefix (prefix)
610 unsigned int prefix;
611{
612 int ret = 1;
613 int q;
614
615 if (prefix >= 0x40 && prefix < 0x50 && flag_code == CODE_64BIT)
616 q = REX_PREFIX;
617 else
618 switch (prefix)
619 {
620 default:
621 abort ();
622
623 case CS_PREFIX_OPCODE:
624 case DS_PREFIX_OPCODE:
625 case ES_PREFIX_OPCODE:
626 case FS_PREFIX_OPCODE:
627 case GS_PREFIX_OPCODE:
628 case SS_PREFIX_OPCODE:
629 q = SEG_PREFIX;
630 break;
631
632 case REPNE_PREFIX_OPCODE:
633 case REPE_PREFIX_OPCODE:
634 ret = 2;
635 /* fall thru */
636 case LOCK_PREFIX_OPCODE:
637 q = LOCKREP_PREFIX;
638 break;
639
640 case FWAIT_OPCODE:
641 q = WAIT_PREFIX;
642 break;
643
644 case ADDR_PREFIX_OPCODE:
645 q = ADDR_PREFIX;
646 break;
647
648 case DATA_PREFIX_OPCODE:
649 q = DATA_PREFIX;
650 break;
651 }
652
653 if (i.prefix[q])
654 {
655 as_bad (_("same type of prefix used twice"));
656 return 0;
657 }
658
659 i.prefixes += 1;
660 i.prefix[q] = prefix;
661 return ret;
662}
663
664static void
665set_code_flag (value)
666 int value;
667{
668 flag_code = value;
669 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
670 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
671 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
672 {
673 as_bad (_("64bit mode not supported on this CPU."));
674 }
675 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
676 {
677 as_bad (_("32bit mode not supported on this CPU."));
678 }
679 stackop_size = '\0';
680}
681
682static void
683set_16bit_gcc_code_flag (new_code_flag)
684 int new_code_flag;
685{
686 flag_code = new_code_flag;
687 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
688 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
689 stackop_size = 'l';
690}
691
692static void
693set_intel_syntax (syntax_flag)
694 int syntax_flag;
695{
696 /* Find out if register prefixing is specified. */
697 int ask_naked_reg = 0;
698
699 SKIP_WHITESPACE ();
700 if (! is_end_of_line[(unsigned char) *input_line_pointer])
701 {
702 char *string = input_line_pointer;
703 int e = get_symbol_end ();
704
705 if (strcmp (string, "prefix") == 0)
706 ask_naked_reg = 1;
707 else if (strcmp (string, "noprefix") == 0)
708 ask_naked_reg = -1;
709 else
710 as_bad (_("bad argument to syntax directive."));
711 *input_line_pointer = e;
712 }
713 demand_empty_rest_of_line ();
714
715 intel_syntax = syntax_flag;
716
717 if (ask_naked_reg == 0)
718 {
719#ifdef BFD_ASSEMBLER
720 allow_naked_reg = (intel_syntax
721 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
722#else
723 /* Conservative default. */
724 allow_naked_reg = 0;
725#endif
726 }
727 else
728 allow_naked_reg = (ask_naked_reg < 0);
729}
730
731static void
732set_cpu_arch (dummy)
733 int dummy ATTRIBUTE_UNUSED;
734{
735 SKIP_WHITESPACE ();
736
737 if (! is_end_of_line[(unsigned char) *input_line_pointer])
738 {
739 char *string = input_line_pointer;
740 int e = get_symbol_end ();
741 int i;
742
743 for (i = 0; cpu_arch[i].name; i++)
744 {
745 if (strcmp (string, cpu_arch[i].name) == 0)
746 {
747 cpu_arch_name = cpu_arch[i].name;
748 cpu_arch_flags = (cpu_arch[i].flags
749 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
750 break;
751 }
752 }
753 if (!cpu_arch[i].name)
754 as_bad (_("no such architecture: `%s'"), string);
755
756 *input_line_pointer = e;
757 }
758 else
759 as_bad (_("missing cpu architecture"));
760
761 no_cond_jump_promotion = 0;
762 if (*input_line_pointer == ','
763 && ! is_end_of_line[(unsigned char) input_line_pointer[1]])
764 {
765 char *string = ++input_line_pointer;
766 int e = get_symbol_end ();
767
768 if (strcmp (string, "nojumps") == 0)
769 no_cond_jump_promotion = 1;
770 else if (strcmp (string, "jumps") == 0)
771 ;
772 else
773 as_bad (_("no such architecture modifier: `%s'"), string);
774
775 *input_line_pointer = e;
776 }
777
778 demand_empty_rest_of_line ();
779}
780
781const pseudo_typeS md_pseudo_table[] =
782{
783#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
784 {"align", s_align_bytes, 0},
785#else
786 {"align", s_align_ptwo, 0},
787#endif
788 {"arch", set_cpu_arch, 0},
789#ifndef I386COFF
790 {"bss", s_bss, 0},
791#endif
792 {"ffloat", float_cons, 'f'},
793 {"dfloat", float_cons, 'd'},
794 {"tfloat", float_cons, 'x'},
795 {"value", cons, 2},
796 {"noopt", s_ignore, 0},
797 {"optim", s_ignore, 0},
798 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
799 {"code16", set_code_flag, CODE_16BIT},
800 {"code32", set_code_flag, CODE_32BIT},
801 {"code64", set_code_flag, CODE_64BIT},
802 {"intel_syntax", set_intel_syntax, 1},
803 {"att_syntax", set_intel_syntax, 0},
804 {"file", dwarf2_directive_file, 0},
805 {"loc", dwarf2_directive_loc, 0},
806 {0, 0, 0}
807};
808
809/* For interface with expression (). */
810extern char *input_line_pointer;
811
812/* Hash table for instruction mnemonic lookup. */
813static struct hash_control *op_hash;
814
815/* Hash table for register lookup. */
816static struct hash_control *reg_hash;
817
818#ifdef BFD_ASSEMBLER
819unsigned long
820i386_mach ()
821{
822 if (!strcmp (default_arch, "x86_64"))
823 return bfd_mach_x86_64;
824 else if (!strcmp (default_arch, "i386"))
825 return bfd_mach_i386_i386;
826 else
827 as_fatal (_("Unknown architecture"));
828}
829#endif
830
831void
832md_begin ()
833{
834 const char *hash_err;
835
836 /* Initialize op_hash hash table. */
837 op_hash = hash_new ();
838
839 {
840 register const template *optab;
841 register templates *core_optab;
842
843 /* Setup for loop. */
844 optab = i386_optab;
845 core_optab = (templates *) xmalloc (sizeof (templates));
846 core_optab->start = optab;
847
848 while (1)
849 {
850 ++optab;
851 if (optab->name == NULL
852 || strcmp (optab->name, (optab - 1)->name) != 0)
853 {
854 /* different name --> ship out current template list;
855 add to hash table; & begin anew. */
856 core_optab->end = optab;
857 hash_err = hash_insert (op_hash,
858 (optab - 1)->name,
859 (PTR) core_optab);
860 if (hash_err)
861 {
862 as_fatal (_("Internal Error: Can't hash %s: %s"),
863 (optab - 1)->name,
864 hash_err);
865 }
866 if (optab->name == NULL)
867 break;
868 core_optab = (templates *) xmalloc (sizeof (templates));
869 core_optab->start = optab;
870 }
871 }
872 }
873
874 /* Initialize reg_hash hash table. */
875 reg_hash = hash_new ();
876 {
877 register const reg_entry *regtab;
878
879 for (regtab = i386_regtab;
880 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
881 regtab++)
882 {
883 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
884 if (hash_err)
885 as_fatal (_("Internal Error: Can't hash %s: %s"),
886 regtab->reg_name,
887 hash_err);
888 }
889 }
890
891 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
892 {
893 register int c;
894 register char *p;
895
896 for (c = 0; c < 256; c++)
897 {
898 if (isdigit (c))
899 {
900 digit_chars[c] = c;
901 mnemonic_chars[c] = c;
902 register_chars[c] = c;
903 operand_chars[c] = c;
904 }
905 else if (islower (c))
906 {
907 mnemonic_chars[c] = c;
908 register_chars[c] = c;
909 operand_chars[c] = c;
910 }
911 else if (isupper (c))
912 {
913 mnemonic_chars[c] = tolower (c);
914 register_chars[c] = mnemonic_chars[c];
915 operand_chars[c] = c;
916 }
917
918 if (isalpha (c) || isdigit (c))
919 identifier_chars[c] = c;
920 else if (c >= 128)
921 {
922 identifier_chars[c] = c;
923 operand_chars[c] = c;
924 }
925 }
926
927#ifdef LEX_AT
928 identifier_chars['@'] = '@';
929#endif
930 digit_chars['-'] = '-';
931 identifier_chars['_'] = '_';
932 identifier_chars['.'] = '.';
933
934 for (p = operand_special_chars; *p != '\0'; p++)
935 operand_chars[(unsigned char) *p] = *p;
936 }
937
938#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
939 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
940 {
941 record_alignment (text_section, 2);
942 record_alignment (data_section, 2);
943 record_alignment (bss_section, 2);
944 }
945#endif
946}
947
948void
949i386_print_statistics (file)
950 FILE *file;
951{
952 hash_print_statistics (file, "i386 opcode", op_hash);
953 hash_print_statistics (file, "i386 register", reg_hash);
954}
955
956#ifdef DEBUG386
957
958/* Debugging routines for md_assemble. */
959static void pi PARAMS ((char *, i386_insn *));
960static void pte PARAMS ((template *));
961static void pt PARAMS ((unsigned int));
962static void pe PARAMS ((expressionS *));
963static void ps PARAMS ((symbolS *));
964
965static void
966pi (line, x)
967 char *line;
968 i386_insn *x;
969{
970 unsigned int i;
971
972 fprintf (stdout, "%s: template ", line);
973 pte (&x->tm);
974 fprintf (stdout, " address: base %s index %s scale %x\n",
975 x->base_reg ? x->base_reg->reg_name : "none",
976 x->index_reg ? x->index_reg->reg_name : "none",
977 x->log2_scale_factor);
978 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
979 x->rm.mode, x->rm.reg, x->rm.regmem);
980 fprintf (stdout, " sib: base %x index %x scale %x\n",
981 x->sib.base, x->sib.index, x->sib.scale);
982 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
983 x->rex.mode64, x->rex.extX, x->rex.extY, x->rex.extZ);
984 for (i = 0; i < x->operands; i++)
985 {
986 fprintf (stdout, " #%d: ", i + 1);
987 pt (x->types[i]);
988 fprintf (stdout, "\n");
989 if (x->types[i]
990 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
991 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
992 if (x->types[i] & Imm)
993 pe (x->op[i].imms);
994 if (x->types[i] & Disp)
995 pe (x->op[i].disps);
996 }
997}
998
999static void
1000pte (t)
1001 template *t;
1002{
1003 unsigned int i;
1004 fprintf (stdout, " %d operands ", t->operands);
1005 fprintf (stdout, "opcode %x ", t->base_opcode);
1006 if (t->extension_opcode != None)
1007 fprintf (stdout, "ext %x ", t->extension_opcode);
1008 if (t->opcode_modifier & D)
1009 fprintf (stdout, "D");
1010 if (t->opcode_modifier & W)
1011 fprintf (stdout, "W");
1012 fprintf (stdout, "\n");
1013 for (i = 0; i < t->operands; i++)
1014 {
1015 fprintf (stdout, " #%d type ", i + 1);
1016 pt (t->operand_types[i]);
1017 fprintf (stdout, "\n");
1018 }
1019}
1020
1021static void
1022pe (e)
1023 expressionS *e;
1024{
1025 fprintf (stdout, " operation %d\n", e->X_op);
1026 fprintf (stdout, " add_number %ld (%lx)\n",
1027 (long) e->X_add_number, (long) e->X_add_number);
1028 if (e->X_add_symbol)
1029 {
1030 fprintf (stdout, " add_symbol ");
1031 ps (e->X_add_symbol);
1032 fprintf (stdout, "\n");
1033 }
1034 if (e->X_op_symbol)
1035 {
1036 fprintf (stdout, " op_symbol ");
1037 ps (e->X_op_symbol);
1038 fprintf (stdout, "\n");
1039 }
1040}
1041
1042static void
1043ps (s)
1044 symbolS *s;
1045{
1046 fprintf (stdout, "%s type %s%s",
1047 S_GET_NAME (s),
1048 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1049 segment_name (S_GET_SEGMENT (s)));
1050}
1051
1052struct type_name
1053 {
1054 unsigned int mask;
1055 char *tname;
1056 }
1057
1058type_names[] =
1059{
1060 { Reg8, "r8" },
1061 { Reg16, "r16" },
1062 { Reg32, "r32" },
1063 { Reg64, "r64" },
1064 { Imm8, "i8" },
1065 { Imm8S, "i8s" },
1066 { Imm16, "i16" },
1067 { Imm32, "i32" },
1068 { Imm32S, "i32s" },
1069 { Imm64, "i64" },
1070 { Imm1, "i1" },
1071 { BaseIndex, "BaseIndex" },
1072 { Disp8, "d8" },
1073 { Disp16, "d16" },
1074 { Disp32, "d32" },
1075 { Disp32S, "d32s" },
1076 { Disp64, "d64" },
1077 { InOutPortReg, "InOutPortReg" },
1078 { ShiftCount, "ShiftCount" },
1079 { Control, "control reg" },
1080 { Test, "test reg" },
1081 { Debug, "debug reg" },
1082 { FloatReg, "FReg" },
1083 { FloatAcc, "FAcc" },
1084 { SReg2, "SReg2" },
1085 { SReg3, "SReg3" },
1086 { Acc, "Acc" },
1087 { JumpAbsolute, "Jump Absolute" },
1088 { RegMMX, "rMMX" },
1089 { RegXMM, "rXMM" },
1090 { EsSeg, "es" },
1091 { 0, "" }
1092};
1093
1094static void
1095pt (t)
1096 unsigned int t;
1097{
1098 register struct type_name *ty;
1099
1100 for (ty = type_names; ty->mask; ty++)
1101 if (t & ty->mask)
1102 fprintf (stdout, "%s, ", ty->tname);
1103 fflush (stdout);
1104}
1105
1106#endif /* DEBUG386 */
1107
1108int
1109tc_i386_force_relocation (fixp)
1110 struct fix *fixp;
1111{
1112#ifdef BFD_ASSEMBLER
1113 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1114 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1115 return 1;
1116 return 0;
1117#else
1118 /* For COFF. */
1119 return fixp->fx_r_type == 7;
1120#endif
1121}
1122
1123#ifdef BFD_ASSEMBLER
1124
1125static bfd_reloc_code_real_type
1126reloc (size, pcrel, sign, other)
1127 int size;
1128 int pcrel;
1129 int sign;
1130 bfd_reloc_code_real_type other;
1131{
1132 if (other != NO_RELOC)
1133 return other;
1134
1135 if (pcrel)
1136 {
1137 if (!sign)
1138 as_bad (_("There are no unsigned pc-relative relocations"));
1139 switch (size)
1140 {
1141 case 1: return BFD_RELOC_8_PCREL;
1142 case 2: return BFD_RELOC_16_PCREL;
1143 case 4: return BFD_RELOC_32_PCREL;
1144 }
1145 as_bad (_("can not do %d byte pc-relative relocation"), size);
1146 }
1147 else
1148 {
1149 if (sign)
1150 switch (size)
1151 {
1152 case 4: return BFD_RELOC_X86_64_32S;
1153 }
1154 else
1155 switch (size)
1156 {
1157 case 1: return BFD_RELOC_8;
1158 case 2: return BFD_RELOC_16;
1159 case 4: return BFD_RELOC_32;
1160 case 8: return BFD_RELOC_64;
1161 }
1162 as_bad (_("can not do %s %d byte relocation"),
1163 sign ? "signed" : "unsigned", size);
1164 }
1165
1166 abort ();
1167 return BFD_RELOC_NONE;
1168}
1169
1170/* Here we decide which fixups can be adjusted to make them relative to
1171 the beginning of the section instead of the symbol. Basically we need
1172 to make sure that the dynamic relocations are done correctly, so in
1173 some cases we force the original symbol to be used. */
1174
1175int
1176tc_i386_fix_adjustable (fixP)
1177 fixS *fixP;
1178{
1179#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1180 /* Prevent all adjustments to global symbols, or else dynamic
1181 linking will not work correctly. */
1182 if (S_IS_EXTERNAL (fixP->fx_addsy)
1183 || S_IS_WEAK (fixP->fx_addsy))
1184 return 0;
1185#endif
1186 /* adjust_reloc_syms doesn't know about the GOT. */
1187 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1188 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1189 || fixP->fx_r_type == BFD_RELOC_386_GOT32
1190 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1191 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
1192 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
1193 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1194 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1195 return 0;
1196 return 1;
1197}
1198#else
1199#define reloc(SIZE,PCREL,SIGN,OTHER) 0
1200#define BFD_RELOC_16 0
1201#define BFD_RELOC_32 0
1202#define BFD_RELOC_16_PCREL 0
1203#define BFD_RELOC_32_PCREL 0
1204#define BFD_RELOC_386_PLT32 0
1205#define BFD_RELOC_386_GOT32 0
1206#define BFD_RELOC_386_GOTOFF 0
1207#define BFD_RELOC_X86_64_PLT32 0
1208#define BFD_RELOC_X86_64_GOT32 0
1209#define BFD_RELOC_X86_64_GOTPCREL 0
1210#endif
1211
1212static int intel_float_operand PARAMS ((char *mnemonic));
1213
1214static int
1215intel_float_operand (mnemonic)
1216 char *mnemonic;
1217{
1218 if (mnemonic[0] == 'f' && mnemonic[1] == 'i')
1219 return 2;
1220
1221 if (mnemonic[0] == 'f')
1222 return 1;
1223
1224 return 0;
1225}
1226
1227/* This is the guts of the machine-dependent assembler. LINE points to a
1228 machine dependent instruction. This function is supposed to emit
1229 the frags/bytes it assembles to. */
1230
1231void
1232md_assemble (line)
1233 char *line;
1234{
1235 /* Points to template once we've found it. */
1236 const template *t;
1237
1238 int j;
1239
1240 char mnemonic[MAX_MNEM_SIZE];
1241
1242 /* Initialize globals. */
1243 memset (&i, '\0', sizeof (i));
1244 for (j = 0; j < MAX_OPERANDS; j++)
1245 i.reloc[j] = NO_RELOC;
1246 memset (disp_expressions, '\0', sizeof (disp_expressions));
1247 memset (im_expressions, '\0', sizeof (im_expressions));
1248 save_stack_p = save_stack;
1249
1250 /* First parse an instruction mnemonic & call i386_operand for the operands.
1251 We assume that the scrubber has arranged it so that line[0] is the valid
1252 start of a (possibly prefixed) mnemonic. */
1253 {
1254 char *l = line;
1255 char *token_start = l;
1256 char *mnem_p;
1257
1258 /* Non-zero if we found a prefix only acceptable with string insns. */
1259 const char *expecting_string_instruction = NULL;
1260
1261 while (1)
1262 {
1263 mnem_p = mnemonic;
1264 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1265 {
1266 mnem_p++;
1267 if (mnem_p >= mnemonic + sizeof (mnemonic))
1268 {
1269 as_bad (_("no such instruction: `%s'"), token_start);
1270 return;
1271 }
1272 l++;
1273 }
1274 if (!is_space_char (*l)
1275 && *l != END_OF_INSN
1276 && *l != PREFIX_SEPARATOR)
1277 {
1278 as_bad (_("invalid character %s in mnemonic"),
1279 output_invalid (*l));
1280 return;
1281 }
1282 if (token_start == l)
1283 {
1284 if (*l == PREFIX_SEPARATOR)
1285 as_bad (_("expecting prefix; got nothing"));
1286 else
1287 as_bad (_("expecting mnemonic; got nothing"));
1288 return;
1289 }
1290
1291 /* Look up instruction (or prefix) via hash table. */
1292 current_templates = hash_find (op_hash, mnemonic);
1293
1294 if (*l != END_OF_INSN
1295 && (! is_space_char (*l) || l[1] != END_OF_INSN)
1296 && current_templates
1297 && (current_templates->start->opcode_modifier & IsPrefix))
1298 {
1299 /* If we are in 16-bit mode, do not allow addr16 or data16.
1300 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1301 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1302 && (((current_templates->start->opcode_modifier & Size32) != 0)
1303 ^ (flag_code == CODE_16BIT)))
1304 {
1305 as_bad (_("redundant %s prefix"),
1306 current_templates->start->name);
1307 return;
1308 }
1309 /* Add prefix, checking for repeated prefixes. */
1310 switch (add_prefix (current_templates->start->base_opcode))
1311 {
1312 case 0:
1313 return;
1314 case 2:
1315 expecting_string_instruction = current_templates->start->name;
1316 break;
1317 }
1318 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1319 token_start = ++l;
1320 }
1321 else
1322 break;
1323 }
1324
1325 if (!current_templates)
1326 {
1327 /* See if we can get a match by trimming off a suffix. */
1328 switch (mnem_p[-1])
1329 {
1330 case WORD_MNEM_SUFFIX:
1331 case BYTE_MNEM_SUFFIX:
1332 case QWORD_MNEM_SUFFIX:
1333 i.suffix = mnem_p[-1];
1334 mnem_p[-1] = '\0';
1335 current_templates = hash_find (op_hash, mnemonic);
1336 break;
1337 case SHORT_MNEM_SUFFIX:
1338 case LONG_MNEM_SUFFIX:
1339 if (!intel_syntax)
1340 {
1341 i.suffix = mnem_p[-1];
1342 mnem_p[-1] = '\0';
1343 current_templates = hash_find (op_hash, mnemonic);
1344 }
1345 break;
1346
1347 /* Intel Syntax. */
1348 case 'd':
1349 if (intel_syntax)
1350 {
1351 if (intel_float_operand (mnemonic))
1352 i.suffix = SHORT_MNEM_SUFFIX;
1353 else
1354 i.suffix = LONG_MNEM_SUFFIX;
1355 mnem_p[-1] = '\0';
1356 current_templates = hash_find (op_hash, mnemonic);
1357 }
1358 break;
1359 }
1360 if (!current_templates)
1361 {
1362 as_bad (_("no such instruction: `%s'"), token_start);
1363 return;
1364 }
1365 }
1366
1367 /* Check if instruction is supported on specified architecture. */
1368 if (cpu_arch_flags != 0)
1369 {
1370 if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
1371 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
1372 {
1373 as_warn (_("`%s' is not supported on `%s'"),
1374 current_templates->start->name, cpu_arch_name);
1375 }
1376 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1377 {
1378 as_warn (_("use .code16 to ensure correct addressing mode"));
1379 }
1380 }
1381
1382 /* Check for rep/repne without a string instruction. */
1383 if (expecting_string_instruction
1384 && !(current_templates->start->opcode_modifier & IsString))
1385 {
1386 as_bad (_("expecting string instruction after `%s'"),
1387 expecting_string_instruction);
1388 return;
1389 }
1390
1391 /* There may be operands to parse. */
1392 if (*l != END_OF_INSN)
1393 {
1394 /* 1 if operand is pending after ','. */
1395 unsigned int expecting_operand = 0;
1396
1397 /* Non-zero if operand parens not balanced. */
1398 unsigned int paren_not_balanced;
1399
1400 do
1401 {
1402 /* Skip optional white space before operand. */
1403 if (is_space_char (*l))
1404 ++l;
1405 if (!is_operand_char (*l) && *l != END_OF_INSN)
1406 {
1407 as_bad (_("invalid character %s before operand %d"),
1408 output_invalid (*l),
1409 i.operands + 1);
1410 return;
1411 }
1412 token_start = l; /* after white space */
1413 paren_not_balanced = 0;
1414 while (paren_not_balanced || *l != ',')
1415 {
1416 if (*l == END_OF_INSN)
1417 {
1418 if (paren_not_balanced)
1419 {
1420 if (!intel_syntax)
1421 as_bad (_("unbalanced parenthesis in operand %d."),
1422 i.operands + 1);
1423 else
1424 as_bad (_("unbalanced brackets in operand %d."),
1425 i.operands + 1);
1426 return;
1427 }
1428 else
1429 break; /* we are done */
1430 }
1431 else if (!is_operand_char (*l) && !is_space_char (*l))
1432 {
1433 as_bad (_("invalid character %s in operand %d"),
1434 output_invalid (*l),
1435 i.operands + 1);
1436 return;
1437 }
1438 if (!intel_syntax)
1439 {
1440 if (*l == '(')
1441 ++paren_not_balanced;
1442 if (*l == ')')
1443 --paren_not_balanced;
1444 }
1445 else
1446 {
1447 if (*l == '[')
1448 ++paren_not_balanced;
1449 if (*l == ']')
1450 --paren_not_balanced;
1451 }
1452 l++;
1453 }
1454 if (l != token_start)
1455 { /* Yes, we've read in another operand. */
1456 unsigned int operand_ok;
1457 this_operand = i.operands++;
1458 if (i.operands > MAX_OPERANDS)
1459 {
1460 as_bad (_("spurious operands; (%d operands/instruction max)"),
1461 MAX_OPERANDS);
1462 return;
1463 }
1464 /* Now parse operand adding info to 'i' as we go along. */
1465 END_STRING_AND_SAVE (l);
1466
1467 if (intel_syntax)
1468 operand_ok =
1469 i386_intel_operand (token_start,
1470 intel_float_operand (mnemonic));
1471 else
1472 operand_ok = i386_operand (token_start);
1473
1474 RESTORE_END_STRING (l);
1475 if (!operand_ok)
1476 return;
1477 }
1478 else
1479 {
1480 if (expecting_operand)
1481 {
1482 expecting_operand_after_comma:
1483 as_bad (_("expecting operand after ','; got nothing"));
1484 return;
1485 }
1486 if (*l == ',')
1487 {
1488 as_bad (_("expecting operand before ','; got nothing"));
1489 return;
1490 }
1491 }
1492
1493 /* Now *l must be either ',' or END_OF_INSN. */
1494 if (*l == ',')
1495 {
1496 if (*++l == END_OF_INSN)
1497 {
1498 /* Just skip it, if it's \n complain. */
1499 goto expecting_operand_after_comma;
1500 }
1501 expecting_operand = 1;
1502 }
1503 }
1504 while (*l != END_OF_INSN);
1505 }
1506 }
1507
1508 /* Now we've parsed the mnemonic into a set of templates, and have the
1509 operands at hand.
1510
1511 Next, we find a template that matches the given insn,
1512 making sure the overlap of the given operands types is consistent
1513 with the template operand types. */
1514
1515#define MATCH(overlap, given, template) \
1516 ((overlap & ~JumpAbsolute) \
1517 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1518
1519 /* If given types r0 and r1 are registers they must be of the same type
1520 unless the expected operand type register overlap is null.
1521 Note that Acc in a template matches every size of reg. */
1522#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1523 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1524 ((g0) & Reg) == ((g1) & Reg) || \
1525 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1526
1527 {
1528 register unsigned int overlap0, overlap1;
1529 unsigned int overlap2;
1530 unsigned int found_reverse_match;
1531 int suffix_check;
1532
1533 /* All intel opcodes have reversed operands except for "bound" and
1534 "enter". We also don't reverse intersegment "jmp" and "call"
1535 instructions with 2 immediate operands so that the immediate segment
1536 precedes the offset, as it does when in AT&T mode. "enter" and the
1537 intersegment "jmp" and "call" instructions are the only ones that
1538 have two immediate operands. */
1539 if (intel_syntax && i.operands > 1
1540 && (strcmp (mnemonic, "bound") != 0)
1541 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1542 {
1543 union i386_op temp_op;
1544 unsigned int temp_type;
1545 RELOC_ENUM temp_reloc;
1546 int xchg1 = 0;
1547 int xchg2 = 0;
1548
1549 if (i.operands == 2)
1550 {
1551 xchg1 = 0;
1552 xchg2 = 1;
1553 }
1554 else if (i.operands == 3)
1555 {
1556 xchg1 = 0;
1557 xchg2 = 2;
1558 }
1559 temp_type = i.types[xchg2];
1560 i.types[xchg2] = i.types[xchg1];
1561 i.types[xchg1] = temp_type;
1562 temp_op = i.op[xchg2];
1563 i.op[xchg2] = i.op[xchg1];
1564 i.op[xchg1] = temp_op;
1565 temp_reloc = i.reloc[xchg2];
1566 i.reloc[xchg2] = i.reloc[xchg1];
1567 i.reloc[xchg1] = temp_reloc;
1568
1569 if (i.mem_operands == 2)
1570 {
1571 const seg_entry *temp_seg;
1572 temp_seg = i.seg[0];
1573 i.seg[0] = i.seg[1];
1574 i.seg[1] = temp_seg;
1575 }
1576 }
1577
1578 if (i.imm_operands)
1579 {
1580 /* Try to ensure constant immediates are represented in the smallest
1581 opcode possible. */
1582 char guess_suffix = 0;
1583 int op;
1584
1585 if (i.suffix)
1586 guess_suffix = i.suffix;
1587 else if (i.reg_operands)
1588 {
1589 /* Figure out a suffix from the last register operand specified.
1590 We can't do this properly yet, ie. excluding InOutPortReg,
1591 but the following works for instructions with immediates.
1592 In any case, we can't set i.suffix yet. */
1593 for (op = i.operands; --op >= 0;)
1594 if (i.types[op] & Reg)
1595 {
1596 if (i.types[op] & Reg8)
1597 guess_suffix = BYTE_MNEM_SUFFIX;
1598 else if (i.types[op] & Reg16)
1599 guess_suffix = WORD_MNEM_SUFFIX;
1600 else if (i.types[op] & Reg32)
1601 guess_suffix = LONG_MNEM_SUFFIX;
1602 else if (i.types[op] & Reg64)
1603 guess_suffix = QWORD_MNEM_SUFFIX;
1604 break;
1605 }
1606 }
1607 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1608 guess_suffix = WORD_MNEM_SUFFIX;
1609
1610 for (op = i.operands; --op >= 0;)
1611 if (i.types[op] & Imm)
1612 {
1613 switch (i.op[op].imms->X_op)
1614 {
1615 case O_constant:
1616 /* If a suffix is given, this operand may be shortened. */
1617 switch (guess_suffix)
1618 {
1619 case LONG_MNEM_SUFFIX:
1620 i.types[op] |= Imm32 | Imm64;
1621 break;
1622 case WORD_MNEM_SUFFIX:
1623 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1624 break;
1625 case BYTE_MNEM_SUFFIX:
1626 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
1627 break;
1628 }
1629
1630 /* If this operand is at most 16 bits, convert it
1631 to a signed 16 bit number before trying to see
1632 whether it will fit in an even smaller size.
1633 This allows a 16-bit operand such as $0xffe0 to
1634 be recognised as within Imm8S range. */
1635 if ((i.types[op] & Imm16)
1636 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
1637 {
1638 i.op[op].imms->X_add_number =
1639 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
1640 }
1641 if ((i.types[op] & Imm32)
1642 && (i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) == 0)
1643 {
1644 i.op[op].imms->X_add_number =
1645 (i.op[op].imms->X_add_number ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
1646 }
1647 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
1648 /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
1649 if (guess_suffix == QWORD_MNEM_SUFFIX)
1650 i.types[op] &= ~Imm32;
1651 break;
1652 case O_absent:
1653 case O_register:
1654 abort ();
1655 /* Symbols and expressions. */
1656 default:
1657 /* Convert symbolic operand to proper sizes for matching. */
1658 switch (guess_suffix)
1659 {
1660 case QWORD_MNEM_SUFFIX:
1661 i.types[op] = Imm64 | Imm32S;
1662 break;
1663 case LONG_MNEM_SUFFIX:
1664 i.types[op] = Imm32 | Imm64;
1665 break;
1666 case WORD_MNEM_SUFFIX:
1667 i.types[op] = Imm16 | Imm32 | Imm64;
1668 break;
1669 break;
1670 case BYTE_MNEM_SUFFIX:
1671 i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32;
1672 break;
1673 break;
1674 }
1675 break;
1676 }
1677 }
1678 }
1679
1680 if (i.disp_operands)
1681 {
1682 /* Try to use the smallest displacement type too. */
1683 int op;
1684
1685 for (op = i.operands; --op >= 0;)
1686 if ((i.types[op] & Disp)
1687 && i.op[op].disps->X_op == O_constant)
1688 {
1689 offsetT disp = i.op[op].disps->X_add_number;
1690
1691 if (i.types[op] & Disp16)
1692 {
1693 /* We know this operand is at most 16 bits, so
1694 convert to a signed 16 bit number before trying
1695 to see whether it will fit in an even smaller
1696 size. */
1697
1698 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
1699 }
1700 else if (i.types[op] & Disp32)
1701 {
1702 /* We know this operand is at most 32 bits, so convert to a
1703 signed 32 bit number before trying to see whether it will
1704 fit in an even smaller size. */
1705 disp &= (((offsetT) 2 << 31) - 1);
1706 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
1707 }
1708 if (flag_code == CODE_64BIT)
1709 {
1710 if (fits_in_signed_long (disp))
1711 i.types[op] |= Disp32S;
1712 if (fits_in_unsigned_long (disp))
1713 i.types[op] |= Disp32;
1714 }
1715 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
1716 && fits_in_signed_byte (disp))
1717 i.types[op] |= Disp8;
1718 }
1719 }
1720
1721 overlap0 = 0;
1722 overlap1 = 0;
1723 overlap2 = 0;
1724 found_reverse_match = 0;
1725 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
1726 ? No_bSuf
1727 : (i.suffix == WORD_MNEM_SUFFIX
1728 ? No_wSuf
1729 : (i.suffix == SHORT_MNEM_SUFFIX
1730 ? No_sSuf
1731 : (i.suffix == LONG_MNEM_SUFFIX
1732 ? No_lSuf
1733 : (i.suffix == QWORD_MNEM_SUFFIX
1734 ? No_qSuf
1735 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX ? No_xSuf : 0))))));
1736
1737 for (t = current_templates->start;
1738 t < current_templates->end;
1739 t++)
1740 {
1741 /* Must have right number of operands. */
1742 if (i.operands != t->operands)
1743 continue;
1744
1745 /* Check the suffix, except for some instructions in intel mode. */
1746 if ((t->opcode_modifier & suffix_check)
1747 && !(intel_syntax
1748 && (t->opcode_modifier & IgnoreSize))
1749 && !(intel_syntax
1750 && t->base_opcode == 0xd9
1751 && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */
1752 || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */
1753 continue;
1754
1755 /* Do not verify operands when there are none. */
1756 else if (!t->operands)
1757 {
1758 if (t->cpu_flags & ~cpu_arch_flags)
1759 continue;
1760 /* We've found a match; break out of loop. */
1761 break;
1762 }
1763
1764 overlap0 = i.types[0] & t->operand_types[0];
1765 switch (t->operands)
1766 {
1767 case 1:
1768 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
1769 continue;
1770 break;
1771 case 2:
1772 case 3:
1773 overlap1 = i.types[1] & t->operand_types[1];
1774 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
1775 || !MATCH (overlap1, i.types[1], t->operand_types[1])
1776 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
1777 t->operand_types[0],
1778 overlap1, i.types[1],
1779 t->operand_types[1]))
1780 {
1781 /* Check if other direction is valid ... */
1782 if ((t->opcode_modifier & (D|FloatD)) == 0)
1783 continue;
1784
1785 /* Try reversing direction of operands. */
1786 overlap0 = i.types[0] & t->operand_types[1];
1787 overlap1 = i.types[1] & t->operand_types[0];
1788 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
1789 || !MATCH (overlap1, i.types[1], t->operand_types[0])
1790 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
1791 t->operand_types[1],
1792 overlap1, i.types[1],
1793 t->operand_types[0]))
1794 {
1795 /* Does not match either direction. */
1796 continue;
1797 }
1798 /* found_reverse_match holds which of D or FloatDR
1799 we've found. */
1800 found_reverse_match = t->opcode_modifier & (D|FloatDR);
1801 }
1802 /* Found a forward 2 operand match here. */
1803 else if (t->operands == 3)
1804 {
1805 /* Here we make use of the fact that there are no
1806 reverse match 3 operand instructions, and all 3
1807 operand instructions only need to be checked for
1808 register consistency between operands 2 and 3. */
1809 overlap2 = i.types[2] & t->operand_types[2];
1810 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
1811 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
1812 t->operand_types[1],
1813 overlap2, i.types[2],
1814 t->operand_types[2]))
1815
1816 continue;
1817 }
1818 /* Found either forward/reverse 2 or 3 operand match here:
1819 slip through to break. */
1820 }
1821 if (t->cpu_flags & ~cpu_arch_flags)
1822 {
1823 found_reverse_match = 0;
1824 continue;
1825 }
1826 /* We've found a match; break out of loop. */
1827 break;
1828 }
1829 if (t == current_templates->end)
1830 {
1831 /* We found no match. */
1832 as_bad (_("suffix or operands invalid for `%s'"),
1833 current_templates->start->name);
1834 return;
1835 }
1836
1837 if (!quiet_warnings)
1838 {
1839 if (!intel_syntax
1840 && ((i.types[0] & JumpAbsolute)
1841 != (t->operand_types[0] & JumpAbsolute)))
1842 {
1843 as_warn (_("indirect %s without `*'"), t->name);
1844 }
1845
1846 if ((t->opcode_modifier & (IsPrefix|IgnoreSize))
1847 == (IsPrefix|IgnoreSize))
1848 {
1849 /* Warn them that a data or address size prefix doesn't
1850 affect assembly of the next line of code. */
1851 as_warn (_("stand-alone `%s' prefix"), t->name);
1852 }
1853 }
1854
1855 /* Copy the template we found. */
1856 i.tm = *t;
1857 if (found_reverse_match)
1858 {
1859 /* If we found a reverse match we must alter the opcode
1860 direction bit. found_reverse_match holds bits to change
1861 (different for int & float insns). */
1862
1863 i.tm.base_opcode ^= found_reverse_match;
1864
1865 i.tm.operand_types[0] = t->operand_types[1];
1866 i.tm.operand_types[1] = t->operand_types[0];
1867 }
1868
1869 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1870 if (SYSV386_COMPAT
1871 && intel_syntax
1872 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1873 i.tm.base_opcode ^= FloatR;
1874
1875 if (i.tm.opcode_modifier & FWait)
1876 if (! add_prefix (FWAIT_OPCODE))
1877 return;
1878
1879 /* Check string instruction segment overrides. */
1880 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1881 {
1882 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
1883 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
1884 {
1885 if (i.seg[0] != NULL && i.seg[0] != &es)
1886 {
1887 as_bad (_("`%s' operand %d must use `%%es' segment"),
1888 i.tm.name,
1889 mem_op + 1);
1890 return;
1891 }
1892 /* There's only ever one segment override allowed per instruction.
1893 This instruction possibly has a legal segment override on the
1894 second operand, so copy the segment to where non-string
1895 instructions store it, allowing common code. */
1896 i.seg[0] = i.seg[1];
1897 }
1898 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
1899 {
1900 if (i.seg[1] != NULL && i.seg[1] != &es)
1901 {
1902 as_bad (_("`%s' operand %d must use `%%es' segment"),
1903 i.tm.name,
1904 mem_op + 2);
1905 return;
1906 }
1907 }
1908 }
1909
| 25
26
27/* Intel 80386 machine specific gas.
28 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
29 x86_64 support by Jan Hubicka (jh@suse.cz)
30 Bugs & suggestions are completely welcome. This is free software.
31 Please help us make it better. */
32
33#include <ctype.h>
34
35#include "as.h"
36#include "subsegs.h"
37#include "dwarf2dbg.h"
38#include "opcode/i386.h"
39
40#ifndef REGISTER_WARNINGS
41#define REGISTER_WARNINGS 1
42#endif
43
44#ifndef INFER_ADDR_PREFIX
45#define INFER_ADDR_PREFIX 1
46#endif
47
48#ifndef SCALE1_WHEN_NO_INDEX
49/* Specifying a scale factor besides 1 when there is no index is
50 futile. eg. `mov (%ebx,2),%al' does exactly the same as
51 `mov (%ebx),%al'. To slavishly follow what the programmer
52 specified, set SCALE1_WHEN_NO_INDEX to 0. */
53#define SCALE1_WHEN_NO_INDEX 1
54#endif
55
56#define true 1
57#define false 0
58
59static unsigned int mode_from_disp_size PARAMS ((unsigned int));
60static int fits_in_signed_byte PARAMS ((offsetT));
61static int fits_in_unsigned_byte PARAMS ((offsetT));
62static int fits_in_unsigned_word PARAMS ((offsetT));
63static int fits_in_signed_word PARAMS ((offsetT));
64static int fits_in_unsigned_long PARAMS ((offsetT));
65static int fits_in_signed_long PARAMS ((offsetT));
66static int smallest_imm_type PARAMS ((offsetT));
67static offsetT offset_in_range PARAMS ((offsetT, int));
68static int add_prefix PARAMS ((unsigned int));
69static void set_code_flag PARAMS ((int));
70static void set_16bit_gcc_code_flag PARAMS ((int));
71static void set_intel_syntax PARAMS ((int));
72static void set_cpu_arch PARAMS ((int));
73
74#ifdef BFD_ASSEMBLER
75static bfd_reloc_code_real_type reloc
76 PARAMS ((int, int, int, bfd_reloc_code_real_type));
77#define RELOC_ENUM enum bfd_reloc_code_real
78#else
79#define RELOC_ENUM int
80#endif
81
82#ifndef DEFAULT_ARCH
83#define DEFAULT_ARCH "i386"
84#endif
85static char *default_arch = DEFAULT_ARCH;
86
87/* 'md_assemble ()' gathers together information and puts it into a
88 i386_insn. */
89
90union i386_op
91 {
92 expressionS *disps;
93 expressionS *imms;
94 const reg_entry *regs;
95 };
96
97struct _i386_insn
98 {
99 /* TM holds the template for the insn were currently assembling. */
100 template tm;
101
102 /* SUFFIX holds the instruction mnemonic suffix if given.
103 (e.g. 'l' for 'movl') */
104 char suffix;
105
106 /* OPERANDS gives the number of given operands. */
107 unsigned int operands;
108
109 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
110 of given register, displacement, memory operands and immediate
111 operands. */
112 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
113
114 /* TYPES [i] is the type (see above #defines) which tells us how to
115 use OP[i] for the corresponding operand. */
116 unsigned int types[MAX_OPERANDS];
117
118 /* Displacement expression, immediate expression, or register for each
119 operand. */
120 union i386_op op[MAX_OPERANDS];
121
122 /* Flags for operands. */
123 unsigned int flags[MAX_OPERANDS];
124#define Operand_PCrel 1
125
126 /* Relocation type for operand */
127 RELOC_ENUM reloc[MAX_OPERANDS];
128
129 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
130 the base index byte below. */
131 const reg_entry *base_reg;
132 const reg_entry *index_reg;
133 unsigned int log2_scale_factor;
134
135 /* SEG gives the seg_entries of this insn. They are zero unless
136 explicit segment overrides are given. */
137 const seg_entry *seg[2];
138
139 /* PREFIX holds all the given prefix opcodes (usually null).
140 PREFIXES is the number of prefix opcodes. */
141 unsigned int prefixes;
142 unsigned char prefix[MAX_PREFIXES];
143
144 /* RM and SIB are the modrm byte and the sib byte where the
145 addressing modes of this insn are encoded. */
146
147 modrm_byte rm;
148 rex_byte rex;
149 sib_byte sib;
150 };
151
152typedef struct _i386_insn i386_insn;
153
154/* List of chars besides those in app.c:symbol_chars that can start an
155 operand. Used to prevent the scrubber eating vital white-space. */
156#ifdef LEX_AT
157const char extra_symbol_chars[] = "*%-(@";
158#else
159const char extra_symbol_chars[] = "*%-(";
160#endif
161
162/* This array holds the chars that always start a comment. If the
163 pre-processor is disabled, these aren't very useful. */
164#if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
165/* Putting '/' here makes it impossible to use the divide operator.
166 However, we need it for compatibility with SVR4 systems. */
167const char comment_chars[] = "#/";
168#define PREFIX_SEPARATOR '\\'
169#else
170const char comment_chars[] = "#";
171#define PREFIX_SEPARATOR '/'
172#endif
173
174/* This array holds the chars that only start a comment at the beginning of
175 a line. If the line seems to have the form '# 123 filename'
176 .line and .file directives will appear in the pre-processed output.
177 Note that input_file.c hand checks for '#' at the beginning of the
178 first line of the input file. This is because the compiler outputs
179 #NO_APP at the beginning of its output.
180 Also note that comments started like this one will always work if
181 '/' isn't otherwise defined. */
182#if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
183const char line_comment_chars[] = "";
184#else
185const char line_comment_chars[] = "/";
186#endif
187
188const char line_separator_chars[] = ";";
189
190/* Chars that can be used to separate mant from exp in floating point
191 nums. */
192const char EXP_CHARS[] = "eE";
193
194/* Chars that mean this number is a floating point constant
195 As in 0f12.456
196 or 0d1.2345e12. */
197const char FLT_CHARS[] = "fFdDxX";
198
199/* Tables for lexical analysis. */
200static char mnemonic_chars[256];
201static char register_chars[256];
202static char operand_chars[256];
203static char identifier_chars[256];
204static char digit_chars[256];
205
206/* Lexical macros. */
207#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
208#define is_operand_char(x) (operand_chars[(unsigned char) x])
209#define is_register_char(x) (register_chars[(unsigned char) x])
210#define is_space_char(x) ((x) == ' ')
211#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
212#define is_digit_char(x) (digit_chars[(unsigned char) x])
213
214/* All non-digit non-letter charcters that may occur in an operand. */
215static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
216
217/* md_assemble() always leaves the strings it's passed unaltered. To
218 effect this we maintain a stack of saved characters that we've smashed
219 with '\0's (indicating end of strings for various sub-fields of the
220 assembler instruction). */
221static char save_stack[32];
222static char *save_stack_p;
223#define END_STRING_AND_SAVE(s) \
224 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
225#define RESTORE_END_STRING(s) \
226 do { *(s) = *--save_stack_p; } while (0)
227
228/* The instruction we're assembling. */
229static i386_insn i;
230
231/* Possible templates for current insn. */
232static const templates *current_templates;
233
234/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
235static expressionS disp_expressions[2], im_expressions[2];
236
237/* Current operand we are working on. */
238static int this_operand;
239
240/* We support four different modes. FLAG_CODE variable is used to distinguish
241 these. */
242
243enum flag_code {
244 CODE_32BIT,
245 CODE_16BIT,
246 CODE_64BIT };
247#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
248
249static enum flag_code flag_code;
250static int use_rela_relocations = 0;
251
252/* The names used to print error messages. */
253static const char *flag_code_names[] =
254 {
255 "32",
256 "16",
257 "64"
258 };
259
260/* 1 for intel syntax,
261 0 if att syntax. */
262static int intel_syntax = 0;
263
264/* 1 if register prefix % not required. */
265static int allow_naked_reg = 0;
266
267/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
268 leave, push, and pop instructions so that gcc has the same stack
269 frame as in 32 bit mode. */
270static char stackop_size = '\0';
271
272/* Non-zero to quieten some warnings. */
273static int quiet_warnings = 0;
274
275/* CPU name. */
276static const char *cpu_arch_name = NULL;
277
278/* CPU feature flags. */
279static unsigned int cpu_arch_flags = CpuUnknownFlags|CpuNo64;
280
281/* If set, conditional jumps are not automatically promoted to handle
282 larger than a byte offset. */
283static unsigned int no_cond_jump_promotion = 0;
284
285/* Interface to relax_segment.
286 There are 3 major relax states for 386 jump insns because the
287 different types of jumps add different sizes to frags when we're
288 figuring out what sort of jump to choose to reach a given label. */
289
290/* Types. */
291#define UNCOND_JUMP 0
292#define COND_JUMP 1
293#define COND_JUMP86 2
294
295/* Sizes. */
296#define CODE16 1
297#define SMALL 0
298#define SMALL16 (SMALL|CODE16)
299#define BIG 2
300#define BIG16 (BIG|CODE16)
301
302#ifndef INLINE
303#ifdef __GNUC__
304#define INLINE __inline__
305#else
306#define INLINE
307#endif
308#endif
309
310#define ENCODE_RELAX_STATE(type, size) \
311 ((relax_substateT) (((type) << 2) | (size)))
312#define TYPE_FROM_RELAX_STATE(s) \
313 ((s) >> 2)
314#define DISP_SIZE_FROM_RELAX_STATE(s) \
315 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
316
317/* This table is used by relax_frag to promote short jumps to long
318 ones where necessary. SMALL (short) jumps may be promoted to BIG
319 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
320 don't allow a short jump in a 32 bit code segment to be promoted to
321 a 16 bit offset jump because it's slower (requires data size
322 prefix), and doesn't work, unless the destination is in the bottom
323 64k of the code segment (The top 16 bits of eip are zeroed). */
324
325const relax_typeS md_relax_table[] =
326{
327 /* The fields are:
328 1) most positive reach of this state,
329 2) most negative reach of this state,
330 3) how many bytes this mode will have in the variable part of the frag
331 4) which index into the table to try if we can't fit into this one. */
332
333 /* UNCOND_JUMP states. */
334 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
335 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
336 /* dword jmp adds 4 bytes to frag:
337 0 extra opcode bytes, 4 displacement bytes. */
338 {0, 0, 4, 0},
339 /* word jmp adds 2 byte2 to frag:
340 0 extra opcode bytes, 2 displacement bytes. */
341 {0, 0, 2, 0},
342
343 /* COND_JUMP states. */
344 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
345 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
346 /* dword conditionals adds 5 bytes to frag:
347 1 extra opcode byte, 4 displacement bytes. */
348 {0, 0, 5, 0},
349 /* word conditionals add 3 bytes to frag:
350 1 extra opcode byte, 2 displacement bytes. */
351 {0, 0, 3, 0},
352
353 /* COND_JUMP86 states. */
354 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
355 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
356 /* dword conditionals adds 5 bytes to frag:
357 1 extra opcode byte, 4 displacement bytes. */
358 {0, 0, 5, 0},
359 /* word conditionals add 4 bytes to frag:
360 1 displacement byte and a 3 byte long branch insn. */
361 {0, 0, 4, 0}
362};
363
364static const arch_entry cpu_arch[] = {
365 {"i8086", Cpu086 },
366 {"i186", Cpu086|Cpu186 },
367 {"i286", Cpu086|Cpu186|Cpu286 },
368 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
369 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
370 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
371 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
372 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
373 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
374 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
375 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
376 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
377 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
378 {NULL, 0 }
379};
380
381void
382i386_align_code (fragP, count)
383 fragS *fragP;
384 int count;
385{
386 /* Various efficient no-op patterns for aligning code labels.
387 Note: Don't try to assemble the instructions in the comments.
388 0L and 0w are not legal. */
389 static const char f32_1[] =
390 {0x90}; /* nop */
391 static const char f32_2[] =
392 {0x89,0xf6}; /* movl %esi,%esi */
393 static const char f32_3[] =
394 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
395 static const char f32_4[] =
396 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
397 static const char f32_5[] =
398 {0x90, /* nop */
399 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
400 static const char f32_6[] =
401 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
402 static const char f32_7[] =
403 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
404 static const char f32_8[] =
405 {0x90, /* nop */
406 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
407 static const char f32_9[] =
408 {0x89,0xf6, /* movl %esi,%esi */
409 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
410 static const char f32_10[] =
411 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
412 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
413 static const char f32_11[] =
414 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
415 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
416 static const char f32_12[] =
417 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
418 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
419 static const char f32_13[] =
420 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
421 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
422 static const char f32_14[] =
423 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
424 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
425 static const char f32_15[] =
426 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
427 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
428 static const char f16_3[] =
429 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
430 static const char f16_4[] =
431 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
432 static const char f16_5[] =
433 {0x90, /* nop */
434 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
435 static const char f16_6[] =
436 {0x89,0xf6, /* mov %si,%si */
437 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
438 static const char f16_7[] =
439 {0x8d,0x74,0x00, /* lea 0(%si),%si */
440 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
441 static const char f16_8[] =
442 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
443 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
444 static const char *const f32_patt[] = {
445 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
446 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
447 };
448 static const char *const f16_patt[] = {
449 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
450 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
451 };
452
453 /* ??? We can't use these fillers for x86_64, since they often kills the
454 upper halves. Solve later. */
455 if (flag_code == CODE_64BIT)
456 count = 1;
457
458 if (count > 0 && count <= 15)
459 {
460 if (flag_code == CODE_16BIT)
461 {
462 memcpy (fragP->fr_literal + fragP->fr_fix,
463 f16_patt[count - 1], count);
464 if (count > 8)
465 /* Adjust jump offset. */
466 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
467 }
468 else
469 memcpy (fragP->fr_literal + fragP->fr_fix,
470 f32_patt[count - 1], count);
471 fragP->fr_var = count;
472 }
473}
474
475static char *output_invalid PARAMS ((int c));
476static int i386_operand PARAMS ((char *operand_string));
477static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
478static const reg_entry *parse_register PARAMS ((char *reg_string,
479 char **end_op));
480
481#ifndef I386COFF
482static void s_bss PARAMS ((int));
483#endif
484
485symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
486
487static INLINE unsigned int
488mode_from_disp_size (t)
489 unsigned int t;
490{
491 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
492}
493
494static INLINE int
495fits_in_signed_byte (num)
496 offsetT num;
497{
498 return (num >= -128) && (num <= 127);
499}
500
501static INLINE int
502fits_in_unsigned_byte (num)
503 offsetT num;
504{
505 return (num & 0xff) == num;
506}
507
508static INLINE int
509fits_in_unsigned_word (num)
510 offsetT num;
511{
512 return (num & 0xffff) == num;
513}
514
515static INLINE int
516fits_in_signed_word (num)
517 offsetT num;
518{
519 return (-32768 <= num) && (num <= 32767);
520}
521static INLINE int
522fits_in_signed_long (num)
523 offsetT num ATTRIBUTE_UNUSED;
524{
525#ifndef BFD64
526 return 1;
527#else
528 return (!(((offsetT) -1 << 31) & num)
529 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
530#endif
531} /* fits_in_signed_long() */
532static INLINE int
533fits_in_unsigned_long (num)
534 offsetT num ATTRIBUTE_UNUSED;
535{
536#ifndef BFD64
537 return 1;
538#else
539 return (num & (((offsetT) 2 << 31) - 1)) == num;
540#endif
541} /* fits_in_unsigned_long() */
542
543static int
544smallest_imm_type (num)
545 offsetT num;
546{
547 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64)
548 && !(cpu_arch_flags & (CpuUnknown)))
549 {
550 /* This code is disabled on the 486 because all the Imm1 forms
551 in the opcode table are slower on the i486. They're the
552 versions with the implicitly specified single-position
553 displacement, which has another syntax if you really want to
554 use that form. */
555 if (num == 1)
556 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
557 }
558 return (fits_in_signed_byte (num)
559 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
560 : fits_in_unsigned_byte (num)
561 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
562 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
563 ? (Imm16 | Imm32 | Imm32S | Imm64)
564 : fits_in_signed_long (num)
565 ? (Imm32 | Imm32S | Imm64)
566 : fits_in_unsigned_long (num)
567 ? (Imm32 | Imm64)
568 : Imm64);
569}
570
571static offsetT
572offset_in_range (val, size)
573 offsetT val;
574 int size;
575{
576 addressT mask;
577
578 switch (size)
579 {
580 case 1: mask = ((addressT) 1 << 8) - 1; break;
581 case 2: mask = ((addressT) 1 << 16) - 1; break;
582 case 4: mask = ((addressT) 2 << 31) - 1; break;
583#ifdef BFD64
584 case 8: mask = ((addressT) 2 << 63) - 1; break;
585#endif
586 default: abort ();
587 }
588
589 /* If BFD64, sign extend val. */
590 if (!use_rela_relocations)
591 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
592 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
593
594 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
595 {
596 char buf1[40], buf2[40];
597
598 sprint_value (buf1, val);
599 sprint_value (buf2, val & mask);
600 as_warn (_("%s shortened to %s"), buf1, buf2);
601 }
602 return val & mask;
603}
604
605/* Returns 0 if attempting to add a prefix where one from the same
606 class already exists, 1 if non rep/repne added, 2 if rep/repne
607 added. */
608static int
609add_prefix (prefix)
610 unsigned int prefix;
611{
612 int ret = 1;
613 int q;
614
615 if (prefix >= 0x40 && prefix < 0x50 && flag_code == CODE_64BIT)
616 q = REX_PREFIX;
617 else
618 switch (prefix)
619 {
620 default:
621 abort ();
622
623 case CS_PREFIX_OPCODE:
624 case DS_PREFIX_OPCODE:
625 case ES_PREFIX_OPCODE:
626 case FS_PREFIX_OPCODE:
627 case GS_PREFIX_OPCODE:
628 case SS_PREFIX_OPCODE:
629 q = SEG_PREFIX;
630 break;
631
632 case REPNE_PREFIX_OPCODE:
633 case REPE_PREFIX_OPCODE:
634 ret = 2;
635 /* fall thru */
636 case LOCK_PREFIX_OPCODE:
637 q = LOCKREP_PREFIX;
638 break;
639
640 case FWAIT_OPCODE:
641 q = WAIT_PREFIX;
642 break;
643
644 case ADDR_PREFIX_OPCODE:
645 q = ADDR_PREFIX;
646 break;
647
648 case DATA_PREFIX_OPCODE:
649 q = DATA_PREFIX;
650 break;
651 }
652
653 if (i.prefix[q])
654 {
655 as_bad (_("same type of prefix used twice"));
656 return 0;
657 }
658
659 i.prefixes += 1;
660 i.prefix[q] = prefix;
661 return ret;
662}
663
664static void
665set_code_flag (value)
666 int value;
667{
668 flag_code = value;
669 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
670 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
671 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
672 {
673 as_bad (_("64bit mode not supported on this CPU."));
674 }
675 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
676 {
677 as_bad (_("32bit mode not supported on this CPU."));
678 }
679 stackop_size = '\0';
680}
681
682static void
683set_16bit_gcc_code_flag (new_code_flag)
684 int new_code_flag;
685{
686 flag_code = new_code_flag;
687 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
688 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
689 stackop_size = 'l';
690}
691
692static void
693set_intel_syntax (syntax_flag)
694 int syntax_flag;
695{
696 /* Find out if register prefixing is specified. */
697 int ask_naked_reg = 0;
698
699 SKIP_WHITESPACE ();
700 if (! is_end_of_line[(unsigned char) *input_line_pointer])
701 {
702 char *string = input_line_pointer;
703 int e = get_symbol_end ();
704
705 if (strcmp (string, "prefix") == 0)
706 ask_naked_reg = 1;
707 else if (strcmp (string, "noprefix") == 0)
708 ask_naked_reg = -1;
709 else
710 as_bad (_("bad argument to syntax directive."));
711 *input_line_pointer = e;
712 }
713 demand_empty_rest_of_line ();
714
715 intel_syntax = syntax_flag;
716
717 if (ask_naked_reg == 0)
718 {
719#ifdef BFD_ASSEMBLER
720 allow_naked_reg = (intel_syntax
721 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
722#else
723 /* Conservative default. */
724 allow_naked_reg = 0;
725#endif
726 }
727 else
728 allow_naked_reg = (ask_naked_reg < 0);
729}
730
731static void
732set_cpu_arch (dummy)
733 int dummy ATTRIBUTE_UNUSED;
734{
735 SKIP_WHITESPACE ();
736
737 if (! is_end_of_line[(unsigned char) *input_line_pointer])
738 {
739 char *string = input_line_pointer;
740 int e = get_symbol_end ();
741 int i;
742
743 for (i = 0; cpu_arch[i].name; i++)
744 {
745 if (strcmp (string, cpu_arch[i].name) == 0)
746 {
747 cpu_arch_name = cpu_arch[i].name;
748 cpu_arch_flags = (cpu_arch[i].flags
749 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
750 break;
751 }
752 }
753 if (!cpu_arch[i].name)
754 as_bad (_("no such architecture: `%s'"), string);
755
756 *input_line_pointer = e;
757 }
758 else
759 as_bad (_("missing cpu architecture"));
760
761 no_cond_jump_promotion = 0;
762 if (*input_line_pointer == ','
763 && ! is_end_of_line[(unsigned char) input_line_pointer[1]])
764 {
765 char *string = ++input_line_pointer;
766 int e = get_symbol_end ();
767
768 if (strcmp (string, "nojumps") == 0)
769 no_cond_jump_promotion = 1;
770 else if (strcmp (string, "jumps") == 0)
771 ;
772 else
773 as_bad (_("no such architecture modifier: `%s'"), string);
774
775 *input_line_pointer = e;
776 }
777
778 demand_empty_rest_of_line ();
779}
780
781const pseudo_typeS md_pseudo_table[] =
782{
783#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
784 {"align", s_align_bytes, 0},
785#else
786 {"align", s_align_ptwo, 0},
787#endif
788 {"arch", set_cpu_arch, 0},
789#ifndef I386COFF
790 {"bss", s_bss, 0},
791#endif
792 {"ffloat", float_cons, 'f'},
793 {"dfloat", float_cons, 'd'},
794 {"tfloat", float_cons, 'x'},
795 {"value", cons, 2},
796 {"noopt", s_ignore, 0},
797 {"optim", s_ignore, 0},
798 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
799 {"code16", set_code_flag, CODE_16BIT},
800 {"code32", set_code_flag, CODE_32BIT},
801 {"code64", set_code_flag, CODE_64BIT},
802 {"intel_syntax", set_intel_syntax, 1},
803 {"att_syntax", set_intel_syntax, 0},
804 {"file", dwarf2_directive_file, 0},
805 {"loc", dwarf2_directive_loc, 0},
806 {0, 0, 0}
807};
808
809/* For interface with expression (). */
810extern char *input_line_pointer;
811
812/* Hash table for instruction mnemonic lookup. */
813static struct hash_control *op_hash;
814
815/* Hash table for register lookup. */
816static struct hash_control *reg_hash;
817
818#ifdef BFD_ASSEMBLER
819unsigned long
820i386_mach ()
821{
822 if (!strcmp (default_arch, "x86_64"))
823 return bfd_mach_x86_64;
824 else if (!strcmp (default_arch, "i386"))
825 return bfd_mach_i386_i386;
826 else
827 as_fatal (_("Unknown architecture"));
828}
829#endif
830
831void
832md_begin ()
833{
834 const char *hash_err;
835
836 /* Initialize op_hash hash table. */
837 op_hash = hash_new ();
838
839 {
840 register const template *optab;
841 register templates *core_optab;
842
843 /* Setup for loop. */
844 optab = i386_optab;
845 core_optab = (templates *) xmalloc (sizeof (templates));
846 core_optab->start = optab;
847
848 while (1)
849 {
850 ++optab;
851 if (optab->name == NULL
852 || strcmp (optab->name, (optab - 1)->name) != 0)
853 {
854 /* different name --> ship out current template list;
855 add to hash table; & begin anew. */
856 core_optab->end = optab;
857 hash_err = hash_insert (op_hash,
858 (optab - 1)->name,
859 (PTR) core_optab);
860 if (hash_err)
861 {
862 as_fatal (_("Internal Error: Can't hash %s: %s"),
863 (optab - 1)->name,
864 hash_err);
865 }
866 if (optab->name == NULL)
867 break;
868 core_optab = (templates *) xmalloc (sizeof (templates));
869 core_optab->start = optab;
870 }
871 }
872 }
873
874 /* Initialize reg_hash hash table. */
875 reg_hash = hash_new ();
876 {
877 register const reg_entry *regtab;
878
879 for (regtab = i386_regtab;
880 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
881 regtab++)
882 {
883 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
884 if (hash_err)
885 as_fatal (_("Internal Error: Can't hash %s: %s"),
886 regtab->reg_name,
887 hash_err);
888 }
889 }
890
891 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
892 {
893 register int c;
894 register char *p;
895
896 for (c = 0; c < 256; c++)
897 {
898 if (isdigit (c))
899 {
900 digit_chars[c] = c;
901 mnemonic_chars[c] = c;
902 register_chars[c] = c;
903 operand_chars[c] = c;
904 }
905 else if (islower (c))
906 {
907 mnemonic_chars[c] = c;
908 register_chars[c] = c;
909 operand_chars[c] = c;
910 }
911 else if (isupper (c))
912 {
913 mnemonic_chars[c] = tolower (c);
914 register_chars[c] = mnemonic_chars[c];
915 operand_chars[c] = c;
916 }
917
918 if (isalpha (c) || isdigit (c))
919 identifier_chars[c] = c;
920 else if (c >= 128)
921 {
922 identifier_chars[c] = c;
923 operand_chars[c] = c;
924 }
925 }
926
927#ifdef LEX_AT
928 identifier_chars['@'] = '@';
929#endif
930 digit_chars['-'] = '-';
931 identifier_chars['_'] = '_';
932 identifier_chars['.'] = '.';
933
934 for (p = operand_special_chars; *p != '\0'; p++)
935 operand_chars[(unsigned char) *p] = *p;
936 }
937
938#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
939 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
940 {
941 record_alignment (text_section, 2);
942 record_alignment (data_section, 2);
943 record_alignment (bss_section, 2);
944 }
945#endif
946}
947
948void
949i386_print_statistics (file)
950 FILE *file;
951{
952 hash_print_statistics (file, "i386 opcode", op_hash);
953 hash_print_statistics (file, "i386 register", reg_hash);
954}
955
956#ifdef DEBUG386
957
958/* Debugging routines for md_assemble. */
959static void pi PARAMS ((char *, i386_insn *));
960static void pte PARAMS ((template *));
961static void pt PARAMS ((unsigned int));
962static void pe PARAMS ((expressionS *));
963static void ps PARAMS ((symbolS *));
964
965static void
966pi (line, x)
967 char *line;
968 i386_insn *x;
969{
970 unsigned int i;
971
972 fprintf (stdout, "%s: template ", line);
973 pte (&x->tm);
974 fprintf (stdout, " address: base %s index %s scale %x\n",
975 x->base_reg ? x->base_reg->reg_name : "none",
976 x->index_reg ? x->index_reg->reg_name : "none",
977 x->log2_scale_factor);
978 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
979 x->rm.mode, x->rm.reg, x->rm.regmem);
980 fprintf (stdout, " sib: base %x index %x scale %x\n",
981 x->sib.base, x->sib.index, x->sib.scale);
982 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
983 x->rex.mode64, x->rex.extX, x->rex.extY, x->rex.extZ);
984 for (i = 0; i < x->operands; i++)
985 {
986 fprintf (stdout, " #%d: ", i + 1);
987 pt (x->types[i]);
988 fprintf (stdout, "\n");
989 if (x->types[i]
990 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
991 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
992 if (x->types[i] & Imm)
993 pe (x->op[i].imms);
994 if (x->types[i] & Disp)
995 pe (x->op[i].disps);
996 }
997}
998
999static void
1000pte (t)
1001 template *t;
1002{
1003 unsigned int i;
1004 fprintf (stdout, " %d operands ", t->operands);
1005 fprintf (stdout, "opcode %x ", t->base_opcode);
1006 if (t->extension_opcode != None)
1007 fprintf (stdout, "ext %x ", t->extension_opcode);
1008 if (t->opcode_modifier & D)
1009 fprintf (stdout, "D");
1010 if (t->opcode_modifier & W)
1011 fprintf (stdout, "W");
1012 fprintf (stdout, "\n");
1013 for (i = 0; i < t->operands; i++)
1014 {
1015 fprintf (stdout, " #%d type ", i + 1);
1016 pt (t->operand_types[i]);
1017 fprintf (stdout, "\n");
1018 }
1019}
1020
1021static void
1022pe (e)
1023 expressionS *e;
1024{
1025 fprintf (stdout, " operation %d\n", e->X_op);
1026 fprintf (stdout, " add_number %ld (%lx)\n",
1027 (long) e->X_add_number, (long) e->X_add_number);
1028 if (e->X_add_symbol)
1029 {
1030 fprintf (stdout, " add_symbol ");
1031 ps (e->X_add_symbol);
1032 fprintf (stdout, "\n");
1033 }
1034 if (e->X_op_symbol)
1035 {
1036 fprintf (stdout, " op_symbol ");
1037 ps (e->X_op_symbol);
1038 fprintf (stdout, "\n");
1039 }
1040}
1041
1042static void
1043ps (s)
1044 symbolS *s;
1045{
1046 fprintf (stdout, "%s type %s%s",
1047 S_GET_NAME (s),
1048 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1049 segment_name (S_GET_SEGMENT (s)));
1050}
1051
1052struct type_name
1053 {
1054 unsigned int mask;
1055 char *tname;
1056 }
1057
1058type_names[] =
1059{
1060 { Reg8, "r8" },
1061 { Reg16, "r16" },
1062 { Reg32, "r32" },
1063 { Reg64, "r64" },
1064 { Imm8, "i8" },
1065 { Imm8S, "i8s" },
1066 { Imm16, "i16" },
1067 { Imm32, "i32" },
1068 { Imm32S, "i32s" },
1069 { Imm64, "i64" },
1070 { Imm1, "i1" },
1071 { BaseIndex, "BaseIndex" },
1072 { Disp8, "d8" },
1073 { Disp16, "d16" },
1074 { Disp32, "d32" },
1075 { Disp32S, "d32s" },
1076 { Disp64, "d64" },
1077 { InOutPortReg, "InOutPortReg" },
1078 { ShiftCount, "ShiftCount" },
1079 { Control, "control reg" },
1080 { Test, "test reg" },
1081 { Debug, "debug reg" },
1082 { FloatReg, "FReg" },
1083 { FloatAcc, "FAcc" },
1084 { SReg2, "SReg2" },
1085 { SReg3, "SReg3" },
1086 { Acc, "Acc" },
1087 { JumpAbsolute, "Jump Absolute" },
1088 { RegMMX, "rMMX" },
1089 { RegXMM, "rXMM" },
1090 { EsSeg, "es" },
1091 { 0, "" }
1092};
1093
1094static void
1095pt (t)
1096 unsigned int t;
1097{
1098 register struct type_name *ty;
1099
1100 for (ty = type_names; ty->mask; ty++)
1101 if (t & ty->mask)
1102 fprintf (stdout, "%s, ", ty->tname);
1103 fflush (stdout);
1104}
1105
1106#endif /* DEBUG386 */
1107
1108int
1109tc_i386_force_relocation (fixp)
1110 struct fix *fixp;
1111{
1112#ifdef BFD_ASSEMBLER
1113 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1114 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1115 return 1;
1116 return 0;
1117#else
1118 /* For COFF. */
1119 return fixp->fx_r_type == 7;
1120#endif
1121}
1122
1123#ifdef BFD_ASSEMBLER
1124
1125static bfd_reloc_code_real_type
1126reloc (size, pcrel, sign, other)
1127 int size;
1128 int pcrel;
1129 int sign;
1130 bfd_reloc_code_real_type other;
1131{
1132 if (other != NO_RELOC)
1133 return other;
1134
1135 if (pcrel)
1136 {
1137 if (!sign)
1138 as_bad (_("There are no unsigned pc-relative relocations"));
1139 switch (size)
1140 {
1141 case 1: return BFD_RELOC_8_PCREL;
1142 case 2: return BFD_RELOC_16_PCREL;
1143 case 4: return BFD_RELOC_32_PCREL;
1144 }
1145 as_bad (_("can not do %d byte pc-relative relocation"), size);
1146 }
1147 else
1148 {
1149 if (sign)
1150 switch (size)
1151 {
1152 case 4: return BFD_RELOC_X86_64_32S;
1153 }
1154 else
1155 switch (size)
1156 {
1157 case 1: return BFD_RELOC_8;
1158 case 2: return BFD_RELOC_16;
1159 case 4: return BFD_RELOC_32;
1160 case 8: return BFD_RELOC_64;
1161 }
1162 as_bad (_("can not do %s %d byte relocation"),
1163 sign ? "signed" : "unsigned", size);
1164 }
1165
1166 abort ();
1167 return BFD_RELOC_NONE;
1168}
1169
1170/* Here we decide which fixups can be adjusted to make them relative to
1171 the beginning of the section instead of the symbol. Basically we need
1172 to make sure that the dynamic relocations are done correctly, so in
1173 some cases we force the original symbol to be used. */
1174
1175int
1176tc_i386_fix_adjustable (fixP)
1177 fixS *fixP;
1178{
1179#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1180 /* Prevent all adjustments to global symbols, or else dynamic
1181 linking will not work correctly. */
1182 if (S_IS_EXTERNAL (fixP->fx_addsy)
1183 || S_IS_WEAK (fixP->fx_addsy))
1184 return 0;
1185#endif
1186 /* adjust_reloc_syms doesn't know about the GOT. */
1187 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1188 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1189 || fixP->fx_r_type == BFD_RELOC_386_GOT32
1190 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1191 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
1192 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
1193 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1194 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1195 return 0;
1196 return 1;
1197}
1198#else
1199#define reloc(SIZE,PCREL,SIGN,OTHER) 0
1200#define BFD_RELOC_16 0
1201#define BFD_RELOC_32 0
1202#define BFD_RELOC_16_PCREL 0
1203#define BFD_RELOC_32_PCREL 0
1204#define BFD_RELOC_386_PLT32 0
1205#define BFD_RELOC_386_GOT32 0
1206#define BFD_RELOC_386_GOTOFF 0
1207#define BFD_RELOC_X86_64_PLT32 0
1208#define BFD_RELOC_X86_64_GOT32 0
1209#define BFD_RELOC_X86_64_GOTPCREL 0
1210#endif
1211
1212static int intel_float_operand PARAMS ((char *mnemonic));
1213
1214static int
1215intel_float_operand (mnemonic)
1216 char *mnemonic;
1217{
1218 if (mnemonic[0] == 'f' && mnemonic[1] == 'i')
1219 return 2;
1220
1221 if (mnemonic[0] == 'f')
1222 return 1;
1223
1224 return 0;
1225}
1226
1227/* This is the guts of the machine-dependent assembler. LINE points to a
1228 machine dependent instruction. This function is supposed to emit
1229 the frags/bytes it assembles to. */
1230
1231void
1232md_assemble (line)
1233 char *line;
1234{
1235 /* Points to template once we've found it. */
1236 const template *t;
1237
1238 int j;
1239
1240 char mnemonic[MAX_MNEM_SIZE];
1241
1242 /* Initialize globals. */
1243 memset (&i, '\0', sizeof (i));
1244 for (j = 0; j < MAX_OPERANDS; j++)
1245 i.reloc[j] = NO_RELOC;
1246 memset (disp_expressions, '\0', sizeof (disp_expressions));
1247 memset (im_expressions, '\0', sizeof (im_expressions));
1248 save_stack_p = save_stack;
1249
1250 /* First parse an instruction mnemonic & call i386_operand for the operands.
1251 We assume that the scrubber has arranged it so that line[0] is the valid
1252 start of a (possibly prefixed) mnemonic. */
1253 {
1254 char *l = line;
1255 char *token_start = l;
1256 char *mnem_p;
1257
1258 /* Non-zero if we found a prefix only acceptable with string insns. */
1259 const char *expecting_string_instruction = NULL;
1260
1261 while (1)
1262 {
1263 mnem_p = mnemonic;
1264 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1265 {
1266 mnem_p++;
1267 if (mnem_p >= mnemonic + sizeof (mnemonic))
1268 {
1269 as_bad (_("no such instruction: `%s'"), token_start);
1270 return;
1271 }
1272 l++;
1273 }
1274 if (!is_space_char (*l)
1275 && *l != END_OF_INSN
1276 && *l != PREFIX_SEPARATOR)
1277 {
1278 as_bad (_("invalid character %s in mnemonic"),
1279 output_invalid (*l));
1280 return;
1281 }
1282 if (token_start == l)
1283 {
1284 if (*l == PREFIX_SEPARATOR)
1285 as_bad (_("expecting prefix; got nothing"));
1286 else
1287 as_bad (_("expecting mnemonic; got nothing"));
1288 return;
1289 }
1290
1291 /* Look up instruction (or prefix) via hash table. */
1292 current_templates = hash_find (op_hash, mnemonic);
1293
1294 if (*l != END_OF_INSN
1295 && (! is_space_char (*l) || l[1] != END_OF_INSN)
1296 && current_templates
1297 && (current_templates->start->opcode_modifier & IsPrefix))
1298 {
1299 /* If we are in 16-bit mode, do not allow addr16 or data16.
1300 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1301 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1302 && (((current_templates->start->opcode_modifier & Size32) != 0)
1303 ^ (flag_code == CODE_16BIT)))
1304 {
1305 as_bad (_("redundant %s prefix"),
1306 current_templates->start->name);
1307 return;
1308 }
1309 /* Add prefix, checking for repeated prefixes. */
1310 switch (add_prefix (current_templates->start->base_opcode))
1311 {
1312 case 0:
1313 return;
1314 case 2:
1315 expecting_string_instruction = current_templates->start->name;
1316 break;
1317 }
1318 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1319 token_start = ++l;
1320 }
1321 else
1322 break;
1323 }
1324
1325 if (!current_templates)
1326 {
1327 /* See if we can get a match by trimming off a suffix. */
1328 switch (mnem_p[-1])
1329 {
1330 case WORD_MNEM_SUFFIX:
1331 case BYTE_MNEM_SUFFIX:
1332 case QWORD_MNEM_SUFFIX:
1333 i.suffix = mnem_p[-1];
1334 mnem_p[-1] = '\0';
1335 current_templates = hash_find (op_hash, mnemonic);
1336 break;
1337 case SHORT_MNEM_SUFFIX:
1338 case LONG_MNEM_SUFFIX:
1339 if (!intel_syntax)
1340 {
1341 i.suffix = mnem_p[-1];
1342 mnem_p[-1] = '\0';
1343 current_templates = hash_find (op_hash, mnemonic);
1344 }
1345 break;
1346
1347 /* Intel Syntax. */
1348 case 'd':
1349 if (intel_syntax)
1350 {
1351 if (intel_float_operand (mnemonic))
1352 i.suffix = SHORT_MNEM_SUFFIX;
1353 else
1354 i.suffix = LONG_MNEM_SUFFIX;
1355 mnem_p[-1] = '\0';
1356 current_templates = hash_find (op_hash, mnemonic);
1357 }
1358 break;
1359 }
1360 if (!current_templates)
1361 {
1362 as_bad (_("no such instruction: `%s'"), token_start);
1363 return;
1364 }
1365 }
1366
1367 /* Check if instruction is supported on specified architecture. */
1368 if (cpu_arch_flags != 0)
1369 {
1370 if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
1371 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
1372 {
1373 as_warn (_("`%s' is not supported on `%s'"),
1374 current_templates->start->name, cpu_arch_name);
1375 }
1376 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1377 {
1378 as_warn (_("use .code16 to ensure correct addressing mode"));
1379 }
1380 }
1381
1382 /* Check for rep/repne without a string instruction. */
1383 if (expecting_string_instruction
1384 && !(current_templates->start->opcode_modifier & IsString))
1385 {
1386 as_bad (_("expecting string instruction after `%s'"),
1387 expecting_string_instruction);
1388 return;
1389 }
1390
1391 /* There may be operands to parse. */
1392 if (*l != END_OF_INSN)
1393 {
1394 /* 1 if operand is pending after ','. */
1395 unsigned int expecting_operand = 0;
1396
1397 /* Non-zero if operand parens not balanced. */
1398 unsigned int paren_not_balanced;
1399
1400 do
1401 {
1402 /* Skip optional white space before operand. */
1403 if (is_space_char (*l))
1404 ++l;
1405 if (!is_operand_char (*l) && *l != END_OF_INSN)
1406 {
1407 as_bad (_("invalid character %s before operand %d"),
1408 output_invalid (*l),
1409 i.operands + 1);
1410 return;
1411 }
1412 token_start = l; /* after white space */
1413 paren_not_balanced = 0;
1414 while (paren_not_balanced || *l != ',')
1415 {
1416 if (*l == END_OF_INSN)
1417 {
1418 if (paren_not_balanced)
1419 {
1420 if (!intel_syntax)
1421 as_bad (_("unbalanced parenthesis in operand %d."),
1422 i.operands + 1);
1423 else
1424 as_bad (_("unbalanced brackets in operand %d."),
1425 i.operands + 1);
1426 return;
1427 }
1428 else
1429 break; /* we are done */
1430 }
1431 else if (!is_operand_char (*l) && !is_space_char (*l))
1432 {
1433 as_bad (_("invalid character %s in operand %d"),
1434 output_invalid (*l),
1435 i.operands + 1);
1436 return;
1437 }
1438 if (!intel_syntax)
1439 {
1440 if (*l == '(')
1441 ++paren_not_balanced;
1442 if (*l == ')')
1443 --paren_not_balanced;
1444 }
1445 else
1446 {
1447 if (*l == '[')
1448 ++paren_not_balanced;
1449 if (*l == ']')
1450 --paren_not_balanced;
1451 }
1452 l++;
1453 }
1454 if (l != token_start)
1455 { /* Yes, we've read in another operand. */
1456 unsigned int operand_ok;
1457 this_operand = i.operands++;
1458 if (i.operands > MAX_OPERANDS)
1459 {
1460 as_bad (_("spurious operands; (%d operands/instruction max)"),
1461 MAX_OPERANDS);
1462 return;
1463 }
1464 /* Now parse operand adding info to 'i' as we go along. */
1465 END_STRING_AND_SAVE (l);
1466
1467 if (intel_syntax)
1468 operand_ok =
1469 i386_intel_operand (token_start,
1470 intel_float_operand (mnemonic));
1471 else
1472 operand_ok = i386_operand (token_start);
1473
1474 RESTORE_END_STRING (l);
1475 if (!operand_ok)
1476 return;
1477 }
1478 else
1479 {
1480 if (expecting_operand)
1481 {
1482 expecting_operand_after_comma:
1483 as_bad (_("expecting operand after ','; got nothing"));
1484 return;
1485 }
1486 if (*l == ',')
1487 {
1488 as_bad (_("expecting operand before ','; got nothing"));
1489 return;
1490 }
1491 }
1492
1493 /* Now *l must be either ',' or END_OF_INSN. */
1494 if (*l == ',')
1495 {
1496 if (*++l == END_OF_INSN)
1497 {
1498 /* Just skip it, if it's \n complain. */
1499 goto expecting_operand_after_comma;
1500 }
1501 expecting_operand = 1;
1502 }
1503 }
1504 while (*l != END_OF_INSN);
1505 }
1506 }
1507
1508 /* Now we've parsed the mnemonic into a set of templates, and have the
1509 operands at hand.
1510
1511 Next, we find a template that matches the given insn,
1512 making sure the overlap of the given operands types is consistent
1513 with the template operand types. */
1514
1515#define MATCH(overlap, given, template) \
1516 ((overlap & ~JumpAbsolute) \
1517 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1518
1519 /* If given types r0 and r1 are registers they must be of the same type
1520 unless the expected operand type register overlap is null.
1521 Note that Acc in a template matches every size of reg. */
1522#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1523 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1524 ((g0) & Reg) == ((g1) & Reg) || \
1525 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1526
1527 {
1528 register unsigned int overlap0, overlap1;
1529 unsigned int overlap2;
1530 unsigned int found_reverse_match;
1531 int suffix_check;
1532
1533 /* All intel opcodes have reversed operands except for "bound" and
1534 "enter". We also don't reverse intersegment "jmp" and "call"
1535 instructions with 2 immediate operands so that the immediate segment
1536 precedes the offset, as it does when in AT&T mode. "enter" and the
1537 intersegment "jmp" and "call" instructions are the only ones that
1538 have two immediate operands. */
1539 if (intel_syntax && i.operands > 1
1540 && (strcmp (mnemonic, "bound") != 0)
1541 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1542 {
1543 union i386_op temp_op;
1544 unsigned int temp_type;
1545 RELOC_ENUM temp_reloc;
1546 int xchg1 = 0;
1547 int xchg2 = 0;
1548
1549 if (i.operands == 2)
1550 {
1551 xchg1 = 0;
1552 xchg2 = 1;
1553 }
1554 else if (i.operands == 3)
1555 {
1556 xchg1 = 0;
1557 xchg2 = 2;
1558 }
1559 temp_type = i.types[xchg2];
1560 i.types[xchg2] = i.types[xchg1];
1561 i.types[xchg1] = temp_type;
1562 temp_op = i.op[xchg2];
1563 i.op[xchg2] = i.op[xchg1];
1564 i.op[xchg1] = temp_op;
1565 temp_reloc = i.reloc[xchg2];
1566 i.reloc[xchg2] = i.reloc[xchg1];
1567 i.reloc[xchg1] = temp_reloc;
1568
1569 if (i.mem_operands == 2)
1570 {
1571 const seg_entry *temp_seg;
1572 temp_seg = i.seg[0];
1573 i.seg[0] = i.seg[1];
1574 i.seg[1] = temp_seg;
1575 }
1576 }
1577
1578 if (i.imm_operands)
1579 {
1580 /* Try to ensure constant immediates are represented in the smallest
1581 opcode possible. */
1582 char guess_suffix = 0;
1583 int op;
1584
1585 if (i.suffix)
1586 guess_suffix = i.suffix;
1587 else if (i.reg_operands)
1588 {
1589 /* Figure out a suffix from the last register operand specified.
1590 We can't do this properly yet, ie. excluding InOutPortReg,
1591 but the following works for instructions with immediates.
1592 In any case, we can't set i.suffix yet. */
1593 for (op = i.operands; --op >= 0;)
1594 if (i.types[op] & Reg)
1595 {
1596 if (i.types[op] & Reg8)
1597 guess_suffix = BYTE_MNEM_SUFFIX;
1598 else if (i.types[op] & Reg16)
1599 guess_suffix = WORD_MNEM_SUFFIX;
1600 else if (i.types[op] & Reg32)
1601 guess_suffix = LONG_MNEM_SUFFIX;
1602 else if (i.types[op] & Reg64)
1603 guess_suffix = QWORD_MNEM_SUFFIX;
1604 break;
1605 }
1606 }
1607 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1608 guess_suffix = WORD_MNEM_SUFFIX;
1609
1610 for (op = i.operands; --op >= 0;)
1611 if (i.types[op] & Imm)
1612 {
1613 switch (i.op[op].imms->X_op)
1614 {
1615 case O_constant:
1616 /* If a suffix is given, this operand may be shortened. */
1617 switch (guess_suffix)
1618 {
1619 case LONG_MNEM_SUFFIX:
1620 i.types[op] |= Imm32 | Imm64;
1621 break;
1622 case WORD_MNEM_SUFFIX:
1623 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1624 break;
1625 case BYTE_MNEM_SUFFIX:
1626 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
1627 break;
1628 }
1629
1630 /* If this operand is at most 16 bits, convert it
1631 to a signed 16 bit number before trying to see
1632 whether it will fit in an even smaller size.
1633 This allows a 16-bit operand such as $0xffe0 to
1634 be recognised as within Imm8S range. */
1635 if ((i.types[op] & Imm16)
1636 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
1637 {
1638 i.op[op].imms->X_add_number =
1639 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
1640 }
1641 if ((i.types[op] & Imm32)
1642 && (i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) == 0)
1643 {
1644 i.op[op].imms->X_add_number =
1645 (i.op[op].imms->X_add_number ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
1646 }
1647 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
1648 /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
1649 if (guess_suffix == QWORD_MNEM_SUFFIX)
1650 i.types[op] &= ~Imm32;
1651 break;
1652 case O_absent:
1653 case O_register:
1654 abort ();
1655 /* Symbols and expressions. */
1656 default:
1657 /* Convert symbolic operand to proper sizes for matching. */
1658 switch (guess_suffix)
1659 {
1660 case QWORD_MNEM_SUFFIX:
1661 i.types[op] = Imm64 | Imm32S;
1662 break;
1663 case LONG_MNEM_SUFFIX:
1664 i.types[op] = Imm32 | Imm64;
1665 break;
1666 case WORD_MNEM_SUFFIX:
1667 i.types[op] = Imm16 | Imm32 | Imm64;
1668 break;
1669 break;
1670 case BYTE_MNEM_SUFFIX:
1671 i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32;
1672 break;
1673 break;
1674 }
1675 break;
1676 }
1677 }
1678 }
1679
1680 if (i.disp_operands)
1681 {
1682 /* Try to use the smallest displacement type too. */
1683 int op;
1684
1685 for (op = i.operands; --op >= 0;)
1686 if ((i.types[op] & Disp)
1687 && i.op[op].disps->X_op == O_constant)
1688 {
1689 offsetT disp = i.op[op].disps->X_add_number;
1690
1691 if (i.types[op] & Disp16)
1692 {
1693 /* We know this operand is at most 16 bits, so
1694 convert to a signed 16 bit number before trying
1695 to see whether it will fit in an even smaller
1696 size. */
1697
1698 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
1699 }
1700 else if (i.types[op] & Disp32)
1701 {
1702 /* We know this operand is at most 32 bits, so convert to a
1703 signed 32 bit number before trying to see whether it will
1704 fit in an even smaller size. */
1705 disp &= (((offsetT) 2 << 31) - 1);
1706 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
1707 }
1708 if (flag_code == CODE_64BIT)
1709 {
1710 if (fits_in_signed_long (disp))
1711 i.types[op] |= Disp32S;
1712 if (fits_in_unsigned_long (disp))
1713 i.types[op] |= Disp32;
1714 }
1715 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
1716 && fits_in_signed_byte (disp))
1717 i.types[op] |= Disp8;
1718 }
1719 }
1720
1721 overlap0 = 0;
1722 overlap1 = 0;
1723 overlap2 = 0;
1724 found_reverse_match = 0;
1725 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
1726 ? No_bSuf
1727 : (i.suffix == WORD_MNEM_SUFFIX
1728 ? No_wSuf
1729 : (i.suffix == SHORT_MNEM_SUFFIX
1730 ? No_sSuf
1731 : (i.suffix == LONG_MNEM_SUFFIX
1732 ? No_lSuf
1733 : (i.suffix == QWORD_MNEM_SUFFIX
1734 ? No_qSuf
1735 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX ? No_xSuf : 0))))));
1736
1737 for (t = current_templates->start;
1738 t < current_templates->end;
1739 t++)
1740 {
1741 /* Must have right number of operands. */
1742 if (i.operands != t->operands)
1743 continue;
1744
1745 /* Check the suffix, except for some instructions in intel mode. */
1746 if ((t->opcode_modifier & suffix_check)
1747 && !(intel_syntax
1748 && (t->opcode_modifier & IgnoreSize))
1749 && !(intel_syntax
1750 && t->base_opcode == 0xd9
1751 && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */
1752 || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */
1753 continue;
1754
1755 /* Do not verify operands when there are none. */
1756 else if (!t->operands)
1757 {
1758 if (t->cpu_flags & ~cpu_arch_flags)
1759 continue;
1760 /* We've found a match; break out of loop. */
1761 break;
1762 }
1763
1764 overlap0 = i.types[0] & t->operand_types[0];
1765 switch (t->operands)
1766 {
1767 case 1:
1768 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
1769 continue;
1770 break;
1771 case 2:
1772 case 3:
1773 overlap1 = i.types[1] & t->operand_types[1];
1774 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
1775 || !MATCH (overlap1, i.types[1], t->operand_types[1])
1776 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
1777 t->operand_types[0],
1778 overlap1, i.types[1],
1779 t->operand_types[1]))
1780 {
1781 /* Check if other direction is valid ... */
1782 if ((t->opcode_modifier & (D|FloatD)) == 0)
1783 continue;
1784
1785 /* Try reversing direction of operands. */
1786 overlap0 = i.types[0] & t->operand_types[1];
1787 overlap1 = i.types[1] & t->operand_types[0];
1788 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
1789 || !MATCH (overlap1, i.types[1], t->operand_types[0])
1790 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
1791 t->operand_types[1],
1792 overlap1, i.types[1],
1793 t->operand_types[0]))
1794 {
1795 /* Does not match either direction. */
1796 continue;
1797 }
1798 /* found_reverse_match holds which of D or FloatDR
1799 we've found. */
1800 found_reverse_match = t->opcode_modifier & (D|FloatDR);
1801 }
1802 /* Found a forward 2 operand match here. */
1803 else if (t->operands == 3)
1804 {
1805 /* Here we make use of the fact that there are no
1806 reverse match 3 operand instructions, and all 3
1807 operand instructions only need to be checked for
1808 register consistency between operands 2 and 3. */
1809 overlap2 = i.types[2] & t->operand_types[2];
1810 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
1811 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
1812 t->operand_types[1],
1813 overlap2, i.types[2],
1814 t->operand_types[2]))
1815
1816 continue;
1817 }
1818 /* Found either forward/reverse 2 or 3 operand match here:
1819 slip through to break. */
1820 }
1821 if (t->cpu_flags & ~cpu_arch_flags)
1822 {
1823 found_reverse_match = 0;
1824 continue;
1825 }
1826 /* We've found a match; break out of loop. */
1827 break;
1828 }
1829 if (t == current_templates->end)
1830 {
1831 /* We found no match. */
1832 as_bad (_("suffix or operands invalid for `%s'"),
1833 current_templates->start->name);
1834 return;
1835 }
1836
1837 if (!quiet_warnings)
1838 {
1839 if (!intel_syntax
1840 && ((i.types[0] & JumpAbsolute)
1841 != (t->operand_types[0] & JumpAbsolute)))
1842 {
1843 as_warn (_("indirect %s without `*'"), t->name);
1844 }
1845
1846 if ((t->opcode_modifier & (IsPrefix|IgnoreSize))
1847 == (IsPrefix|IgnoreSize))
1848 {
1849 /* Warn them that a data or address size prefix doesn't
1850 affect assembly of the next line of code. */
1851 as_warn (_("stand-alone `%s' prefix"), t->name);
1852 }
1853 }
1854
1855 /* Copy the template we found. */
1856 i.tm = *t;
1857 if (found_reverse_match)
1858 {
1859 /* If we found a reverse match we must alter the opcode
1860 direction bit. found_reverse_match holds bits to change
1861 (different for int & float insns). */
1862
1863 i.tm.base_opcode ^= found_reverse_match;
1864
1865 i.tm.operand_types[0] = t->operand_types[1];
1866 i.tm.operand_types[1] = t->operand_types[0];
1867 }
1868
1869 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1870 if (SYSV386_COMPAT
1871 && intel_syntax
1872 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1873 i.tm.base_opcode ^= FloatR;
1874
1875 if (i.tm.opcode_modifier & FWait)
1876 if (! add_prefix (FWAIT_OPCODE))
1877 return;
1878
1879 /* Check string instruction segment overrides. */
1880 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1881 {
1882 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
1883 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
1884 {
1885 if (i.seg[0] != NULL && i.seg[0] != &es)
1886 {
1887 as_bad (_("`%s' operand %d must use `%%es' segment"),
1888 i.tm.name,
1889 mem_op + 1);
1890 return;
1891 }
1892 /* There's only ever one segment override allowed per instruction.
1893 This instruction possibly has a legal segment override on the
1894 second operand, so copy the segment to where non-string
1895 instructions store it, allowing common code. */
1896 i.seg[0] = i.seg[1];
1897 }
1898 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
1899 {
1900 if (i.seg[1] != NULL && i.seg[1] != &es)
1901 {
1902 as_bad (_("`%s' operand %d must use `%%es' segment"),
1903 i.tm.name,
1904 mem_op + 2);
1905 return;
1906 }
1907 }
1908 }
1909
|
1923 /* If matched instruction specifies an explicit instruction mnemonic
1924 suffix, use it. */
1925 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
1926 {
1927 if (i.tm.opcode_modifier & Size16)
1928 i.suffix = WORD_MNEM_SUFFIX;
1929 else if (i.tm.opcode_modifier & Size64)
1930 i.suffix = QWORD_MNEM_SUFFIX;
1931 else
1932 i.suffix = LONG_MNEM_SUFFIX;
1933 }
1934 else if (i.reg_operands)
1935 {
1936 /* If there's no instruction mnemonic suffix we try to invent one
1937 based on register operands. */
1938 if (!i.suffix)
1939 {
1940 /* We take i.suffix from the last register operand specified,
1941 Destination register type is more significant than source
1942 register type. */
1943 int op;
1944 for (op = i.operands; --op >= 0;)
1945 if ((i.types[op] & Reg)
1946 && !(i.tm.operand_types[op] & InOutPortReg))
1947 {
1948 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
1949 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
1950 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
1951 LONG_MNEM_SUFFIX);
1952 break;
1953 }
1954 }
1955 else if (i.suffix == BYTE_MNEM_SUFFIX)
1956 {
1957 int op;
1958 for (op = i.operands; --op >= 0;)
1959 {
1960 /* If this is an eight bit register, it's OK. If it's
1961 the 16 or 32 bit version of an eight bit register,
1962 we will just use the low portion, and that's OK too. */
1963 if (i.types[op] & Reg8)
1964 continue;
1965
1966 /* movzx and movsx should not generate this warning. */
1967 if (intel_syntax
1968 && (i.tm.base_opcode == 0xfb7
1969 || i.tm.base_opcode == 0xfb6
1970 || i.tm.base_opcode == 0x63
1971 || i.tm.base_opcode == 0xfbe
1972 || i.tm.base_opcode == 0xfbf))
1973 continue;
1974
1975 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
1976#if 0
1977 /* Check that the template allows eight bit regs
1978 This kills insns such as `orb $1,%edx', which
1979 maybe should be allowed. */
1980 && (i.tm.operand_types[op] & (Reg8|InOutPortReg))
1981#endif
1982 )
1983 {
1984 /* Prohibit these changes in the 64bit mode, since
1985 the lowering is more complicated. */
1986 if (flag_code == CODE_64BIT
1987 && (i.tm.operand_types[op] & InOutPortReg) == 0)
1988 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1989 i.op[op].regs->reg_name,
1990 i.suffix);
1991#if REGISTER_WARNINGS
1992 if (!quiet_warnings
1993 && (i.tm.operand_types[op] & InOutPortReg) == 0)
1994 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1995 (i.op[op].regs
1996 + (i.types[op] & Reg16
1997 ? REGNAM_AL - REGNAM_AX
1998 : REGNAM_AL - REGNAM_EAX))->reg_name,
1999 i.op[op].regs->reg_name,
2000 i.suffix);
2001#endif
2002 continue;
2003 }
2004 /* Any other register is bad. */
2005 if (i.types[op] & (Reg | RegMMX | RegXMM
2006 | SReg2 | SReg3
2007 | Control | Debug | Test
2008 | FloatReg | FloatAcc))
2009 {
2010 as_bad (_("`%%%s' not allowed with `%s%c'"),
2011 i.op[op].regs->reg_name,
2012 i.tm.name,
2013 i.suffix);
2014 return;
2015 }
2016 }
2017 }
2018 else if (i.suffix == LONG_MNEM_SUFFIX)
2019 {
2020 int op;
2021
2022 for (op = i.operands; --op >= 0;)
2023 /* Reject eight bit registers, except where the template
2024 requires them. (eg. movzb) */
2025 if ((i.types[op] & Reg8) != 0
2026 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2027 {
2028 as_bad (_("`%%%s' not allowed with `%s%c'"),
2029 i.op[op].regs->reg_name,
2030 i.tm.name,
2031 i.suffix);
2032 return;
2033 }
2034 /* Warn if the e prefix on a general reg is missing. */
2035 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2036 && (i.types[op] & Reg16) != 0
2037 && (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
2038 {
2039 /* Prohibit these changes in the 64bit mode, since
2040 the lowering is more complicated. */
2041 if (flag_code == CODE_64BIT)
2042 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2043 i.op[op].regs->reg_name,
2044 i.suffix);
2045#if REGISTER_WARNINGS
2046 else
2047 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2048 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2049 i.op[op].regs->reg_name,
2050 i.suffix);
2051#endif
2052 }
2053 /* Warn if the r prefix on a general reg is missing. */
2054 else if ((i.types[op] & Reg64) != 0
2055 && (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
2056 {
2057 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2058 i.op[op].regs->reg_name,
2059 i.suffix);
2060 }
2061 }
2062 else if (i.suffix == QWORD_MNEM_SUFFIX)
2063 {
2064 int op;
2065
2066 for (op = i.operands; --op >= 0; )
2067 /* Reject eight bit registers, except where the template
2068 requires them. (eg. movzb) */
2069 if ((i.types[op] & Reg8) != 0
2070 && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0)
2071 {
2072 as_bad (_("`%%%s' not allowed with `%s%c'"),
2073 i.op[op].regs->reg_name,
2074 i.tm.name,
2075 i.suffix);
2076 return;
2077 }
2078 /* Warn if the e prefix on a general reg is missing. */
2079 else if (((i.types[op] & Reg16) != 0
2080 || (i.types[op] & Reg32) != 0)
2081 && (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
2082 {
2083 /* Prohibit these changes in the 64bit mode, since
2084 the lowering is more complicated. */
2085 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2086 i.op[op].regs->reg_name,
2087 i.suffix);
2088 }
2089 }
2090 else if (i.suffix == WORD_MNEM_SUFFIX)
2091 {
2092 int op;
2093 for (op = i.operands; --op >= 0;)
2094 /* Reject eight bit registers, except where the template
2095 requires them. (eg. movzb) */
2096 if ((i.types[op] & Reg8) != 0
2097 && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0)
2098 {
2099 as_bad (_("`%%%s' not allowed with `%s%c'"),
2100 i.op[op].regs->reg_name,
2101 i.tm.name,
2102 i.suffix);
2103 return;
2104 }
2105 /* Warn if the e prefix on a general reg is present. */
2106 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2107 && (i.types[op] & Reg32) != 0
2108 && (i.tm.operand_types[op] & (Reg16|Acc)) != 0)
2109 {
2110 /* Prohibit these changes in the 64bit mode, since
2111 the lowering is more complicated. */
2112 if (flag_code == CODE_64BIT)
2113 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2114 i.op[op].regs->reg_name,
2115 i.suffix);
2116 else
2117#if REGISTER_WARNINGS
2118 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2119 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2120 i.op[op].regs->reg_name,
2121 i.suffix);
2122#endif
2123 }
2124 }
2125 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2126 /* Do nothing if the instruction is going to ignore the prefix. */
2127 ;
2128 else
2129 abort ();
2130 }
2131 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
2132 {
2133 i.suffix = stackop_size;
2134 }
2135 /* Make still unresolved immediate matches conform to size of immediate
2136 given in i.suffix. Note: overlap2 cannot be an immediate! */
2137 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S))
2138 && overlap0 != Imm8 && overlap0 != Imm8S
2139 && overlap0 != Imm16 && overlap0 != Imm32S
2140 && overlap0 != Imm32 && overlap0 != Imm64)
2141 {
2142 if (i.suffix)
2143 {
2144 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) :
2145 (i.suffix == WORD_MNEM_SUFFIX ? Imm16 :
2146 (i.suffix == QWORD_MNEM_SUFFIX ? Imm64 | Imm32S : Imm32)));
2147 }
2148 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2149 || overlap0 == (Imm16 | Imm32)
2150 || overlap0 == (Imm16 | Imm32S))
2151 {
2152 overlap0 =
2153 ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32S;
2154 }
2155 if (overlap0 != Imm8 && overlap0 != Imm8S
2156 && overlap0 != Imm16 && overlap0 != Imm32S
2157 && overlap0 != Imm32 && overlap0 != Imm64)
2158 {
2159 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2160 return;
2161 }
2162 }
2163 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
2164 && overlap1 != Imm8 && overlap1 != Imm8S
2165 && overlap1 != Imm16 && overlap1 != Imm32S
2166 && overlap1 != Imm32 && overlap1 != Imm64)
2167 {
2168 if (i.suffix)
2169 {
2170 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) :
2171 (i.suffix == WORD_MNEM_SUFFIX ? Imm16 :
2172 (i.suffix == QWORD_MNEM_SUFFIX ? Imm64 | Imm32S : Imm32)));
2173 }
2174 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2175 || overlap1 == (Imm16 | Imm32)
2176 || overlap1 == (Imm16 | Imm32S))
2177 {
2178 overlap1 =
2179 ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32S;
2180 }
2181 if (overlap1 != Imm8 && overlap1 != Imm8S
2182 && overlap1 != Imm16 && overlap1 != Imm32S
2183 && overlap1 != Imm32 && overlap1 != Imm64)
2184 {
2185 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2186 return;
2187 }
2188 }
2189 assert ((overlap2 & Imm) == 0);
2190
2191 i.types[0] = overlap0;
2192 if (overlap0 & ImplicitRegister)
2193 i.reg_operands--;
2194 if (overlap0 & Imm1)
2195 i.imm_operands = 0; /* kludge for shift insns. */
2196
2197 i.types[1] = overlap1;
2198 if (overlap1 & ImplicitRegister)
2199 i.reg_operands--;
2200
2201 i.types[2] = overlap2;
2202 if (overlap2 & ImplicitRegister)
2203 i.reg_operands--;
2204
2205 /* Finalize opcode. First, we change the opcode based on the operand
2206 size given by i.suffix: We need not change things for byte insns. */
2207
2208 if (!i.suffix && (i.tm.opcode_modifier & W))
2209 {
2210 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2211 return;
2212 }
2213
2214 /* For movzx and movsx, need to check the register type. */
2215 if (intel_syntax
2216 && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe))
2217 if (i.suffix && i.suffix == BYTE_MNEM_SUFFIX)
2218 {
2219 unsigned int prefix = DATA_PREFIX_OPCODE;
2220
2221 if ((i.op[1].regs->reg_type & Reg16) != 0)
2222 if (!add_prefix (prefix))
2223 return;
2224 }
2225
2226 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2227 {
2228 /* It's not a byte, select word/dword operation. */
2229 if (i.tm.opcode_modifier & W)
2230 {
2231 if (i.tm.opcode_modifier & ShortForm)
2232 i.tm.base_opcode |= 8;
2233 else
2234 i.tm.base_opcode |= 1;
2235 }
2236 /* Now select between word & dword operations via the operand
2237 size prefix, except for instructions that will ignore this
2238 prefix anyway. */
2239 if (i.suffix != QWORD_MNEM_SUFFIX
2240 && (i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2241 && !(i.tm.opcode_modifier & IgnoreSize))
2242 {
2243 unsigned int prefix = DATA_PREFIX_OPCODE;
2244 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2245 prefix = ADDR_PREFIX_OPCODE;
2246
2247 if (! add_prefix (prefix))
2248 return;
2249 }
2250
2251 /* Set mode64 for an operand. */
2252 if (i.suffix == QWORD_MNEM_SUFFIX
2253 && !(i.tm.opcode_modifier & NoRex64))
2254 {
2255 i.rex.mode64 = 1;
2256 if (flag_code < CODE_64BIT)
2257 {
2258 as_bad (_("64bit operations available only in 64bit modes."));
2259 return;
2260 }
2261 }
2262
2263 /* Size floating point instruction. */
2264 if (i.suffix == LONG_MNEM_SUFFIX)
2265 {
2266 if (i.tm.opcode_modifier & FloatMF)
2267 i.tm.base_opcode ^= 4;
2268 }
2269 }
2270
2271 if (i.tm.opcode_modifier & ImmExt)
2272 {
2273 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2274 opcode suffix which is coded in the same place as an 8-bit
2275 immediate field would be. Here we fake an 8-bit immediate
2276 operand from the opcode suffix stored in tm.extension_opcode. */
2277
2278 expressionS *exp;
2279
2280 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
2281
2282 exp = &im_expressions[i.imm_operands++];
2283 i.op[i.operands].imms = exp;
2284 i.types[i.operands++] = Imm8;
2285 exp->X_op = O_constant;
2286 exp->X_add_number = i.tm.extension_opcode;
2287 i.tm.extension_opcode = None;
2288 }
2289
2290 /* For insns with operands there are more diddles to do to the opcode. */
2291 if (i.operands)
2292 {
2293 /* Default segment register this instruction will use
2294 for memory accesses. 0 means unknown.
2295 This is only for optimizing out unnecessary segment overrides. */
2296 const seg_entry *default_seg = 0;
2297
2298 /* The imul $imm, %reg instruction is converted into
2299 imul $imm, %reg, %reg, and the clr %reg instruction
2300 is converted into xor %reg, %reg. */
2301 if (i.tm.opcode_modifier & regKludge)
2302 {
2303 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2304 /* Pretend we saw the extra register operand. */
2305 assert (i.op[first_reg_op + 1].regs == 0);
2306 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2307 i.types[first_reg_op + 1] = i.types[first_reg_op];
2308 i.reg_operands = 2;
2309 }
2310
2311 if (i.tm.opcode_modifier & ShortForm)
2312 {
2313 /* The register or float register operand is in operand 0 or 1. */
2314 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2315 /* Register goes in low 3 bits of opcode. */
2316 i.tm.base_opcode |= i.op[op].regs->reg_num;
2317 if (i.op[op].regs->reg_flags & RegRex)
2318 i.rex.extZ = 1;
2319 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2320 {
2321 /* Warn about some common errors, but press on regardless.
2322 The first case can be generated by gcc (<= 2.8.1). */
2323 if (i.operands == 2)
2324 {
2325 /* Reversed arguments on faddp, fsubp, etc. */
2326 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2327 i.op[1].regs->reg_name,
2328 i.op[0].regs->reg_name);
2329 }
2330 else
2331 {
2332 /* Extraneous `l' suffix on fp insn. */
2333 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2334 i.op[0].regs->reg_name);
2335 }
2336 }
2337 }
2338 else if (i.tm.opcode_modifier & Modrm)
2339 {
2340 /* The opcode is completed (modulo i.tm.extension_opcode which
2341 must be put into the modrm byte).
2342 Now, we make the modrm & index base bytes based on all the
2343 info we've collected. */
2344
2345 /* i.reg_operands MUST be the number of real register operands;
2346 implicit registers do not count. */
2347 if (i.reg_operands == 2)
2348 {
2349 unsigned int source, dest;
2350 source = ((i.types[0]
2351 & (Reg | RegMMX | RegXMM
2352 | SReg2 | SReg3
2353 | Control | Debug | Test))
2354 ? 0 : 1);
2355 dest = source + 1;
2356
2357 i.rm.mode = 3;
2358 /* One of the register operands will be encoded in the
2359 i.tm.reg field, the other in the combined i.tm.mode
2360 and i.tm.regmem fields. If no form of this
2361 instruction supports a memory destination operand,
2362 then we assume the source operand may sometimes be
2363 a memory operand and so we need to store the
2364 destination in the i.rm.reg field. */
2365 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2366 {
2367 i.rm.reg = i.op[dest].regs->reg_num;
2368 i.rm.regmem = i.op[source].regs->reg_num;
2369 if (i.op[dest].regs->reg_flags & RegRex)
2370 i.rex.extX = 1;
2371 if (i.op[source].regs->reg_flags & RegRex)
2372 i.rex.extZ = 1;
2373 }
2374 else
2375 {
2376 i.rm.reg = i.op[source].regs->reg_num;
2377 i.rm.regmem = i.op[dest].regs->reg_num;
2378 if (i.op[dest].regs->reg_flags & RegRex)
2379 i.rex.extZ = 1;
2380 if (i.op[source].regs->reg_flags & RegRex)
2381 i.rex.extX = 1;
2382 }
2383 }
2384 else
2385 { /* If it's not 2 reg operands... */
2386 if (i.mem_operands)
2387 {
2388 unsigned int fake_zero_displacement = 0;
2389 unsigned int op = ((i.types[0] & AnyMem)
2390 ? 0
2391 : (i.types[1] & AnyMem) ? 1 : 2);
2392
2393 default_seg = &ds;
2394
2395 if (! i.base_reg)
2396 {
2397 i.rm.mode = 0;
2398 if (! i.disp_operands)
2399 fake_zero_displacement = 1;
2400 if (! i.index_reg)
2401 {
2402 /* Operand is just <disp> */
2403 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
2404 {
2405 i.rm.regmem = NO_BASE_REGISTER_16;
2406 i.types[op] &= ~Disp;
2407 i.types[op] |= Disp16;
2408 }
2409 else if (flag_code != CODE_64BIT)
2410 {
2411 i.rm.regmem = NO_BASE_REGISTER;
2412 i.types[op] &= ~Disp;
2413 i.types[op] |= Disp32;
2414 }
2415 else
2416 {
2417 /* 64bit mode overwrites the 32bit
2418 absolute addressing by RIP relative
2419 addressing and absolute addressing
2420 is encoded by one of the redundant
2421 SIB forms. */
2422
2423 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2424 i.sib.base = NO_BASE_REGISTER;
2425 i.sib.index = NO_INDEX_REGISTER;
2426 i.types[op] &= ~Disp;
2427 i.types[op] |= Disp32S;
2428 }
2429 }
2430 else /* ! i.base_reg && i.index_reg */
2431 {
2432 i.sib.index = i.index_reg->reg_num;
2433 i.sib.base = NO_BASE_REGISTER;
2434 i.sib.scale = i.log2_scale_factor;
2435 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2436 i.types[op] &= ~Disp;
2437 if (flag_code != CODE_64BIT)
2438 i.types[op] |= Disp32; /* Must be 32 bit */
2439 else
2440 i.types[op] |= Disp32S;
2441 if (i.index_reg->reg_flags & RegRex)
2442 i.rex.extY = 1;
2443 }
2444 }
2445 /* RIP addressing for 64bit mode. */
2446 else if (i.base_reg->reg_type == BaseIndex)
2447 {
2448 i.rm.regmem = NO_BASE_REGISTER;
2449 i.types[op] &= ~Disp;
2450 i.types[op] |= Disp32S;
2451 i.flags[op] = Operand_PCrel;
2452 }
2453 else if (i.base_reg->reg_type & Reg16)
2454 {
2455 switch (i.base_reg->reg_num)
2456 {
2457 case 3: /* (%bx) */
2458 if (! i.index_reg)
2459 i.rm.regmem = 7;
2460 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2461 i.rm.regmem = i.index_reg->reg_num - 6;
2462 break;
2463 case 5: /* (%bp) */
2464 default_seg = &ss;
2465 if (! i.index_reg)
2466 {
2467 i.rm.regmem = 6;
2468 if ((i.types[op] & Disp) == 0)
2469 {
2470 /* fake (%bp) into 0(%bp) */
2471 i.types[op] |= Disp8;
2472 fake_zero_displacement = 1;
2473 }
2474 }
2475 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2476 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2477 break;
2478 default: /* (%si) -> 4 or (%di) -> 5 */
2479 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2480 }
2481 i.rm.mode = mode_from_disp_size (i.types[op]);
2482 }
2483 else /* i.base_reg and 32/64 bit mode */
2484 {
2485 if (flag_code == CODE_64BIT
2486 && (i.types[op] & Disp))
2487 {
2488 if (i.types[op] & Disp8)
2489 i.types[op] = Disp8 | Disp32S;
2490 else
2491 i.types[op] = Disp32S;
2492 }
2493 i.rm.regmem = i.base_reg->reg_num;
2494 if (i.base_reg->reg_flags & RegRex)
2495 i.rex.extZ = 1;
2496 i.sib.base = i.base_reg->reg_num;
2497 /* x86-64 ignores REX prefix bit here to avoid
2498 decoder complications. */
2499 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
2500 {
2501 default_seg = &ss;
2502 if (i.disp_operands == 0)
2503 {
2504 fake_zero_displacement = 1;
2505 i.types[op] |= Disp8;
2506 }
2507 }
2508 else if (i.base_reg->reg_num == ESP_REG_NUM)
2509 {
2510 default_seg = &ss;
2511 }
2512 i.sib.scale = i.log2_scale_factor;
2513 if (! i.index_reg)
2514 {
2515 /* <disp>(%esp) becomes two byte modrm
2516 with no index register. We've already
2517 stored the code for esp in i.rm.regmem
2518 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2519 base register besides %esp will not use
2520 the extra modrm byte. */
2521 i.sib.index = NO_INDEX_REGISTER;
2522#if ! SCALE1_WHEN_NO_INDEX
2523 /* Another case where we force the second
2524 modrm byte. */
2525 if (i.log2_scale_factor)
2526 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2527#endif
2528 }
2529 else
2530 {
2531 i.sib.index = i.index_reg->reg_num;
2532 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2533 if (i.index_reg->reg_flags & RegRex)
2534 i.rex.extY = 1;
2535 }
2536 i.rm.mode = mode_from_disp_size (i.types[op]);
2537 }
2538
2539 if (fake_zero_displacement)
2540 {
2541 /* Fakes a zero displacement assuming that i.types[op]
2542 holds the correct displacement size. */
2543 expressionS *exp;
2544
2545 assert (i.op[op].disps == 0);
2546 exp = &disp_expressions[i.disp_operands++];
2547 i.op[op].disps = exp;
2548 exp->X_op = O_constant;
2549 exp->X_add_number = 0;
2550 exp->X_add_symbol = (symbolS *) 0;
2551 exp->X_op_symbol = (symbolS *) 0;
2552 }
2553 }
2554
2555 /* Fill in i.rm.reg or i.rm.regmem field with register
2556 operand (if any) based on i.tm.extension_opcode.
2557 Again, we must be careful to make sure that
2558 segment/control/debug/test/MMX registers are coded
2559 into the i.rm.reg field. */
2560 if (i.reg_operands)
2561 {
2562 unsigned int op =
2563 ((i.types[0]
2564 & (Reg | RegMMX | RegXMM
2565 | SReg2 | SReg3
2566 | Control | Debug | Test))
2567 ? 0
2568 : ((i.types[1]
2569 & (Reg | RegMMX | RegXMM
2570 | SReg2 | SReg3
2571 | Control | Debug | Test))
2572 ? 1
2573 : 2));
2574 /* If there is an extension opcode to put here, the
2575 register number must be put into the regmem field. */
2576 if (i.tm.extension_opcode != None)
2577 {
2578 i.rm.regmem = i.op[op].regs->reg_num;
2579 if (i.op[op].regs->reg_flags & RegRex)
2580 i.rex.extZ = 1;
2581 }
2582 else
2583 {
2584 i.rm.reg = i.op[op].regs->reg_num;
2585 if (i.op[op].regs->reg_flags & RegRex)
2586 i.rex.extX = 1;
2587 }
2588
2589 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2590 we must set it to 3 to indicate this is a register
2591 operand in the regmem field. */
2592 if (!i.mem_operands)
2593 i.rm.mode = 3;
2594 }
2595
2596 /* Fill in i.rm.reg field with extension opcode (if any). */
2597 if (i.tm.extension_opcode != None)
2598 i.rm.reg = i.tm.extension_opcode;
2599 }
2600 }
2601 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2602 {
2603 if (i.tm.base_opcode == POP_SEG_SHORT
2604 && i.op[0].regs->reg_num == 1)
2605 {
2606 as_bad (_("you can't `pop %%cs'"));
2607 return;
2608 }
2609 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2610 if (i.op[0].regs->reg_flags & RegRex)
2611 i.rex.extZ = 1;
2612 }
2613 else if ((i.tm.base_opcode & ~(D|W)) == MOV_AX_DISP32)
2614 {
2615 default_seg = &ds;
2616 }
2617 else if ((i.tm.opcode_modifier & IsString) != 0)
2618 {
2619 /* For the string instructions that allow a segment override
2620 on one of their operands, the default segment is ds. */
2621 default_seg = &ds;
2622 }
2623
2624 /* If a segment was explicitly specified,
2625 and the specified segment is not the default,
2626 use an opcode prefix to select it.
2627 If we never figured out what the default segment is,
2628 then default_seg will be zero at this point,
2629 and the specified segment prefix will always be used. */
2630 if ((i.seg[0]) && (i.seg[0] != default_seg))
2631 {
2632 if (! add_prefix (i.seg[0]->seg_prefix))
2633 return;
2634 }
2635 }
2636 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2637 {
2638 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2639 as_warn (_("translating to `%sp'"), i.tm.name);
2640 }
2641 }
2642
2643 /* Handle conversion of 'int $3' --> special int3 insn. */
2644 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2645 {
2646 i.tm.base_opcode = INT3_OPCODE;
2647 i.imm_operands = 0;
2648 }
2649
2650 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
2651 && i.op[0].disps->X_op == O_constant)
2652 {
2653 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2654 the absolute address given by the constant. Since ix86 jumps and
2655 calls are pc relative, we need to generate a reloc. */
2656 i.op[0].disps->X_add_symbol = &abs_symbol;
2657 i.op[0].disps->X_op = O_symbol;
2658 }
2659
2660 if (i.tm.opcode_modifier & Rex64)
2661 i.rex.mode64 = 1;
2662
2663 /* For 8bit registers we would need an empty rex prefix.
2664 Also in the case instruction is already having prefix,
2665 we need to convert old registers to new ones. */
2666
2667 if (((i.types[0] & Reg8) && (i.op[0].regs->reg_flags & RegRex64))
2668 || ((i.types[1] & Reg8) && (i.op[1].regs->reg_flags & RegRex64))
2669 || ((i.rex.mode64 || i.rex.extX || i.rex.extY || i.rex.extZ || i.rex.empty)
2670 && ((i.types[0] & Reg8) || (i.types[1] & Reg8))))
2671 {
2672 int x;
2673 i.rex.empty = 1;
2674 for (x = 0; x < 2; x++)
2675 {
2676 /* Look for 8bit operand that does use old registers. */
2677 if (i.types[x] & Reg8
2678 && !(i.op[x].regs->reg_flags & RegRex64))
2679 {
2680 /* In case it is "hi" register, give up. */
2681 if (i.op[x].regs->reg_num > 3)
2682 as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"),
2683 i.op[x].regs->reg_name);
2684
2685 /* Otherwise it is equivalent to the extended register.
2686 Since the encoding don't change this is merely cosmetical
2687 cleanup for debug output. */
2688
2689 i.op[x].regs = i.op[x].regs + 8;
2690 }
2691 }
2692 }
2693
2694 if (i.rex.mode64 || i.rex.extX || i.rex.extY || i.rex.extZ || i.rex.empty)
2695 add_prefix (0x40
2696 | (i.rex.mode64 ? 8 : 0)
2697 | (i.rex.extX ? 4 : 0)
2698 | (i.rex.extY ? 2 : 0)
2699 | (i.rex.extZ ? 1 : 0));
2700
2701 /* We are ready to output the insn. */
2702 {
2703 register char *p;
2704
2705 /* Tie dwarf2 debug info to the address at the start of the insn.
2706 We can't do this after the insn has been output as the current
2707 frag may have been closed off. eg. by frag_var. */
2708 dwarf2_emit_insn (0);
2709
2710 /* Output jumps. */
2711 if (i.tm.opcode_modifier & Jump)
2712 {
2713 int code16;
2714 int prefix;
2715
2716 code16 = 0;
2717 if (flag_code == CODE_16BIT)
2718 code16 = CODE16;
2719
2720 prefix = 0;
2721 if (i.prefix[DATA_PREFIX])
2722 {
2723 prefix = 1;
2724 i.prefixes -= 1;
2725 code16 ^= CODE16;
2726 }
2727 /* Pentium4 branch hints. */
2728 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
2729 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2730 {
2731 prefix++;
2732 i.prefixes--;
2733 }
2734 if (i.prefix[REX_PREFIX])
2735 {
2736 prefix++;
2737 i.prefixes--;
2738 }
2739
2740 if (i.prefixes != 0 && !intel_syntax)
2741 as_warn (_("skipping prefixes on this instruction"));
2742
2743 /* It's always a symbol; End frag & setup for relax.
2744 Make sure there is enough room in this frag for the largest
2745 instruction we may generate in md_convert_frag. This is 2
2746 bytes for the opcode and room for the prefix and largest
2747 displacement. */
2748 frag_grow (prefix + 2 + 4);
2749 /* Prefix and 1 opcode byte go in fr_fix. */
2750 p = frag_more (prefix + 1);
2751 if (i.prefix[DATA_PREFIX])
2752 *p++ = DATA_PREFIX_OPCODE;
2753 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
2754 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
2755 *p++ = i.prefix[SEG_PREFIX];
2756 if (i.prefix[REX_PREFIX])
2757 *p++ = i.prefix[REX_PREFIX];
2758 *p = i.tm.base_opcode;
2759 /* 1 possible extra opcode + displacement go in var part.
2760 Pass reloc in fr_var. */
2761 frag_var (rs_machine_dependent,
2762 1 + 4,
2763 i.reloc[0],
2764 ((unsigned char) *p == JUMP_PC_RELATIVE
2765 ? ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL) | code16
2766 : ((cpu_arch_flags & Cpu386) != 0
2767 ? ENCODE_RELAX_STATE (COND_JUMP, SMALL) | code16
2768 : ENCODE_RELAX_STATE (COND_JUMP86, SMALL) | code16)),
2769 i.op[0].disps->X_add_symbol,
2770 i.op[0].disps->X_add_number,
2771 p);
2772 }
2773 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
2774 {
2775 int size;
2776
2777 if (i.tm.opcode_modifier & JumpByte)
2778 {
2779 /* This is a loop or jecxz type instruction. */
2780 size = 1;
2781 if (i.prefix[ADDR_PREFIX])
2782 {
2783 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
2784 i.prefixes -= 1;
2785 }
2786 /* Pentium4 branch hints. */
2787 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
2788 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2789 {
2790 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
2791 i.prefixes--;
2792 }
2793 }
2794 else
2795 {
2796 int code16;
2797
2798 code16 = 0;
2799 if (flag_code == CODE_16BIT)
2800 code16 = CODE16;
2801
2802 if (i.prefix[DATA_PREFIX])
2803 {
2804 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
2805 i.prefixes -= 1;
2806 code16 ^= CODE16;
2807 }
2808
2809 size = 4;
2810 if (code16)
2811 size = 2;
2812 }
2813
2814 if (i.prefix[REX_PREFIX])
2815 {
2816 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
2817 i.prefixes -= 1;
2818 }
2819
2820 if (i.prefixes != 0 && !intel_syntax)
2821 as_warn (_("skipping prefixes on this instruction"));
2822
2823 p = frag_more (1 + size);
2824 *p++ = i.tm.base_opcode;
2825
2826 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2827 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
2828 }
2829 else if (i.tm.opcode_modifier & JumpInterSegment)
2830 {
2831 int size;
2832 int prefix;
2833 int code16;
2834
2835 code16 = 0;
2836 if (flag_code == CODE_16BIT)
2837 code16 = CODE16;
2838
2839 prefix = 0;
2840 if (i.prefix[DATA_PREFIX])
2841 {
2842 prefix = 1;
2843 i.prefixes -= 1;
2844 code16 ^= CODE16;
2845 }
2846 if (i.prefix[REX_PREFIX])
2847 {
2848 prefix++;
2849 i.prefixes -= 1;
2850 }
2851
2852 size = 4;
2853 if (code16)
2854 size = 2;
2855
2856 if (i.prefixes != 0 && !intel_syntax)
2857 as_warn (_("skipping prefixes on this instruction"));
2858
2859 /* 1 opcode; 2 segment; offset */
2860 p = frag_more (prefix + 1 + 2 + size);
2861
2862 if (i.prefix[DATA_PREFIX])
2863 *p++ = DATA_PREFIX_OPCODE;
2864
2865 if (i.prefix[REX_PREFIX])
2866 *p++ = i.prefix[REX_PREFIX];
2867
2868 *p++ = i.tm.base_opcode;
2869 if (i.op[1].imms->X_op == O_constant)
2870 {
2871 offsetT n = i.op[1].imms->X_add_number;
2872
2873 if (size == 2
2874 && !fits_in_unsigned_word (n)
2875 && !fits_in_signed_word (n))
2876 {
2877 as_bad (_("16-bit jump out of range"));
2878 return;
2879 }
2880 md_number_to_chars (p, n, size);
2881 }
2882 else
2883 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2884 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
2885 if (i.op[0].imms->X_op != O_constant)
2886 as_bad (_("can't handle non absolute segment in `%s'"),
2887 i.tm.name);
2888 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
2889 }
2890 else
2891 {
2892 /* Output normal instructions here. */
2893 unsigned char *q;
2894
2895 /* All opcodes on i386 have eighter 1 or 2 bytes. We may use third
2896 byte for the SSE instructions to specify prefix they require. */
2897 if (i.tm.base_opcode & 0xff0000)
2898 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
2899
2900 /* The prefix bytes. */
2901 for (q = i.prefix;
2902 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
2903 q++)
2904 {
2905 if (*q)
2906 {
2907 p = frag_more (1);
2908 md_number_to_chars (p, (valueT) *q, 1);
2909 }
2910 }
2911
2912 /* Now the opcode; be careful about word order here! */
2913 if (fits_in_unsigned_byte (i.tm.base_opcode))
2914 {
2915 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
2916 }
2917 else
2918 {
2919 p = frag_more (2);
2920 /* Put out high byte first: can't use md_number_to_chars! */
2921 *p++ = (i.tm.base_opcode >> 8) & 0xff;
2922 *p = i.tm.base_opcode & 0xff;
2923 }
2924
2925 /* Now the modrm byte and sib byte (if present). */
2926 if (i.tm.opcode_modifier & Modrm)
2927 {
2928 p = frag_more (1);
2929 md_number_to_chars (p,
2930 (valueT) (i.rm.regmem << 0
2931 | i.rm.reg << 3
2932 | i.rm.mode << 6),
2933 1);
2934 /* If i.rm.regmem == ESP (4)
2935 && i.rm.mode != (Register mode)
2936 && not 16 bit
2937 ==> need second modrm byte. */
2938 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
2939 && i.rm.mode != 3
2940 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
2941 {
2942 p = frag_more (1);
2943 md_number_to_chars (p,
2944 (valueT) (i.sib.base << 0
2945 | i.sib.index << 3
2946 | i.sib.scale << 6),
2947 1);
2948 }
2949 }
2950
2951 if (i.disp_operands)
2952 {
2953 register unsigned int n;
2954
2955 for (n = 0; n < i.operands; n++)
2956 {
2957 if (i.types[n] & Disp)
2958 {
2959 if (i.op[n].disps->X_op == O_constant)
2960 {
2961 int size;
2962 offsetT val;
2963
2964 size = 4;
2965 if (i.types[n] & (Disp8 | Disp16 | Disp64))
2966 {
2967 size = 2;
2968 if (i.types[n] & Disp8)
2969 size = 1;
2970 if (i.types[n] & Disp64)
2971 size = 8;
2972 }
2973 val = offset_in_range (i.op[n].disps->X_add_number,
2974 size);
2975 p = frag_more (size);
2976 md_number_to_chars (p, val, size);
2977 }
2978 else
2979 {
2980 int size = 4;
2981 int sign = 0;
2982 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
2983
2984 /* The PC relative address is computed relative
2985 to the instruction boundary, so in case immediate
2986 fields follows, we need to adjust the value. */
2987 if (pcrel && i.imm_operands)
2988 {
2989 int imm_size = 4;
2990 register unsigned int n1;
2991
2992 for (n1 = 0; n1 < i.operands; n1++)
2993 if (i.types[n1] & Imm)
2994 {
2995 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
2996 {
2997 imm_size = 2;
2998 if (i.types[n1] & (Imm8 | Imm8S))
2999 imm_size = 1;
3000 if (i.types[n1] & Imm64)
3001 imm_size = 8;
3002 }
3003 break;
3004 }
3005 /* We should find the immediate. */
3006 if (n1 == i.operands)
3007 abort ();
3008 i.op[n].disps->X_add_number -= imm_size;
3009 }
3010
3011 if (i.types[n] & Disp32S)
3012 sign = 1;
3013
3014 if (i.types[n] & (Disp16 | Disp64))
3015 {
3016 size = 2;
3017 if (i.types[n] & Disp64)
3018 size = 8;
3019 }
3020
3021 p = frag_more (size);
3022 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3023 i.op[n].disps, pcrel,
3024 reloc (size, pcrel, sign, i.reloc[n]));
3025 }
3026 }
3027 }
3028 }
3029
3030 /* Output immediate. */
3031 if (i.imm_operands)
3032 {
3033 register unsigned int n;
3034
3035 for (n = 0; n < i.operands; n++)
3036 {
3037 if (i.types[n] & Imm)
3038 {
3039 if (i.op[n].imms->X_op == O_constant)
3040 {
3041 int size;
3042 offsetT val;
3043
3044 size = 4;
3045 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3046 {
3047 size = 2;
3048 if (i.types[n] & (Imm8 | Imm8S))
3049 size = 1;
3050 else if (i.types[n] & Imm64)
3051 size = 8;
3052 }
3053 val = offset_in_range (i.op[n].imms->X_add_number,
3054 size);
3055 p = frag_more (size);
3056 md_number_to_chars (p, val, size);
3057 }
3058 else
3059 {
3060 /* Not absolute_section.
3061 Need a 32-bit fixup (don't support 8bit
3062 non-absolute imms). Try to support other
3063 sizes ... */
3064 RELOC_ENUM reloc_type;
3065 int size = 4;
3066 int sign = 0;
3067
3068 if ((i.types[n] & (Imm32S))
3069 && i.suffix == QWORD_MNEM_SUFFIX)
3070 sign = 1;
3071 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3072 {
3073 size = 2;
3074 if (i.types[n] & (Imm8 | Imm8S))
3075 size = 1;
3076 if (i.types[n] & Imm64)
3077 size = 8;
3078 }
3079
3080 p = frag_more (size);
3081 reloc_type = reloc (size, 0, sign, i.reloc[n]);
3082#ifdef BFD_ASSEMBLER
3083 if (reloc_type == BFD_RELOC_32
3084 && GOT_symbol
3085 && GOT_symbol == i.op[n].imms->X_add_symbol
3086 && (i.op[n].imms->X_op == O_symbol
3087 || (i.op[n].imms->X_op == O_add
3088 && ((symbol_get_value_expression
3089 (i.op[n].imms->X_op_symbol)->X_op)
3090 == O_subtract))))
3091 {
3092 /* We don't support dynamic linking on x86-64 yet. */
3093 if (flag_code == CODE_64BIT)
3094 abort ();
3095 reloc_type = BFD_RELOC_386_GOTPC;
3096 i.op[n].imms->X_add_number += 3;
3097 }
3098#endif
3099 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3100 i.op[n].imms, 0, reloc_type);
3101 }
3102 }
3103 }
3104 }
3105 }
3106
3107#ifdef DEBUG386
3108 if (flag_debug)
3109 {
3110 pi (line, &i);
3111 }
3112#endif /* DEBUG386 */
3113 }
3114}
3115
3116#ifndef LEX_AT
3117static char *lex_got PARAMS ((RELOC_ENUM *, int *));
3118
3119/* Parse operands of the form
3120 <symbol>@GOTOFF+<nnn>
3121 and similar .plt or .got references.
3122
3123 If we find one, set up the correct relocation in RELOC and copy the
3124 input string, minus the `@GOTOFF' into a malloc'd buffer for
3125 parsing by the calling routine. Return this buffer, and if ADJUST
3126 is non-null set it to the length of the string we removed from the
3127 input line. Otherwise return NULL. */
3128static char *
3129lex_got (reloc, adjust)
3130 RELOC_ENUM *reloc;
3131 int *adjust;
3132{
3133 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3134 static const struct {
3135 const char *str;
3136 const RELOC_ENUM rel[NUM_FLAG_CODE];
3137 } gotrel[] = {
3138 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3139 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } },
3140 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
3141 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
3142 };
3143 char *cp;
3144 unsigned int j;
3145
3146 for (cp = input_line_pointer; *cp != '@'; cp++)
3147 if (is_end_of_line[(unsigned char) *cp])
3148 return NULL;
3149
3150 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3151 {
3152 int len;
3153
3154 len = strlen (gotrel[j].str);
3155 if (strncmp (cp + 1, gotrel[j].str, len) == 0)
3156 {
3157 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3158 {
3159 int first;
3160 char *tmpbuf;
3161
3162 *reloc = gotrel[j].rel[(unsigned int) flag_code];
3163
3164 if (GOT_symbol == NULL)
3165 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3166
3167 /* Replace the relocation token with ' ', so that
3168 errors like foo@GOTOFF1 will be detected. */
3169 first = cp - input_line_pointer;
3170 tmpbuf = xmalloc (strlen (input_line_pointer));
3171 memcpy (tmpbuf, input_line_pointer, first);
3172 tmpbuf[first] = ' ';
3173 strcpy (tmpbuf + first + 1, cp + 1 + len);
3174 if (adjust)
3175 *adjust = len;
3176 return tmpbuf;
3177 }
3178
3179 as_bad (_("@%s reloc is not supported in %s bit mode"),
3180 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3181 return NULL;
3182 }
3183 }
3184
3185 /* Might be a symbol version string. Don't as_bad here. */
3186 return NULL;
3187}
3188
3189/* x86_cons_fix_new is called via the expression parsing code when a
3190 reloc is needed. We use this hook to get the correct .got reloc. */
3191static RELOC_ENUM got_reloc = NO_RELOC;
3192
3193void
3194x86_cons_fix_new (frag, off, len, exp)
3195 fragS *frag;
3196 unsigned int off;
3197 unsigned int len;
3198 expressionS *exp;
3199{
3200 RELOC_ENUM r = reloc (len, 0, 0, got_reloc);
3201 got_reloc = NO_RELOC;
3202 fix_new_exp (frag, off, len, exp, 0, r);
3203}
3204
3205void
3206x86_cons (exp, size)
3207 expressionS *exp;
3208 int size;
3209{
3210 if (size == 4)
3211 {
3212 /* Handle @GOTOFF and the like in an expression. */
3213 char *save;
3214 char *gotfree_input_line;
3215 int adjust;
3216
3217 save = input_line_pointer;
3218 gotfree_input_line = lex_got (&got_reloc, &adjust);
3219 if (gotfree_input_line)
3220 input_line_pointer = gotfree_input_line;
3221
3222 expression (exp);
3223
3224 if (gotfree_input_line)
3225 {
3226 /* expression () has merrily parsed up to the end of line,
3227 or a comma - in the wrong buffer. Transfer how far
3228 input_line_pointer has moved to the right buffer. */
3229 input_line_pointer = (save
3230 + (input_line_pointer - gotfree_input_line)
3231 + adjust);
3232 free (gotfree_input_line);
3233 }
3234 }
3235 else
3236 expression (exp);
3237}
3238#endif
3239
3240static int i386_immediate PARAMS ((char *));
3241
3242static int
3243i386_immediate (imm_start)
3244 char *imm_start;
3245{
3246 char *save_input_line_pointer;
3247#ifndef LEX_AT
3248 char *gotfree_input_line;
3249#endif
3250 segT exp_seg = 0;
3251 expressionS *exp;
3252
3253 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3254 {
3255 as_bad (_("only 1 or 2 immediate operands are allowed"));
3256 return 0;
3257 }
3258
3259 exp = &im_expressions[i.imm_operands++];
3260 i.op[this_operand].imms = exp;
3261
3262 if (is_space_char (*imm_start))
3263 ++imm_start;
3264
3265 save_input_line_pointer = input_line_pointer;
3266 input_line_pointer = imm_start;
3267
3268#ifndef LEX_AT
3269 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3270 if (gotfree_input_line)
3271 input_line_pointer = gotfree_input_line;
3272#endif
3273
3274 exp_seg = expression (exp);
3275
3276 SKIP_WHITESPACE ();
3277 if (*input_line_pointer)
3278 as_bad (_("junk `%s' after expression"), input_line_pointer);
3279
3280 input_line_pointer = save_input_line_pointer;
3281#ifndef LEX_AT
3282 if (gotfree_input_line)
3283 free (gotfree_input_line);
3284#endif
3285
3286 if (exp->X_op == O_absent || exp->X_op == O_big)
3287 {
3288 /* Missing or bad expr becomes absolute 0. */
3289 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3290 imm_start);
3291 exp->X_op = O_constant;
3292 exp->X_add_number = 0;
3293 exp->X_add_symbol = (symbolS *) 0;
3294 exp->X_op_symbol = (symbolS *) 0;
3295 }
3296 else if (exp->X_op == O_constant)
3297 {
3298 /* Size it properly later. */
3299 i.types[this_operand] |= Imm64;
3300 /* If BFD64, sign extend val. */
3301 if (!use_rela_relocations)
3302 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3303 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
3304 }
3305#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3306 else if (1
3307#ifdef BFD_ASSEMBLER
3308 && OUTPUT_FLAVOR == bfd_target_aout_flavour
3309#endif
3310 && exp_seg != text_section
3311 && exp_seg != data_section
3312 && exp_seg != bss_section
3313 && exp_seg != undefined_section
3314#ifdef BFD_ASSEMBLER
3315 && !bfd_is_com_section (exp_seg)
3316#endif
3317 )
3318 {
3319#ifdef BFD_ASSEMBLER
3320 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3321#else
3322 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
3323#endif
3324 return 0;
3325 }
3326#endif
3327 else
3328 {
3329 /* This is an address. The size of the address will be
3330 determined later, depending on destination register,
3331 suffix, or the default for the section. */
3332 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3333 }
3334
3335 return 1;
3336}
3337
3338static char *i386_scale PARAMS ((char *));
3339
3340static char *
3341i386_scale (scale)
3342 char *scale;
3343{
3344 offsetT val;
3345 char *save = input_line_pointer;
3346
3347 input_line_pointer = scale;
3348 val = get_absolute_expression ();
3349
3350 switch (val)
3351 {
3352 case 0:
3353 case 1:
3354 i.log2_scale_factor = 0;
3355 break;
3356 case 2:
3357 i.log2_scale_factor = 1;
3358 break;
3359 case 4:
3360 i.log2_scale_factor = 2;
3361 break;
3362 case 8:
3363 i.log2_scale_factor = 3;
3364 break;
3365 default:
3366 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3367 scale);
3368 input_line_pointer = save;
3369 return NULL;
3370 }
3371 if (i.log2_scale_factor != 0 && ! i.index_reg)
3372 {
3373 as_warn (_("scale factor of %d without an index register"),
3374 1 << i.log2_scale_factor);
3375#if SCALE1_WHEN_NO_INDEX
3376 i.log2_scale_factor = 0;
3377#endif
3378 }
3379 scale = input_line_pointer;
3380 input_line_pointer = save;
3381 return scale;
3382}
3383
3384static int i386_displacement PARAMS ((char *, char *));
3385
3386static int
3387i386_displacement (disp_start, disp_end)
3388 char *disp_start;
3389 char *disp_end;
3390{
3391 register expressionS *exp;
3392 segT exp_seg = 0;
3393 char *save_input_line_pointer;
3394#ifndef LEX_AT
3395 char *gotfree_input_line;
3396#endif
3397 int bigdisp = Disp32;
3398
3399 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3400 bigdisp = Disp16;
3401 if (flag_code == CODE_64BIT)
3402 bigdisp = Disp64;
3403 i.types[this_operand] |= bigdisp;
3404
3405 exp = &disp_expressions[i.disp_operands];
3406 i.op[this_operand].disps = exp;
3407 i.disp_operands++;
3408 save_input_line_pointer = input_line_pointer;
3409 input_line_pointer = disp_start;
3410 END_STRING_AND_SAVE (disp_end);
3411
3412#ifndef GCC_ASM_O_HACK
3413#define GCC_ASM_O_HACK 0
3414#endif
3415#if GCC_ASM_O_HACK
3416 END_STRING_AND_SAVE (disp_end + 1);
3417 if ((i.types[this_operand] & BaseIndex) != 0
3418 && displacement_string_end[-1] == '+')
3419 {
3420 /* This hack is to avoid a warning when using the "o"
3421 constraint within gcc asm statements.
3422 For instance:
3423
3424 #define _set_tssldt_desc(n,addr,limit,type) \
3425 __asm__ __volatile__ ( \
3426 "movw %w2,%0\n\t" \
3427 "movw %w1,2+%0\n\t" \
3428 "rorl $16,%1\n\t" \
3429 "movb %b1,4+%0\n\t" \
3430 "movb %4,5+%0\n\t" \
3431 "movb $0,6+%0\n\t" \
3432 "movb %h1,7+%0\n\t" \
3433 "rorl $16,%1" \
3434 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3435
3436 This works great except that the output assembler ends
3437 up looking a bit weird if it turns out that there is
3438 no offset. You end up producing code that looks like:
3439
3440 #APP
3441 movw $235,(%eax)
3442 movw %dx,2+(%eax)
3443 rorl $16,%edx
3444 movb %dl,4+(%eax)
3445 movb $137,5+(%eax)
3446 movb $0,6+(%eax)
3447 movb %dh,7+(%eax)
3448 rorl $16,%edx
3449 #NO_APP
3450
3451 So here we provide the missing zero. */
3452
3453 *displacement_string_end = '0';
3454 }
3455#endif
3456#ifndef LEX_AT
3457 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3458 if (gotfree_input_line)
3459 input_line_pointer = gotfree_input_line;
3460#endif
3461
3462 exp_seg = expression (exp);
3463
3464 SKIP_WHITESPACE ();
3465 if (*input_line_pointer)
3466 as_bad (_("junk `%s' after expression"), input_line_pointer);
3467#if GCC_ASM_O_HACK
3468 RESTORE_END_STRING (disp_end + 1);
3469#endif
3470 RESTORE_END_STRING (disp_end);
3471 input_line_pointer = save_input_line_pointer;
3472#ifndef LEX_AT
3473 if (gotfree_input_line)
3474 free (gotfree_input_line);
3475#endif
3476
3477#ifdef BFD_ASSEMBLER
3478 /* We do this to make sure that the section symbol is in
3479 the symbol table. We will ultimately change the relocation
3480 to be relative to the beginning of the section. */
3481 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
3482 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
3483 {
3484 if (exp->X_op != O_symbol)
3485 {
3486 as_bad (_("bad expression used with @%s"),
3487 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
3488 ? "GOTPCREL"
3489 : "GOTOFF"));
3490 return 0;
3491 }
3492
3493 if (S_IS_LOCAL (exp->X_add_symbol)
3494 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
3495 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
3496 exp->X_op = O_subtract;
3497 exp->X_op_symbol = GOT_symbol;
3498 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
3499 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
3500 else
3501 i.reloc[this_operand] = BFD_RELOC_32;
3502 }
3503#endif
3504
3505 if (exp->X_op == O_absent || exp->X_op == O_big)
3506 {
3507 /* Missing or bad expr becomes absolute 0. */
3508 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3509 disp_start);
3510 exp->X_op = O_constant;
3511 exp->X_add_number = 0;
3512 exp->X_add_symbol = (symbolS *) 0;
3513 exp->X_op_symbol = (symbolS *) 0;
3514 }
3515
3516#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3517 if (exp->X_op != O_constant
3518#ifdef BFD_ASSEMBLER
3519 && OUTPUT_FLAVOR == bfd_target_aout_flavour
3520#endif
3521 && exp_seg != text_section
3522 && exp_seg != data_section
3523 && exp_seg != bss_section
3524 && exp_seg != undefined_section)
3525 {
3526#ifdef BFD_ASSEMBLER
3527 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3528#else
3529 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
3530#endif
3531 return 0;
3532 }
3533#endif
3534 else if (flag_code == CODE_64BIT)
3535 i.types[this_operand] |= Disp32S | Disp32;
3536 return 1;
3537}
3538
3539static int i386_index_check PARAMS ((const char *));
3540
3541/* Make sure the memory operand we've been dealt is valid.
3542 Return 1 on success, 0 on a failure. */
3543
3544static int
3545i386_index_check (operand_string)
3546 const char *operand_string;
3547{
3548 int ok;
3549#if INFER_ADDR_PREFIX
3550 int fudged = 0;
3551
3552 tryprefix:
3553#endif
3554 ok = 1;
3555 if (flag_code == CODE_64BIT)
3556 {
3557 /* 64bit checks. */
3558 if ((i.base_reg
3559 && ((i.base_reg->reg_type & Reg64) == 0)
3560 && (i.base_reg->reg_type != BaseIndex
3561 || i.index_reg))
3562 || (i.index_reg
3563 && ((i.index_reg->reg_type & (Reg64|BaseIndex))
3564 != (Reg64|BaseIndex))))
3565 ok = 0;
3566 }
3567 else
3568 {
3569 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3570 {
3571 /* 16bit checks. */
3572 if ((i.base_reg
3573 && ((i.base_reg->reg_type & (Reg16|BaseIndex|RegRex))
3574 != (Reg16|BaseIndex)))
3575 || (i.index_reg
3576 && (((i.index_reg->reg_type & (Reg16|BaseIndex))
3577 != (Reg16|BaseIndex))
3578 || ! (i.base_reg
3579 && i.base_reg->reg_num < 6
3580 && i.index_reg->reg_num >= 6
3581 && i.log2_scale_factor == 0))))
3582 ok = 0;
3583 }
3584 else
3585 {
3586 /* 32bit checks. */
3587 if ((i.base_reg
3588 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3589 || (i.index_reg
3590 && ((i.index_reg->reg_type & (Reg32|BaseIndex|RegRex))
3591 != (Reg32|BaseIndex))))
3592 ok = 0;
3593 }
3594 }
3595 if (!ok)
3596 {
3597#if INFER_ADDR_PREFIX
3598 if (flag_code != CODE_64BIT
3599 && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
3600 {
3601 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
3602 i.prefixes += 1;
3603 /* Change the size of any displacement too. At most one of
3604 Disp16 or Disp32 is set.
3605 FIXME. There doesn't seem to be any real need for separate
3606 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3607 Removing them would probably clean up the code quite a lot. */
3608 if (i.types[this_operand] & (Disp16|Disp32))
3609 i.types[this_operand] ^= (Disp16|Disp32);
3610 fudged = 1;
3611 goto tryprefix;
3612 }
3613 if (fudged)
3614 as_bad (_("`%s' is not a valid base/index expression"),
3615 operand_string);
3616 else
3617#endif
3618 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3619 operand_string,
3620 flag_code_names[flag_code]);
3621 return 0;
3622 }
3623 return 1;
3624}
3625
3626/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3627 on error. */
3628
3629static int
3630i386_operand (operand_string)
3631 char *operand_string;
3632{
3633 const reg_entry *r;
3634 char *end_op;
3635 char *op_string = operand_string;
3636
3637 if (is_space_char (*op_string))
3638 ++op_string;
3639
3640 /* We check for an absolute prefix (differentiating,
3641 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3642 if (*op_string == ABSOLUTE_PREFIX)
3643 {
3644 ++op_string;
3645 if (is_space_char (*op_string))
3646 ++op_string;
3647 i.types[this_operand] |= JumpAbsolute;
3648 }
3649
3650 /* Check if operand is a register. */
3651 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
3652 && (r = parse_register (op_string, &end_op)) != NULL)
3653 {
3654 /* Check for a segment override by searching for ':' after a
3655 segment register. */
3656 op_string = end_op;
3657 if (is_space_char (*op_string))
3658 ++op_string;
3659 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
3660 {
3661 switch (r->reg_num)
3662 {
3663 case 0:
3664 i.seg[i.mem_operands] = &es;
3665 break;
3666 case 1:
3667 i.seg[i.mem_operands] = &cs;
3668 break;
3669 case 2:
3670 i.seg[i.mem_operands] = &ss;
3671 break;
3672 case 3:
3673 i.seg[i.mem_operands] = &ds;
3674 break;
3675 case 4:
3676 i.seg[i.mem_operands] = &fs;
3677 break;
3678 case 5:
3679 i.seg[i.mem_operands] = &gs;
3680 break;
3681 }
3682
3683 /* Skip the ':' and whitespace. */
3684 ++op_string;
3685 if (is_space_char (*op_string))
3686 ++op_string;
3687
3688 if (!is_digit_char (*op_string)
3689 && !is_identifier_char (*op_string)
3690 && *op_string != '('
3691 && *op_string != ABSOLUTE_PREFIX)
3692 {
3693 as_bad (_("bad memory operand `%s'"), op_string);
3694 return 0;
3695 }
3696 /* Handle case of %es:*foo. */
3697 if (*op_string == ABSOLUTE_PREFIX)
3698 {
3699 ++op_string;
3700 if (is_space_char (*op_string))
3701 ++op_string;
3702 i.types[this_operand] |= JumpAbsolute;
3703 }
3704 goto do_memory_reference;
3705 }
3706 if (*op_string)
3707 {
3708 as_bad (_("junk `%s' after register"), op_string);
3709 return 0;
3710 }
3711 i.types[this_operand] |= r->reg_type & ~BaseIndex;
3712 i.op[this_operand].regs = r;
3713 i.reg_operands++;
3714 }
3715 else if (*op_string == REGISTER_PREFIX)
3716 {
3717 as_bad (_("bad register name `%s'"), op_string);
3718 return 0;
3719 }
3720 else if (*op_string == IMMEDIATE_PREFIX)
3721 {
3722 ++op_string;
3723 if (i.types[this_operand] & JumpAbsolute)
3724 {
3725 as_bad (_("immediate operand illegal with absolute jump"));
3726 return 0;
3727 }
3728 if (!i386_immediate (op_string))
3729 return 0;
3730 }
3731 else if (is_digit_char (*op_string)
3732 || is_identifier_char (*op_string)
3733 || *op_string == '(')
3734 {
3735 /* This is a memory reference of some sort. */
3736 char *base_string;
3737
3738 /* Start and end of displacement string expression (if found). */
3739 char *displacement_string_start;
3740 char *displacement_string_end;
3741
3742 do_memory_reference:
3743 if ((i.mem_operands == 1
3744 && (current_templates->start->opcode_modifier & IsString) == 0)
3745 || i.mem_operands == 2)
3746 {
3747 as_bad (_("too many memory references for `%s'"),
3748 current_templates->start->name);
3749 return 0;
3750 }
3751
3752 /* Check for base index form. We detect the base index form by
3753 looking for an ')' at the end of the operand, searching
3754 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3755 after the '('. */
3756 base_string = op_string + strlen (op_string);
3757
3758 --base_string;
3759 if (is_space_char (*base_string))
3760 --base_string;
3761
3762 /* If we only have a displacement, set-up for it to be parsed later. */
3763 displacement_string_start = op_string;
3764 displacement_string_end = base_string + 1;
3765
3766 if (*base_string == ')')
3767 {
3768 char *temp_string;
3769 unsigned int parens_balanced = 1;
3770 /* We've already checked that the number of left & right ()'s are
3771 equal, so this loop will not be infinite. */
3772 do
3773 {
3774 base_string--;
3775 if (*base_string == ')')
3776 parens_balanced++;
3777 if (*base_string == '(')
3778 parens_balanced--;
3779 }
3780 while (parens_balanced);
3781
3782 temp_string = base_string;
3783
3784 /* Skip past '(' and whitespace. */
3785 ++base_string;
3786 if (is_space_char (*base_string))
3787 ++base_string;
3788
3789 if (*base_string == ','
3790 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
3791 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
3792 {
3793 displacement_string_end = temp_string;
3794
3795 i.types[this_operand] |= BaseIndex;
3796
3797 if (i.base_reg)
3798 {
3799 base_string = end_op;
3800 if (is_space_char (*base_string))
3801 ++base_string;
3802 }
3803
3804 /* There may be an index reg or scale factor here. */
3805 if (*base_string == ',')
3806 {
3807 ++base_string;
3808 if (is_space_char (*base_string))
3809 ++base_string;
3810
3811 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
3812 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
3813 {
3814 base_string = end_op;
3815 if (is_space_char (*base_string))
3816 ++base_string;
3817 if (*base_string == ',')
3818 {
3819 ++base_string;
3820 if (is_space_char (*base_string))
3821 ++base_string;
3822 }
3823 else if (*base_string != ')')
3824 {
3825 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3826 operand_string);
3827 return 0;
3828 }
3829 }
3830 else if (*base_string == REGISTER_PREFIX)
3831 {
3832 as_bad (_("bad register name `%s'"), base_string);
3833 return 0;
3834 }
3835
3836 /* Check for scale factor. */
3837 if (*base_string != ')')
3838 {
3839 char *end_scale = i386_scale (base_string);
3840
3841 if (!end_scale)
3842 return 0;
3843
3844 base_string = end_scale;
3845 if (is_space_char (*base_string))
3846 ++base_string;
3847 if (*base_string != ')')
3848 {
3849 as_bad (_("expecting `)' after scale factor in `%s'"),
3850 operand_string);
3851 return 0;
3852 }
3853 }
3854 else if (!i.index_reg)
3855 {
3856 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3857 *base_string);
3858 return 0;
3859 }
3860 }
3861 else if (*base_string != ')')
3862 {
3863 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3864 operand_string);
3865 return 0;
3866 }
3867 }
3868 else if (*base_string == REGISTER_PREFIX)
3869 {
3870 as_bad (_("bad register name `%s'"), base_string);
3871 return 0;
3872 }
3873 }
3874
3875 /* If there's an expression beginning the operand, parse it,
3876 assuming displacement_string_start and
3877 displacement_string_end are meaningful. */
3878 if (displacement_string_start != displacement_string_end)
3879 {
3880 if (!i386_displacement (displacement_string_start,
3881 displacement_string_end))
3882 return 0;
3883 }
3884
3885 /* Special case for (%dx) while doing input/output op. */
3886 if (i.base_reg
3887 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
3888 && i.index_reg == 0
3889 && i.log2_scale_factor == 0
3890 && i.seg[i.mem_operands] == 0
3891 && (i.types[this_operand] & Disp) == 0)
3892 {
3893 i.types[this_operand] = InOutPortReg;
3894 return 1;
3895 }
3896
3897 if (i386_index_check (operand_string) == 0)
3898 return 0;
3899 i.mem_operands++;
3900 }
3901 else
3902 {
3903 /* It's not a memory operand; argh! */
3904 as_bad (_("invalid char %s beginning operand %d `%s'"),
3905 output_invalid (*op_string),
3906 this_operand + 1,
3907 op_string);
3908 return 0;
3909 }
3910 return 1; /* Normal return. */
3911}
3912
3913/* md_estimate_size_before_relax()
3914
3915 Called just before relax() for rs_machine_dependent frags. The x86
3916 assembler uses these frags to handle variable size jump
3917 instructions.
3918
3919 Any symbol that is now undefined will not become defined.
3920 Return the correct fr_subtype in the frag.
3921 Return the initial "guess for variable size of frag" to caller.
3922 The guess is actually the growth beyond the fixed part. Whatever
3923 we do to grow the fixed or variable part contributes to our
3924 returned value. */
3925
3926int
3927md_estimate_size_before_relax (fragP, segment)
3928 register fragS *fragP;
3929 register segT segment;
3930{
3931 /* We've already got fragP->fr_subtype right; all we have to do is
3932 check for un-relaxable symbols. On an ELF system, we can't relax
3933 an externally visible symbol, because it may be overridden by a
3934 shared library. */
3935 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
3936#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3937 || S_IS_EXTERNAL (fragP->fr_symbol)
3938 || S_IS_WEAK (fragP->fr_symbol)
3939#endif
3940 )
3941 {
3942 /* Symbol is undefined in this segment, or we need to keep a
3943 reloc so that weak symbols can be overridden. */
3944 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
3945 RELOC_ENUM reloc_type;
3946 unsigned char *opcode;
3947 int old_fr_fix;
3948
3949 if (fragP->fr_var != NO_RELOC)
3950 reloc_type = fragP->fr_var;
3951 else if (size == 2)
3952 reloc_type = BFD_RELOC_16_PCREL;
3953 else
3954 reloc_type = BFD_RELOC_32_PCREL;
3955
3956 old_fr_fix = fragP->fr_fix;
3957 opcode = (unsigned char *) fragP->fr_opcode;
3958
3959 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
3960 {
3961 case UNCOND_JUMP:
3962 /* Make jmp (0xeb) a (d)word displacement jump. */
3963 opcode[0] = 0xe9;
3964 fragP->fr_fix += size;
3965 fix_new (fragP, old_fr_fix, size,
3966 fragP->fr_symbol,
3967 fragP->fr_offset, 1,
3968 reloc_type);
3969 break;
3970
3971 case COND_JUMP86:
3972 if (no_cond_jump_promotion)
3973 goto relax_guess;
3974
3975 if (size == 2)
3976 {
3977 /* Negate the condition, and branch past an
3978 unconditional jump. */
3979 opcode[0] ^= 1;
3980 opcode[1] = 3;
3981 /* Insert an unconditional jump. */
3982 opcode[2] = 0xe9;
3983 /* We added two extra opcode bytes, and have a two byte
3984 offset. */
3985 fragP->fr_fix += 2 + 2;
3986 fix_new (fragP, old_fr_fix + 2, 2,
3987 fragP->fr_symbol,
3988 fragP->fr_offset, 1,
3989 reloc_type);
3990 break;
3991 }
3992 /* Fall through. */
3993
3994 case COND_JUMP:
3995 if (no_cond_jump_promotion)
3996 goto relax_guess;
3997
3998 /* This changes the byte-displacement jump 0x7N
3999 to the (d)word-displacement jump 0x0f,0x8N. */
4000 opcode[1] = opcode[0] + 0x10;
4001 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4002 /* We've added an opcode byte. */
4003 fragP->fr_fix += 1 + size;
4004 fix_new (fragP, old_fr_fix + 1, size,
4005 fragP->fr_symbol,
4006 fragP->fr_offset, 1,
4007 reloc_type);
4008 break;
4009
4010 default:
4011 BAD_CASE (fragP->fr_subtype);
4012 break;
4013 }
4014 frag_wane (fragP);
4015 return fragP->fr_fix - old_fr_fix;
4016 }
4017
4018 relax_guess:
4019 /* Guess size depending on current relax state. Initially the relax
4020 state will correspond to a short jump and we return 1, because
4021 the variable part of the frag (the branch offset) is one byte
4022 long. However, we can relax a section more than once and in that
4023 case we must either set fr_subtype back to the unrelaxed state,
4024 or return the value for the appropriate branch. */
4025 return md_relax_table[fragP->fr_subtype].rlx_length;
4026}
4027
4028/* Called after relax() is finished.
4029
4030 In: Address of frag.
4031 fr_type == rs_machine_dependent.
4032 fr_subtype is what the address relaxed to.
4033
4034 Out: Any fixSs and constants are set up.
4035 Caller will turn frag into a ".space 0". */
4036
4037#ifndef BFD_ASSEMBLER
4038void
4039md_convert_frag (headers, sec, fragP)
4040 object_headers *headers ATTRIBUTE_UNUSED;
4041 segT sec ATTRIBUTE_UNUSED;
4042 register fragS *fragP;
4043#else
4044void
4045md_convert_frag (abfd, sec, fragP)
4046 bfd *abfd ATTRIBUTE_UNUSED;
4047 segT sec ATTRIBUTE_UNUSED;
4048 register fragS *fragP;
4049#endif
4050{
4051 register unsigned char *opcode;
4052 unsigned char *where_to_put_displacement = NULL;
4053 offsetT target_address;
4054 offsetT opcode_address;
4055 unsigned int extension = 0;
4056 offsetT displacement_from_opcode_start;
4057
4058 opcode = (unsigned char *) fragP->fr_opcode;
4059
4060 /* Address we want to reach in file space. */
4061 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
4062#ifdef BFD_ASSEMBLER
4063 /* Not needed otherwise? */
4064 {
4065 /* Local symbols which have already been resolved have a NULL frag. */
4066 fragS *sym_frag = symbol_get_frag (fragP->fr_symbol);
4067 if (sym_frag)
4068 target_address += sym_frag->fr_address;
4069 }
4070#endif
4071
4072 /* Address opcode resides at in file space. */
4073 opcode_address = fragP->fr_address + fragP->fr_fix;
4074
4075 /* Displacement from opcode start to fill into instruction. */
4076 displacement_from_opcode_start = target_address - opcode_address;
4077
4078 if ((fragP->fr_subtype & BIG) == 0)
4079 {
4080 /* Don't have to change opcode. */
4081 extension = 1; /* 1 opcode + 1 displacement */
4082 where_to_put_displacement = &opcode[1];
4083 }
4084 else
4085 {
4086 if (no_cond_jump_promotion
4087 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4088 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
4089
4090 switch (fragP->fr_subtype)
4091 {
4092 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4093 extension = 4; /* 1 opcode + 4 displacement */
4094 opcode[0] = 0xe9;
4095 where_to_put_displacement = &opcode[1];
4096 break;
4097
4098 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4099 extension = 2; /* 1 opcode + 2 displacement */
4100 opcode[0] = 0xe9;
4101 where_to_put_displacement = &opcode[1];
4102 break;
4103
4104 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4105 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4106 extension = 5; /* 2 opcode + 4 displacement */
4107 opcode[1] = opcode[0] + 0x10;
4108 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4109 where_to_put_displacement = &opcode[2];
4110 break;
4111
4112 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4113 extension = 3; /* 2 opcode + 2 displacement */
4114 opcode[1] = opcode[0] + 0x10;
4115 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4116 where_to_put_displacement = &opcode[2];
4117 break;
4118
4119 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4120 extension = 4;
4121 opcode[0] ^= 1;
4122 opcode[1] = 3;
4123 opcode[2] = 0xe9;
4124 where_to_put_displacement = &opcode[3];
4125 break;
4126
4127 default:
4128 BAD_CASE (fragP->fr_subtype);
4129 break;
4130 }
4131 }
4132
4133 /* Now put displacement after opcode. */
4134 md_number_to_chars ((char *) where_to_put_displacement,
4135 (valueT) (displacement_from_opcode_start - extension),
4136 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
4137 fragP->fr_fix += extension;
4138}
4139
4140/* Size of byte displacement jmp. */
4141int md_short_jump_size = 2;
4142
4143/* Size of dword displacement jmp. */
4144int md_long_jump_size = 5;
4145
4146/* Size of relocation record. */
4147const int md_reloc_size = 8;
4148
4149void
4150md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4151 char *ptr;
4152 addressT from_addr, to_addr;
4153 fragS *frag ATTRIBUTE_UNUSED;
4154 symbolS *to_symbol ATTRIBUTE_UNUSED;
4155{
4156 offsetT offset;
4157
4158 offset = to_addr - (from_addr + 2);
4159 /* Opcode for byte-disp jump. */
4160 md_number_to_chars (ptr, (valueT) 0xeb, 1);
4161 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4162}
4163
4164void
4165md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4166 char *ptr;
4167 addressT from_addr, to_addr;
4168 fragS *frag ATTRIBUTE_UNUSED;
4169 symbolS *to_symbol ATTRIBUTE_UNUSED;
4170{
4171 offsetT offset;
4172
4173 offset = to_addr - (from_addr + 5);
4174 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4175 md_number_to_chars (ptr + 1, (valueT) offset, 4);
4176}
4177
4178/* Apply a fixup (fixS) to segment data, once it has been determined
4179 by our caller that we have all the info we need to fix it up.
4180
4181 On the 386, immediates, displacements, and data pointers are all in
4182 the same (little-endian) format, so we don't need to care about which
4183 we are handling. */
4184
4185int
4186md_apply_fix3 (fixP, valp, seg)
4187 /* The fix we're to put in. */
4188 fixS *fixP;
4189
4190 /* Pointer to the value of the bits. */
4191 valueT *valp;
4192
4193 /* Segment fix is from. */
4194 segT seg ATTRIBUTE_UNUSED;
4195{
4196 register char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
4197 valueT value = *valp;
4198
4199#if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4200 if (fixP->fx_pcrel)
4201 {
4202 switch (fixP->fx_r_type)
4203 {
4204 default:
4205 break;
4206
4207 case BFD_RELOC_32:
4208 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4209 break;
4210 case BFD_RELOC_16:
4211 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4212 break;
4213 case BFD_RELOC_8:
4214 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4215 break;
4216 }
4217 }
4218
4219 /* This is a hack. There should be a better way to handle this.
4220 This covers for the fact that bfd_install_relocation will
4221 subtract the current location (for partial_inplace, PC relative
4222 relocations); see more below. */
4223 if ((fixP->fx_r_type == BFD_RELOC_32_PCREL
4224 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4225 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4226 && fixP->fx_addsy && !use_rela_relocations)
4227 {
4228#ifndef OBJ_AOUT
4229 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4230#ifdef TE_PE
4231 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4232#endif
4233 )
4234 value += fixP->fx_where + fixP->fx_frag->fr_address;
4235#endif
4236#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4237 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
4238 {
4239 segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
4240
4241 if ((fseg == seg
4242 || (symbol_section_p (fixP->fx_addsy)
4243 && fseg != absolute_section))
4244 && ! S_IS_EXTERNAL (fixP->fx_addsy)
4245 && ! S_IS_WEAK (fixP->fx_addsy)
4246 && S_IS_DEFINED (fixP->fx_addsy)
4247 && ! S_IS_COMMON (fixP->fx_addsy))
4248 {
4249 /* Yes, we add the values in twice. This is because
4250 bfd_perform_relocation subtracts them out again. I think
4251 bfd_perform_relocation is broken, but I don't dare change
4252 it. FIXME. */
4253 value += fixP->fx_where + fixP->fx_frag->fr_address;
4254 }
4255 }
4256#endif
4257#if defined (OBJ_COFF) && defined (TE_PE)
4258 /* For some reason, the PE format does not store a section
4259 address offset for a PC relative symbol. */
4260 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
4261 value += md_pcrel_from (fixP);
4262#endif
4263 }
4264
4265 /* Fix a few things - the dynamic linker expects certain values here,
4266 and we must not dissappoint it. */
4267#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4268 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4269 && fixP->fx_addsy)
4270 switch (fixP->fx_r_type)
4271 {
4272 case BFD_RELOC_386_PLT32:
4273 case BFD_RELOC_X86_64_PLT32:
4274 /* Make the jump instruction point to the address of the operand. At
4275 runtime we merely add the offset to the actual PLT entry. */
4276 value = -4;
4277 break;
4278 case BFD_RELOC_386_GOTPC:
4279
4280/* This is tough to explain. We end up with this one if we have
4281 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4282 * here is to obtain the absolute address of the GOT, and it is strongly
4283 * preferable from a performance point of view to avoid using a runtime
4284 * relocation for this. The actual sequence of instructions often look
4285 * something like:
4286 *
4287 * call .L66
4288 * .L66:
4289 * popl %ebx
4290 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4291 *
4292 * The call and pop essentially return the absolute address of
4293 * the label .L66 and store it in %ebx. The linker itself will
4294 * ultimately change the first operand of the addl so that %ebx points to
4295 * the GOT, but to keep things simple, the .o file must have this operand
4296 * set so that it generates not the absolute address of .L66, but the
4297 * absolute address of itself. This allows the linker itself simply
4298 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4299 * added in, and the addend of the relocation is stored in the operand
4300 * field for the instruction itself.
4301 *
4302 * Our job here is to fix the operand so that it would add the correct
4303 * offset so that %ebx would point to itself. The thing that is tricky is
4304 * that .-.L66 will point to the beginning of the instruction, so we need
4305 * to further modify the operand so that it will point to itself.
4306 * There are other cases where you have something like:
4307 *
4308 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4309 *
4310 * and here no correction would be required. Internally in the assembler
4311 * we treat operands of this form as not being pcrel since the '.' is
4312 * explicitly mentioned, and I wonder whether it would simplify matters
4313 * to do it this way. Who knows. In earlier versions of the PIC patches,
4314 * the pcrel_adjust field was used to store the correction, but since the
4315 * expression is not pcrel, I felt it would be confusing to do it this
4316 * way. */
4317
4318 value -= 1;
4319 break;
4320 case BFD_RELOC_386_GOT32:
4321 case BFD_RELOC_X86_64_GOT32:
4322 value = 0; /* Fully resolved at runtime. No addend. */
4323 break;
4324 case BFD_RELOC_386_GOTOFF:
4325 case BFD_RELOC_X86_64_GOTPCREL:
4326 break;
4327
4328 case BFD_RELOC_VTABLE_INHERIT:
4329 case BFD_RELOC_VTABLE_ENTRY:
4330 fixP->fx_done = 0;
4331 return 1;
4332
4333 default:
4334 break;
4335 }
4336#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4337 *valp = value;
4338#endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4339
4340#ifndef BFD_ASSEMBLER
4341 md_number_to_chars (p, value, fixP->fx_size);
4342#else
4343 /* Are we finished with this relocation now? */
4344 if (fixP->fx_addsy == 0 && fixP->fx_pcrel == 0)
4345 fixP->fx_done = 1;
4346 else if (use_rela_relocations)
4347 {
4348 fixP->fx_no_overflow = 1;
4349 value = 0;
4350 }
4351 md_number_to_chars (p, value, fixP->fx_size);
4352#endif
4353
4354 return 1;
4355}
4356
4357#define MAX_LITTLENUMS 6
4358
4359/* Turn the string pointed to by litP into a floating point constant
4360 of type TYPE, and emit the appropriate bytes. The number of
4361 LITTLENUMS emitted is stored in *SIZEP. An error message is
4362 returned, or NULL on OK. */
4363
4364char *
4365md_atof (type, litP, sizeP)
4366 int type;
4367 char *litP;
4368 int *sizeP;
4369{
4370 int prec;
4371 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4372 LITTLENUM_TYPE *wordP;
4373 char *t;
4374
4375 switch (type)
4376 {
4377 case 'f':
4378 case 'F':
4379 prec = 2;
4380 break;
4381
4382 case 'd':
4383 case 'D':
4384 prec = 4;
4385 break;
4386
4387 case 'x':
4388 case 'X':
4389 prec = 5;
4390 break;
4391
4392 default:
4393 *sizeP = 0;
4394 return _("Bad call to md_atof ()");
4395 }
4396 t = atof_ieee (input_line_pointer, type, words);
4397 if (t)
4398 input_line_pointer = t;
4399
4400 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4401 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4402 the bigendian 386. */
4403 for (wordP = words + prec - 1; prec--;)
4404 {
4405 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4406 litP += sizeof (LITTLENUM_TYPE);
4407 }
4408 return 0;
4409}
4410
4411char output_invalid_buf[8];
4412
4413static char *
4414output_invalid (c)
4415 int c;
4416{
4417 if (isprint (c))
4418 sprintf (output_invalid_buf, "'%c'", c);
4419 else
4420 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4421 return output_invalid_buf;
4422}
4423
4424/* REG_STRING starts *before* REGISTER_PREFIX. */
4425
4426static const reg_entry *
4427parse_register (reg_string, end_op)
4428 char *reg_string;
4429 char **end_op;
4430{
4431 char *s = reg_string;
4432 char *p;
4433 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4434 const reg_entry *r;
4435
4436 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4437 if (*s == REGISTER_PREFIX)
4438 ++s;
4439
4440 if (is_space_char (*s))
4441 ++s;
4442
4443 p = reg_name_given;
4444 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
4445 {
4446 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
4447 return (const reg_entry *) NULL;
4448 s++;
4449 }
4450
4451 /* For naked regs, make sure that we are not dealing with an identifier.
4452 This prevents confusing an identifier like `eax_var' with register
4453 `eax'. */
4454 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
4455 return (const reg_entry *) NULL;
4456
4457 *end_op = s;
4458
4459 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
4460
4461 /* Handle floating point regs, allowing spaces in the (i) part. */
4462 if (r == i386_regtab /* %st is first entry of table */)
4463 {
4464 if (is_space_char (*s))
4465 ++s;
4466 if (*s == '(')
4467 {
4468 ++s;
4469 if (is_space_char (*s))
4470 ++s;
4471 if (*s >= '0' && *s <= '7')
4472 {
4473 r = &i386_float_regtab[*s - '0'];
4474 ++s;
4475 if (is_space_char (*s))
4476 ++s;
4477 if (*s == ')')
4478 {
4479 *end_op = s + 1;
4480 return r;
4481 }
4482 }
4483 /* We have "%st(" then garbage. */
4484 return (const reg_entry *) NULL;
4485 }
4486 }
4487
| 1910 /* If matched instruction specifies an explicit instruction mnemonic
1911 suffix, use it. */
1912 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
1913 {
1914 if (i.tm.opcode_modifier & Size16)
1915 i.suffix = WORD_MNEM_SUFFIX;
1916 else if (i.tm.opcode_modifier & Size64)
1917 i.suffix = QWORD_MNEM_SUFFIX;
1918 else
1919 i.suffix = LONG_MNEM_SUFFIX;
1920 }
1921 else if (i.reg_operands)
1922 {
1923 /* If there's no instruction mnemonic suffix we try to invent one
1924 based on register operands. */
1925 if (!i.suffix)
1926 {
1927 /* We take i.suffix from the last register operand specified,
1928 Destination register type is more significant than source
1929 register type. */
1930 int op;
1931 for (op = i.operands; --op >= 0;)
1932 if ((i.types[op] & Reg)
1933 && !(i.tm.operand_types[op] & InOutPortReg))
1934 {
1935 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
1936 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
1937 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
1938 LONG_MNEM_SUFFIX);
1939 break;
1940 }
1941 }
1942 else if (i.suffix == BYTE_MNEM_SUFFIX)
1943 {
1944 int op;
1945 for (op = i.operands; --op >= 0;)
1946 {
1947 /* If this is an eight bit register, it's OK. If it's
1948 the 16 or 32 bit version of an eight bit register,
1949 we will just use the low portion, and that's OK too. */
1950 if (i.types[op] & Reg8)
1951 continue;
1952
1953 /* movzx and movsx should not generate this warning. */
1954 if (intel_syntax
1955 && (i.tm.base_opcode == 0xfb7
1956 || i.tm.base_opcode == 0xfb6
1957 || i.tm.base_opcode == 0x63
1958 || i.tm.base_opcode == 0xfbe
1959 || i.tm.base_opcode == 0xfbf))
1960 continue;
1961
1962 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
1963#if 0
1964 /* Check that the template allows eight bit regs
1965 This kills insns such as `orb $1,%edx', which
1966 maybe should be allowed. */
1967 && (i.tm.operand_types[op] & (Reg8|InOutPortReg))
1968#endif
1969 )
1970 {
1971 /* Prohibit these changes in the 64bit mode, since
1972 the lowering is more complicated. */
1973 if (flag_code == CODE_64BIT
1974 && (i.tm.operand_types[op] & InOutPortReg) == 0)
1975 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1976 i.op[op].regs->reg_name,
1977 i.suffix);
1978#if REGISTER_WARNINGS
1979 if (!quiet_warnings
1980 && (i.tm.operand_types[op] & InOutPortReg) == 0)
1981 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1982 (i.op[op].regs
1983 + (i.types[op] & Reg16
1984 ? REGNAM_AL - REGNAM_AX
1985 : REGNAM_AL - REGNAM_EAX))->reg_name,
1986 i.op[op].regs->reg_name,
1987 i.suffix);
1988#endif
1989 continue;
1990 }
1991 /* Any other register is bad. */
1992 if (i.types[op] & (Reg | RegMMX | RegXMM
1993 | SReg2 | SReg3
1994 | Control | Debug | Test
1995 | FloatReg | FloatAcc))
1996 {
1997 as_bad (_("`%%%s' not allowed with `%s%c'"),
1998 i.op[op].regs->reg_name,
1999 i.tm.name,
2000 i.suffix);
2001 return;
2002 }
2003 }
2004 }
2005 else if (i.suffix == LONG_MNEM_SUFFIX)
2006 {
2007 int op;
2008
2009 for (op = i.operands; --op >= 0;)
2010 /* Reject eight bit registers, except where the template
2011 requires them. (eg. movzb) */
2012 if ((i.types[op] & Reg8) != 0
2013 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2014 {
2015 as_bad (_("`%%%s' not allowed with `%s%c'"),
2016 i.op[op].regs->reg_name,
2017 i.tm.name,
2018 i.suffix);
2019 return;
2020 }
2021 /* Warn if the e prefix on a general reg is missing. */
2022 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2023 && (i.types[op] & Reg16) != 0
2024 && (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
2025 {
2026 /* Prohibit these changes in the 64bit mode, since
2027 the lowering is more complicated. */
2028 if (flag_code == CODE_64BIT)
2029 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2030 i.op[op].regs->reg_name,
2031 i.suffix);
2032#if REGISTER_WARNINGS
2033 else
2034 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2035 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2036 i.op[op].regs->reg_name,
2037 i.suffix);
2038#endif
2039 }
2040 /* Warn if the r prefix on a general reg is missing. */
2041 else if ((i.types[op] & Reg64) != 0
2042 && (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
2043 {
2044 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2045 i.op[op].regs->reg_name,
2046 i.suffix);
2047 }
2048 }
2049 else if (i.suffix == QWORD_MNEM_SUFFIX)
2050 {
2051 int op;
2052
2053 for (op = i.operands; --op >= 0; )
2054 /* Reject eight bit registers, except where the template
2055 requires them. (eg. movzb) */
2056 if ((i.types[op] & Reg8) != 0
2057 && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0)
2058 {
2059 as_bad (_("`%%%s' not allowed with `%s%c'"),
2060 i.op[op].regs->reg_name,
2061 i.tm.name,
2062 i.suffix);
2063 return;
2064 }
2065 /* Warn if the e prefix on a general reg is missing. */
2066 else if (((i.types[op] & Reg16) != 0
2067 || (i.types[op] & Reg32) != 0)
2068 && (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
2069 {
2070 /* Prohibit these changes in the 64bit mode, since
2071 the lowering is more complicated. */
2072 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2073 i.op[op].regs->reg_name,
2074 i.suffix);
2075 }
2076 }
2077 else if (i.suffix == WORD_MNEM_SUFFIX)
2078 {
2079 int op;
2080 for (op = i.operands; --op >= 0;)
2081 /* Reject eight bit registers, except where the template
2082 requires them. (eg. movzb) */
2083 if ((i.types[op] & Reg8) != 0
2084 && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0)
2085 {
2086 as_bad (_("`%%%s' not allowed with `%s%c'"),
2087 i.op[op].regs->reg_name,
2088 i.tm.name,
2089 i.suffix);
2090 return;
2091 }
2092 /* Warn if the e prefix on a general reg is present. */
2093 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2094 && (i.types[op] & Reg32) != 0
2095 && (i.tm.operand_types[op] & (Reg16|Acc)) != 0)
2096 {
2097 /* Prohibit these changes in the 64bit mode, since
2098 the lowering is more complicated. */
2099 if (flag_code == CODE_64BIT)
2100 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2101 i.op[op].regs->reg_name,
2102 i.suffix);
2103 else
2104#if REGISTER_WARNINGS
2105 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2106 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2107 i.op[op].regs->reg_name,
2108 i.suffix);
2109#endif
2110 }
2111 }
2112 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2113 /* Do nothing if the instruction is going to ignore the prefix. */
2114 ;
2115 else
2116 abort ();
2117 }
2118 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
2119 {
2120 i.suffix = stackop_size;
2121 }
2122 /* Make still unresolved immediate matches conform to size of immediate
2123 given in i.suffix. Note: overlap2 cannot be an immediate! */
2124 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S))
2125 && overlap0 != Imm8 && overlap0 != Imm8S
2126 && overlap0 != Imm16 && overlap0 != Imm32S
2127 && overlap0 != Imm32 && overlap0 != Imm64)
2128 {
2129 if (i.suffix)
2130 {
2131 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) :
2132 (i.suffix == WORD_MNEM_SUFFIX ? Imm16 :
2133 (i.suffix == QWORD_MNEM_SUFFIX ? Imm64 | Imm32S : Imm32)));
2134 }
2135 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2136 || overlap0 == (Imm16 | Imm32)
2137 || overlap0 == (Imm16 | Imm32S))
2138 {
2139 overlap0 =
2140 ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32S;
2141 }
2142 if (overlap0 != Imm8 && overlap0 != Imm8S
2143 && overlap0 != Imm16 && overlap0 != Imm32S
2144 && overlap0 != Imm32 && overlap0 != Imm64)
2145 {
2146 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2147 return;
2148 }
2149 }
2150 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
2151 && overlap1 != Imm8 && overlap1 != Imm8S
2152 && overlap1 != Imm16 && overlap1 != Imm32S
2153 && overlap1 != Imm32 && overlap1 != Imm64)
2154 {
2155 if (i.suffix)
2156 {
2157 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) :
2158 (i.suffix == WORD_MNEM_SUFFIX ? Imm16 :
2159 (i.suffix == QWORD_MNEM_SUFFIX ? Imm64 | Imm32S : Imm32)));
2160 }
2161 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2162 || overlap1 == (Imm16 | Imm32)
2163 || overlap1 == (Imm16 | Imm32S))
2164 {
2165 overlap1 =
2166 ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32S;
2167 }
2168 if (overlap1 != Imm8 && overlap1 != Imm8S
2169 && overlap1 != Imm16 && overlap1 != Imm32S
2170 && overlap1 != Imm32 && overlap1 != Imm64)
2171 {
2172 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2173 return;
2174 }
2175 }
2176 assert ((overlap2 & Imm) == 0);
2177
2178 i.types[0] = overlap0;
2179 if (overlap0 & ImplicitRegister)
2180 i.reg_operands--;
2181 if (overlap0 & Imm1)
2182 i.imm_operands = 0; /* kludge for shift insns. */
2183
2184 i.types[1] = overlap1;
2185 if (overlap1 & ImplicitRegister)
2186 i.reg_operands--;
2187
2188 i.types[2] = overlap2;
2189 if (overlap2 & ImplicitRegister)
2190 i.reg_operands--;
2191
2192 /* Finalize opcode. First, we change the opcode based on the operand
2193 size given by i.suffix: We need not change things for byte insns. */
2194
2195 if (!i.suffix && (i.tm.opcode_modifier & W))
2196 {
2197 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2198 return;
2199 }
2200
2201 /* For movzx and movsx, need to check the register type. */
2202 if (intel_syntax
2203 && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe))
2204 if (i.suffix && i.suffix == BYTE_MNEM_SUFFIX)
2205 {
2206 unsigned int prefix = DATA_PREFIX_OPCODE;
2207
2208 if ((i.op[1].regs->reg_type & Reg16) != 0)
2209 if (!add_prefix (prefix))
2210 return;
2211 }
2212
2213 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2214 {
2215 /* It's not a byte, select word/dword operation. */
2216 if (i.tm.opcode_modifier & W)
2217 {
2218 if (i.tm.opcode_modifier & ShortForm)
2219 i.tm.base_opcode |= 8;
2220 else
2221 i.tm.base_opcode |= 1;
2222 }
2223 /* Now select between word & dword operations via the operand
2224 size prefix, except for instructions that will ignore this
2225 prefix anyway. */
2226 if (i.suffix != QWORD_MNEM_SUFFIX
2227 && (i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2228 && !(i.tm.opcode_modifier & IgnoreSize))
2229 {
2230 unsigned int prefix = DATA_PREFIX_OPCODE;
2231 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2232 prefix = ADDR_PREFIX_OPCODE;
2233
2234 if (! add_prefix (prefix))
2235 return;
2236 }
2237
2238 /* Set mode64 for an operand. */
2239 if (i.suffix == QWORD_MNEM_SUFFIX
2240 && !(i.tm.opcode_modifier & NoRex64))
2241 {
2242 i.rex.mode64 = 1;
2243 if (flag_code < CODE_64BIT)
2244 {
2245 as_bad (_("64bit operations available only in 64bit modes."));
2246 return;
2247 }
2248 }
2249
2250 /* Size floating point instruction. */
2251 if (i.suffix == LONG_MNEM_SUFFIX)
2252 {
2253 if (i.tm.opcode_modifier & FloatMF)
2254 i.tm.base_opcode ^= 4;
2255 }
2256 }
2257
2258 if (i.tm.opcode_modifier & ImmExt)
2259 {
2260 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2261 opcode suffix which is coded in the same place as an 8-bit
2262 immediate field would be. Here we fake an 8-bit immediate
2263 operand from the opcode suffix stored in tm.extension_opcode. */
2264
2265 expressionS *exp;
2266
2267 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
2268
2269 exp = &im_expressions[i.imm_operands++];
2270 i.op[i.operands].imms = exp;
2271 i.types[i.operands++] = Imm8;
2272 exp->X_op = O_constant;
2273 exp->X_add_number = i.tm.extension_opcode;
2274 i.tm.extension_opcode = None;
2275 }
2276
2277 /* For insns with operands there are more diddles to do to the opcode. */
2278 if (i.operands)
2279 {
2280 /* Default segment register this instruction will use
2281 for memory accesses. 0 means unknown.
2282 This is only for optimizing out unnecessary segment overrides. */
2283 const seg_entry *default_seg = 0;
2284
2285 /* The imul $imm, %reg instruction is converted into
2286 imul $imm, %reg, %reg, and the clr %reg instruction
2287 is converted into xor %reg, %reg. */
2288 if (i.tm.opcode_modifier & regKludge)
2289 {
2290 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2291 /* Pretend we saw the extra register operand. */
2292 assert (i.op[first_reg_op + 1].regs == 0);
2293 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2294 i.types[first_reg_op + 1] = i.types[first_reg_op];
2295 i.reg_operands = 2;
2296 }
2297
2298 if (i.tm.opcode_modifier & ShortForm)
2299 {
2300 /* The register or float register operand is in operand 0 or 1. */
2301 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2302 /* Register goes in low 3 bits of opcode. */
2303 i.tm.base_opcode |= i.op[op].regs->reg_num;
2304 if (i.op[op].regs->reg_flags & RegRex)
2305 i.rex.extZ = 1;
2306 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2307 {
2308 /* Warn about some common errors, but press on regardless.
2309 The first case can be generated by gcc (<= 2.8.1). */
2310 if (i.operands == 2)
2311 {
2312 /* Reversed arguments on faddp, fsubp, etc. */
2313 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2314 i.op[1].regs->reg_name,
2315 i.op[0].regs->reg_name);
2316 }
2317 else
2318 {
2319 /* Extraneous `l' suffix on fp insn. */
2320 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2321 i.op[0].regs->reg_name);
2322 }
2323 }
2324 }
2325 else if (i.tm.opcode_modifier & Modrm)
2326 {
2327 /* The opcode is completed (modulo i.tm.extension_opcode which
2328 must be put into the modrm byte).
2329 Now, we make the modrm & index base bytes based on all the
2330 info we've collected. */
2331
2332 /* i.reg_operands MUST be the number of real register operands;
2333 implicit registers do not count. */
2334 if (i.reg_operands == 2)
2335 {
2336 unsigned int source, dest;
2337 source = ((i.types[0]
2338 & (Reg | RegMMX | RegXMM
2339 | SReg2 | SReg3
2340 | Control | Debug | Test))
2341 ? 0 : 1);
2342 dest = source + 1;
2343
2344 i.rm.mode = 3;
2345 /* One of the register operands will be encoded in the
2346 i.tm.reg field, the other in the combined i.tm.mode
2347 and i.tm.regmem fields. If no form of this
2348 instruction supports a memory destination operand,
2349 then we assume the source operand may sometimes be
2350 a memory operand and so we need to store the
2351 destination in the i.rm.reg field. */
2352 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2353 {
2354 i.rm.reg = i.op[dest].regs->reg_num;
2355 i.rm.regmem = i.op[source].regs->reg_num;
2356 if (i.op[dest].regs->reg_flags & RegRex)
2357 i.rex.extX = 1;
2358 if (i.op[source].regs->reg_flags & RegRex)
2359 i.rex.extZ = 1;
2360 }
2361 else
2362 {
2363 i.rm.reg = i.op[source].regs->reg_num;
2364 i.rm.regmem = i.op[dest].regs->reg_num;
2365 if (i.op[dest].regs->reg_flags & RegRex)
2366 i.rex.extZ = 1;
2367 if (i.op[source].regs->reg_flags & RegRex)
2368 i.rex.extX = 1;
2369 }
2370 }
2371 else
2372 { /* If it's not 2 reg operands... */
2373 if (i.mem_operands)
2374 {
2375 unsigned int fake_zero_displacement = 0;
2376 unsigned int op = ((i.types[0] & AnyMem)
2377 ? 0
2378 : (i.types[1] & AnyMem) ? 1 : 2);
2379
2380 default_seg = &ds;
2381
2382 if (! i.base_reg)
2383 {
2384 i.rm.mode = 0;
2385 if (! i.disp_operands)
2386 fake_zero_displacement = 1;
2387 if (! i.index_reg)
2388 {
2389 /* Operand is just <disp> */
2390 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
2391 {
2392 i.rm.regmem = NO_BASE_REGISTER_16;
2393 i.types[op] &= ~Disp;
2394 i.types[op] |= Disp16;
2395 }
2396 else if (flag_code != CODE_64BIT)
2397 {
2398 i.rm.regmem = NO_BASE_REGISTER;
2399 i.types[op] &= ~Disp;
2400 i.types[op] |= Disp32;
2401 }
2402 else
2403 {
2404 /* 64bit mode overwrites the 32bit
2405 absolute addressing by RIP relative
2406 addressing and absolute addressing
2407 is encoded by one of the redundant
2408 SIB forms. */
2409
2410 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2411 i.sib.base = NO_BASE_REGISTER;
2412 i.sib.index = NO_INDEX_REGISTER;
2413 i.types[op] &= ~Disp;
2414 i.types[op] |= Disp32S;
2415 }
2416 }
2417 else /* ! i.base_reg && i.index_reg */
2418 {
2419 i.sib.index = i.index_reg->reg_num;
2420 i.sib.base = NO_BASE_REGISTER;
2421 i.sib.scale = i.log2_scale_factor;
2422 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2423 i.types[op] &= ~Disp;
2424 if (flag_code != CODE_64BIT)
2425 i.types[op] |= Disp32; /* Must be 32 bit */
2426 else
2427 i.types[op] |= Disp32S;
2428 if (i.index_reg->reg_flags & RegRex)
2429 i.rex.extY = 1;
2430 }
2431 }
2432 /* RIP addressing for 64bit mode. */
2433 else if (i.base_reg->reg_type == BaseIndex)
2434 {
2435 i.rm.regmem = NO_BASE_REGISTER;
2436 i.types[op] &= ~Disp;
2437 i.types[op] |= Disp32S;
2438 i.flags[op] = Operand_PCrel;
2439 }
2440 else if (i.base_reg->reg_type & Reg16)
2441 {
2442 switch (i.base_reg->reg_num)
2443 {
2444 case 3: /* (%bx) */
2445 if (! i.index_reg)
2446 i.rm.regmem = 7;
2447 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2448 i.rm.regmem = i.index_reg->reg_num - 6;
2449 break;
2450 case 5: /* (%bp) */
2451 default_seg = &ss;
2452 if (! i.index_reg)
2453 {
2454 i.rm.regmem = 6;
2455 if ((i.types[op] & Disp) == 0)
2456 {
2457 /* fake (%bp) into 0(%bp) */
2458 i.types[op] |= Disp8;
2459 fake_zero_displacement = 1;
2460 }
2461 }
2462 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2463 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2464 break;
2465 default: /* (%si) -> 4 or (%di) -> 5 */
2466 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2467 }
2468 i.rm.mode = mode_from_disp_size (i.types[op]);
2469 }
2470 else /* i.base_reg and 32/64 bit mode */
2471 {
2472 if (flag_code == CODE_64BIT
2473 && (i.types[op] & Disp))
2474 {
2475 if (i.types[op] & Disp8)
2476 i.types[op] = Disp8 | Disp32S;
2477 else
2478 i.types[op] = Disp32S;
2479 }
2480 i.rm.regmem = i.base_reg->reg_num;
2481 if (i.base_reg->reg_flags & RegRex)
2482 i.rex.extZ = 1;
2483 i.sib.base = i.base_reg->reg_num;
2484 /* x86-64 ignores REX prefix bit here to avoid
2485 decoder complications. */
2486 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
2487 {
2488 default_seg = &ss;
2489 if (i.disp_operands == 0)
2490 {
2491 fake_zero_displacement = 1;
2492 i.types[op] |= Disp8;
2493 }
2494 }
2495 else if (i.base_reg->reg_num == ESP_REG_NUM)
2496 {
2497 default_seg = &ss;
2498 }
2499 i.sib.scale = i.log2_scale_factor;
2500 if (! i.index_reg)
2501 {
2502 /* <disp>(%esp) becomes two byte modrm
2503 with no index register. We've already
2504 stored the code for esp in i.rm.regmem
2505 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2506 base register besides %esp will not use
2507 the extra modrm byte. */
2508 i.sib.index = NO_INDEX_REGISTER;
2509#if ! SCALE1_WHEN_NO_INDEX
2510 /* Another case where we force the second
2511 modrm byte. */
2512 if (i.log2_scale_factor)
2513 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2514#endif
2515 }
2516 else
2517 {
2518 i.sib.index = i.index_reg->reg_num;
2519 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2520 if (i.index_reg->reg_flags & RegRex)
2521 i.rex.extY = 1;
2522 }
2523 i.rm.mode = mode_from_disp_size (i.types[op]);
2524 }
2525
2526 if (fake_zero_displacement)
2527 {
2528 /* Fakes a zero displacement assuming that i.types[op]
2529 holds the correct displacement size. */
2530 expressionS *exp;
2531
2532 assert (i.op[op].disps == 0);
2533 exp = &disp_expressions[i.disp_operands++];
2534 i.op[op].disps = exp;
2535 exp->X_op = O_constant;
2536 exp->X_add_number = 0;
2537 exp->X_add_symbol = (symbolS *) 0;
2538 exp->X_op_symbol = (symbolS *) 0;
2539 }
2540 }
2541
2542 /* Fill in i.rm.reg or i.rm.regmem field with register
2543 operand (if any) based on i.tm.extension_opcode.
2544 Again, we must be careful to make sure that
2545 segment/control/debug/test/MMX registers are coded
2546 into the i.rm.reg field. */
2547 if (i.reg_operands)
2548 {
2549 unsigned int op =
2550 ((i.types[0]
2551 & (Reg | RegMMX | RegXMM
2552 | SReg2 | SReg3
2553 | Control | Debug | Test))
2554 ? 0
2555 : ((i.types[1]
2556 & (Reg | RegMMX | RegXMM
2557 | SReg2 | SReg3
2558 | Control | Debug | Test))
2559 ? 1
2560 : 2));
2561 /* If there is an extension opcode to put here, the
2562 register number must be put into the regmem field. */
2563 if (i.tm.extension_opcode != None)
2564 {
2565 i.rm.regmem = i.op[op].regs->reg_num;
2566 if (i.op[op].regs->reg_flags & RegRex)
2567 i.rex.extZ = 1;
2568 }
2569 else
2570 {
2571 i.rm.reg = i.op[op].regs->reg_num;
2572 if (i.op[op].regs->reg_flags & RegRex)
2573 i.rex.extX = 1;
2574 }
2575
2576 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2577 we must set it to 3 to indicate this is a register
2578 operand in the regmem field. */
2579 if (!i.mem_operands)
2580 i.rm.mode = 3;
2581 }
2582
2583 /* Fill in i.rm.reg field with extension opcode (if any). */
2584 if (i.tm.extension_opcode != None)
2585 i.rm.reg = i.tm.extension_opcode;
2586 }
2587 }
2588 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2589 {
2590 if (i.tm.base_opcode == POP_SEG_SHORT
2591 && i.op[0].regs->reg_num == 1)
2592 {
2593 as_bad (_("you can't `pop %%cs'"));
2594 return;
2595 }
2596 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2597 if (i.op[0].regs->reg_flags & RegRex)
2598 i.rex.extZ = 1;
2599 }
2600 else if ((i.tm.base_opcode & ~(D|W)) == MOV_AX_DISP32)
2601 {
2602 default_seg = &ds;
2603 }
2604 else if ((i.tm.opcode_modifier & IsString) != 0)
2605 {
2606 /* For the string instructions that allow a segment override
2607 on one of their operands, the default segment is ds. */
2608 default_seg = &ds;
2609 }
2610
2611 /* If a segment was explicitly specified,
2612 and the specified segment is not the default,
2613 use an opcode prefix to select it.
2614 If we never figured out what the default segment is,
2615 then default_seg will be zero at this point,
2616 and the specified segment prefix will always be used. */
2617 if ((i.seg[0]) && (i.seg[0] != default_seg))
2618 {
2619 if (! add_prefix (i.seg[0]->seg_prefix))
2620 return;
2621 }
2622 }
2623 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2624 {
2625 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2626 as_warn (_("translating to `%sp'"), i.tm.name);
2627 }
2628 }
2629
2630 /* Handle conversion of 'int $3' --> special int3 insn. */
2631 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2632 {
2633 i.tm.base_opcode = INT3_OPCODE;
2634 i.imm_operands = 0;
2635 }
2636
2637 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
2638 && i.op[0].disps->X_op == O_constant)
2639 {
2640 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2641 the absolute address given by the constant. Since ix86 jumps and
2642 calls are pc relative, we need to generate a reloc. */
2643 i.op[0].disps->X_add_symbol = &abs_symbol;
2644 i.op[0].disps->X_op = O_symbol;
2645 }
2646
2647 if (i.tm.opcode_modifier & Rex64)
2648 i.rex.mode64 = 1;
2649
2650 /* For 8bit registers we would need an empty rex prefix.
2651 Also in the case instruction is already having prefix,
2652 we need to convert old registers to new ones. */
2653
2654 if (((i.types[0] & Reg8) && (i.op[0].regs->reg_flags & RegRex64))
2655 || ((i.types[1] & Reg8) && (i.op[1].regs->reg_flags & RegRex64))
2656 || ((i.rex.mode64 || i.rex.extX || i.rex.extY || i.rex.extZ || i.rex.empty)
2657 && ((i.types[0] & Reg8) || (i.types[1] & Reg8))))
2658 {
2659 int x;
2660 i.rex.empty = 1;
2661 for (x = 0; x < 2; x++)
2662 {
2663 /* Look for 8bit operand that does use old registers. */
2664 if (i.types[x] & Reg8
2665 && !(i.op[x].regs->reg_flags & RegRex64))
2666 {
2667 /* In case it is "hi" register, give up. */
2668 if (i.op[x].regs->reg_num > 3)
2669 as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"),
2670 i.op[x].regs->reg_name);
2671
2672 /* Otherwise it is equivalent to the extended register.
2673 Since the encoding don't change this is merely cosmetical
2674 cleanup for debug output. */
2675
2676 i.op[x].regs = i.op[x].regs + 8;
2677 }
2678 }
2679 }
2680
2681 if (i.rex.mode64 || i.rex.extX || i.rex.extY || i.rex.extZ || i.rex.empty)
2682 add_prefix (0x40
2683 | (i.rex.mode64 ? 8 : 0)
2684 | (i.rex.extX ? 4 : 0)
2685 | (i.rex.extY ? 2 : 0)
2686 | (i.rex.extZ ? 1 : 0));
2687
2688 /* We are ready to output the insn. */
2689 {
2690 register char *p;
2691
2692 /* Tie dwarf2 debug info to the address at the start of the insn.
2693 We can't do this after the insn has been output as the current
2694 frag may have been closed off. eg. by frag_var. */
2695 dwarf2_emit_insn (0);
2696
2697 /* Output jumps. */
2698 if (i.tm.opcode_modifier & Jump)
2699 {
2700 int code16;
2701 int prefix;
2702
2703 code16 = 0;
2704 if (flag_code == CODE_16BIT)
2705 code16 = CODE16;
2706
2707 prefix = 0;
2708 if (i.prefix[DATA_PREFIX])
2709 {
2710 prefix = 1;
2711 i.prefixes -= 1;
2712 code16 ^= CODE16;
2713 }
2714 /* Pentium4 branch hints. */
2715 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
2716 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2717 {
2718 prefix++;
2719 i.prefixes--;
2720 }
2721 if (i.prefix[REX_PREFIX])
2722 {
2723 prefix++;
2724 i.prefixes--;
2725 }
2726
2727 if (i.prefixes != 0 && !intel_syntax)
2728 as_warn (_("skipping prefixes on this instruction"));
2729
2730 /* It's always a symbol; End frag & setup for relax.
2731 Make sure there is enough room in this frag for the largest
2732 instruction we may generate in md_convert_frag. This is 2
2733 bytes for the opcode and room for the prefix and largest
2734 displacement. */
2735 frag_grow (prefix + 2 + 4);
2736 /* Prefix and 1 opcode byte go in fr_fix. */
2737 p = frag_more (prefix + 1);
2738 if (i.prefix[DATA_PREFIX])
2739 *p++ = DATA_PREFIX_OPCODE;
2740 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
2741 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
2742 *p++ = i.prefix[SEG_PREFIX];
2743 if (i.prefix[REX_PREFIX])
2744 *p++ = i.prefix[REX_PREFIX];
2745 *p = i.tm.base_opcode;
2746 /* 1 possible extra opcode + displacement go in var part.
2747 Pass reloc in fr_var. */
2748 frag_var (rs_machine_dependent,
2749 1 + 4,
2750 i.reloc[0],
2751 ((unsigned char) *p == JUMP_PC_RELATIVE
2752 ? ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL) | code16
2753 : ((cpu_arch_flags & Cpu386) != 0
2754 ? ENCODE_RELAX_STATE (COND_JUMP, SMALL) | code16
2755 : ENCODE_RELAX_STATE (COND_JUMP86, SMALL) | code16)),
2756 i.op[0].disps->X_add_symbol,
2757 i.op[0].disps->X_add_number,
2758 p);
2759 }
2760 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
2761 {
2762 int size;
2763
2764 if (i.tm.opcode_modifier & JumpByte)
2765 {
2766 /* This is a loop or jecxz type instruction. */
2767 size = 1;
2768 if (i.prefix[ADDR_PREFIX])
2769 {
2770 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
2771 i.prefixes -= 1;
2772 }
2773 /* Pentium4 branch hints. */
2774 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
2775 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2776 {
2777 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
2778 i.prefixes--;
2779 }
2780 }
2781 else
2782 {
2783 int code16;
2784
2785 code16 = 0;
2786 if (flag_code == CODE_16BIT)
2787 code16 = CODE16;
2788
2789 if (i.prefix[DATA_PREFIX])
2790 {
2791 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
2792 i.prefixes -= 1;
2793 code16 ^= CODE16;
2794 }
2795
2796 size = 4;
2797 if (code16)
2798 size = 2;
2799 }
2800
2801 if (i.prefix[REX_PREFIX])
2802 {
2803 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
2804 i.prefixes -= 1;
2805 }
2806
2807 if (i.prefixes != 0 && !intel_syntax)
2808 as_warn (_("skipping prefixes on this instruction"));
2809
2810 p = frag_more (1 + size);
2811 *p++ = i.tm.base_opcode;
2812
2813 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2814 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
2815 }
2816 else if (i.tm.opcode_modifier & JumpInterSegment)
2817 {
2818 int size;
2819 int prefix;
2820 int code16;
2821
2822 code16 = 0;
2823 if (flag_code == CODE_16BIT)
2824 code16 = CODE16;
2825
2826 prefix = 0;
2827 if (i.prefix[DATA_PREFIX])
2828 {
2829 prefix = 1;
2830 i.prefixes -= 1;
2831 code16 ^= CODE16;
2832 }
2833 if (i.prefix[REX_PREFIX])
2834 {
2835 prefix++;
2836 i.prefixes -= 1;
2837 }
2838
2839 size = 4;
2840 if (code16)
2841 size = 2;
2842
2843 if (i.prefixes != 0 && !intel_syntax)
2844 as_warn (_("skipping prefixes on this instruction"));
2845
2846 /* 1 opcode; 2 segment; offset */
2847 p = frag_more (prefix + 1 + 2 + size);
2848
2849 if (i.prefix[DATA_PREFIX])
2850 *p++ = DATA_PREFIX_OPCODE;
2851
2852 if (i.prefix[REX_PREFIX])
2853 *p++ = i.prefix[REX_PREFIX];
2854
2855 *p++ = i.tm.base_opcode;
2856 if (i.op[1].imms->X_op == O_constant)
2857 {
2858 offsetT n = i.op[1].imms->X_add_number;
2859
2860 if (size == 2
2861 && !fits_in_unsigned_word (n)
2862 && !fits_in_signed_word (n))
2863 {
2864 as_bad (_("16-bit jump out of range"));
2865 return;
2866 }
2867 md_number_to_chars (p, n, size);
2868 }
2869 else
2870 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2871 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
2872 if (i.op[0].imms->X_op != O_constant)
2873 as_bad (_("can't handle non absolute segment in `%s'"),
2874 i.tm.name);
2875 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
2876 }
2877 else
2878 {
2879 /* Output normal instructions here. */
2880 unsigned char *q;
2881
2882 /* All opcodes on i386 have eighter 1 or 2 bytes. We may use third
2883 byte for the SSE instructions to specify prefix they require. */
2884 if (i.tm.base_opcode & 0xff0000)
2885 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
2886
2887 /* The prefix bytes. */
2888 for (q = i.prefix;
2889 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
2890 q++)
2891 {
2892 if (*q)
2893 {
2894 p = frag_more (1);
2895 md_number_to_chars (p, (valueT) *q, 1);
2896 }
2897 }
2898
2899 /* Now the opcode; be careful about word order here! */
2900 if (fits_in_unsigned_byte (i.tm.base_opcode))
2901 {
2902 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
2903 }
2904 else
2905 {
2906 p = frag_more (2);
2907 /* Put out high byte first: can't use md_number_to_chars! */
2908 *p++ = (i.tm.base_opcode >> 8) & 0xff;
2909 *p = i.tm.base_opcode & 0xff;
2910 }
2911
2912 /* Now the modrm byte and sib byte (if present). */
2913 if (i.tm.opcode_modifier & Modrm)
2914 {
2915 p = frag_more (1);
2916 md_number_to_chars (p,
2917 (valueT) (i.rm.regmem << 0
2918 | i.rm.reg << 3
2919 | i.rm.mode << 6),
2920 1);
2921 /* If i.rm.regmem == ESP (4)
2922 && i.rm.mode != (Register mode)
2923 && not 16 bit
2924 ==> need second modrm byte. */
2925 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
2926 && i.rm.mode != 3
2927 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
2928 {
2929 p = frag_more (1);
2930 md_number_to_chars (p,
2931 (valueT) (i.sib.base << 0
2932 | i.sib.index << 3
2933 | i.sib.scale << 6),
2934 1);
2935 }
2936 }
2937
2938 if (i.disp_operands)
2939 {
2940 register unsigned int n;
2941
2942 for (n = 0; n < i.operands; n++)
2943 {
2944 if (i.types[n] & Disp)
2945 {
2946 if (i.op[n].disps->X_op == O_constant)
2947 {
2948 int size;
2949 offsetT val;
2950
2951 size = 4;
2952 if (i.types[n] & (Disp8 | Disp16 | Disp64))
2953 {
2954 size = 2;
2955 if (i.types[n] & Disp8)
2956 size = 1;
2957 if (i.types[n] & Disp64)
2958 size = 8;
2959 }
2960 val = offset_in_range (i.op[n].disps->X_add_number,
2961 size);
2962 p = frag_more (size);
2963 md_number_to_chars (p, val, size);
2964 }
2965 else
2966 {
2967 int size = 4;
2968 int sign = 0;
2969 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
2970
2971 /* The PC relative address is computed relative
2972 to the instruction boundary, so in case immediate
2973 fields follows, we need to adjust the value. */
2974 if (pcrel && i.imm_operands)
2975 {
2976 int imm_size = 4;
2977 register unsigned int n1;
2978
2979 for (n1 = 0; n1 < i.operands; n1++)
2980 if (i.types[n1] & Imm)
2981 {
2982 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
2983 {
2984 imm_size = 2;
2985 if (i.types[n1] & (Imm8 | Imm8S))
2986 imm_size = 1;
2987 if (i.types[n1] & Imm64)
2988 imm_size = 8;
2989 }
2990 break;
2991 }
2992 /* We should find the immediate. */
2993 if (n1 == i.operands)
2994 abort ();
2995 i.op[n].disps->X_add_number -= imm_size;
2996 }
2997
2998 if (i.types[n] & Disp32S)
2999 sign = 1;
3000
3001 if (i.types[n] & (Disp16 | Disp64))
3002 {
3003 size = 2;
3004 if (i.types[n] & Disp64)
3005 size = 8;
3006 }
3007
3008 p = frag_more (size);
3009 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3010 i.op[n].disps, pcrel,
3011 reloc (size, pcrel, sign, i.reloc[n]));
3012 }
3013 }
3014 }
3015 }
3016
3017 /* Output immediate. */
3018 if (i.imm_operands)
3019 {
3020 register unsigned int n;
3021
3022 for (n = 0; n < i.operands; n++)
3023 {
3024 if (i.types[n] & Imm)
3025 {
3026 if (i.op[n].imms->X_op == O_constant)
3027 {
3028 int size;
3029 offsetT val;
3030
3031 size = 4;
3032 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3033 {
3034 size = 2;
3035 if (i.types[n] & (Imm8 | Imm8S))
3036 size = 1;
3037 else if (i.types[n] & Imm64)
3038 size = 8;
3039 }
3040 val = offset_in_range (i.op[n].imms->X_add_number,
3041 size);
3042 p = frag_more (size);
3043 md_number_to_chars (p, val, size);
3044 }
3045 else
3046 {
3047 /* Not absolute_section.
3048 Need a 32-bit fixup (don't support 8bit
3049 non-absolute imms). Try to support other
3050 sizes ... */
3051 RELOC_ENUM reloc_type;
3052 int size = 4;
3053 int sign = 0;
3054
3055 if ((i.types[n] & (Imm32S))
3056 && i.suffix == QWORD_MNEM_SUFFIX)
3057 sign = 1;
3058 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3059 {
3060 size = 2;
3061 if (i.types[n] & (Imm8 | Imm8S))
3062 size = 1;
3063 if (i.types[n] & Imm64)
3064 size = 8;
3065 }
3066
3067 p = frag_more (size);
3068 reloc_type = reloc (size, 0, sign, i.reloc[n]);
3069#ifdef BFD_ASSEMBLER
3070 if (reloc_type == BFD_RELOC_32
3071 && GOT_symbol
3072 && GOT_symbol == i.op[n].imms->X_add_symbol
3073 && (i.op[n].imms->X_op == O_symbol
3074 || (i.op[n].imms->X_op == O_add
3075 && ((symbol_get_value_expression
3076 (i.op[n].imms->X_op_symbol)->X_op)
3077 == O_subtract))))
3078 {
3079 /* We don't support dynamic linking on x86-64 yet. */
3080 if (flag_code == CODE_64BIT)
3081 abort ();
3082 reloc_type = BFD_RELOC_386_GOTPC;
3083 i.op[n].imms->X_add_number += 3;
3084 }
3085#endif
3086 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3087 i.op[n].imms, 0, reloc_type);
3088 }
3089 }
3090 }
3091 }
3092 }
3093
3094#ifdef DEBUG386
3095 if (flag_debug)
3096 {
3097 pi (line, &i);
3098 }
3099#endif /* DEBUG386 */
3100 }
3101}
3102
3103#ifndef LEX_AT
3104static char *lex_got PARAMS ((RELOC_ENUM *, int *));
3105
3106/* Parse operands of the form
3107 <symbol>@GOTOFF+<nnn>
3108 and similar .plt or .got references.
3109
3110 If we find one, set up the correct relocation in RELOC and copy the
3111 input string, minus the `@GOTOFF' into a malloc'd buffer for
3112 parsing by the calling routine. Return this buffer, and if ADJUST
3113 is non-null set it to the length of the string we removed from the
3114 input line. Otherwise return NULL. */
3115static char *
3116lex_got (reloc, adjust)
3117 RELOC_ENUM *reloc;
3118 int *adjust;
3119{
3120 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3121 static const struct {
3122 const char *str;
3123 const RELOC_ENUM rel[NUM_FLAG_CODE];
3124 } gotrel[] = {
3125 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3126 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } },
3127 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
3128 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
3129 };
3130 char *cp;
3131 unsigned int j;
3132
3133 for (cp = input_line_pointer; *cp != '@'; cp++)
3134 if (is_end_of_line[(unsigned char) *cp])
3135 return NULL;
3136
3137 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3138 {
3139 int len;
3140
3141 len = strlen (gotrel[j].str);
3142 if (strncmp (cp + 1, gotrel[j].str, len) == 0)
3143 {
3144 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3145 {
3146 int first;
3147 char *tmpbuf;
3148
3149 *reloc = gotrel[j].rel[(unsigned int) flag_code];
3150
3151 if (GOT_symbol == NULL)
3152 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3153
3154 /* Replace the relocation token with ' ', so that
3155 errors like foo@GOTOFF1 will be detected. */
3156 first = cp - input_line_pointer;
3157 tmpbuf = xmalloc (strlen (input_line_pointer));
3158 memcpy (tmpbuf, input_line_pointer, first);
3159 tmpbuf[first] = ' ';
3160 strcpy (tmpbuf + first + 1, cp + 1 + len);
3161 if (adjust)
3162 *adjust = len;
3163 return tmpbuf;
3164 }
3165
3166 as_bad (_("@%s reloc is not supported in %s bit mode"),
3167 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3168 return NULL;
3169 }
3170 }
3171
3172 /* Might be a symbol version string. Don't as_bad here. */
3173 return NULL;
3174}
3175
3176/* x86_cons_fix_new is called via the expression parsing code when a
3177 reloc is needed. We use this hook to get the correct .got reloc. */
3178static RELOC_ENUM got_reloc = NO_RELOC;
3179
3180void
3181x86_cons_fix_new (frag, off, len, exp)
3182 fragS *frag;
3183 unsigned int off;
3184 unsigned int len;
3185 expressionS *exp;
3186{
3187 RELOC_ENUM r = reloc (len, 0, 0, got_reloc);
3188 got_reloc = NO_RELOC;
3189 fix_new_exp (frag, off, len, exp, 0, r);
3190}
3191
3192void
3193x86_cons (exp, size)
3194 expressionS *exp;
3195 int size;
3196{
3197 if (size == 4)
3198 {
3199 /* Handle @GOTOFF and the like in an expression. */
3200 char *save;
3201 char *gotfree_input_line;
3202 int adjust;
3203
3204 save = input_line_pointer;
3205 gotfree_input_line = lex_got (&got_reloc, &adjust);
3206 if (gotfree_input_line)
3207 input_line_pointer = gotfree_input_line;
3208
3209 expression (exp);
3210
3211 if (gotfree_input_line)
3212 {
3213 /* expression () has merrily parsed up to the end of line,
3214 or a comma - in the wrong buffer. Transfer how far
3215 input_line_pointer has moved to the right buffer. */
3216 input_line_pointer = (save
3217 + (input_line_pointer - gotfree_input_line)
3218 + adjust);
3219 free (gotfree_input_line);
3220 }
3221 }
3222 else
3223 expression (exp);
3224}
3225#endif
3226
3227static int i386_immediate PARAMS ((char *));
3228
3229static int
3230i386_immediate (imm_start)
3231 char *imm_start;
3232{
3233 char *save_input_line_pointer;
3234#ifndef LEX_AT
3235 char *gotfree_input_line;
3236#endif
3237 segT exp_seg = 0;
3238 expressionS *exp;
3239
3240 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3241 {
3242 as_bad (_("only 1 or 2 immediate operands are allowed"));
3243 return 0;
3244 }
3245
3246 exp = &im_expressions[i.imm_operands++];
3247 i.op[this_operand].imms = exp;
3248
3249 if (is_space_char (*imm_start))
3250 ++imm_start;
3251
3252 save_input_line_pointer = input_line_pointer;
3253 input_line_pointer = imm_start;
3254
3255#ifndef LEX_AT
3256 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3257 if (gotfree_input_line)
3258 input_line_pointer = gotfree_input_line;
3259#endif
3260
3261 exp_seg = expression (exp);
3262
3263 SKIP_WHITESPACE ();
3264 if (*input_line_pointer)
3265 as_bad (_("junk `%s' after expression"), input_line_pointer);
3266
3267 input_line_pointer = save_input_line_pointer;
3268#ifndef LEX_AT
3269 if (gotfree_input_line)
3270 free (gotfree_input_line);
3271#endif
3272
3273 if (exp->X_op == O_absent || exp->X_op == O_big)
3274 {
3275 /* Missing or bad expr becomes absolute 0. */
3276 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3277 imm_start);
3278 exp->X_op = O_constant;
3279 exp->X_add_number = 0;
3280 exp->X_add_symbol = (symbolS *) 0;
3281 exp->X_op_symbol = (symbolS *) 0;
3282 }
3283 else if (exp->X_op == O_constant)
3284 {
3285 /* Size it properly later. */
3286 i.types[this_operand] |= Imm64;
3287 /* If BFD64, sign extend val. */
3288 if (!use_rela_relocations)
3289 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3290 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
3291 }
3292#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3293 else if (1
3294#ifdef BFD_ASSEMBLER
3295 && OUTPUT_FLAVOR == bfd_target_aout_flavour
3296#endif
3297 && exp_seg != text_section
3298 && exp_seg != data_section
3299 && exp_seg != bss_section
3300 && exp_seg != undefined_section
3301#ifdef BFD_ASSEMBLER
3302 && !bfd_is_com_section (exp_seg)
3303#endif
3304 )
3305 {
3306#ifdef BFD_ASSEMBLER
3307 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3308#else
3309 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
3310#endif
3311 return 0;
3312 }
3313#endif
3314 else
3315 {
3316 /* This is an address. The size of the address will be
3317 determined later, depending on destination register,
3318 suffix, or the default for the section. */
3319 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3320 }
3321
3322 return 1;
3323}
3324
3325static char *i386_scale PARAMS ((char *));
3326
3327static char *
3328i386_scale (scale)
3329 char *scale;
3330{
3331 offsetT val;
3332 char *save = input_line_pointer;
3333
3334 input_line_pointer = scale;
3335 val = get_absolute_expression ();
3336
3337 switch (val)
3338 {
3339 case 0:
3340 case 1:
3341 i.log2_scale_factor = 0;
3342 break;
3343 case 2:
3344 i.log2_scale_factor = 1;
3345 break;
3346 case 4:
3347 i.log2_scale_factor = 2;
3348 break;
3349 case 8:
3350 i.log2_scale_factor = 3;
3351 break;
3352 default:
3353 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3354 scale);
3355 input_line_pointer = save;
3356 return NULL;
3357 }
3358 if (i.log2_scale_factor != 0 && ! i.index_reg)
3359 {
3360 as_warn (_("scale factor of %d without an index register"),
3361 1 << i.log2_scale_factor);
3362#if SCALE1_WHEN_NO_INDEX
3363 i.log2_scale_factor = 0;
3364#endif
3365 }
3366 scale = input_line_pointer;
3367 input_line_pointer = save;
3368 return scale;
3369}
3370
3371static int i386_displacement PARAMS ((char *, char *));
3372
3373static int
3374i386_displacement (disp_start, disp_end)
3375 char *disp_start;
3376 char *disp_end;
3377{
3378 register expressionS *exp;
3379 segT exp_seg = 0;
3380 char *save_input_line_pointer;
3381#ifndef LEX_AT
3382 char *gotfree_input_line;
3383#endif
3384 int bigdisp = Disp32;
3385
3386 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3387 bigdisp = Disp16;
3388 if (flag_code == CODE_64BIT)
3389 bigdisp = Disp64;
3390 i.types[this_operand] |= bigdisp;
3391
3392 exp = &disp_expressions[i.disp_operands];
3393 i.op[this_operand].disps = exp;
3394 i.disp_operands++;
3395 save_input_line_pointer = input_line_pointer;
3396 input_line_pointer = disp_start;
3397 END_STRING_AND_SAVE (disp_end);
3398
3399#ifndef GCC_ASM_O_HACK
3400#define GCC_ASM_O_HACK 0
3401#endif
3402#if GCC_ASM_O_HACK
3403 END_STRING_AND_SAVE (disp_end + 1);
3404 if ((i.types[this_operand] & BaseIndex) != 0
3405 && displacement_string_end[-1] == '+')
3406 {
3407 /* This hack is to avoid a warning when using the "o"
3408 constraint within gcc asm statements.
3409 For instance:
3410
3411 #define _set_tssldt_desc(n,addr,limit,type) \
3412 __asm__ __volatile__ ( \
3413 "movw %w2,%0\n\t" \
3414 "movw %w1,2+%0\n\t" \
3415 "rorl $16,%1\n\t" \
3416 "movb %b1,4+%0\n\t" \
3417 "movb %4,5+%0\n\t" \
3418 "movb $0,6+%0\n\t" \
3419 "movb %h1,7+%0\n\t" \
3420 "rorl $16,%1" \
3421 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3422
3423 This works great except that the output assembler ends
3424 up looking a bit weird if it turns out that there is
3425 no offset. You end up producing code that looks like:
3426
3427 #APP
3428 movw $235,(%eax)
3429 movw %dx,2+(%eax)
3430 rorl $16,%edx
3431 movb %dl,4+(%eax)
3432 movb $137,5+(%eax)
3433 movb $0,6+(%eax)
3434 movb %dh,7+(%eax)
3435 rorl $16,%edx
3436 #NO_APP
3437
3438 So here we provide the missing zero. */
3439
3440 *displacement_string_end = '0';
3441 }
3442#endif
3443#ifndef LEX_AT
3444 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3445 if (gotfree_input_line)
3446 input_line_pointer = gotfree_input_line;
3447#endif
3448
3449 exp_seg = expression (exp);
3450
3451 SKIP_WHITESPACE ();
3452 if (*input_line_pointer)
3453 as_bad (_("junk `%s' after expression"), input_line_pointer);
3454#if GCC_ASM_O_HACK
3455 RESTORE_END_STRING (disp_end + 1);
3456#endif
3457 RESTORE_END_STRING (disp_end);
3458 input_line_pointer = save_input_line_pointer;
3459#ifndef LEX_AT
3460 if (gotfree_input_line)
3461 free (gotfree_input_line);
3462#endif
3463
3464#ifdef BFD_ASSEMBLER
3465 /* We do this to make sure that the section symbol is in
3466 the symbol table. We will ultimately change the relocation
3467 to be relative to the beginning of the section. */
3468 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
3469 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
3470 {
3471 if (exp->X_op != O_symbol)
3472 {
3473 as_bad (_("bad expression used with @%s"),
3474 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
3475 ? "GOTPCREL"
3476 : "GOTOFF"));
3477 return 0;
3478 }
3479
3480 if (S_IS_LOCAL (exp->X_add_symbol)
3481 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
3482 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
3483 exp->X_op = O_subtract;
3484 exp->X_op_symbol = GOT_symbol;
3485 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
3486 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
3487 else
3488 i.reloc[this_operand] = BFD_RELOC_32;
3489 }
3490#endif
3491
3492 if (exp->X_op == O_absent || exp->X_op == O_big)
3493 {
3494 /* Missing or bad expr becomes absolute 0. */
3495 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3496 disp_start);
3497 exp->X_op = O_constant;
3498 exp->X_add_number = 0;
3499 exp->X_add_symbol = (symbolS *) 0;
3500 exp->X_op_symbol = (symbolS *) 0;
3501 }
3502
3503#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3504 if (exp->X_op != O_constant
3505#ifdef BFD_ASSEMBLER
3506 && OUTPUT_FLAVOR == bfd_target_aout_flavour
3507#endif
3508 && exp_seg != text_section
3509 && exp_seg != data_section
3510 && exp_seg != bss_section
3511 && exp_seg != undefined_section)
3512 {
3513#ifdef BFD_ASSEMBLER
3514 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3515#else
3516 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
3517#endif
3518 return 0;
3519 }
3520#endif
3521 else if (flag_code == CODE_64BIT)
3522 i.types[this_operand] |= Disp32S | Disp32;
3523 return 1;
3524}
3525
3526static int i386_index_check PARAMS ((const char *));
3527
3528/* Make sure the memory operand we've been dealt is valid.
3529 Return 1 on success, 0 on a failure. */
3530
3531static int
3532i386_index_check (operand_string)
3533 const char *operand_string;
3534{
3535 int ok;
3536#if INFER_ADDR_PREFIX
3537 int fudged = 0;
3538
3539 tryprefix:
3540#endif
3541 ok = 1;
3542 if (flag_code == CODE_64BIT)
3543 {
3544 /* 64bit checks. */
3545 if ((i.base_reg
3546 && ((i.base_reg->reg_type & Reg64) == 0)
3547 && (i.base_reg->reg_type != BaseIndex
3548 || i.index_reg))
3549 || (i.index_reg
3550 && ((i.index_reg->reg_type & (Reg64|BaseIndex))
3551 != (Reg64|BaseIndex))))
3552 ok = 0;
3553 }
3554 else
3555 {
3556 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3557 {
3558 /* 16bit checks. */
3559 if ((i.base_reg
3560 && ((i.base_reg->reg_type & (Reg16|BaseIndex|RegRex))
3561 != (Reg16|BaseIndex)))
3562 || (i.index_reg
3563 && (((i.index_reg->reg_type & (Reg16|BaseIndex))
3564 != (Reg16|BaseIndex))
3565 || ! (i.base_reg
3566 && i.base_reg->reg_num < 6
3567 && i.index_reg->reg_num >= 6
3568 && i.log2_scale_factor == 0))))
3569 ok = 0;
3570 }
3571 else
3572 {
3573 /* 32bit checks. */
3574 if ((i.base_reg
3575 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3576 || (i.index_reg
3577 && ((i.index_reg->reg_type & (Reg32|BaseIndex|RegRex))
3578 != (Reg32|BaseIndex))))
3579 ok = 0;
3580 }
3581 }
3582 if (!ok)
3583 {
3584#if INFER_ADDR_PREFIX
3585 if (flag_code != CODE_64BIT
3586 && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
3587 {
3588 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
3589 i.prefixes += 1;
3590 /* Change the size of any displacement too. At most one of
3591 Disp16 or Disp32 is set.
3592 FIXME. There doesn't seem to be any real need for separate
3593 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3594 Removing them would probably clean up the code quite a lot. */
3595 if (i.types[this_operand] & (Disp16|Disp32))
3596 i.types[this_operand] ^= (Disp16|Disp32);
3597 fudged = 1;
3598 goto tryprefix;
3599 }
3600 if (fudged)
3601 as_bad (_("`%s' is not a valid base/index expression"),
3602 operand_string);
3603 else
3604#endif
3605 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3606 operand_string,
3607 flag_code_names[flag_code]);
3608 return 0;
3609 }
3610 return 1;
3611}
3612
3613/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3614 on error. */
3615
3616static int
3617i386_operand (operand_string)
3618 char *operand_string;
3619{
3620 const reg_entry *r;
3621 char *end_op;
3622 char *op_string = operand_string;
3623
3624 if (is_space_char (*op_string))
3625 ++op_string;
3626
3627 /* We check for an absolute prefix (differentiating,
3628 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3629 if (*op_string == ABSOLUTE_PREFIX)
3630 {
3631 ++op_string;
3632 if (is_space_char (*op_string))
3633 ++op_string;
3634 i.types[this_operand] |= JumpAbsolute;
3635 }
3636
3637 /* Check if operand is a register. */
3638 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
3639 && (r = parse_register (op_string, &end_op)) != NULL)
3640 {
3641 /* Check for a segment override by searching for ':' after a
3642 segment register. */
3643 op_string = end_op;
3644 if (is_space_char (*op_string))
3645 ++op_string;
3646 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
3647 {
3648 switch (r->reg_num)
3649 {
3650 case 0:
3651 i.seg[i.mem_operands] = &es;
3652 break;
3653 case 1:
3654 i.seg[i.mem_operands] = &cs;
3655 break;
3656 case 2:
3657 i.seg[i.mem_operands] = &ss;
3658 break;
3659 case 3:
3660 i.seg[i.mem_operands] = &ds;
3661 break;
3662 case 4:
3663 i.seg[i.mem_operands] = &fs;
3664 break;
3665 case 5:
3666 i.seg[i.mem_operands] = &gs;
3667 break;
3668 }
3669
3670 /* Skip the ':' and whitespace. */
3671 ++op_string;
3672 if (is_space_char (*op_string))
3673 ++op_string;
3674
3675 if (!is_digit_char (*op_string)
3676 && !is_identifier_char (*op_string)
3677 && *op_string != '('
3678 && *op_string != ABSOLUTE_PREFIX)
3679 {
3680 as_bad (_("bad memory operand `%s'"), op_string);
3681 return 0;
3682 }
3683 /* Handle case of %es:*foo. */
3684 if (*op_string == ABSOLUTE_PREFIX)
3685 {
3686 ++op_string;
3687 if (is_space_char (*op_string))
3688 ++op_string;
3689 i.types[this_operand] |= JumpAbsolute;
3690 }
3691 goto do_memory_reference;
3692 }
3693 if (*op_string)
3694 {
3695 as_bad (_("junk `%s' after register"), op_string);
3696 return 0;
3697 }
3698 i.types[this_operand] |= r->reg_type & ~BaseIndex;
3699 i.op[this_operand].regs = r;
3700 i.reg_operands++;
3701 }
3702 else if (*op_string == REGISTER_PREFIX)
3703 {
3704 as_bad (_("bad register name `%s'"), op_string);
3705 return 0;
3706 }
3707 else if (*op_string == IMMEDIATE_PREFIX)
3708 {
3709 ++op_string;
3710 if (i.types[this_operand] & JumpAbsolute)
3711 {
3712 as_bad (_("immediate operand illegal with absolute jump"));
3713 return 0;
3714 }
3715 if (!i386_immediate (op_string))
3716 return 0;
3717 }
3718 else if (is_digit_char (*op_string)
3719 || is_identifier_char (*op_string)
3720 || *op_string == '(')
3721 {
3722 /* This is a memory reference of some sort. */
3723 char *base_string;
3724
3725 /* Start and end of displacement string expression (if found). */
3726 char *displacement_string_start;
3727 char *displacement_string_end;
3728
3729 do_memory_reference:
3730 if ((i.mem_operands == 1
3731 && (current_templates->start->opcode_modifier & IsString) == 0)
3732 || i.mem_operands == 2)
3733 {
3734 as_bad (_("too many memory references for `%s'"),
3735 current_templates->start->name);
3736 return 0;
3737 }
3738
3739 /* Check for base index form. We detect the base index form by
3740 looking for an ')' at the end of the operand, searching
3741 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3742 after the '('. */
3743 base_string = op_string + strlen (op_string);
3744
3745 --base_string;
3746 if (is_space_char (*base_string))
3747 --base_string;
3748
3749 /* If we only have a displacement, set-up for it to be parsed later. */
3750 displacement_string_start = op_string;
3751 displacement_string_end = base_string + 1;
3752
3753 if (*base_string == ')')
3754 {
3755 char *temp_string;
3756 unsigned int parens_balanced = 1;
3757 /* We've already checked that the number of left & right ()'s are
3758 equal, so this loop will not be infinite. */
3759 do
3760 {
3761 base_string--;
3762 if (*base_string == ')')
3763 parens_balanced++;
3764 if (*base_string == '(')
3765 parens_balanced--;
3766 }
3767 while (parens_balanced);
3768
3769 temp_string = base_string;
3770
3771 /* Skip past '(' and whitespace. */
3772 ++base_string;
3773 if (is_space_char (*base_string))
3774 ++base_string;
3775
3776 if (*base_string == ','
3777 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
3778 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
3779 {
3780 displacement_string_end = temp_string;
3781
3782 i.types[this_operand] |= BaseIndex;
3783
3784 if (i.base_reg)
3785 {
3786 base_string = end_op;
3787 if (is_space_char (*base_string))
3788 ++base_string;
3789 }
3790
3791 /* There may be an index reg or scale factor here. */
3792 if (*base_string == ',')
3793 {
3794 ++base_string;
3795 if (is_space_char (*base_string))
3796 ++base_string;
3797
3798 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
3799 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
3800 {
3801 base_string = end_op;
3802 if (is_space_char (*base_string))
3803 ++base_string;
3804 if (*base_string == ',')
3805 {
3806 ++base_string;
3807 if (is_space_char (*base_string))
3808 ++base_string;
3809 }
3810 else if (*base_string != ')')
3811 {
3812 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3813 operand_string);
3814 return 0;
3815 }
3816 }
3817 else if (*base_string == REGISTER_PREFIX)
3818 {
3819 as_bad (_("bad register name `%s'"), base_string);
3820 return 0;
3821 }
3822
3823 /* Check for scale factor. */
3824 if (*base_string != ')')
3825 {
3826 char *end_scale = i386_scale (base_string);
3827
3828 if (!end_scale)
3829 return 0;
3830
3831 base_string = end_scale;
3832 if (is_space_char (*base_string))
3833 ++base_string;
3834 if (*base_string != ')')
3835 {
3836 as_bad (_("expecting `)' after scale factor in `%s'"),
3837 operand_string);
3838 return 0;
3839 }
3840 }
3841 else if (!i.index_reg)
3842 {
3843 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3844 *base_string);
3845 return 0;
3846 }
3847 }
3848 else if (*base_string != ')')
3849 {
3850 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3851 operand_string);
3852 return 0;
3853 }
3854 }
3855 else if (*base_string == REGISTER_PREFIX)
3856 {
3857 as_bad (_("bad register name `%s'"), base_string);
3858 return 0;
3859 }
3860 }
3861
3862 /* If there's an expression beginning the operand, parse it,
3863 assuming displacement_string_start and
3864 displacement_string_end are meaningful. */
3865 if (displacement_string_start != displacement_string_end)
3866 {
3867 if (!i386_displacement (displacement_string_start,
3868 displacement_string_end))
3869 return 0;
3870 }
3871
3872 /* Special case for (%dx) while doing input/output op. */
3873 if (i.base_reg
3874 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
3875 && i.index_reg == 0
3876 && i.log2_scale_factor == 0
3877 && i.seg[i.mem_operands] == 0
3878 && (i.types[this_operand] & Disp) == 0)
3879 {
3880 i.types[this_operand] = InOutPortReg;
3881 return 1;
3882 }
3883
3884 if (i386_index_check (operand_string) == 0)
3885 return 0;
3886 i.mem_operands++;
3887 }
3888 else
3889 {
3890 /* It's not a memory operand; argh! */
3891 as_bad (_("invalid char %s beginning operand %d `%s'"),
3892 output_invalid (*op_string),
3893 this_operand + 1,
3894 op_string);
3895 return 0;
3896 }
3897 return 1; /* Normal return. */
3898}
3899
3900/* md_estimate_size_before_relax()
3901
3902 Called just before relax() for rs_machine_dependent frags. The x86
3903 assembler uses these frags to handle variable size jump
3904 instructions.
3905
3906 Any symbol that is now undefined will not become defined.
3907 Return the correct fr_subtype in the frag.
3908 Return the initial "guess for variable size of frag" to caller.
3909 The guess is actually the growth beyond the fixed part. Whatever
3910 we do to grow the fixed or variable part contributes to our
3911 returned value. */
3912
3913int
3914md_estimate_size_before_relax (fragP, segment)
3915 register fragS *fragP;
3916 register segT segment;
3917{
3918 /* We've already got fragP->fr_subtype right; all we have to do is
3919 check for un-relaxable symbols. On an ELF system, we can't relax
3920 an externally visible symbol, because it may be overridden by a
3921 shared library. */
3922 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
3923#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3924 || S_IS_EXTERNAL (fragP->fr_symbol)
3925 || S_IS_WEAK (fragP->fr_symbol)
3926#endif
3927 )
3928 {
3929 /* Symbol is undefined in this segment, or we need to keep a
3930 reloc so that weak symbols can be overridden. */
3931 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
3932 RELOC_ENUM reloc_type;
3933 unsigned char *opcode;
3934 int old_fr_fix;
3935
3936 if (fragP->fr_var != NO_RELOC)
3937 reloc_type = fragP->fr_var;
3938 else if (size == 2)
3939 reloc_type = BFD_RELOC_16_PCREL;
3940 else
3941 reloc_type = BFD_RELOC_32_PCREL;
3942
3943 old_fr_fix = fragP->fr_fix;
3944 opcode = (unsigned char *) fragP->fr_opcode;
3945
3946 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
3947 {
3948 case UNCOND_JUMP:
3949 /* Make jmp (0xeb) a (d)word displacement jump. */
3950 opcode[0] = 0xe9;
3951 fragP->fr_fix += size;
3952 fix_new (fragP, old_fr_fix, size,
3953 fragP->fr_symbol,
3954 fragP->fr_offset, 1,
3955 reloc_type);
3956 break;
3957
3958 case COND_JUMP86:
3959 if (no_cond_jump_promotion)
3960 goto relax_guess;
3961
3962 if (size == 2)
3963 {
3964 /* Negate the condition, and branch past an
3965 unconditional jump. */
3966 opcode[0] ^= 1;
3967 opcode[1] = 3;
3968 /* Insert an unconditional jump. */
3969 opcode[2] = 0xe9;
3970 /* We added two extra opcode bytes, and have a two byte
3971 offset. */
3972 fragP->fr_fix += 2 + 2;
3973 fix_new (fragP, old_fr_fix + 2, 2,
3974 fragP->fr_symbol,
3975 fragP->fr_offset, 1,
3976 reloc_type);
3977 break;
3978 }
3979 /* Fall through. */
3980
3981 case COND_JUMP:
3982 if (no_cond_jump_promotion)
3983 goto relax_guess;
3984
3985 /* This changes the byte-displacement jump 0x7N
3986 to the (d)word-displacement jump 0x0f,0x8N. */
3987 opcode[1] = opcode[0] + 0x10;
3988 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
3989 /* We've added an opcode byte. */
3990 fragP->fr_fix += 1 + size;
3991 fix_new (fragP, old_fr_fix + 1, size,
3992 fragP->fr_symbol,
3993 fragP->fr_offset, 1,
3994 reloc_type);
3995 break;
3996
3997 default:
3998 BAD_CASE (fragP->fr_subtype);
3999 break;
4000 }
4001 frag_wane (fragP);
4002 return fragP->fr_fix - old_fr_fix;
4003 }
4004
4005 relax_guess:
4006 /* Guess size depending on current relax state. Initially the relax
4007 state will correspond to a short jump and we return 1, because
4008 the variable part of the frag (the branch offset) is one byte
4009 long. However, we can relax a section more than once and in that
4010 case we must either set fr_subtype back to the unrelaxed state,
4011 or return the value for the appropriate branch. */
4012 return md_relax_table[fragP->fr_subtype].rlx_length;
4013}
4014
4015/* Called after relax() is finished.
4016
4017 In: Address of frag.
4018 fr_type == rs_machine_dependent.
4019 fr_subtype is what the address relaxed to.
4020
4021 Out: Any fixSs and constants are set up.
4022 Caller will turn frag into a ".space 0". */
4023
4024#ifndef BFD_ASSEMBLER
4025void
4026md_convert_frag (headers, sec, fragP)
4027 object_headers *headers ATTRIBUTE_UNUSED;
4028 segT sec ATTRIBUTE_UNUSED;
4029 register fragS *fragP;
4030#else
4031void
4032md_convert_frag (abfd, sec, fragP)
4033 bfd *abfd ATTRIBUTE_UNUSED;
4034 segT sec ATTRIBUTE_UNUSED;
4035 register fragS *fragP;
4036#endif
4037{
4038 register unsigned char *opcode;
4039 unsigned char *where_to_put_displacement = NULL;
4040 offsetT target_address;
4041 offsetT opcode_address;
4042 unsigned int extension = 0;
4043 offsetT displacement_from_opcode_start;
4044
4045 opcode = (unsigned char *) fragP->fr_opcode;
4046
4047 /* Address we want to reach in file space. */
4048 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
4049#ifdef BFD_ASSEMBLER
4050 /* Not needed otherwise? */
4051 {
4052 /* Local symbols which have already been resolved have a NULL frag. */
4053 fragS *sym_frag = symbol_get_frag (fragP->fr_symbol);
4054 if (sym_frag)
4055 target_address += sym_frag->fr_address;
4056 }
4057#endif
4058
4059 /* Address opcode resides at in file space. */
4060 opcode_address = fragP->fr_address + fragP->fr_fix;
4061
4062 /* Displacement from opcode start to fill into instruction. */
4063 displacement_from_opcode_start = target_address - opcode_address;
4064
4065 if ((fragP->fr_subtype & BIG) == 0)
4066 {
4067 /* Don't have to change opcode. */
4068 extension = 1; /* 1 opcode + 1 displacement */
4069 where_to_put_displacement = &opcode[1];
4070 }
4071 else
4072 {
4073 if (no_cond_jump_promotion
4074 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4075 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
4076
4077 switch (fragP->fr_subtype)
4078 {
4079 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4080 extension = 4; /* 1 opcode + 4 displacement */
4081 opcode[0] = 0xe9;
4082 where_to_put_displacement = &opcode[1];
4083 break;
4084
4085 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4086 extension = 2; /* 1 opcode + 2 displacement */
4087 opcode[0] = 0xe9;
4088 where_to_put_displacement = &opcode[1];
4089 break;
4090
4091 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4092 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4093 extension = 5; /* 2 opcode + 4 displacement */
4094 opcode[1] = opcode[0] + 0x10;
4095 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4096 where_to_put_displacement = &opcode[2];
4097 break;
4098
4099 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4100 extension = 3; /* 2 opcode + 2 displacement */
4101 opcode[1] = opcode[0] + 0x10;
4102 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4103 where_to_put_displacement = &opcode[2];
4104 break;
4105
4106 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4107 extension = 4;
4108 opcode[0] ^= 1;
4109 opcode[1] = 3;
4110 opcode[2] = 0xe9;
4111 where_to_put_displacement = &opcode[3];
4112 break;
4113
4114 default:
4115 BAD_CASE (fragP->fr_subtype);
4116 break;
4117 }
4118 }
4119
4120 /* Now put displacement after opcode. */
4121 md_number_to_chars ((char *) where_to_put_displacement,
4122 (valueT) (displacement_from_opcode_start - extension),
4123 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
4124 fragP->fr_fix += extension;
4125}
4126
4127/* Size of byte displacement jmp. */
4128int md_short_jump_size = 2;
4129
4130/* Size of dword displacement jmp. */
4131int md_long_jump_size = 5;
4132
4133/* Size of relocation record. */
4134const int md_reloc_size = 8;
4135
4136void
4137md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4138 char *ptr;
4139 addressT from_addr, to_addr;
4140 fragS *frag ATTRIBUTE_UNUSED;
4141 symbolS *to_symbol ATTRIBUTE_UNUSED;
4142{
4143 offsetT offset;
4144
4145 offset = to_addr - (from_addr + 2);
4146 /* Opcode for byte-disp jump. */
4147 md_number_to_chars (ptr, (valueT) 0xeb, 1);
4148 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4149}
4150
4151void
4152md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4153 char *ptr;
4154 addressT from_addr, to_addr;
4155 fragS *frag ATTRIBUTE_UNUSED;
4156 symbolS *to_symbol ATTRIBUTE_UNUSED;
4157{
4158 offsetT offset;
4159
4160 offset = to_addr - (from_addr + 5);
4161 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4162 md_number_to_chars (ptr + 1, (valueT) offset, 4);
4163}
4164
4165/* Apply a fixup (fixS) to segment data, once it has been determined
4166 by our caller that we have all the info we need to fix it up.
4167
4168 On the 386, immediates, displacements, and data pointers are all in
4169 the same (little-endian) format, so we don't need to care about which
4170 we are handling. */
4171
4172int
4173md_apply_fix3 (fixP, valp, seg)
4174 /* The fix we're to put in. */
4175 fixS *fixP;
4176
4177 /* Pointer to the value of the bits. */
4178 valueT *valp;
4179
4180 /* Segment fix is from. */
4181 segT seg ATTRIBUTE_UNUSED;
4182{
4183 register char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
4184 valueT value = *valp;
4185
4186#if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4187 if (fixP->fx_pcrel)
4188 {
4189 switch (fixP->fx_r_type)
4190 {
4191 default:
4192 break;
4193
4194 case BFD_RELOC_32:
4195 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4196 break;
4197 case BFD_RELOC_16:
4198 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4199 break;
4200 case BFD_RELOC_8:
4201 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4202 break;
4203 }
4204 }
4205
4206 /* This is a hack. There should be a better way to handle this.
4207 This covers for the fact that bfd_install_relocation will
4208 subtract the current location (for partial_inplace, PC relative
4209 relocations); see more below. */
4210 if ((fixP->fx_r_type == BFD_RELOC_32_PCREL
4211 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4212 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4213 && fixP->fx_addsy && !use_rela_relocations)
4214 {
4215#ifndef OBJ_AOUT
4216 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4217#ifdef TE_PE
4218 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4219#endif
4220 )
4221 value += fixP->fx_where + fixP->fx_frag->fr_address;
4222#endif
4223#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4224 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
4225 {
4226 segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
4227
4228 if ((fseg == seg
4229 || (symbol_section_p (fixP->fx_addsy)
4230 && fseg != absolute_section))
4231 && ! S_IS_EXTERNAL (fixP->fx_addsy)
4232 && ! S_IS_WEAK (fixP->fx_addsy)
4233 && S_IS_DEFINED (fixP->fx_addsy)
4234 && ! S_IS_COMMON (fixP->fx_addsy))
4235 {
4236 /* Yes, we add the values in twice. This is because
4237 bfd_perform_relocation subtracts them out again. I think
4238 bfd_perform_relocation is broken, but I don't dare change
4239 it. FIXME. */
4240 value += fixP->fx_where + fixP->fx_frag->fr_address;
4241 }
4242 }
4243#endif
4244#if defined (OBJ_COFF) && defined (TE_PE)
4245 /* For some reason, the PE format does not store a section
4246 address offset for a PC relative symbol. */
4247 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
4248 value += md_pcrel_from (fixP);
4249#endif
4250 }
4251
4252 /* Fix a few things - the dynamic linker expects certain values here,
4253 and we must not dissappoint it. */
4254#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4255 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4256 && fixP->fx_addsy)
4257 switch (fixP->fx_r_type)
4258 {
4259 case BFD_RELOC_386_PLT32:
4260 case BFD_RELOC_X86_64_PLT32:
4261 /* Make the jump instruction point to the address of the operand. At
4262 runtime we merely add the offset to the actual PLT entry. */
4263 value = -4;
4264 break;
4265 case BFD_RELOC_386_GOTPC:
4266
4267/* This is tough to explain. We end up with this one if we have
4268 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4269 * here is to obtain the absolute address of the GOT, and it is strongly
4270 * preferable from a performance point of view to avoid using a runtime
4271 * relocation for this. The actual sequence of instructions often look
4272 * something like:
4273 *
4274 * call .L66
4275 * .L66:
4276 * popl %ebx
4277 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4278 *
4279 * The call and pop essentially return the absolute address of
4280 * the label .L66 and store it in %ebx. The linker itself will
4281 * ultimately change the first operand of the addl so that %ebx points to
4282 * the GOT, but to keep things simple, the .o file must have this operand
4283 * set so that it generates not the absolute address of .L66, but the
4284 * absolute address of itself. This allows the linker itself simply
4285 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4286 * added in, and the addend of the relocation is stored in the operand
4287 * field for the instruction itself.
4288 *
4289 * Our job here is to fix the operand so that it would add the correct
4290 * offset so that %ebx would point to itself. The thing that is tricky is
4291 * that .-.L66 will point to the beginning of the instruction, so we need
4292 * to further modify the operand so that it will point to itself.
4293 * There are other cases where you have something like:
4294 *
4295 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4296 *
4297 * and here no correction would be required. Internally in the assembler
4298 * we treat operands of this form as not being pcrel since the '.' is
4299 * explicitly mentioned, and I wonder whether it would simplify matters
4300 * to do it this way. Who knows. In earlier versions of the PIC patches,
4301 * the pcrel_adjust field was used to store the correction, but since the
4302 * expression is not pcrel, I felt it would be confusing to do it this
4303 * way. */
4304
4305 value -= 1;
4306 break;
4307 case BFD_RELOC_386_GOT32:
4308 case BFD_RELOC_X86_64_GOT32:
4309 value = 0; /* Fully resolved at runtime. No addend. */
4310 break;
4311 case BFD_RELOC_386_GOTOFF:
4312 case BFD_RELOC_X86_64_GOTPCREL:
4313 break;
4314
4315 case BFD_RELOC_VTABLE_INHERIT:
4316 case BFD_RELOC_VTABLE_ENTRY:
4317 fixP->fx_done = 0;
4318 return 1;
4319
4320 default:
4321 break;
4322 }
4323#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4324 *valp = value;
4325#endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4326
4327#ifndef BFD_ASSEMBLER
4328 md_number_to_chars (p, value, fixP->fx_size);
4329#else
4330 /* Are we finished with this relocation now? */
4331 if (fixP->fx_addsy == 0 && fixP->fx_pcrel == 0)
4332 fixP->fx_done = 1;
4333 else if (use_rela_relocations)
4334 {
4335 fixP->fx_no_overflow = 1;
4336 value = 0;
4337 }
4338 md_number_to_chars (p, value, fixP->fx_size);
4339#endif
4340
4341 return 1;
4342}
4343
4344#define MAX_LITTLENUMS 6
4345
4346/* Turn the string pointed to by litP into a floating point constant
4347 of type TYPE, and emit the appropriate bytes. The number of
4348 LITTLENUMS emitted is stored in *SIZEP. An error message is
4349 returned, or NULL on OK. */
4350
4351char *
4352md_atof (type, litP, sizeP)
4353 int type;
4354 char *litP;
4355 int *sizeP;
4356{
4357 int prec;
4358 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4359 LITTLENUM_TYPE *wordP;
4360 char *t;
4361
4362 switch (type)
4363 {
4364 case 'f':
4365 case 'F':
4366 prec = 2;
4367 break;
4368
4369 case 'd':
4370 case 'D':
4371 prec = 4;
4372 break;
4373
4374 case 'x':
4375 case 'X':
4376 prec = 5;
4377 break;
4378
4379 default:
4380 *sizeP = 0;
4381 return _("Bad call to md_atof ()");
4382 }
4383 t = atof_ieee (input_line_pointer, type, words);
4384 if (t)
4385 input_line_pointer = t;
4386
4387 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4388 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4389 the bigendian 386. */
4390 for (wordP = words + prec - 1; prec--;)
4391 {
4392 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4393 litP += sizeof (LITTLENUM_TYPE);
4394 }
4395 return 0;
4396}
4397
4398char output_invalid_buf[8];
4399
4400static char *
4401output_invalid (c)
4402 int c;
4403{
4404 if (isprint (c))
4405 sprintf (output_invalid_buf, "'%c'", c);
4406 else
4407 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4408 return output_invalid_buf;
4409}
4410
4411/* REG_STRING starts *before* REGISTER_PREFIX. */
4412
4413static const reg_entry *
4414parse_register (reg_string, end_op)
4415 char *reg_string;
4416 char **end_op;
4417{
4418 char *s = reg_string;
4419 char *p;
4420 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4421 const reg_entry *r;
4422
4423 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4424 if (*s == REGISTER_PREFIX)
4425 ++s;
4426
4427 if (is_space_char (*s))
4428 ++s;
4429
4430 p = reg_name_given;
4431 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
4432 {
4433 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
4434 return (const reg_entry *) NULL;
4435 s++;
4436 }
4437
4438 /* For naked regs, make sure that we are not dealing with an identifier.
4439 This prevents confusing an identifier like `eax_var' with register
4440 `eax'. */
4441 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
4442 return (const reg_entry *) NULL;
4443
4444 *end_op = s;
4445
4446 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
4447
4448 /* Handle floating point regs, allowing spaces in the (i) part. */
4449 if (r == i386_regtab /* %st is first entry of table */)
4450 {
4451 if (is_space_char (*s))
4452 ++s;
4453 if (*s == '(')
4454 {
4455 ++s;
4456 if (is_space_char (*s))
4457 ++s;
4458 if (*s >= '0' && *s <= '7')
4459 {
4460 r = &i386_float_regtab[*s - '0'];
4461 ++s;
4462 if (is_space_char (*s))
4463 ++s;
4464 if (*s == ')')
4465 {
4466 *end_op = s + 1;
4467 return r;
4468 }
4469 }
4470 /* We have "%st(" then garbage. */
4471 return (const reg_entry *) NULL;
4472 }
4473 }
4474
|