1/* i386.c -- Assemble code for the Intel 80386
| 1/* i386.c -- Assemble code for the Intel 80386
|
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 1997 Free Software Foundation.
| 2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 1998
3 Free Software Foundation.
|
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
19 02111-1307, USA. */
20
21/*
22 Intel 80386 machine specific gas.
23 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
24 Bugs & suggestions are completely welcome. This is free software.
25 Please help us make it better.
26 */
27
28#include <ctype.h>
29
30#include "as.h"
31#include "subsegs.h"
32
33#include "obstack.h"
34#include "opcode/i386.h"
35
36#ifndef TC_RELOC
37#define TC_RELOC(X,Y) (Y)
38#endif
39
40static unsigned long mode_from_disp_size PARAMS ((unsigned long));
41static int fits_in_signed_byte PARAMS ((long));
42static int fits_in_unsigned_byte PARAMS ((long));
43static int fits_in_unsigned_word PARAMS ((long));
44static int fits_in_signed_word PARAMS ((long));
45static int smallest_imm_type PARAMS ((long));
46static void set_16bit_code_flag PARAMS ((int));
47#ifdef BFD_ASSEMBLER
48static bfd_reloc_code_real_type reloc
49 PARAMS ((int, int, bfd_reloc_code_real_type));
50#endif
51
52/* 'md_assemble ()' gathers together information and puts it into a
53 i386_insn. */
54
55struct _i386_insn
56 {
57 /* TM holds the template for the insn were currently assembling. */
58 template tm;
59 /* SUFFIX holds the opcode suffix (e.g. 'l' for 'movl') if given. */
60 char suffix;
61 /* Operands are coded with OPERANDS, TYPES, DISPS, IMMS, and REGS. */
62
63 /* OPERANDS gives the number of given operands. */
64 unsigned int operands;
65
66 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
67 of given register, displacement, memory operands and immediate
68 operands. */
69 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
70
71 /* TYPES [i] is the type (see above #defines) which tells us how to
72 search through DISPS [i] & IMMS [i] & REGS [i] for the required
73 operand. */
74 unsigned int types[MAX_OPERANDS];
75
76 /* Displacements (if given) for each operand. */
77 expressionS *disps[MAX_OPERANDS];
78
79 /* Relocation type for operand */
80#ifdef BFD_ASSEMBLER
81 enum bfd_reloc_code_real disp_reloc[MAX_OPERANDS];
82#else
83 int disp_reloc[MAX_OPERANDS];
84#endif
85
86 /* Immediate operands (if given) for each operand. */
87 expressionS *imms[MAX_OPERANDS];
88
89 /* Register operands (if given) for each operand. */
90 reg_entry *regs[MAX_OPERANDS];
91
92 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
93 the base index byte below. */
94 reg_entry *base_reg;
95 reg_entry *index_reg;
96 unsigned int log2_scale_factor;
97
98 /* SEG gives the seg_entry of this insn. It is equal to zero unless
99 an explicit segment override is given. */
100 const seg_entry *seg; /* segment for memory operands (if given) */
101
102 /* PREFIX holds all the given prefix opcodes (usually null).
103 PREFIXES is the size of PREFIX. */
104 /* richfix: really unsigned? */
105 unsigned char prefix[MAX_PREFIXES];
106 unsigned int prefixes;
107
| 4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
22/*
23 Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better.
27 */
28
29#include <ctype.h>
30
31#include "as.h"
32#include "subsegs.h"
33
34#include "obstack.h"
35#include "opcode/i386.h"
36
37#ifndef TC_RELOC
38#define TC_RELOC(X,Y) (Y)
39#endif
40
41static unsigned long mode_from_disp_size PARAMS ((unsigned long));
42static int fits_in_signed_byte PARAMS ((long));
43static int fits_in_unsigned_byte PARAMS ((long));
44static int fits_in_unsigned_word PARAMS ((long));
45static int fits_in_signed_word PARAMS ((long));
46static int smallest_imm_type PARAMS ((long));
47static void set_16bit_code_flag PARAMS ((int));
48#ifdef BFD_ASSEMBLER
49static bfd_reloc_code_real_type reloc
50 PARAMS ((int, int, bfd_reloc_code_real_type));
51#endif
52
53/* 'md_assemble ()' gathers together information and puts it into a
54 i386_insn. */
55
56struct _i386_insn
57 {
58 /* TM holds the template for the insn were currently assembling. */
59 template tm;
60 /* SUFFIX holds the opcode suffix (e.g. 'l' for 'movl') if given. */
61 char suffix;
62 /* Operands are coded with OPERANDS, TYPES, DISPS, IMMS, and REGS. */
63
64 /* OPERANDS gives the number of given operands. */
65 unsigned int operands;
66
67 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
68 of given register, displacement, memory operands and immediate
69 operands. */
70 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
71
72 /* TYPES [i] is the type (see above #defines) which tells us how to
73 search through DISPS [i] & IMMS [i] & REGS [i] for the required
74 operand. */
75 unsigned int types[MAX_OPERANDS];
76
77 /* Displacements (if given) for each operand. */
78 expressionS *disps[MAX_OPERANDS];
79
80 /* Relocation type for operand */
81#ifdef BFD_ASSEMBLER
82 enum bfd_reloc_code_real disp_reloc[MAX_OPERANDS];
83#else
84 int disp_reloc[MAX_OPERANDS];
85#endif
86
87 /* Immediate operands (if given) for each operand. */
88 expressionS *imms[MAX_OPERANDS];
89
90 /* Register operands (if given) for each operand. */
91 reg_entry *regs[MAX_OPERANDS];
92
93 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
94 the base index byte below. */
95 reg_entry *base_reg;
96 reg_entry *index_reg;
97 unsigned int log2_scale_factor;
98
99 /* SEG gives the seg_entry of this insn. It is equal to zero unless
100 an explicit segment override is given. */
101 const seg_entry *seg; /* segment for memory operands (if given) */
102
103 /* PREFIX holds all the given prefix opcodes (usually null).
104 PREFIXES is the size of PREFIX. */
105 /* richfix: really unsigned? */
106 unsigned char prefix[MAX_PREFIXES];
107 unsigned int prefixes;
108
|
108 /* RM and IB are the modrm byte and the base index byte where the
| 109 /* RM and BI are the modrm byte and the base index byte where the
|
109 addressing modes of this insn are encoded. */
110
111 modrm_byte rm;
112 base_index_byte bi;
113 };
114
115typedef struct _i386_insn i386_insn;
116
117/* This array holds the chars that always start a comment. If the
118 pre-processor is disabled, these aren't very useful */
119#if defined (TE_I386AIX) || (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && !defined(TE_FreeBSD)
120const char comment_chars[] = "#/";
121#else
122const char comment_chars[] = "#";
123#endif
124
125/* This array holds the chars that only start a comment at the beginning of
126 a line. If the line seems to have the form '# 123 filename'
127 .line and .file directives will appear in the pre-processed output */
128/* Note that input_file.c hand checks for '#' at the beginning of the
129 first line of the input file. This is because the compiler outputs
130 #NO_APP at the beginning of its output. */
131/* Also note that comments started like this one will always work if
132 '/' isn't otherwise defined. */
133#if defined (TE_I386AIX) || (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && !defined(TE_FreeBSD)
134const char line_comment_chars[] = "";
135#else
136const char line_comment_chars[] = "/";
137#endif
138const char line_separator_chars[] = "";
139
140/* Chars that can be used to separate mant from exp in floating point nums */
141const char EXP_CHARS[] = "eE";
142
143/* Chars that mean this number is a floating point constant */
144/* As in 0f12.456 */
145/* or 0d1.2345e12 */
146const char FLT_CHARS[] = "fFdDxX";
147
148/* tables for lexical analysis */
149static char opcode_chars[256];
150static char register_chars[256];
151static char operand_chars[256];
152static char space_chars[256];
153static char identifier_chars[256];
154static char digit_chars[256];
155
156/* lexical macros */
157#define is_opcode_char(x) (opcode_chars[(unsigned char) x])
158#define is_operand_char(x) (operand_chars[(unsigned char) x])
159#define is_register_char(x) (register_chars[(unsigned char) x])
160#define is_space_char(x) (space_chars[(unsigned char) x])
161#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
162#define is_digit_char(x) (digit_chars[(unsigned char) x])
163
164/* put here all non-digit non-letter charcters that may occur in an operand */
165static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
166
167static char *ordinal_names[] = {"first", "second", "third"}; /* for printfs */
168
169/* md_assemble() always leaves the strings it's passed unaltered. To
170 effect this we maintain a stack of saved characters that we've smashed
171 with '\0's (indicating end of strings for various sub-fields of the
172 assembler instruction). */
173static char save_stack[32];
174static char *save_stack_p; /* stack pointer */
175#define END_STRING_AND_SAVE(s) *save_stack_p++ = *s; *s = '\0'
176#define RESTORE_END_STRING(s) *s = *--save_stack_p
177
178/* The instruction we're assembling. */
179static i386_insn i;
180
181/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
182static expressionS disp_expressions[2], im_expressions[2];
183
184/* pointers to ebp & esp entries in reg_hash hash table */
185static reg_entry *ebp, *esp;
186
187static int this_operand; /* current operand we are working on */
188
189static int flag_do_long_jump; /* FIXME what does this do? */
190
191static int flag_16bit_code; /* 1 if we're writing 16-bit code, 0 if 32-bit */
192
193/* Interface to relax_segment.
194 There are 2 relax states for 386 jump insns: one for conditional &
195 one for unconditional jumps. This is because the these two types
196 of jumps add different sizes to frags when we're figuring out what
197 sort of jump to choose to reach a given label. */
198
199/* types */
200#define COND_JUMP 1 /* conditional jump */
201#define UNCOND_JUMP 2 /* unconditional jump */
202/* sizes */
203#define BYTE 0
204#define WORD 1
205#define DWORD 2
206#define UNKNOWN_SIZE 3
207
208#ifndef INLINE
209#ifdef __GNUC__
210#define INLINE __inline__
211#else
212#define INLINE
213#endif
214#endif
215
216#define ENCODE_RELAX_STATE(type,size) \
217 ((relax_substateT)((type<<2) | (size)))
218#define SIZE_FROM_RELAX_STATE(s) \
219 ( (((s) & 0x3) == BYTE ? 1 : (((s) & 0x3) == WORD ? 2 : 4)) )
220
221const relax_typeS md_relax_table[] =
222{
223/* The fields are:
224 1) most positive reach of this state,
225 2) most negative reach of this state,
226 3) how many bytes this mode will add to the size of the current frag
227 4) which index into the table to try if we can't fit into this one.
228 */
229 {1, 1, 0, 0},
230 {1, 1, 0, 0},
231 {1, 1, 0, 0},
232 {1, 1, 0, 0},
233
234 /* For now we don't use word displacement jumps; they may be
235 untrustworthy. */
236 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, DWORD)},
237 /* word conditionals add 3 bytes to frag:
238 2 opcode prefix; 1 displacement bytes */
239 {32767 + 2, -32768 + 2, 3, ENCODE_RELAX_STATE (COND_JUMP, DWORD)},
240 /* dword conditionals adds 4 bytes to frag:
241 1 opcode prefix; 3 displacement bytes */
242 {0, 0, 4, 0},
243 {1, 1, 0, 0},
244
245 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, DWORD)},
246 /* word jmp adds 2 bytes to frag:
247 1 opcode prefix; 1 displacement bytes */
248 {32767 + 2, -32768 + 2, 2, ENCODE_RELAX_STATE (UNCOND_JUMP, DWORD)},
249 /* dword jmp adds 3 bytes to frag:
250 0 opcode prefix; 3 displacement bytes */
251 {0, 0, 3, 0},
252 {1, 1, 0, 0},
253
254};
255
256
257void
258i386_align_code (fragP, count)
259 fragS *fragP;
260 int count;
261{
262 /* Various efficient no-op patterns for aligning code labels. */
263 /* Note: Don't try to assemble the instructions in the comments. */
264 /* 0L and 0w are not legal */
265 static const char f32_1[] =
266 {0x90}; /* nop */
267 static const char f32_2[] =
268 {0x89,0xf6}; /* movl %esi,%esi */
269 static const char f32_3[] =
270 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
271 static const char f32_4[] =
272 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
273 static const char f32_5[] =
274 {0x90, /* nop */
275 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
276 static const char f32_6[] =
277 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
278 static const char f32_7[] =
279 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
280 static const char f32_8[] =
281 {0x90, /* nop */
282 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
283 static const char f32_9[] =
284 {0x89,0xf6, /* movl %esi,%esi */
285 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
286 static const char f32_10[] =
287 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
288 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
289 static const char f32_11[] =
290 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
291 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
292 static const char f32_12[] =
293 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
294 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
295 static const char f32_13[] =
296 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
297 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
298 static const char f32_14[] =
299 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
300 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
301 static const char f32_15[] =
302 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
303 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
304 static const char f16_4[] =
| 110 addressing modes of this insn are encoded. */
111
112 modrm_byte rm;
113 base_index_byte bi;
114 };
115
116typedef struct _i386_insn i386_insn;
117
118/* This array holds the chars that always start a comment. If the
119 pre-processor is disabled, these aren't very useful */
120#if defined (TE_I386AIX) || (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && !defined(TE_FreeBSD)
121const char comment_chars[] = "#/";
122#else
123const char comment_chars[] = "#";
124#endif
125
126/* This array holds the chars that only start a comment at the beginning of
127 a line. If the line seems to have the form '# 123 filename'
128 .line and .file directives will appear in the pre-processed output */
129/* Note that input_file.c hand checks for '#' at the beginning of the
130 first line of the input file. This is because the compiler outputs
131 #NO_APP at the beginning of its output. */
132/* Also note that comments started like this one will always work if
133 '/' isn't otherwise defined. */
134#if defined (TE_I386AIX) || (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && !defined(TE_FreeBSD)
135const char line_comment_chars[] = "";
136#else
137const char line_comment_chars[] = "/";
138#endif
139const char line_separator_chars[] = "";
140
141/* Chars that can be used to separate mant from exp in floating point nums */
142const char EXP_CHARS[] = "eE";
143
144/* Chars that mean this number is a floating point constant */
145/* As in 0f12.456 */
146/* or 0d1.2345e12 */
147const char FLT_CHARS[] = "fFdDxX";
148
149/* tables for lexical analysis */
150static char opcode_chars[256];
151static char register_chars[256];
152static char operand_chars[256];
153static char space_chars[256];
154static char identifier_chars[256];
155static char digit_chars[256];
156
157/* lexical macros */
158#define is_opcode_char(x) (opcode_chars[(unsigned char) x])
159#define is_operand_char(x) (operand_chars[(unsigned char) x])
160#define is_register_char(x) (register_chars[(unsigned char) x])
161#define is_space_char(x) (space_chars[(unsigned char) x])
162#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
163#define is_digit_char(x) (digit_chars[(unsigned char) x])
164
165/* put here all non-digit non-letter charcters that may occur in an operand */
166static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
167
168static char *ordinal_names[] = {"first", "second", "third"}; /* for printfs */
169
170/* md_assemble() always leaves the strings it's passed unaltered. To
171 effect this we maintain a stack of saved characters that we've smashed
172 with '\0's (indicating end of strings for various sub-fields of the
173 assembler instruction). */
174static char save_stack[32];
175static char *save_stack_p; /* stack pointer */
176#define END_STRING_AND_SAVE(s) *save_stack_p++ = *s; *s = '\0'
177#define RESTORE_END_STRING(s) *s = *--save_stack_p
178
179/* The instruction we're assembling. */
180static i386_insn i;
181
182/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
183static expressionS disp_expressions[2], im_expressions[2];
184
185/* pointers to ebp & esp entries in reg_hash hash table */
186static reg_entry *ebp, *esp;
187
188static int this_operand; /* current operand we are working on */
189
190static int flag_do_long_jump; /* FIXME what does this do? */
191
192static int flag_16bit_code; /* 1 if we're writing 16-bit code, 0 if 32-bit */
193
194/* Interface to relax_segment.
195 There are 2 relax states for 386 jump insns: one for conditional &
196 one for unconditional jumps. This is because the these two types
197 of jumps add different sizes to frags when we're figuring out what
198 sort of jump to choose to reach a given label. */
199
200/* types */
201#define COND_JUMP 1 /* conditional jump */
202#define UNCOND_JUMP 2 /* unconditional jump */
203/* sizes */
204#define BYTE 0
205#define WORD 1
206#define DWORD 2
207#define UNKNOWN_SIZE 3
208
209#ifndef INLINE
210#ifdef __GNUC__
211#define INLINE __inline__
212#else
213#define INLINE
214#endif
215#endif
216
217#define ENCODE_RELAX_STATE(type,size) \
218 ((relax_substateT)((type<<2) | (size)))
219#define SIZE_FROM_RELAX_STATE(s) \
220 ( (((s) & 0x3) == BYTE ? 1 : (((s) & 0x3) == WORD ? 2 : 4)) )
221
222const relax_typeS md_relax_table[] =
223{
224/* The fields are:
225 1) most positive reach of this state,
226 2) most negative reach of this state,
227 3) how many bytes this mode will add to the size of the current frag
228 4) which index into the table to try if we can't fit into this one.
229 */
230 {1, 1, 0, 0},
231 {1, 1, 0, 0},
232 {1, 1, 0, 0},
233 {1, 1, 0, 0},
234
235 /* For now we don't use word displacement jumps; they may be
236 untrustworthy. */
237 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, DWORD)},
238 /* word conditionals add 3 bytes to frag:
239 2 opcode prefix; 1 displacement bytes */
240 {32767 + 2, -32768 + 2, 3, ENCODE_RELAX_STATE (COND_JUMP, DWORD)},
241 /* dword conditionals adds 4 bytes to frag:
242 1 opcode prefix; 3 displacement bytes */
243 {0, 0, 4, 0},
244 {1, 1, 0, 0},
245
246 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, DWORD)},
247 /* word jmp adds 2 bytes to frag:
248 1 opcode prefix; 1 displacement bytes */
249 {32767 + 2, -32768 + 2, 2, ENCODE_RELAX_STATE (UNCOND_JUMP, DWORD)},
250 /* dword jmp adds 3 bytes to frag:
251 0 opcode prefix; 3 displacement bytes */
252 {0, 0, 3, 0},
253 {1, 1, 0, 0},
254
255};
256
257
258void
259i386_align_code (fragP, count)
260 fragS *fragP;
261 int count;
262{
263 /* Various efficient no-op patterns for aligning code labels. */
264 /* Note: Don't try to assemble the instructions in the comments. */
265 /* 0L and 0w are not legal */
266 static const char f32_1[] =
267 {0x90}; /* nop */
268 static const char f32_2[] =
269 {0x89,0xf6}; /* movl %esi,%esi */
270 static const char f32_3[] =
271 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
272 static const char f32_4[] =
273 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
274 static const char f32_5[] =
275 {0x90, /* nop */
276 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
277 static const char f32_6[] =
278 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
279 static const char f32_7[] =
280 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
281 static const char f32_8[] =
282 {0x90, /* nop */
283 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
284 static const char f32_9[] =
285 {0x89,0xf6, /* movl %esi,%esi */
286 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
287 static const char f32_10[] =
288 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
289 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
290 static const char f32_11[] =
291 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
292 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
293 static const char f32_12[] =
294 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
295 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
296 static const char f32_13[] =
297 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
298 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
299 static const char f32_14[] =
300 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
301 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
302 static const char f32_15[] =
303 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
304 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
305 static const char f16_4[] =
|
305 {0x8d,0xb6,0x00,0x00}; /* lea 0w(%si),%si */
| 306 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
|
306 static const char f16_5[] =
307 {0x90, /* nop */
| 307 static const char f16_5[] =
308 {0x90, /* nop */
|
308 0x8d,0xb6,0x00,0x00}; /* lea 0w(%si),%si */
| 309 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
|
309 static const char f16_6[] =
310 {0x89,0xf6, /* mov %si,%si */
311 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
312 static const char f16_7[] =
| 310 static const char f16_6[] =
311 {0x89,0xf6, /* mov %si,%si */
312 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
313 static const char f16_7[] =
|
313 {0x8d,0x76,0x00, /* lea 0(%si),%si */
| 314 {0x8d,0x74,0x00, /* lea 0(%si),%si */
|
314 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
315 static const char f16_8[] =
| 315 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
316 static const char f16_8[] =
|
316 {0x8d,0xb6,0x00,0x00, /* lea 0w(%si),%si */
| 317 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
|
317 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
318 static const char *const f32_patt[] = {
319 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
320 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
321 };
322 static const char *const f16_patt[] = {
323 f32_1, f32_2, f32_3, f16_4, f16_5, f16_6, f16_7, f16_8,
324 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
325 };
326
327 if (count > 0 && count <= 15)
328 {
329 if (flag_16bit_code)
330 {
331 memcpy(fragP->fr_literal + fragP->fr_fix,
332 f16_patt[count - 1], count);
333 if (count > 8) /* adjust jump offset */
334 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
335 }
336 else
337 memcpy(fragP->fr_literal + fragP->fr_fix,
338 f32_patt[count - 1], count);
339 fragP->fr_var = count;
340 }
341}
342
343static char *output_invalid PARAMS ((int c));
344static int i386_operand PARAMS ((char *operand_string));
345static reg_entry *parse_register PARAMS ((char *reg_string));
346#ifndef I386COFF
347static void s_bss PARAMS ((int));
348#endif
349
350symbolS *GOT_symbol; /* Pre-defined "__GLOBAL_OFFSET_TABLE" */
351
352static INLINE unsigned long
353mode_from_disp_size (t)
354 unsigned long t;
355{
356 return (t & Disp8) ? 1 : (t & Disp32) ? 2 : 0;
357}
358
359#if 0
360/* Not used. */
361/* convert opcode suffix ('b' 'w' 'l' typically) into type specifier */
362
363static INLINE unsigned long
364opcode_suffix_to_type (s)
365 unsigned long s;
366{
367 return (s == BYTE_OPCODE_SUFFIX
368 ? Byte : (s == WORD_OPCODE_SUFFIX
369 ? Word : DWord));
370} /* opcode_suffix_to_type() */
371#endif
372
373static INLINE int
374fits_in_signed_byte (num)
375 long num;
376{
377 return (num >= -128) && (num <= 127);
378} /* fits_in_signed_byte() */
379
380static INLINE int
381fits_in_unsigned_byte (num)
382 long num;
383{
384 return (num & 0xff) == num;
385} /* fits_in_unsigned_byte() */
386
387static INLINE int
388fits_in_unsigned_word (num)
389 long num;
390{
391 return (num & 0xffff) == num;
392} /* fits_in_unsigned_word() */
393
394static INLINE int
395fits_in_signed_word (num)
396 long num;
397{
398 return (-32768 <= num) && (num <= 32767);
399} /* fits_in_signed_word() */
400
401static int
402smallest_imm_type (num)
403 long num;
404{
405#if 0
406 /* This code is disabled because all the Imm1 forms in the opcode table
407 are slower on the i486, and they're the versions with the implicitly
408 specified single-position displacement, which has another syntax if
409 you really want to use that form. If you really prefer to have the
410 one-byte-shorter Imm1 form despite these problems, re-enable this
411 code. */
412 if (num == 1)
413 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32;
414#endif
415 return (fits_in_signed_byte (num)
416 ? (Imm8S | Imm8 | Imm16 | Imm32)
417 : fits_in_unsigned_byte (num)
418 ? (Imm8 | Imm16 | Imm32)
419 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
420 ? (Imm16 | Imm32)
421 : (Imm32));
422} /* smallest_imm_type() */
423
424static void
425set_16bit_code_flag (new_16bit_code_flag)
426 int new_16bit_code_flag;
427{
428 flag_16bit_code = new_16bit_code_flag;
429}
430
431const pseudo_typeS md_pseudo_table[] =
432{
433#ifndef I386COFF
434 {"bss", s_bss, 0},
435#endif
| 318 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
319 static const char *const f32_patt[] = {
320 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
321 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
322 };
323 static const char *const f16_patt[] = {
324 f32_1, f32_2, f32_3, f16_4, f16_5, f16_6, f16_7, f16_8,
325 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
326 };
327
328 if (count > 0 && count <= 15)
329 {
330 if (flag_16bit_code)
331 {
332 memcpy(fragP->fr_literal + fragP->fr_fix,
333 f16_patt[count - 1], count);
334 if (count > 8) /* adjust jump offset */
335 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
336 }
337 else
338 memcpy(fragP->fr_literal + fragP->fr_fix,
339 f32_patt[count - 1], count);
340 fragP->fr_var = count;
341 }
342}
343
344static char *output_invalid PARAMS ((int c));
345static int i386_operand PARAMS ((char *operand_string));
346static reg_entry *parse_register PARAMS ((char *reg_string));
347#ifndef I386COFF
348static void s_bss PARAMS ((int));
349#endif
350
351symbolS *GOT_symbol; /* Pre-defined "__GLOBAL_OFFSET_TABLE" */
352
353static INLINE unsigned long
354mode_from_disp_size (t)
355 unsigned long t;
356{
357 return (t & Disp8) ? 1 : (t & Disp32) ? 2 : 0;
358}
359
360#if 0
361/* Not used. */
362/* convert opcode suffix ('b' 'w' 'l' typically) into type specifier */
363
364static INLINE unsigned long
365opcode_suffix_to_type (s)
366 unsigned long s;
367{
368 return (s == BYTE_OPCODE_SUFFIX
369 ? Byte : (s == WORD_OPCODE_SUFFIX
370 ? Word : DWord));
371} /* opcode_suffix_to_type() */
372#endif
373
374static INLINE int
375fits_in_signed_byte (num)
376 long num;
377{
378 return (num >= -128) && (num <= 127);
379} /* fits_in_signed_byte() */
380
381static INLINE int
382fits_in_unsigned_byte (num)
383 long num;
384{
385 return (num & 0xff) == num;
386} /* fits_in_unsigned_byte() */
387
388static INLINE int
389fits_in_unsigned_word (num)
390 long num;
391{
392 return (num & 0xffff) == num;
393} /* fits_in_unsigned_word() */
394
395static INLINE int
396fits_in_signed_word (num)
397 long num;
398{
399 return (-32768 <= num) && (num <= 32767);
400} /* fits_in_signed_word() */
401
402static int
403smallest_imm_type (num)
404 long num;
405{
406#if 0
407 /* This code is disabled because all the Imm1 forms in the opcode table
408 are slower on the i486, and they're the versions with the implicitly
409 specified single-position displacement, which has another syntax if
410 you really want to use that form. If you really prefer to have the
411 one-byte-shorter Imm1 form despite these problems, re-enable this
412 code. */
413 if (num == 1)
414 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32;
415#endif
416 return (fits_in_signed_byte (num)
417 ? (Imm8S | Imm8 | Imm16 | Imm32)
418 : fits_in_unsigned_byte (num)
419 ? (Imm8 | Imm16 | Imm32)
420 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
421 ? (Imm16 | Imm32)
422 : (Imm32));
423} /* smallest_imm_type() */
424
425static void
426set_16bit_code_flag (new_16bit_code_flag)
427 int new_16bit_code_flag;
428{
429 flag_16bit_code = new_16bit_code_flag;
430}
431
432const pseudo_typeS md_pseudo_table[] =
433{
434#ifndef I386COFF
435 {"bss", s_bss, 0},
436#endif
|
436#ifndef OBJ_AOUT
| 437#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
|
437 {"align", s_align_bytes, 0},
438#else
439 {"align", s_align_ptwo, 0},
440#endif
441 {"ffloat", float_cons, 'f'},
442 {"dfloat", float_cons, 'd'},
443 {"tfloat", float_cons, 'x'},
444 {"value", cons, 2},
445 {"noopt", s_ignore, 0},
446 {"optim", s_ignore, 0},
447 {"code16", set_16bit_code_flag, 1},
448 {"code32", set_16bit_code_flag, 0},
449 {0, 0, 0}
450};
451
452/* for interface with expression () */
453extern char *input_line_pointer;
454
455/* obstack for constructing various things in md_begin */
456struct obstack o;
457
458/* hash table for opcode lookup */
459static struct hash_control *op_hash;
460/* hash table for register lookup */
461static struct hash_control *reg_hash;
462/* hash table for prefix lookup */
463static struct hash_control *prefix_hash;
464
465
466void
467md_begin ()
468{
469 const char *hash_err;
470
471 obstack_begin (&o, 4096);
472
473 /* initialize op_hash hash table */
474 op_hash = hash_new ();
475
476 {
477 register const template *optab;
478 register templates *core_optab;
479 char *prev_name;
480
481 optab = i386_optab; /* setup for loop */
482 prev_name = optab->name;
483 obstack_grow (&o, optab, sizeof (template));
484 core_optab = (templates *) xmalloc (sizeof (templates));
485
486 for (optab++; optab < i386_optab_end; optab++)
487 {
488 if (!strcmp (optab->name, prev_name))
489 {
490 /* same name as before --> append to current template list */
491 obstack_grow (&o, optab, sizeof (template));
492 }
493 else
494 {
495 /* different name --> ship out current template list;
496 add to hash table; & begin anew */
497 /* Note: end must be set before start! since obstack_next_free
498 changes upon opstack_finish */
499 core_optab->end = (template *) obstack_next_free (&o);
500 core_optab->start = (template *) obstack_finish (&o);
501 hash_err = hash_insert (op_hash, prev_name, (char *) core_optab);
502 if (hash_err)
503 {
504 hash_error:
505 as_fatal ("Internal Error: Can't hash %s: %s", prev_name,
506 hash_err);
507 }
508 prev_name = optab->name;
509 core_optab = (templates *) xmalloc (sizeof (templates));
510 obstack_grow (&o, optab, sizeof (template));
511 }
512 }
513 }
514
515 /* initialize reg_hash hash table */
516 reg_hash = hash_new ();
517 {
518 register const reg_entry *regtab;
519
520 for (regtab = i386_regtab; regtab < i386_regtab_end; regtab++)
521 {
522 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
523 if (hash_err)
524 goto hash_error;
525 }
526 }
527
528 esp = (reg_entry *) hash_find (reg_hash, "esp");
529 ebp = (reg_entry *) hash_find (reg_hash, "ebp");
530
531 /* initialize reg_hash hash table */
532 prefix_hash = hash_new ();
533 {
534 register const prefix_entry *prefixtab;
535
536 for (prefixtab = i386_prefixtab;
537 prefixtab < i386_prefixtab_end; prefixtab++)
538 {
539 hash_err = hash_insert (prefix_hash, prefixtab->prefix_name,
540 (PTR) prefixtab);
541 if (hash_err)
542 goto hash_error;
543 }
544 }
545
546 /* fill in lexical tables: opcode_chars, operand_chars, space_chars */
547 {
548 register int c;
549 register char *p;
550
551 for (c = 0; c < 256; c++)
552 {
553 if (islower (c) || isdigit (c))
554 {
555 opcode_chars[c] = c;
556 register_chars[c] = c;
557 }
558 else if (isupper (c))
559 {
560 opcode_chars[c] = tolower (c);
561 register_chars[c] = opcode_chars[c];
562 }
563 else if (c == PREFIX_SEPERATOR)
564 {
565 opcode_chars[c] = c;
566 }
567 else if (c == ')' || c == '(')
568 {
569 register_chars[c] = c;
570 }
571
572 if (isupper (c) || islower (c) || isdigit (c))
573 operand_chars[c] = c;
574
575 if (isdigit (c) || c == '-')
576 digit_chars[c] = c;
577
578 if (isalpha (c) || c == '_' || c == '.' || isdigit (c))
579 identifier_chars[c] = c;
580
581#ifdef LEX_AT
582 identifier_chars['@'] = '@';
583#endif
584
585 if (c == ' ' || c == '\t')
586 space_chars[c] = c;
587 }
588
589 for (p = operand_special_chars; *p != '\0'; p++)
590 operand_chars[(unsigned char) *p] = *p;
591 }
592
593#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
594 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
595 {
596 record_alignment (text_section, 2);
597 record_alignment (data_section, 2);
598 record_alignment (bss_section, 2);
599 }
600#endif
601}
602
603void
604i386_print_statistics (file)
605 FILE *file;
606{
607 hash_print_statistics (file, "i386 opcode", op_hash);
608 hash_print_statistics (file, "i386 register", reg_hash);
609 hash_print_statistics (file, "i386 prefix", prefix_hash);
610}
611
612
613#ifdef DEBUG386
614
615/* debugging routines for md_assemble */
616static void pi PARAMS ((char *, i386_insn *));
617static void pte PARAMS ((template *));
618static void pt PARAMS ((unsigned int));
619static void pe PARAMS ((expressionS *));
620static void ps PARAMS ((symbolS *));
621
622static void
623pi (line, x)
624 char *line;
625 i386_insn *x;
626{
627 register template *p;
628 int i;
629
630 fprintf (stdout, "%s: template ", line);
631 pte (&x->tm);
632 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x",
633 x->rm.mode, x->rm.reg, x->rm.regmem);
634 fprintf (stdout, " base %x index %x scale %x\n",
635 x->bi.base, x->bi.index, x->bi.scale);
636 for (i = 0; i < x->operands; i++)
637 {
638 fprintf (stdout, " #%d: ", i + 1);
639 pt (x->types[i]);
640 fprintf (stdout, "\n");
641 if (x->types[i]
642 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX))
643 fprintf (stdout, "%s\n", x->regs[i]->reg_name);
644 if (x->types[i] & Imm)
645 pe (x->imms[i]);
646 if (x->types[i] & (Disp | Abs))
647 pe (x->disps[i]);
648 }
649}
650
651static void
652pte (t)
653 template *t;
654{
655 int i;
656 fprintf (stdout, " %d operands ", t->operands);
657 fprintf (stdout, "opcode %x ",
658 t->base_opcode);
659 if (t->extension_opcode != None)
660 fprintf (stdout, "ext %x ", t->extension_opcode);
661 if (t->opcode_modifier & D)
662 fprintf (stdout, "D");
663 if (t->opcode_modifier & W)
664 fprintf (stdout, "W");
665 fprintf (stdout, "\n");
666 for (i = 0; i < t->operands; i++)
667 {
668 fprintf (stdout, " #%d type ", i + 1);
669 pt (t->operand_types[i]);
670 fprintf (stdout, "\n");
671 }
672}
673
674static void
675pe (e)
676 expressionS *e;
677{
678 fprintf (stdout, " operation %d\n", e->X_op);
679 fprintf (stdout, " add_number %d (%x)\n",
680 e->X_add_number, e->X_add_number);
681 if (e->X_add_symbol)
682 {
683 fprintf (stdout, " add_symbol ");
684 ps (e->X_add_symbol);
685 fprintf (stdout, "\n");
686 }
687 if (e->X_op_symbol)
688 {
689 fprintf (stdout, " op_symbol ");
690 ps (e->X_op_symbol);
691 fprintf (stdout, "\n");
692 }
693}
694
695static void
696ps (s)
697 symbolS *s;
698{
699 fprintf (stdout, "%s type %s%s",
700 S_GET_NAME (s),
701 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
702 segment_name (S_GET_SEGMENT (s)));
703}
704
705struct type_name
706 {
707 unsigned int mask;
708 char *tname;
709 }
710
711type_names[] =
712{
713 { Reg8, "r8" },
714 { Reg16, "r16" },
715 { Reg32, "r32" },
716 { Imm8, "i8" },
717 { Imm8S, "i8s" },
718 { Imm16, "i16" },
719 { Imm32, "i32" },
720 { Mem8, "Mem8" },
721 { Mem16, "Mem16" },
722 { Mem32, "Mem32" },
723 { BaseIndex, "BaseIndex" },
724 { Abs8, "Abs8" },
725 { Abs16, "Abs16" },
726 { Abs32, "Abs32" },
727 { Disp8, "d8" },
728 { Disp16, "d16" },
729 { Disp32, "d32" },
730 { SReg2, "SReg2" },
731 { SReg3, "SReg3" },
732 { Acc, "Acc" },
733 { InOutPortReg, "InOutPortReg" },
734 { ShiftCount, "ShiftCount" },
735 { Imm1, "i1" },
736 { Control, "control reg" },
737 { Test, "test reg" },
738 { FloatReg, "FReg" },
739 { FloatAcc, "FAcc" },
740 { JumpAbsolute, "Jump Absolute" },
741 { RegMMX, "rMMX" },
742 { 0, "" }
743};
744
745static void
746pt (t)
747 unsigned int t;
748{
749 register struct type_name *ty;
750
751 if (t == Unknown)
752 {
753 fprintf (stdout, "Unknown");
754 }
755 else
756 {
757 for (ty = type_names; ty->mask; ty++)
758 if (t & ty->mask)
759 fprintf (stdout, "%s, ", ty->tname);
760 }
761 fflush (stdout);
762}
763
764#endif /* DEBUG386 */
765
766#ifdef BFD_ASSEMBLER
767static bfd_reloc_code_real_type
768reloc (size, pcrel, other)
769 int size;
770 int pcrel;
771 bfd_reloc_code_real_type other;
772{
773 if (other != NO_RELOC) return other;
774
775 if (pcrel)
776 switch (size)
777 {
778 case 1: return BFD_RELOC_8_PCREL;
779 case 2: return BFD_RELOC_16_PCREL;
780 case 4: return BFD_RELOC_32_PCREL;
781 }
782 else
783 switch (size)
784 {
785 case 1: return BFD_RELOC_8;
786 case 2: return BFD_RELOC_16;
787 case 4: return BFD_RELOC_32;
788 }
789
790 as_bad ("Can not do %d byte %srelocation", size,
791 pcrel ? "pc-relative " : "");
792 return BFD_RELOC_NONE;
793}
794
795/*
796 * Here we decide which fixups can be adjusted to make them relative to
797 * the beginning of the section instead of the symbol. Basically we need
798 * to make sure that the dynamic relocations are done correctly, so in
799 * some cases we force the original symbol to be used.
800 */
801int
802tc_i386_fix_adjustable(fixP)
803 fixS * fixP;
804{
| 438 {"align", s_align_bytes, 0},
439#else
440 {"align", s_align_ptwo, 0},
441#endif
442 {"ffloat", float_cons, 'f'},
443 {"dfloat", float_cons, 'd'},
444 {"tfloat", float_cons, 'x'},
445 {"value", cons, 2},
446 {"noopt", s_ignore, 0},
447 {"optim", s_ignore, 0},
448 {"code16", set_16bit_code_flag, 1},
449 {"code32", set_16bit_code_flag, 0},
450 {0, 0, 0}
451};
452
453/* for interface with expression () */
454extern char *input_line_pointer;
455
456/* obstack for constructing various things in md_begin */
457struct obstack o;
458
459/* hash table for opcode lookup */
460static struct hash_control *op_hash;
461/* hash table for register lookup */
462static struct hash_control *reg_hash;
463/* hash table for prefix lookup */
464static struct hash_control *prefix_hash;
465
466
467void
468md_begin ()
469{
470 const char *hash_err;
471
472 obstack_begin (&o, 4096);
473
474 /* initialize op_hash hash table */
475 op_hash = hash_new ();
476
477 {
478 register const template *optab;
479 register templates *core_optab;
480 char *prev_name;
481
482 optab = i386_optab; /* setup for loop */
483 prev_name = optab->name;
484 obstack_grow (&o, optab, sizeof (template));
485 core_optab = (templates *) xmalloc (sizeof (templates));
486
487 for (optab++; optab < i386_optab_end; optab++)
488 {
489 if (!strcmp (optab->name, prev_name))
490 {
491 /* same name as before --> append to current template list */
492 obstack_grow (&o, optab, sizeof (template));
493 }
494 else
495 {
496 /* different name --> ship out current template list;
497 add to hash table; & begin anew */
498 /* Note: end must be set before start! since obstack_next_free
499 changes upon opstack_finish */
500 core_optab->end = (template *) obstack_next_free (&o);
501 core_optab->start = (template *) obstack_finish (&o);
502 hash_err = hash_insert (op_hash, prev_name, (char *) core_optab);
503 if (hash_err)
504 {
505 hash_error:
506 as_fatal ("Internal Error: Can't hash %s: %s", prev_name,
507 hash_err);
508 }
509 prev_name = optab->name;
510 core_optab = (templates *) xmalloc (sizeof (templates));
511 obstack_grow (&o, optab, sizeof (template));
512 }
513 }
514 }
515
516 /* initialize reg_hash hash table */
517 reg_hash = hash_new ();
518 {
519 register const reg_entry *regtab;
520
521 for (regtab = i386_regtab; regtab < i386_regtab_end; regtab++)
522 {
523 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
524 if (hash_err)
525 goto hash_error;
526 }
527 }
528
529 esp = (reg_entry *) hash_find (reg_hash, "esp");
530 ebp = (reg_entry *) hash_find (reg_hash, "ebp");
531
532 /* initialize reg_hash hash table */
533 prefix_hash = hash_new ();
534 {
535 register const prefix_entry *prefixtab;
536
537 for (prefixtab = i386_prefixtab;
538 prefixtab < i386_prefixtab_end; prefixtab++)
539 {
540 hash_err = hash_insert (prefix_hash, prefixtab->prefix_name,
541 (PTR) prefixtab);
542 if (hash_err)
543 goto hash_error;
544 }
545 }
546
547 /* fill in lexical tables: opcode_chars, operand_chars, space_chars */
548 {
549 register int c;
550 register char *p;
551
552 for (c = 0; c < 256; c++)
553 {
554 if (islower (c) || isdigit (c))
555 {
556 opcode_chars[c] = c;
557 register_chars[c] = c;
558 }
559 else if (isupper (c))
560 {
561 opcode_chars[c] = tolower (c);
562 register_chars[c] = opcode_chars[c];
563 }
564 else if (c == PREFIX_SEPERATOR)
565 {
566 opcode_chars[c] = c;
567 }
568 else if (c == ')' || c == '(')
569 {
570 register_chars[c] = c;
571 }
572
573 if (isupper (c) || islower (c) || isdigit (c))
574 operand_chars[c] = c;
575
576 if (isdigit (c) || c == '-')
577 digit_chars[c] = c;
578
579 if (isalpha (c) || c == '_' || c == '.' || isdigit (c))
580 identifier_chars[c] = c;
581
582#ifdef LEX_AT
583 identifier_chars['@'] = '@';
584#endif
585
586 if (c == ' ' || c == '\t')
587 space_chars[c] = c;
588 }
589
590 for (p = operand_special_chars; *p != '\0'; p++)
591 operand_chars[(unsigned char) *p] = *p;
592 }
593
594#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
595 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
596 {
597 record_alignment (text_section, 2);
598 record_alignment (data_section, 2);
599 record_alignment (bss_section, 2);
600 }
601#endif
602}
603
604void
605i386_print_statistics (file)
606 FILE *file;
607{
608 hash_print_statistics (file, "i386 opcode", op_hash);
609 hash_print_statistics (file, "i386 register", reg_hash);
610 hash_print_statistics (file, "i386 prefix", prefix_hash);
611}
612
613
614#ifdef DEBUG386
615
616/* debugging routines for md_assemble */
617static void pi PARAMS ((char *, i386_insn *));
618static void pte PARAMS ((template *));
619static void pt PARAMS ((unsigned int));
620static void pe PARAMS ((expressionS *));
621static void ps PARAMS ((symbolS *));
622
623static void
624pi (line, x)
625 char *line;
626 i386_insn *x;
627{
628 register template *p;
629 int i;
630
631 fprintf (stdout, "%s: template ", line);
632 pte (&x->tm);
633 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x",
634 x->rm.mode, x->rm.reg, x->rm.regmem);
635 fprintf (stdout, " base %x index %x scale %x\n",
636 x->bi.base, x->bi.index, x->bi.scale);
637 for (i = 0; i < x->operands; i++)
638 {
639 fprintf (stdout, " #%d: ", i + 1);
640 pt (x->types[i]);
641 fprintf (stdout, "\n");
642 if (x->types[i]
643 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX))
644 fprintf (stdout, "%s\n", x->regs[i]->reg_name);
645 if (x->types[i] & Imm)
646 pe (x->imms[i]);
647 if (x->types[i] & (Disp | Abs))
648 pe (x->disps[i]);
649 }
650}
651
652static void
653pte (t)
654 template *t;
655{
656 int i;
657 fprintf (stdout, " %d operands ", t->operands);
658 fprintf (stdout, "opcode %x ",
659 t->base_opcode);
660 if (t->extension_opcode != None)
661 fprintf (stdout, "ext %x ", t->extension_opcode);
662 if (t->opcode_modifier & D)
663 fprintf (stdout, "D");
664 if (t->opcode_modifier & W)
665 fprintf (stdout, "W");
666 fprintf (stdout, "\n");
667 for (i = 0; i < t->operands; i++)
668 {
669 fprintf (stdout, " #%d type ", i + 1);
670 pt (t->operand_types[i]);
671 fprintf (stdout, "\n");
672 }
673}
674
675static void
676pe (e)
677 expressionS *e;
678{
679 fprintf (stdout, " operation %d\n", e->X_op);
680 fprintf (stdout, " add_number %d (%x)\n",
681 e->X_add_number, e->X_add_number);
682 if (e->X_add_symbol)
683 {
684 fprintf (stdout, " add_symbol ");
685 ps (e->X_add_symbol);
686 fprintf (stdout, "\n");
687 }
688 if (e->X_op_symbol)
689 {
690 fprintf (stdout, " op_symbol ");
691 ps (e->X_op_symbol);
692 fprintf (stdout, "\n");
693 }
694}
695
696static void
697ps (s)
698 symbolS *s;
699{
700 fprintf (stdout, "%s type %s%s",
701 S_GET_NAME (s),
702 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
703 segment_name (S_GET_SEGMENT (s)));
704}
705
706struct type_name
707 {
708 unsigned int mask;
709 char *tname;
710 }
711
712type_names[] =
713{
714 { Reg8, "r8" },
715 { Reg16, "r16" },
716 { Reg32, "r32" },
717 { Imm8, "i8" },
718 { Imm8S, "i8s" },
719 { Imm16, "i16" },
720 { Imm32, "i32" },
721 { Mem8, "Mem8" },
722 { Mem16, "Mem16" },
723 { Mem32, "Mem32" },
724 { BaseIndex, "BaseIndex" },
725 { Abs8, "Abs8" },
726 { Abs16, "Abs16" },
727 { Abs32, "Abs32" },
728 { Disp8, "d8" },
729 { Disp16, "d16" },
730 { Disp32, "d32" },
731 { SReg2, "SReg2" },
732 { SReg3, "SReg3" },
733 { Acc, "Acc" },
734 { InOutPortReg, "InOutPortReg" },
735 { ShiftCount, "ShiftCount" },
736 { Imm1, "i1" },
737 { Control, "control reg" },
738 { Test, "test reg" },
739 { FloatReg, "FReg" },
740 { FloatAcc, "FAcc" },
741 { JumpAbsolute, "Jump Absolute" },
742 { RegMMX, "rMMX" },
743 { 0, "" }
744};
745
746static void
747pt (t)
748 unsigned int t;
749{
750 register struct type_name *ty;
751
752 if (t == Unknown)
753 {
754 fprintf (stdout, "Unknown");
755 }
756 else
757 {
758 for (ty = type_names; ty->mask; ty++)
759 if (t & ty->mask)
760 fprintf (stdout, "%s, ", ty->tname);
761 }
762 fflush (stdout);
763}
764
765#endif /* DEBUG386 */
766
767#ifdef BFD_ASSEMBLER
768static bfd_reloc_code_real_type
769reloc (size, pcrel, other)
770 int size;
771 int pcrel;
772 bfd_reloc_code_real_type other;
773{
774 if (other != NO_RELOC) return other;
775
776 if (pcrel)
777 switch (size)
778 {
779 case 1: return BFD_RELOC_8_PCREL;
780 case 2: return BFD_RELOC_16_PCREL;
781 case 4: return BFD_RELOC_32_PCREL;
782 }
783 else
784 switch (size)
785 {
786 case 1: return BFD_RELOC_8;
787 case 2: return BFD_RELOC_16;
788 case 4: return BFD_RELOC_32;
789 }
790
791 as_bad ("Can not do %d byte %srelocation", size,
792 pcrel ? "pc-relative " : "");
793 return BFD_RELOC_NONE;
794}
795
796/*
797 * Here we decide which fixups can be adjusted to make them relative to
798 * the beginning of the section instead of the symbol. Basically we need
799 * to make sure that the dynamic relocations are done correctly, so in
800 * some cases we force the original symbol to be used.
801 */
802int
803tc_i386_fix_adjustable(fixP)
804 fixS * fixP;
805{
|
805#ifndef OBJ_AOUT
| 806#ifdef OBJ_ELF
|
806 /* Prevent all adjustments to global symbols. */
807 if (S_IS_EXTERN (fixP->fx_addsy))
808 return 0;
809 if (S_IS_WEAK (fixP->fx_addsy))
810 return 0;
811#endif /* ! defined (OBJ_AOUT) */
812 /* adjust_reloc_syms doesn't know about the GOT */
813 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
814 || fixP->fx_r_type == BFD_RELOC_386_PLT32
815 || fixP->fx_r_type == BFD_RELOC_386_GOT32)
816 return 0;
817 return 1;
818}
819#else
820#define reloc(SIZE,PCREL,OTHER) 0
821#define BFD_RELOC_32 0
822#define BFD_RELOC_32_PCREL 0
823#define BFD_RELOC_386_PLT32 0
824#define BFD_RELOC_386_GOT32 0
825#define BFD_RELOC_386_GOTOFF 0
826#endif
827
828/* This is the guts of the machine-dependent assembler. LINE points to a
829 machine dependent instruction. This function is supposed to emit
830 the frags/bytes it assembles to. */
831
832void
833md_assemble (line)
834 char *line;
835{
| 807 /* Prevent all adjustments to global symbols. */
808 if (S_IS_EXTERN (fixP->fx_addsy))
809 return 0;
810 if (S_IS_WEAK (fixP->fx_addsy))
811 return 0;
812#endif /* ! defined (OBJ_AOUT) */
813 /* adjust_reloc_syms doesn't know about the GOT */
814 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
815 || fixP->fx_r_type == BFD_RELOC_386_PLT32
816 || fixP->fx_r_type == BFD_RELOC_386_GOT32)
817 return 0;
818 return 1;
819}
820#else
821#define reloc(SIZE,PCREL,OTHER) 0
822#define BFD_RELOC_32 0
823#define BFD_RELOC_32_PCREL 0
824#define BFD_RELOC_386_PLT32 0
825#define BFD_RELOC_386_GOT32 0
826#define BFD_RELOC_386_GOTOFF 0
827#endif
828
829/* This is the guts of the machine-dependent assembler. LINE points to a
830 machine dependent instruction. This function is supposed to emit
831 the frags/bytes it assembles to. */
832
833void
834md_assemble (line)
835 char *line;
836{
|
836 /* Holds template once we've found it. */
837 template *t;
| 837 /* Points to template once we've found it. */
838 const template *t;
|
838
839 /* Count the size of the instruction generated. */
840 int insn_size = 0;
841
842 /* Possible templates for current insn */
843 templates *current_templates = (templates *) 0;
844
845 int j;
846
| 839
840 /* Count the size of the instruction generated. */
841 int insn_size = 0;
842
843 /* Possible templates for current insn */
844 templates *current_templates = (templates *) 0;
845
846 int j;
847
|
| 848 /* Wait prefix needs to come before any other prefixes, so handle it
849 specially. wait_prefix will hold the opcode modifier flag FWait
850 if a wait prefix is given. */
851 int wait_prefix = 0;
852
|
847 /* Initialize globals. */
848 memset (&i, '\0', sizeof (i));
849 for (j = 0; j < MAX_OPERANDS; j++)
850 i.disp_reloc[j] = NO_RELOC;
851 memset (disp_expressions, '\0', sizeof (disp_expressions));
852 memset (im_expressions, '\0', sizeof (im_expressions));
853 save_stack_p = save_stack; /* reset stack pointer */
854
| 853 /* Initialize globals. */
854 memset (&i, '\0', sizeof (i));
855 for (j = 0; j < MAX_OPERANDS; j++)
856 i.disp_reloc[j] = NO_RELOC;
857 memset (disp_expressions, '\0', sizeof (disp_expressions));
858 memset (im_expressions, '\0', sizeof (im_expressions));
859 save_stack_p = save_stack; /* reset stack pointer */
860
|
855 /* Fist parse an opcode & call i386_operand for the operands.
| 861 /* First parse an opcode & call i386_operand for the operands.
|
856 We assume that the scrubber has arranged it so that line[0] is the valid
857 start of a (possibly prefixed) opcode. */
858 {
859 char *l = line;
860
861 /* 1 if operand is pending after ','. */
862 unsigned int expecting_operand = 0;
863 /* 1 if we found a prefix only acceptable with string insns. */
864 unsigned int expecting_string_instruction = 0;
865 /* Non-zero if operand parens not balanced. */
866 unsigned int paren_not_balanced;
867 char *token_start = l;
868
869 while (!is_space_char (*l) && *l != END_OF_INSN)
870 {
871 if (!is_opcode_char (*l))
872 {
873 as_bad ("invalid character %s in opcode", output_invalid (*l));
874 return;
875 }
876 else if (*l != PREFIX_SEPERATOR)
877 {
878 *l = opcode_chars[(unsigned char) *l]; /* fold case of opcodes */
879 l++;
880 }
881 else
882 {
883 /* This opcode's got a prefix. */
884 unsigned int q;
885 prefix_entry *prefix;
886
887 if (l == token_start)
888 {
889 as_bad ("expecting prefix; got nothing");
890 return;
891 }
892 END_STRING_AND_SAVE (l);
893 prefix = (prefix_entry *) hash_find (prefix_hash, token_start);
894 if (!prefix)
895 {
896 as_bad ("no such opcode prefix ('%s')", token_start);
897 return;
898 }
899 RESTORE_END_STRING (l);
900 /* check for repeated prefix */
901 for (q = 0; q < i.prefixes; q++)
902 if (i.prefix[q] == prefix->prefix_code)
903 {
904 as_bad ("same prefix used twice; you don't really want this!");
905 return;
906 }
| 862 We assume that the scrubber has arranged it so that line[0] is the valid
863 start of a (possibly prefixed) opcode. */
864 {
865 char *l = line;
866
867 /* 1 if operand is pending after ','. */
868 unsigned int expecting_operand = 0;
869 /* 1 if we found a prefix only acceptable with string insns. */
870 unsigned int expecting_string_instruction = 0;
871 /* Non-zero if operand parens not balanced. */
872 unsigned int paren_not_balanced;
873 char *token_start = l;
874
875 while (!is_space_char (*l) && *l != END_OF_INSN)
876 {
877 if (!is_opcode_char (*l))
878 {
879 as_bad ("invalid character %s in opcode", output_invalid (*l));
880 return;
881 }
882 else if (*l != PREFIX_SEPERATOR)
883 {
884 *l = opcode_chars[(unsigned char) *l]; /* fold case of opcodes */
885 l++;
886 }
887 else
888 {
889 /* This opcode's got a prefix. */
890 unsigned int q;
891 prefix_entry *prefix;
892
893 if (l == token_start)
894 {
895 as_bad ("expecting prefix; got nothing");
896 return;
897 }
898 END_STRING_AND_SAVE (l);
899 prefix = (prefix_entry *) hash_find (prefix_hash, token_start);
900 if (!prefix)
901 {
902 as_bad ("no such opcode prefix ('%s')", token_start);
903 return;
904 }
905 RESTORE_END_STRING (l);
906 /* check for repeated prefix */
907 for (q = 0; q < i.prefixes; q++)
908 if (i.prefix[q] == prefix->prefix_code)
909 {
910 as_bad ("same prefix used twice; you don't really want this!");
911 return;
912 }
|
907 if (i.prefixes == MAX_PREFIXES)
| 913 if (prefix->prefix_code == FWAIT_OPCODE)
|
908 {
| 914 {
|
909 as_bad ("too many opcode prefixes");
910 return;
| 915 if (wait_prefix != 0)
916 {
917 as_bad ("same prefix used twice; you don't really want this!");
918 return;
919 }
920 wait_prefix = FWait;
|
911 }
| 921 }
|
912 i.prefix[i.prefixes++] = prefix->prefix_code;
913 if (prefix->prefix_code == REPE || prefix->prefix_code == REPNE)
914 expecting_string_instruction = 1;
| 922 else
923 {
924 if (i.prefixes == MAX_PREFIXES)
925 {
926 as_bad ("too many opcode prefixes");
927 return;
928 }
929 i.prefix[i.prefixes++] = prefix->prefix_code;
930 if (prefix->prefix_code == REPE
931 || prefix->prefix_code == REPNE)
932 expecting_string_instruction = 1;
933 }
|
915 /* skip past PREFIX_SEPERATOR and reset token_start */
916 token_start = ++l;
917 }
918 }
919 END_STRING_AND_SAVE (l);
920 if (token_start == l)
921 {
922 as_bad ("expecting opcode; got nothing");
923 return;
924 }
925
926 /* Lookup insn in hash; try intel & att naming conventions if appropriate;
927 that is: we only use the opcode suffix 'b' 'w' or 'l' if we need to. */
928 current_templates = (templates *) hash_find (op_hash, token_start);
929 if (!current_templates)
930 {
931 int last_index = strlen (token_start) - 1;
932 char last_char = token_start[last_index];
933 switch (last_char)
934 {
935 case DWORD_OPCODE_SUFFIX:
936 case WORD_OPCODE_SUFFIX:
937 case BYTE_OPCODE_SUFFIX:
938 token_start[last_index] = '\0';
939 current_templates = (templates *) hash_find (op_hash, token_start);
940 token_start[last_index] = last_char;
941 i.suffix = last_char;
942 }
943 if (!current_templates)
944 {
945 as_bad ("no such 386 instruction: `%s'", token_start);
946 return;
947 }
948 }
949 RESTORE_END_STRING (l);
950
951 /* check for rep/repne without a string instruction */
952 if (expecting_string_instruction &&
953 !IS_STRING_INSTRUCTION (current_templates->
954 start->base_opcode))
955 {
956 as_bad ("expecting string instruction after rep/repne");
957 return;
958 }
959
960 /* There may be operands to parse. */
961 if (*l != END_OF_INSN &&
962 /* For string instructions, we ignore any operands if given. This
963 kludges, for example, 'rep/movsb %ds:(%esi), %es:(%edi)' where
964 the operands are always going to be the same, and are not really
965 encoded in machine code. */
966 !IS_STRING_INSTRUCTION (current_templates->
967 start->base_opcode))
968 {
969 /* parse operands */
970 do
971 {
972 /* skip optional white space before operand */
973 while (!is_operand_char (*l) && *l != END_OF_INSN)
974 {
975 if (!is_space_char (*l))
976 {
977 as_bad ("invalid character %s before %s operand",
978 output_invalid (*l),
979 ordinal_names[i.operands]);
980 return;
981 }
982 l++;
983 }
984 token_start = l; /* after white space */
985 paren_not_balanced = 0;
986 while (paren_not_balanced || *l != ',')
987 {
988 if (*l == END_OF_INSN)
989 {
990 if (paren_not_balanced)
991 {
992 as_bad ("unbalanced parenthesis in %s operand.",
993 ordinal_names[i.operands]);
994 return;
995 }
996 else
997 break; /* we are done */
998 }
999 else if (!is_operand_char (*l) && !is_space_char (*l))
1000 {
1001 as_bad ("invalid character %s in %s operand",
1002 output_invalid (*l),
1003 ordinal_names[i.operands]);
1004 return;
1005 }
1006 if (*l == '(')
1007 ++paren_not_balanced;
1008 if (*l == ')')
1009 --paren_not_balanced;
1010 l++;
1011 }
1012 if (l != token_start)
1013 { /* yes, we've read in another operand */
1014 unsigned int operand_ok;
1015 this_operand = i.operands++;
1016 if (i.operands > MAX_OPERANDS)
1017 {
1018 as_bad ("spurious operands; (%d operands/instruction max)",
1019 MAX_OPERANDS);
1020 return;
1021 }
1022 /* now parse operand adding info to 'i' as we go along */
1023 END_STRING_AND_SAVE (l);
1024 operand_ok = i386_operand (token_start);
1025 RESTORE_END_STRING (l); /* restore old contents */
1026 if (!operand_ok)
1027 return;
1028 }
1029 else
1030 {
1031 if (expecting_operand)
1032 {
1033 expecting_operand_after_comma:
1034 as_bad ("expecting operand after ','; got nothing");
1035 return;
1036 }
1037 if (*l == ',')
1038 {
1039 as_bad ("expecting operand before ','; got nothing");
1040 return;
1041 }
1042 }
1043
1044 /* now *l must be either ',' or END_OF_INSN */
1045 if (*l == ',')
1046 {
1047 if (*++l == END_OF_INSN)
1048 { /* just skip it, if it's \n complain */
1049 goto expecting_operand_after_comma;
1050 }
1051 expecting_operand = 1;
1052 }
1053 }
1054 while (*l != END_OF_INSN); /* until we get end of insn */
1055 }
1056 }
1057
1058 /* Now we've parsed the opcode into a set of templates, and have the
1059 operands at hand.
1060
1061 Next, we find a template that matches the given insn,
1062 making sure the overlap of the given operands types is consistent
1063 with the template operand types. */
1064
1065#define MATCH(overlap,given_type) \
1066 (overlap && \
1067 (((overlap & (JumpAbsolute|BaseIndex|Mem8)) \
1068 == (given_type & (JumpAbsolute|BaseIndex|Mem8))) \
1069 || (overlap == InOutPortReg)))
1070
1071
1072 /* If m0 and m1 are register matches they must be consistent
1073 with the expected operand types t0 and t1.
1074 That is, if both m0 & m1 are register matches
1075 i.e. ( ((m0 & (Reg)) && (m1 & (Reg)) ) ?
1076 then, either 1. or 2. must be true:
1077 1. the expected operand type register overlap is null:
1078 (t0 & t1 & Reg) == 0
1079 AND
1080 the given register overlap is null:
1081 (m0 & m1 & Reg) == 0
1082 2. the expected operand type register overlap == the given
1083 operand type overlap: (t0 & t1 & m0 & m1 & Reg).
1084 */
1085#define CONSISTENT_REGISTER_MATCH(m0, m1, t0, t1) \
1086 ( ((m0 & (Reg)) && (m1 & (Reg))) ? \
1087 ( ((t0 & t1 & (Reg)) == 0 && (m0 & m1 & (Reg)) == 0) || \
1088 ((t0 & t1) & (m0 & m1) & (Reg)) \
1089 ) : 1)
1090 {
1091 register unsigned int overlap0, overlap1;
1092 expressionS *exp;
1093 unsigned int overlap2;
1094 unsigned int found_reverse_match;
1095
1096 overlap0 = overlap1 = overlap2 = found_reverse_match = 0;
1097 for (t = current_templates->start;
1098 t < current_templates->end;
1099 t++)
1100 {
1101 /* must have right number of operands */
1102 if (i.operands != t->operands)
1103 continue;
1104 else if (!t->operands)
1105 break; /* 0 operands always matches */
1106
1107 overlap0 = i.types[0] & t->operand_types[0];
1108 switch (t->operands)
1109 {
1110 case 1:
1111 if (!MATCH (overlap0, i.types[0]))
1112 continue;
1113 break;
1114 case 2:
1115 case 3:
1116 overlap1 = i.types[1] & t->operand_types[1];
1117 if (!MATCH (overlap0, i.types[0]) ||
1118 !MATCH (overlap1, i.types[1]) ||
1119 !CONSISTENT_REGISTER_MATCH (overlap0, overlap1,
1120 t->operand_types[0],
1121 t->operand_types[1]))
1122 {
1123
1124 /* check if other direction is valid ... */
1125 if (!(t->opcode_modifier & COMES_IN_BOTH_DIRECTIONS))
1126 continue;
1127
1128 /* try reversing direction of operands */
1129 overlap0 = i.types[0] & t->operand_types[1];
1130 overlap1 = i.types[1] & t->operand_types[0];
1131 if (!MATCH (overlap0, i.types[0]) ||
1132 !MATCH (overlap1, i.types[1]) ||
1133 !CONSISTENT_REGISTER_MATCH (overlap0, overlap1,
| 934 /* skip past PREFIX_SEPERATOR and reset token_start */
935 token_start = ++l;
936 }
937 }
938 END_STRING_AND_SAVE (l);
939 if (token_start == l)
940 {
941 as_bad ("expecting opcode; got nothing");
942 return;
943 }
944
945 /* Lookup insn in hash; try intel & att naming conventions if appropriate;
946 that is: we only use the opcode suffix 'b' 'w' or 'l' if we need to. */
947 current_templates = (templates *) hash_find (op_hash, token_start);
948 if (!current_templates)
949 {
950 int last_index = strlen (token_start) - 1;
951 char last_char = token_start[last_index];
952 switch (last_char)
953 {
954 case DWORD_OPCODE_SUFFIX:
955 case WORD_OPCODE_SUFFIX:
956 case BYTE_OPCODE_SUFFIX:
957 token_start[last_index] = '\0';
958 current_templates = (templates *) hash_find (op_hash, token_start);
959 token_start[last_index] = last_char;
960 i.suffix = last_char;
961 }
962 if (!current_templates)
963 {
964 as_bad ("no such 386 instruction: `%s'", token_start);
965 return;
966 }
967 }
968 RESTORE_END_STRING (l);
969
970 /* check for rep/repne without a string instruction */
971 if (expecting_string_instruction &&
972 !IS_STRING_INSTRUCTION (current_templates->
973 start->base_opcode))
974 {
975 as_bad ("expecting string instruction after rep/repne");
976 return;
977 }
978
979 /* There may be operands to parse. */
980 if (*l != END_OF_INSN &&
981 /* For string instructions, we ignore any operands if given. This
982 kludges, for example, 'rep/movsb %ds:(%esi), %es:(%edi)' where
983 the operands are always going to be the same, and are not really
984 encoded in machine code. */
985 !IS_STRING_INSTRUCTION (current_templates->
986 start->base_opcode))
987 {
988 /* parse operands */
989 do
990 {
991 /* skip optional white space before operand */
992 while (!is_operand_char (*l) && *l != END_OF_INSN)
993 {
994 if (!is_space_char (*l))
995 {
996 as_bad ("invalid character %s before %s operand",
997 output_invalid (*l),
998 ordinal_names[i.operands]);
999 return;
1000 }
1001 l++;
1002 }
1003 token_start = l; /* after white space */
1004 paren_not_balanced = 0;
1005 while (paren_not_balanced || *l != ',')
1006 {
1007 if (*l == END_OF_INSN)
1008 {
1009 if (paren_not_balanced)
1010 {
1011 as_bad ("unbalanced parenthesis in %s operand.",
1012 ordinal_names[i.operands]);
1013 return;
1014 }
1015 else
1016 break; /* we are done */
1017 }
1018 else if (!is_operand_char (*l) && !is_space_char (*l))
1019 {
1020 as_bad ("invalid character %s in %s operand",
1021 output_invalid (*l),
1022 ordinal_names[i.operands]);
1023 return;
1024 }
1025 if (*l == '(')
1026 ++paren_not_balanced;
1027 if (*l == ')')
1028 --paren_not_balanced;
1029 l++;
1030 }
1031 if (l != token_start)
1032 { /* yes, we've read in another operand */
1033 unsigned int operand_ok;
1034 this_operand = i.operands++;
1035 if (i.operands > MAX_OPERANDS)
1036 {
1037 as_bad ("spurious operands; (%d operands/instruction max)",
1038 MAX_OPERANDS);
1039 return;
1040 }
1041 /* now parse operand adding info to 'i' as we go along */
1042 END_STRING_AND_SAVE (l);
1043 operand_ok = i386_operand (token_start);
1044 RESTORE_END_STRING (l); /* restore old contents */
1045 if (!operand_ok)
1046 return;
1047 }
1048 else
1049 {
1050 if (expecting_operand)
1051 {
1052 expecting_operand_after_comma:
1053 as_bad ("expecting operand after ','; got nothing");
1054 return;
1055 }
1056 if (*l == ',')
1057 {
1058 as_bad ("expecting operand before ','; got nothing");
1059 return;
1060 }
1061 }
1062
1063 /* now *l must be either ',' or END_OF_INSN */
1064 if (*l == ',')
1065 {
1066 if (*++l == END_OF_INSN)
1067 { /* just skip it, if it's \n complain */
1068 goto expecting_operand_after_comma;
1069 }
1070 expecting_operand = 1;
1071 }
1072 }
1073 while (*l != END_OF_INSN); /* until we get end of insn */
1074 }
1075 }
1076
1077 /* Now we've parsed the opcode into a set of templates, and have the
1078 operands at hand.
1079
1080 Next, we find a template that matches the given insn,
1081 making sure the overlap of the given operands types is consistent
1082 with the template operand types. */
1083
1084#define MATCH(overlap,given_type) \
1085 (overlap && \
1086 (((overlap & (JumpAbsolute|BaseIndex|Mem8)) \
1087 == (given_type & (JumpAbsolute|BaseIndex|Mem8))) \
1088 || (overlap == InOutPortReg)))
1089
1090
1091 /* If m0 and m1 are register matches they must be consistent
1092 with the expected operand types t0 and t1.
1093 That is, if both m0 & m1 are register matches
1094 i.e. ( ((m0 & (Reg)) && (m1 & (Reg)) ) ?
1095 then, either 1. or 2. must be true:
1096 1. the expected operand type register overlap is null:
1097 (t0 & t1 & Reg) == 0
1098 AND
1099 the given register overlap is null:
1100 (m0 & m1 & Reg) == 0
1101 2. the expected operand type register overlap == the given
1102 operand type overlap: (t0 & t1 & m0 & m1 & Reg).
1103 */
1104#define CONSISTENT_REGISTER_MATCH(m0, m1, t0, t1) \
1105 ( ((m0 & (Reg)) && (m1 & (Reg))) ? \
1106 ( ((t0 & t1 & (Reg)) == 0 && (m0 & m1 & (Reg)) == 0) || \
1107 ((t0 & t1) & (m0 & m1) & (Reg)) \
1108 ) : 1)
1109 {
1110 register unsigned int overlap0, overlap1;
1111 expressionS *exp;
1112 unsigned int overlap2;
1113 unsigned int found_reverse_match;
1114
1115 overlap0 = overlap1 = overlap2 = found_reverse_match = 0;
1116 for (t = current_templates->start;
1117 t < current_templates->end;
1118 t++)
1119 {
1120 /* must have right number of operands */
1121 if (i.operands != t->operands)
1122 continue;
1123 else if (!t->operands)
1124 break; /* 0 operands always matches */
1125
1126 overlap0 = i.types[0] & t->operand_types[0];
1127 switch (t->operands)
1128 {
1129 case 1:
1130 if (!MATCH (overlap0, i.types[0]))
1131 continue;
1132 break;
1133 case 2:
1134 case 3:
1135 overlap1 = i.types[1] & t->operand_types[1];
1136 if (!MATCH (overlap0, i.types[0]) ||
1137 !MATCH (overlap1, i.types[1]) ||
1138 !CONSISTENT_REGISTER_MATCH (overlap0, overlap1,
1139 t->operand_types[0],
1140 t->operand_types[1]))
1141 {
1142
1143 /* check if other direction is valid ... */
1144 if (!(t->opcode_modifier & COMES_IN_BOTH_DIRECTIONS))
1145 continue;
1146
1147 /* try reversing direction of operands */
1148 overlap0 = i.types[0] & t->operand_types[1];
1149 overlap1 = i.types[1] & t->operand_types[0];
1150 if (!MATCH (overlap0, i.types[0]) ||
1151 !MATCH (overlap1, i.types[1]) ||
1152 !CONSISTENT_REGISTER_MATCH (overlap0, overlap1,
|
1134 t->operand_types[0],
1135 t->operand_types[1]))
| 1153 t->operand_types[1],
1154 t->operand_types[0]))
|
1136 {
1137 /* does not match either direction */
1138 continue;
1139 }
1140 /* found a reverse match here -- slip through */
1141 /* found_reverse_match holds which of D or FloatD we've found */
1142 found_reverse_match = t->opcode_modifier & COMES_IN_BOTH_DIRECTIONS;
1143 } /* endif: not forward match */
1144 /* found either forward/reverse 2 operand match here */
1145 if (t->operands == 3)
1146 {
1147 overlap2 = i.types[2] & t->operand_types[2];
1148 if (!MATCH (overlap2, i.types[2]) ||
1149 !CONSISTENT_REGISTER_MATCH (overlap0, overlap2,
1150 t->operand_types[0],
1151 t->operand_types[2]) ||
1152 !CONSISTENT_REGISTER_MATCH (overlap1, overlap2,
1153 t->operand_types[1],
1154 t->operand_types[2]))
1155 continue;
1156 }
1157 /* found either forward/reverse 2 or 3 operand match here:
1158 slip through to break */
1159 }
1160 break; /* we've found a match; break out of loop */
1161 } /* for (t = ... */
1162 if (t == current_templates->end)
1163 { /* we found no match */
1164 as_bad ("operands given don't match any known 386 instruction");
1165 return;
1166 }
1167
| 1155 {
1156 /* does not match either direction */
1157 continue;
1158 }
1159 /* found a reverse match here -- slip through */
1160 /* found_reverse_match holds which of D or FloatD we've found */
1161 found_reverse_match = t->opcode_modifier & COMES_IN_BOTH_DIRECTIONS;
1162 } /* endif: not forward match */
1163 /* found either forward/reverse 2 operand match here */
1164 if (t->operands == 3)
1165 {
1166 overlap2 = i.types[2] & t->operand_types[2];
1167 if (!MATCH (overlap2, i.types[2]) ||
1168 !CONSISTENT_REGISTER_MATCH (overlap0, overlap2,
1169 t->operand_types[0],
1170 t->operand_types[2]) ||
1171 !CONSISTENT_REGISTER_MATCH (overlap1, overlap2,
1172 t->operand_types[1],
1173 t->operand_types[2]))
1174 continue;
1175 }
1176 /* found either forward/reverse 2 or 3 operand match here:
1177 slip through to break */
1178 }
1179 break; /* we've found a match; break out of loop */
1180 } /* for (t = ... */
1181 if (t == current_templates->end)
1182 { /* we found no match */
1183 as_bad ("operands given don't match any known 386 instruction");
1184 return;
1185 }
1186
|
1168 /* Copy the template we found (we may change it!). */
| 1187 /* Copy the template we found. */
|
1169 i.tm = *t;
| 1188 i.tm = *t;
|
1170 t = &i.tm; /* alter new copy of template */
| 1189 i.tm.opcode_modifier |= wait_prefix;
|
1171
| 1190
|
| 1191 if (found_reverse_match)
1192 {
1193 i.tm.operand_types[0] = t->operand_types[1];
1194 i.tm.operand_types[1] = t->operand_types[0];
1195 }
1196
|
1172 /* If the matched instruction specifies an explicit opcode suffix,
1173 use it - and make sure none has already been specified. */
| 1197 /* If the matched instruction specifies an explicit opcode suffix,
1198 use it - and make sure none has already been specified. */
|
1174 if (t->opcode_modifier & (Data16|Data32))
| 1199 if (i.tm.opcode_modifier & (Data16|Data32))
|
1175 {
1176 if (i.suffix)
1177 {
1178 as_bad ("extraneous opcode suffix given");
1179 return;
1180 }
| 1200 {
1201 if (i.suffix)
1202 {
1203 as_bad ("extraneous opcode suffix given");
1204 return;
1205 }
|
1181 if (t->opcode_modifier & Data16)
| 1206 if (i.tm.opcode_modifier & Data16)
|
1182 i.suffix = WORD_OPCODE_SUFFIX;
1183 else
1184 i.suffix = DWORD_OPCODE_SUFFIX;
1185 }
1186
1187 /* If there's no opcode suffix we try to invent one based on register
1188 operands. */
1189 if (!i.suffix && i.reg_operands)
1190 {
1191 /* We take i.suffix from the LAST register operand specified. This
1192 assumes that the last register operands is the destination register
1193 operand. */
1194 int op;
1195 for (op = 0; op < MAX_OPERANDS; op++)
1196 if (i.types[op] & Reg)
1197 {
1198 i.suffix = ((i.types[op] & Reg8) ? BYTE_OPCODE_SUFFIX :
1199 (i.types[op] & Reg16) ? WORD_OPCODE_SUFFIX :
1200 DWORD_OPCODE_SUFFIX);
1201 }
1202 }
1203 else if (i.suffix != 0
1204 && i.reg_operands != 0
1205 && (i.types[i.operands - 1] & Reg) != 0)
1206 {
1207 int bad;
1208
1209 /* If the last operand is a register, make sure it is
1210 compatible with the suffix. */
1211
1212 bad = 0;
1213 switch (i.suffix)
1214 {
1215 default:
1216 abort ();
1217 case BYTE_OPCODE_SUFFIX:
1218 /* If this is an eight bit register, it's OK. If it's the
1219 16 or 32 bit version of an eight bit register, we will
1220 just use the low portion, and that's OK too. */
1221 if ((i.types[i.operands - 1] & Reg8) == 0
1222 && i.regs[i.operands - 1]->reg_num >= 4)
1223 bad = 1;
1224 break;
1225 case WORD_OPCODE_SUFFIX:
1226 case DWORD_OPCODE_SUFFIX:
1227 /* We don't insist on the presence or absence of the e
1228 prefix on the register, but we reject eight bit
1229 registers. */
1230 if ((i.types[i.operands - 1] & Reg8) != 0)
1231 bad = 1;
1232 }
1233 if (bad)
1234 as_bad ("register does not match opcode suffix");
1235 }
1236
1237 /* Make still unresolved immediate matches conform to size of immediate
1238 given in i.suffix. Note: overlap2 cannot be an immediate!
1239 We assume this. */
1240 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32))
1241 && overlap0 != Imm8 && overlap0 != Imm8S
1242 && overlap0 != Imm16 && overlap0 != Imm32)
1243 {
1244 if (!i.suffix)
1245 {
1246 as_bad ("no opcode suffix given; can't determine immediate size");
1247 return;
1248 }
1249 overlap0 &= (i.suffix == BYTE_OPCODE_SUFFIX ? (Imm8 | Imm8S) :
1250 (i.suffix == WORD_OPCODE_SUFFIX ? Imm16 : Imm32));
1251 }
1252 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32))
1253 && overlap1 != Imm8 && overlap1 != Imm8S
1254 && overlap1 != Imm16 && overlap1 != Imm32)
1255 {
1256 if (!i.suffix)
1257 {
1258 as_bad ("no opcode suffix given; can't determine immediate size");
1259 return;
1260 }
1261 overlap1 &= (i.suffix == BYTE_OPCODE_SUFFIX ? (Imm8 | Imm8S) :
1262 (i.suffix == WORD_OPCODE_SUFFIX ? Imm16 : Imm32));
1263 }
1264
1265 i.types[0] = overlap0;
1266 i.types[1] = overlap1;
1267 i.types[2] = overlap2;
1268
1269 if (overlap0 & ImplicitRegister)
1270 i.reg_operands--;
1271 if (overlap1 & ImplicitRegister)
1272 i.reg_operands--;
1273 if (overlap2 & ImplicitRegister)
1274 i.reg_operands--;
1275 if (overlap0 & Imm1)
1276 i.imm_operands = 0; /* kludge for shift insns */
1277
| 1207 i.suffix = WORD_OPCODE_SUFFIX;
1208 else
1209 i.suffix = DWORD_OPCODE_SUFFIX;
1210 }
1211
1212 /* If there's no opcode suffix we try to invent one based on register
1213 operands. */
1214 if (!i.suffix && i.reg_operands)
1215 {
1216 /* We take i.suffix from the LAST register operand specified. This
1217 assumes that the last register operands is the destination register
1218 operand. */
1219 int op;
1220 for (op = 0; op < MAX_OPERANDS; op++)
1221 if (i.types[op] & Reg)
1222 {
1223 i.suffix = ((i.types[op] & Reg8) ? BYTE_OPCODE_SUFFIX :
1224 (i.types[op] & Reg16) ? WORD_OPCODE_SUFFIX :
1225 DWORD_OPCODE_SUFFIX);
1226 }
1227 }
1228 else if (i.suffix != 0
1229 && i.reg_operands != 0
1230 && (i.types[i.operands - 1] & Reg) != 0)
1231 {
1232 int bad;
1233
1234 /* If the last operand is a register, make sure it is
1235 compatible with the suffix. */
1236
1237 bad = 0;
1238 switch (i.suffix)
1239 {
1240 default:
1241 abort ();
1242 case BYTE_OPCODE_SUFFIX:
1243 /* If this is an eight bit register, it's OK. If it's the
1244 16 or 32 bit version of an eight bit register, we will
1245 just use the low portion, and that's OK too. */
1246 if ((i.types[i.operands - 1] & Reg8) == 0
1247 && i.regs[i.operands - 1]->reg_num >= 4)
1248 bad = 1;
1249 break;
1250 case WORD_OPCODE_SUFFIX:
1251 case DWORD_OPCODE_SUFFIX:
1252 /* We don't insist on the presence or absence of the e
1253 prefix on the register, but we reject eight bit
1254 registers. */
1255 if ((i.types[i.operands - 1] & Reg8) != 0)
1256 bad = 1;
1257 }
1258 if (bad)
1259 as_bad ("register does not match opcode suffix");
1260 }
1261
1262 /* Make still unresolved immediate matches conform to size of immediate
1263 given in i.suffix. Note: overlap2 cannot be an immediate!
1264 We assume this. */
1265 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32))
1266 && overlap0 != Imm8 && overlap0 != Imm8S
1267 && overlap0 != Imm16 && overlap0 != Imm32)
1268 {
1269 if (!i.suffix)
1270 {
1271 as_bad ("no opcode suffix given; can't determine immediate size");
1272 return;
1273 }
1274 overlap0 &= (i.suffix == BYTE_OPCODE_SUFFIX ? (Imm8 | Imm8S) :
1275 (i.suffix == WORD_OPCODE_SUFFIX ? Imm16 : Imm32));
1276 }
1277 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32))
1278 && overlap1 != Imm8 && overlap1 != Imm8S
1279 && overlap1 != Imm16 && overlap1 != Imm32)
1280 {
1281 if (!i.suffix)
1282 {
1283 as_bad ("no opcode suffix given; can't determine immediate size");
1284 return;
1285 }
1286 overlap1 &= (i.suffix == BYTE_OPCODE_SUFFIX ? (Imm8 | Imm8S) :
1287 (i.suffix == WORD_OPCODE_SUFFIX ? Imm16 : Imm32));
1288 }
1289
1290 i.types[0] = overlap0;
1291 i.types[1] = overlap1;
1292 i.types[2] = overlap2;
1293
1294 if (overlap0 & ImplicitRegister)
1295 i.reg_operands--;
1296 if (overlap1 & ImplicitRegister)
1297 i.reg_operands--;
1298 if (overlap2 & ImplicitRegister)
1299 i.reg_operands--;
1300 if (overlap0 & Imm1)
1301 i.imm_operands = 0; /* kludge for shift insns */
1302
|
1278 if (found_reverse_match)
1279 {
1280 unsigned int save;
1281 save = t->operand_types[0];
1282 t->operand_types[0] = t->operand_types[1];
1283 t->operand_types[1] = save;
1284 }
1285
| |
1286 /* Finalize opcode. First, we change the opcode based on the operand
1287 size given by i.suffix: we never have to change things for byte insns,
1288 or when no opcode suffix is need to size the operands. */
1289
| 1303 /* Finalize opcode. First, we change the opcode based on the operand
1304 size given by i.suffix: we never have to change things for byte insns,
1305 or when no opcode suffix is need to size the operands. */
1306
|
1290 if (!i.suffix && (t->opcode_modifier & W))
| 1307 if (!i.suffix && (i.tm.opcode_modifier & W))
|
1291 {
1292 as_bad ("no opcode suffix given and no register operands; can't size instruction");
1293 return;
1294 }
1295
1296 if (i.suffix && i.suffix != BYTE_OPCODE_SUFFIX)
1297 {
1298 /* Select between byte and word/dword operations. */
| 1308 {
1309 as_bad ("no opcode suffix given and no register operands; can't size instruction");
1310 return;
1311 }
1312
1313 if (i.suffix && i.suffix != BYTE_OPCODE_SUFFIX)
1314 {
1315 /* Select between byte and word/dword operations. */
|
1299 if (t->opcode_modifier & W)
1300 t->base_opcode |= W;
| 1316 if (i.tm.opcode_modifier & W)
1317 i.tm.base_opcode |= W;
|
1301 /* Now select between word & dword operations via the
1302 operand size prefix. */
1303 if ((i.suffix == WORD_OPCODE_SUFFIX) ^ flag_16bit_code)
1304 {
1305 if (i.prefixes == MAX_PREFIXES)
1306 {
| 1318 /* Now select between word & dword operations via the
1319 operand size prefix. */
1320 if ((i.suffix == WORD_OPCODE_SUFFIX) ^ flag_16bit_code)
1321 {
1322 if (i.prefixes == MAX_PREFIXES)
1323 {
|
1307 as_bad ("%d prefixes given and 'w' opcode suffix gives too many prefixes",
| 1324 as_bad ("%d prefixes given and data size prefix gives too many prefixes",
|
1308 MAX_PREFIXES);
1309 return;
1310 }
1311 i.prefix[i.prefixes++] = WORD_PREFIX_OPCODE;
1312 }
1313 }
1314
1315 /* For insns with operands there are more diddles to do to the opcode. */
1316 if (i.operands)
1317 {
1318 /* Default segment register this instruction will use
1319 for memory accesses. 0 means unknown.
1320 This is only for optimizing out unnecessary segment overrides. */
1321 const seg_entry *default_seg = 0;
1322
1323 /* True if this instruction uses a memory addressing mode,
1324 and therefore may need an address-size prefix. */
1325 int uses_mem_addrmode = 0;
1326
1327
1328 /* If we found a reverse match we must alter the opcode direction bit
1329 found_reverse_match holds bit to set (different for int &
1330 float insns). */
1331
1332 if (found_reverse_match)
1333 {
| 1325 MAX_PREFIXES);
1326 return;
1327 }
1328 i.prefix[i.prefixes++] = WORD_PREFIX_OPCODE;
1329 }
1330 }
1331
1332 /* For insns with operands there are more diddles to do to the opcode. */
1333 if (i.operands)
1334 {
1335 /* Default segment register this instruction will use
1336 for memory accesses. 0 means unknown.
1337 This is only for optimizing out unnecessary segment overrides. */
1338 const seg_entry *default_seg = 0;
1339
1340 /* True if this instruction uses a memory addressing mode,
1341 and therefore may need an address-size prefix. */
1342 int uses_mem_addrmode = 0;
1343
1344
1345 /* If we found a reverse match we must alter the opcode direction bit
1346 found_reverse_match holds bit to set (different for int &
1347 float insns). */
1348
1349 if (found_reverse_match)
1350 {
|
1334 t->base_opcode |= found_reverse_match;
| 1351 i.tm.base_opcode |= found_reverse_match;
|
1335 }
1336
1337 /* The imul $imm, %reg instruction is converted into
1338 imul $imm, %reg, %reg. */
| 1352 }
1353
1354 /* The imul $imm, %reg instruction is converted into
1355 imul $imm, %reg, %reg. */
|
1339 if (t->opcode_modifier & imulKludge)
| 1356 if (i.tm.opcode_modifier & imulKludge)
|
1340 {
1341 /* Pretend we saw the 3 operand case. */
1342 i.regs[2] = i.regs[1];
1343 i.reg_operands = 2;
1344 }
1345
1346 /* The clr %reg instruction is converted into xor %reg, %reg. */
| 1357 {
1358 /* Pretend we saw the 3 operand case. */
1359 i.regs[2] = i.regs[1];
1360 i.reg_operands = 2;
1361 }
1362
1363 /* The clr %reg instruction is converted into xor %reg, %reg. */
|
1347 if (t->opcode_modifier & iclrKludge)
| 1364 if (i.tm.opcode_modifier & iclrKludge)
|
1348 {
1349 i.regs[1] = i.regs[0];
1350 i.reg_operands = 2;
1351 }
1352
1353 /* Certain instructions expect the destination to be in the i.rm.reg
1354 field. This is by far the exceptional case. For these
1355 instructions, if the source operand is a register, we must reverse
1356 the i.rm.reg and i.rm.regmem fields. We accomplish this by faking
1357 that the two register operands were given in the reverse order. */
| 1365 {
1366 i.regs[1] = i.regs[0];
1367 i.reg_operands = 2;
1368 }
1369
1370 /* Certain instructions expect the destination to be in the i.rm.reg
1371 field. This is by far the exceptional case. For these
1372 instructions, if the source operand is a register, we must reverse
1373 the i.rm.reg and i.rm.regmem fields. We accomplish this by faking
1374 that the two register operands were given in the reverse order. */
|
1358 if ((t->opcode_modifier & ReverseRegRegmem) && i.reg_operands == 2)
| 1375 if ((i.tm.opcode_modifier & ReverseRegRegmem) && i.reg_operands == 2)
|
1359 {
1360 unsigned int first_reg_operand = (i.types[0] & Reg) ? 0 : 1;
1361 unsigned int second_reg_operand = first_reg_operand + 1;
1362 reg_entry *tmp = i.regs[first_reg_operand];
1363 i.regs[first_reg_operand] = i.regs[second_reg_operand];
1364 i.regs[second_reg_operand] = tmp;
1365 }
1366
| 1376 {
1377 unsigned int first_reg_operand = (i.types[0] & Reg) ? 0 : 1;
1378 unsigned int second_reg_operand = first_reg_operand + 1;
1379 reg_entry *tmp = i.regs[first_reg_operand];
1380 i.regs[first_reg_operand] = i.regs[second_reg_operand];
1381 i.regs[second_reg_operand] = tmp;
1382 }
1383
|
1367 if (t->opcode_modifier & ShortForm)
| 1384 if (i.tm.opcode_modifier & ShortForm)
|
1368 {
1369 /* The register or float register operand is in operand 0 or 1. */
1370 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
1371 /* Register goes in low 3 bits of opcode. */
| 1385 {
1386 /* The register or float register operand is in operand 0 or 1. */
1387 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
1388 /* Register goes in low 3 bits of opcode. */
|
1372 t->base_opcode |= i.regs[op]->reg_num;
| 1389 i.tm.base_opcode |= i.regs[op]->reg_num;
|
1373 }
| 1390 }
|
1374 else if (t->opcode_modifier & ShortFormW)
| 1391 else if (i.tm.opcode_modifier & ShortFormW)
|
1375 {
1376 /* Short form with 0x8 width bit. Register is always dest. operand */
| 1392 {
1393 /* Short form with 0x8 width bit. Register is always dest. operand */
|
1377 t->base_opcode |= i.regs[1]->reg_num;
| 1394 i.tm.base_opcode |= i.regs[1]->reg_num;
|
1378 if (i.suffix == WORD_OPCODE_SUFFIX ||
1379 i.suffix == DWORD_OPCODE_SUFFIX)
| 1395 if (i.suffix == WORD_OPCODE_SUFFIX ||
1396 i.suffix == DWORD_OPCODE_SUFFIX)
|
1380 t->base_opcode |= 0x8;
| 1397 i.tm.base_opcode |= 0x8;
|
1381 }
| 1398 }
|
1382 else if (t->opcode_modifier & Seg2ShortForm)
| 1399 else if (i.tm.opcode_modifier & Seg2ShortForm)
|
1383 {
| 1400 {
|
1384 if (t->base_opcode == POP_SEG_SHORT && i.regs[0]->reg_num == 1)
| 1401 if (i.tm.base_opcode == POP_SEG_SHORT && i.regs[0]->reg_num == 1)
|
1385 {
1386 as_bad ("you can't 'pop cs' on the 386.");
1387 return;
1388 }
| 1402 {
1403 as_bad ("you can't 'pop cs' on the 386.");
1404 return;
1405 }
|
1389 t->base_opcode |= (i.regs[0]->reg_num << 3);
| 1406 i.tm.base_opcode |= (i.regs[0]->reg_num << 3);
|
1390 }
| 1407 }
|
1391 else if (t->opcode_modifier & Seg3ShortForm)
| 1408 else if (i.tm.opcode_modifier & Seg3ShortForm)
|
1392 {
1393 /* 'push %fs' is 0x0fa0; 'pop %fs' is 0x0fa1.
1394 'push %gs' is 0x0fa8; 'pop %fs' is 0x0fa9.
1395 So, only if i.regs[0]->reg_num == 5 (%gs) do we need
1396 to change the opcode. */
1397 if (i.regs[0]->reg_num == 5)
| 1409 {
1410 /* 'push %fs' is 0x0fa0; 'pop %fs' is 0x0fa1.
1411 'push %gs' is 0x0fa8; 'pop %fs' is 0x0fa9.
1412 So, only if i.regs[0]->reg_num == 5 (%gs) do we need
1413 to change the opcode. */
1414 if (i.regs[0]->reg_num == 5)
|
1398 t->base_opcode |= 0x08;
| 1415 i.tm.base_opcode |= 0x08;
|
1399 }
| 1416 }
|
1400 else if ((t->base_opcode & ~DW) == MOV_AX_DISP32)
| 1417 else if ((i.tm.base_opcode & ~DW) == MOV_AX_DISP32)
|
1401 {
1402 /* This is a special non-modrm instruction
1403 that addresses memory with a 32-bit displacement mode anyway,
1404 and thus requires an address-size prefix if in 16-bit mode. */
1405 uses_mem_addrmode = 1;
1406 default_seg = &ds;
1407 }
| 1418 {
1419 /* This is a special non-modrm instruction
1420 that addresses memory with a 32-bit displacement mode anyway,
1421 and thus requires an address-size prefix if in 16-bit mode. */
1422 uses_mem_addrmode = 1;
1423 default_seg = &ds;
1424 }
|
1408 else if (t->opcode_modifier & Modrm)
| 1425 else if (i.tm.opcode_modifier & Modrm)
|
1409 {
| 1426 {
|
1410 /* The opcode is completed (modulo t->extension_opcode which must
1411 be put into the modrm byte.
1412 Now, we make the modrm & index base bytes based on all the info
1413 we've collected. */
| 1427 /* The opcode is completed (modulo i.tm.extension_opcode which
1428 must be put into the modrm byte).
1429 Now, we make the modrm & index base bytes based on all the
1430 info we've collected. */
|
1414
1415 /* i.reg_operands MUST be the number of real register operands;
1416 implicit registers do not count. */
1417 if (i.reg_operands == 2)
1418 {
1419 unsigned int source, dest;
1420 source = ((i.types[0]
1421 & (Reg
1422 | SReg2
1423 | SReg3
1424 | Control
1425 | Debug
1426 | Test
1427 | RegMMX))
1428 ? 0 : 1);
1429 dest = source + 1;
1430 i.rm.mode = 3;
1431 /* We must be careful to make sure that all
1432 segment/control/test/debug/MMX registers go into
1433 the i.rm.reg field (despite the whether they are
1434 source or destination operands). */
1435 if (i.regs[dest]->reg_type
1436 & (SReg2 | SReg3 | Control | Debug | Test | RegMMX))
1437 {
1438 i.rm.reg = i.regs[dest]->reg_num;
1439 i.rm.regmem = i.regs[source]->reg_num;
1440 }
1441 else
1442 {
1443 i.rm.reg = i.regs[source]->reg_num;
1444 i.rm.regmem = i.regs[dest]->reg_num;
1445 }
1446 }
1447 else
1448 { /* if it's not 2 reg operands... */
1449 if (i.mem_operands)
1450 {
1451 unsigned int fake_zero_displacement = 0;
1452 unsigned int op = (i.types[0] & Mem) ? 0 : ((i.types[1] & Mem) ? 1 : 2);
1453
1454 /* Encode memory operand into modrm byte and base index
1455 byte. */
1456
1457 if (i.base_reg == esp && !i.index_reg)
1458 {
1459 /* <disp>(%esp) becomes two byte modrm with no index
1460 register. */
1461 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
1462 i.rm.mode = mode_from_disp_size (i.types[op]);
1463 i.bi.base = ESP_REG_NUM;
1464 i.bi.index = NO_INDEX_REGISTER;
1465 i.bi.scale = 0; /* Must be zero! */
1466 }
1467 else if (i.base_reg == ebp && !i.index_reg)
1468 {
1469 if (!(i.types[op] & Disp))
1470 {
1471 /* Must fake a zero byte displacement. There is
1472 no direct way to code '(%ebp)' directly. */
1473 fake_zero_displacement = 1;
1474 /* fake_zero_displacement code does not set this. */
1475 i.types[op] |= Disp8;
1476 }
1477 i.rm.mode = mode_from_disp_size (i.types[op]);
1478 i.rm.regmem = EBP_REG_NUM;
1479 }
1480 else if (!i.base_reg && (i.types[op] & BaseIndex))
1481 {
1482 /* There are three cases here.
1483 Case 1: '<32bit disp>(,1)' -- indirect absolute.
1484 (Same as cases 2 & 3 with NO index register)
1485 Case 2: <32bit disp> (,<index>) -- no base register with disp
1486 Case 3: (, <index>) --- no base register;
1487 no disp (must add 32bit 0 disp). */
1488 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
1489 i.rm.mode = 0; /* 32bit mode */
1490 i.bi.base = NO_BASE_REGISTER;
1491 i.types[op] &= ~Disp;
1492 i.types[op] |= Disp32; /* Must be 32bit! */
1493 if (i.index_reg)
1494 { /* case 2 or case 3 */
1495 i.bi.index = i.index_reg->reg_num;
1496 i.bi.scale = i.log2_scale_factor;
1497 if (i.disp_operands == 0)
1498 fake_zero_displacement = 1; /* case 3 */
1499 }
1500 else
1501 {
1502 i.bi.index = NO_INDEX_REGISTER;
1503 i.bi.scale = 0;
1504 }
1505 }
1506 else if (i.disp_operands && !i.base_reg && !i.index_reg)
1507 {
1508 /* Operand is just <32bit disp> */
1509 i.rm.regmem = EBP_REG_NUM;
1510 i.rm.mode = 0;
1511 i.types[op] &= ~Disp;
1512 i.types[op] |= Disp32;
1513 }
1514 else
1515 {
1516 /* It's not a special case; rev'em up. */
1517 i.rm.regmem = i.base_reg->reg_num;
1518 i.rm.mode = mode_from_disp_size (i.types[op]);
1519 if (i.index_reg)
1520 {
1521 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
1522 i.bi.base = i.base_reg->reg_num;
1523 i.bi.index = i.index_reg->reg_num;
1524 i.bi.scale = i.log2_scale_factor;
1525 if (i.base_reg == ebp && i.disp_operands == 0)
1526 { /* pace */
1527 fake_zero_displacement = 1;
1528 i.types[op] |= Disp8;
1529 i.rm.mode = mode_from_disp_size (i.types[op]);
1530 }
1531 }
1532 }
1533 if (fake_zero_displacement)
1534 {
1535 /* Fakes a zero displacement assuming that i.types[op]
1536 holds the correct displacement size. */
1537 exp = &disp_expressions[i.disp_operands++];
1538 i.disps[op] = exp;
1539 exp->X_op = O_constant;
1540 exp->X_add_number = 0;
1541 exp->X_add_symbol = (symbolS *) 0;
1542 exp->X_op_symbol = (symbolS *) 0;
1543 }
1544
1545 /* Find the default segment for the memory operand.
1546 Used to optimize out explicit segment specifications. */
1547 if (i.seg)
1548 {
1549 unsigned int seg_index;
1550
1551 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING)
1552 {
1553 seg_index = (i.rm.mode << 3) | i.bi.base;
1554 default_seg = two_byte_segment_defaults[seg_index];
1555 }
1556 else
1557 {
1558 seg_index = (i.rm.mode << 3) | i.rm.regmem;
1559 default_seg = one_byte_segment_defaults[seg_index];
1560 }
1561 }
1562 }
1563
1564 /* Fill in i.rm.reg or i.rm.regmem field with register
| 1431
1432 /* i.reg_operands MUST be the number of real register operands;
1433 implicit registers do not count. */
1434 if (i.reg_operands == 2)
1435 {
1436 unsigned int source, dest;
1437 source = ((i.types[0]
1438 & (Reg
1439 | SReg2
1440 | SReg3
1441 | Control
1442 | Debug
1443 | Test
1444 | RegMMX))
1445 ? 0 : 1);
1446 dest = source + 1;
1447 i.rm.mode = 3;
1448 /* We must be careful to make sure that all
1449 segment/control/test/debug/MMX registers go into
1450 the i.rm.reg field (despite the whether they are
1451 source or destination operands). */
1452 if (i.regs[dest]->reg_type
1453 & (SReg2 | SReg3 | Control | Debug | Test | RegMMX))
1454 {
1455 i.rm.reg = i.regs[dest]->reg_num;
1456 i.rm.regmem = i.regs[source]->reg_num;
1457 }
1458 else
1459 {
1460 i.rm.reg = i.regs[source]->reg_num;
1461 i.rm.regmem = i.regs[dest]->reg_num;
1462 }
1463 }
1464 else
1465 { /* if it's not 2 reg operands... */
1466 if (i.mem_operands)
1467 {
1468 unsigned int fake_zero_displacement = 0;
1469 unsigned int op = (i.types[0] & Mem) ? 0 : ((i.types[1] & Mem) ? 1 : 2);
1470
1471 /* Encode memory operand into modrm byte and base index
1472 byte. */
1473
1474 if (i.base_reg == esp && !i.index_reg)
1475 {
1476 /* <disp>(%esp) becomes two byte modrm with no index
1477 register. */
1478 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
1479 i.rm.mode = mode_from_disp_size (i.types[op]);
1480 i.bi.base = ESP_REG_NUM;
1481 i.bi.index = NO_INDEX_REGISTER;
1482 i.bi.scale = 0; /* Must be zero! */
1483 }
1484 else if (i.base_reg == ebp && !i.index_reg)
1485 {
1486 if (!(i.types[op] & Disp))
1487 {
1488 /* Must fake a zero byte displacement. There is
1489 no direct way to code '(%ebp)' directly. */
1490 fake_zero_displacement = 1;
1491 /* fake_zero_displacement code does not set this. */
1492 i.types[op] |= Disp8;
1493 }
1494 i.rm.mode = mode_from_disp_size (i.types[op]);
1495 i.rm.regmem = EBP_REG_NUM;
1496 }
1497 else if (!i.base_reg && (i.types[op] & BaseIndex))
1498 {
1499 /* There are three cases here.
1500 Case 1: '<32bit disp>(,1)' -- indirect absolute.
1501 (Same as cases 2 & 3 with NO index register)
1502 Case 2: <32bit disp> (,<index>) -- no base register with disp
1503 Case 3: (, <index>) --- no base register;
1504 no disp (must add 32bit 0 disp). */
1505 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
1506 i.rm.mode = 0; /* 32bit mode */
1507 i.bi.base = NO_BASE_REGISTER;
1508 i.types[op] &= ~Disp;
1509 i.types[op] |= Disp32; /* Must be 32bit! */
1510 if (i.index_reg)
1511 { /* case 2 or case 3 */
1512 i.bi.index = i.index_reg->reg_num;
1513 i.bi.scale = i.log2_scale_factor;
1514 if (i.disp_operands == 0)
1515 fake_zero_displacement = 1; /* case 3 */
1516 }
1517 else
1518 {
1519 i.bi.index = NO_INDEX_REGISTER;
1520 i.bi.scale = 0;
1521 }
1522 }
1523 else if (i.disp_operands && !i.base_reg && !i.index_reg)
1524 {
1525 /* Operand is just <32bit disp> */
1526 i.rm.regmem = EBP_REG_NUM;
1527 i.rm.mode = 0;
1528 i.types[op] &= ~Disp;
1529 i.types[op] |= Disp32;
1530 }
1531 else
1532 {
1533 /* It's not a special case; rev'em up. */
1534 i.rm.regmem = i.base_reg->reg_num;
1535 i.rm.mode = mode_from_disp_size (i.types[op]);
1536 if (i.index_reg)
1537 {
1538 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
1539 i.bi.base = i.base_reg->reg_num;
1540 i.bi.index = i.index_reg->reg_num;
1541 i.bi.scale = i.log2_scale_factor;
1542 if (i.base_reg == ebp && i.disp_operands == 0)
1543 { /* pace */
1544 fake_zero_displacement = 1;
1545 i.types[op] |= Disp8;
1546 i.rm.mode = mode_from_disp_size (i.types[op]);
1547 }
1548 }
1549 }
1550 if (fake_zero_displacement)
1551 {
1552 /* Fakes a zero displacement assuming that i.types[op]
1553 holds the correct displacement size. */
1554 exp = &disp_expressions[i.disp_operands++];
1555 i.disps[op] = exp;
1556 exp->X_op = O_constant;
1557 exp->X_add_number = 0;
1558 exp->X_add_symbol = (symbolS *) 0;
1559 exp->X_op_symbol = (symbolS *) 0;
1560 }
1561
1562 /* Find the default segment for the memory operand.
1563 Used to optimize out explicit segment specifications. */
1564 if (i.seg)
1565 {
1566 unsigned int seg_index;
1567
1568 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING)
1569 {
1570 seg_index = (i.rm.mode << 3) | i.bi.base;
1571 default_seg = two_byte_segment_defaults[seg_index];
1572 }
1573 else
1574 {
1575 seg_index = (i.rm.mode << 3) | i.rm.regmem;
1576 default_seg = one_byte_segment_defaults[seg_index];
1577 }
1578 }
1579 }
1580
1581 /* Fill in i.rm.reg or i.rm.regmem field with register
|
1565 operand (if any) based on
1566 t->extension_opcode. Again, we must be careful to
1567 make sure that segment/control/debug/test/MMX
1568 registers are coded into the i.rm.reg field. */
| 1582 operand (if any) based on i.tm.extension_opcode.
1583 Again, we must be careful to make sure that
1584 segment/control/debug/test/MMX registers are coded
1585 into the i.rm.reg field. */
|
1569 if (i.reg_operands)
1570 {
1571 unsigned int op =
1572 ((i.types[0]
1573 & (Reg | SReg2 | SReg3 | Control | Debug
1574 | Test | RegMMX))
1575 ? 0
1576 : ((i.types[1]
1577 & (Reg | SReg2 | SReg3 | Control | Debug
1578 | Test | RegMMX))
1579 ? 1
1580 : 2));
1581 /* If there is an extension opcode to put here, the
1582 register number must be put into the regmem field. */
| 1586 if (i.reg_operands)
1587 {
1588 unsigned int op =
1589 ((i.types[0]
1590 & (Reg | SReg2 | SReg3 | Control | Debug
1591 | Test | RegMMX))
1592 ? 0
1593 : ((i.types[1]
1594 & (Reg | SReg2 | SReg3 | Control | Debug
1595 | Test | RegMMX))
1596 ? 1
1597 : 2));
1598 /* If there is an extension opcode to put here, the
1599 register number must be put into the regmem field. */
|
1583 if (t->extension_opcode != None)
| 1600 if (i.tm.extension_opcode != None)
|
1584 i.rm.regmem = i.regs[op]->reg_num;
1585 else
1586 i.rm.reg = i.regs[op]->reg_num;
1587
1588 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
1589 we must set it to 3 to indicate this is a register
1590 operand int the regmem field */
1591 if (!i.mem_operands)
1592 i.rm.mode = 3;
1593 }
1594
1595 /* Fill in i.rm.reg field with extension opcode (if any). */
| 1601 i.rm.regmem = i.regs[op]->reg_num;
1602 else
1603 i.rm.reg = i.regs[op]->reg_num;
1604
1605 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
1606 we must set it to 3 to indicate this is a register
1607 operand int the regmem field */
1608 if (!i.mem_operands)
1609 i.rm.mode = 3;
1610 }
1611
1612 /* Fill in i.rm.reg field with extension opcode (if any). */
|
1596 if (t->extension_opcode != None)
1597 i.rm.reg = t->extension_opcode;
| 1613 if (i.tm.extension_opcode != None)
1614 i.rm.reg = i.tm.extension_opcode;
|
1598 }
1599
1600 if (i.rm.mode != 3)
1601 uses_mem_addrmode = 1;
1602 }
1603
1604 /* GAS currently doesn't support 16-bit memory addressing modes at all,
1605 so if we're writing 16-bit code and using a memory addressing mode,
1606 always spew out an address size prefix. */
1607 if (uses_mem_addrmode && flag_16bit_code)
1608 {
1609 if (i.prefixes == MAX_PREFIXES)
1610 {
1611 as_bad ("%d prefixes given and address size override gives too many prefixes",
1612 MAX_PREFIXES);
1613 return;
1614 }
1615 i.prefix[i.prefixes++] = ADDR_PREFIX_OPCODE;
1616 }
1617
1618 /* If a segment was explicitly specified,
1619 and the specified segment is not the default,
1620 use an opcode prefix to select it.
1621 If we never figured out what the default segment is,
1622 then default_seg will be zero at this point,
1623 and the specified segment prefix will always be used. */
1624 if ((i.seg) && (i.seg != default_seg))
1625 {
1626 if (i.prefixes == MAX_PREFIXES)
1627 {
1628 as_bad ("%d prefixes given and %s segment override gives too many prefixes",
1629 MAX_PREFIXES, i.seg->seg_name);
1630 return;
1631 }
1632 i.prefix[i.prefixes++] = i.seg->seg_prefix;
1633 }
1634 }
1635 }
1636
1637 /* Handle conversion of 'int $3' --> special int3 insn. */
| 1615 }
1616
1617 if (i.rm.mode != 3)
1618 uses_mem_addrmode = 1;
1619 }
1620
1621 /* GAS currently doesn't support 16-bit memory addressing modes at all,
1622 so if we're writing 16-bit code and using a memory addressing mode,
1623 always spew out an address size prefix. */
1624 if (uses_mem_addrmode && flag_16bit_code)
1625 {
1626 if (i.prefixes == MAX_PREFIXES)
1627 {
1628 as_bad ("%d prefixes given and address size override gives too many prefixes",
1629 MAX_PREFIXES);
1630 return;
1631 }
1632 i.prefix[i.prefixes++] = ADDR_PREFIX_OPCODE;
1633 }
1634
1635 /* If a segment was explicitly specified,
1636 and the specified segment is not the default,
1637 use an opcode prefix to select it.
1638 If we never figured out what the default segment is,
1639 then default_seg will be zero at this point,
1640 and the specified segment prefix will always be used. */
1641 if ((i.seg) && (i.seg != default_seg))
1642 {
1643 if (i.prefixes == MAX_PREFIXES)
1644 {
1645 as_bad ("%d prefixes given and %s segment override gives too many prefixes",
1646 MAX_PREFIXES, i.seg->seg_name);
1647 return;
1648 }
1649 i.prefix[i.prefixes++] = i.seg->seg_prefix;
1650 }
1651 }
1652 }
1653
1654 /* Handle conversion of 'int $3' --> special int3 insn. */
|
1638 if (t->base_opcode == INT_OPCODE && i.imms[0]->X_add_number == 3)
| 1655 if (i.tm.base_opcode == INT_OPCODE && i.imms[0]->X_add_number == 3)
|
1639 {
| 1656 {
|
1640 t->base_opcode = INT3_OPCODE;
| 1657 i.tm.base_opcode = INT3_OPCODE;
|
1641 i.imm_operands = 0;
1642 }
1643
1644 /* We are ready to output the insn. */
1645 {
1646 register char *p;
1647
1648 /* Output jumps. */
| 1658 i.imm_operands = 0;
1659 }
1660
1661 /* We are ready to output the insn. */
1662 {
1663 register char *p;
1664
1665 /* Output jumps. */
|
1649 if (t->opcode_modifier & Jump)
| 1666 if (i.tm.opcode_modifier & Jump)
|
1650 {
1651 unsigned long n = i.disps[0]->X_add_number;
1652
1653 if (i.disps[0]->X_op == O_constant)
1654 {
1655 if (fits_in_signed_byte (n))
1656 {
1657 p = frag_more (2);
1658 insn_size += 2;
| 1667 {
1668 unsigned long n = i.disps[0]->X_add_number;
1669
1670 if (i.disps[0]->X_op == O_constant)
1671 {
1672 if (fits_in_signed_byte (n))
1673 {
1674 p = frag_more (2);
1675 insn_size += 2;
|
1659 p[0] = t->base_opcode;
| 1676 p[0] = i.tm.base_opcode;
|
1660 p[1] = n;
1661 }
1662 else
1663 { /* It's an absolute word/dword displacement. */
1664
1665 /* Use only 16-bit jumps for 16-bit code,
1666 because text segments are limited to 64K anyway;
1667 use only 32-bit jumps for 32-bit code,
1668 because they're faster. */
1669 int jmp_size = flag_16bit_code ? 2 : 4;
1670 if (flag_16bit_code && !fits_in_signed_word (n))
1671 {
1672 as_bad ("16-bit jump out of range");
1673 return;
1674 }
1675
| 1677 p[1] = n;
1678 }
1679 else
1680 { /* It's an absolute word/dword displacement. */
1681
1682 /* Use only 16-bit jumps for 16-bit code,
1683 because text segments are limited to 64K anyway;
1684 use only 32-bit jumps for 32-bit code,
1685 because they're faster. */
1686 int jmp_size = flag_16bit_code ? 2 : 4;
1687 if (flag_16bit_code && !fits_in_signed_word (n))
1688 {
1689 as_bad ("16-bit jump out of range");
1690 return;
1691 }
1692
|
1676 if (t->base_opcode == JUMP_PC_RELATIVE)
| 1693 if (i.tm.base_opcode == JUMP_PC_RELATIVE)
|
1677 { /* pace */
1678 /* unconditional jump */
1679 p = frag_more (1 + jmp_size);
1680 insn_size += 1 + jmp_size;
1681 p[0] = (char) 0xe9;
1682 md_number_to_chars (&p[1], (valueT) n, jmp_size);
1683 }
1684 else
1685 {
1686 /* conditional jump */
1687 p = frag_more (2 + jmp_size);
1688 insn_size += 2 + jmp_size;
1689 p[0] = TWO_BYTE_OPCODE_ESCAPE;
| 1694 { /* pace */
1695 /* unconditional jump */
1696 p = frag_more (1 + jmp_size);
1697 insn_size += 1 + jmp_size;
1698 p[0] = (char) 0xe9;
1699 md_number_to_chars (&p[1], (valueT) n, jmp_size);
1700 }
1701 else
1702 {
1703 /* conditional jump */
1704 p = frag_more (2 + jmp_size);
1705 insn_size += 2 + jmp_size;
1706 p[0] = TWO_BYTE_OPCODE_ESCAPE;
|
1690 p[1] = t->base_opcode + 0x10;
| 1707 p[1] = i.tm.base_opcode + 0x10;
|
1691 md_number_to_chars (&p[2], (valueT) n, jmp_size);
1692 }
1693 }
1694 }
1695 else
1696 {
1697 if (flag_16bit_code)
1698 {
1699 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
1700 insn_size += 1;
1701 }
1702
1703 /* It's a symbol; end frag & setup for relax.
1704 Make sure there are more than 6 chars left in the current frag;
1705 if not we'll have to start a new one. */
1706 frag_grow (7);
1707 p = frag_more (1);
1708 insn_size += 1;
| 1708 md_number_to_chars (&p[2], (valueT) n, jmp_size);
1709 }
1710 }
1711 }
1712 else
1713 {
1714 if (flag_16bit_code)
1715 {
1716 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
1717 insn_size += 1;
1718 }
1719
1720 /* It's a symbol; end frag & setup for relax.
1721 Make sure there are more than 6 chars left in the current frag;
1722 if not we'll have to start a new one. */
1723 frag_grow (7);
1724 p = frag_more (1);
1725 insn_size += 1;
|
1709 p[0] = t->base_opcode;
| 1726 p[0] = i.tm.base_opcode;
|
1710 frag_var (rs_machine_dependent,
1711 6, /* 2 opcode/prefix + 4 displacement */
1712 1,
1713 ((unsigned char) *p == JUMP_PC_RELATIVE
1714 ? ENCODE_RELAX_STATE (UNCOND_JUMP, BYTE)
1715 : ENCODE_RELAX_STATE (COND_JUMP, BYTE)),
1716 i.disps[0]->X_add_symbol,
1717 (offsetT) n, p);
1718 }
1719 }
| 1727 frag_var (rs_machine_dependent,
1728 6, /* 2 opcode/prefix + 4 displacement */
1729 1,
1730 ((unsigned char) *p == JUMP_PC_RELATIVE
1731 ? ENCODE_RELAX_STATE (UNCOND_JUMP, BYTE)
1732 : ENCODE_RELAX_STATE (COND_JUMP, BYTE)),
1733 i.disps[0]->X_add_symbol,
1734 (offsetT) n, p);
1735 }
1736 }
|
1720 else if (t->opcode_modifier & (JumpByte | JumpDword))
| 1737 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
|
1721 {
| 1738 {
|
1722 int size = (t->opcode_modifier & JumpByte) ? 1 : 4;
| 1739 int size = (i.tm.opcode_modifier & JumpByte) ? 1 : 4;
|
1723 unsigned long n = i.disps[0]->X_add_number;
1724 unsigned char *q;
1725
1726 /* The jcx/jecx instruction might need a data size prefix. */
1727 for (q = i.prefix; q < i.prefix + i.prefixes; q++)
1728 {
1729 if (*q == WORD_PREFIX_OPCODE)
1730 {
| 1740 unsigned long n = i.disps[0]->X_add_number;
1741 unsigned char *q;
1742
1743 /* The jcx/jecx instruction might need a data size prefix. */
1744 for (q = i.prefix; q < i.prefix + i.prefixes; q++)
1745 {
1746 if (*q == WORD_PREFIX_OPCODE)
1747 {
|
1731 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
| 1748 /* The jcxz/jecxz instructions are marked with Data16
1749 and Data32, which means that they may get
1750 WORD_PREFIX_OPCODE added to the list of prefixes.
1751 However, the are correctly distinguished using
1752 ADDR_PREFIX_OPCODE. Here we look for
1753 WORD_PREFIX_OPCODE, and actually emit
1754 ADDR_PREFIX_OPCODE. This is a hack, but, then, so
1755 is the instruction itself.
1756
1757 If an explicit suffix is used for the loop
1758 instruction, that actually controls whether we use
1759 cx vs. ecx. This is also controlled by
1760 ADDR_PREFIX_OPCODE.
1761
1762 I don't know if there is any valid case in which we
1763 want to emit WORD_PREFIX_OPCODE, but I am keeping
1764 the old behaviour for safety. */
1765
1766 if (IS_JUMP_ON_CX_ZERO (i.tm.base_opcode)
1767 || IS_LOOP_ECX_TIMES (i.tm.base_opcode))
1768 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
1769 else
1770 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
|
1732 insn_size += 1;
1733 break;
1734 }
1735 }
1736
1737 if ((size == 4) && (flag_16bit_code))
1738 {
1739 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
1740 insn_size += 1;
1741 }
1742
| 1771 insn_size += 1;
1772 break;
1773 }
1774 }
1775
1776 if ((size == 4) && (flag_16bit_code))
1777 {
1778 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
1779 insn_size += 1;
1780 }
1781
|
1743 if (fits_in_unsigned_byte (t->base_opcode))
| 1782 if (fits_in_unsigned_byte (i.tm.base_opcode))
|
1744 {
| 1783 {
|
1745 FRAG_APPEND_1_CHAR (t->base_opcode);
| 1784 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
|
1746 insn_size += 1;
1747 }
1748 else
1749 {
1750 p = frag_more (2); /* opcode can be at most two bytes */
1751 insn_size += 2;
1752 /* put out high byte first: can't use md_number_to_chars! */
| 1785 insn_size += 1;
1786 }
1787 else
1788 {
1789 p = frag_more (2); /* opcode can be at most two bytes */
1790 insn_size += 2;
1791 /* put out high byte first: can't use md_number_to_chars! */
|
1753 *p++ = (t->base_opcode >> 8) & 0xff;
1754 *p = t->base_opcode & 0xff;
| 1792 *p++ = (i.tm.base_opcode >> 8) & 0xff;
1793 *p = i.tm.base_opcode & 0xff;
|
1755 }
1756
1757 p = frag_more (size);
1758 insn_size += size;
1759 if (i.disps[0]->X_op == O_constant)
1760 {
1761 md_number_to_chars (p, (valueT) n, size);
1762 if (size == 1 && !fits_in_signed_byte (n))
1763 {
1764 as_bad ("loop/jecx only takes byte displacement; %lu shortened to %d",
1765 n, *p);
1766 }
1767 }
1768 else
1769 {
1770 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
1771 i.disps[0], 1, reloc (size, 1, i.disp_reloc[0]));
1772
1773 }
1774 }
| 1794 }
1795
1796 p = frag_more (size);
1797 insn_size += size;
1798 if (i.disps[0]->X_op == O_constant)
1799 {
1800 md_number_to_chars (p, (valueT) n, size);
1801 if (size == 1 && !fits_in_signed_byte (n))
1802 {
1803 as_bad ("loop/jecx only takes byte displacement; %lu shortened to %d",
1804 n, *p);
1805 }
1806 }
1807 else
1808 {
1809 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
1810 i.disps[0], 1, reloc (size, 1, i.disp_reloc[0]));
1811
1812 }
1813 }
|
1775 else if (t->opcode_modifier & JumpInterSegment)
| 1814 else if (i.tm.opcode_modifier & JumpInterSegment)
|
1776 {
1777 if (flag_16bit_code)
1778 {
1779 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
1780 insn_size += 1;
1781 }
1782
1783 p = frag_more (1 + 2 + 4); /* 1 opcode; 2 segment; 4 offset */
1784 insn_size += 1 + 2 + 4;
| 1815 {
1816 if (flag_16bit_code)
1817 {
1818 FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
1819 insn_size += 1;
1820 }
1821
1822 p = frag_more (1 + 2 + 4); /* 1 opcode; 2 segment; 4 offset */
1823 insn_size += 1 + 2 + 4;
|
1785 p[0] = t->base_opcode;
| 1824 p[0] = i.tm.base_opcode;
|
1786 if (i.imms[1]->X_op == O_constant)
1787 md_number_to_chars (p + 1, (valueT) i.imms[1]->X_add_number, 4);
1788 else
1789 fix_new_exp (frag_now, p + 1 - frag_now->fr_literal, 4,
1790 i.imms[1], 0, BFD_RELOC_32);
1791 if (i.imms[0]->X_op != O_constant)
1792 as_bad ("can't handle non absolute segment in long call/jmp");
1793 md_number_to_chars (p + 5, (valueT) i.imms[0]->X_add_number, 2);
1794 }
1795 else
1796 {
1797 /* Output normal instructions here. */
1798 unsigned char *q;
1799
| 1825 if (i.imms[1]->X_op == O_constant)
1826 md_number_to_chars (p + 1, (valueT) i.imms[1]->X_add_number, 4);
1827 else
1828 fix_new_exp (frag_now, p + 1 - frag_now->fr_literal, 4,
1829 i.imms[1], 0, BFD_RELOC_32);
1830 if (i.imms[0]->X_op != O_constant)
1831 as_bad ("can't handle non absolute segment in long call/jmp");
1832 md_number_to_chars (p + 5, (valueT) i.imms[0]->X_add_number, 2);
1833 }
1834 else
1835 {
1836 /* Output normal instructions here. */
1837 unsigned char *q;
1838
|
1800 /* First the prefix bytes. */
| 1839 /* Hack for fwait. It must come before any prefixes, as it
1840 really is an instruction rather than a prefix. */
1841 if ((i.tm.opcode_modifier & FWait) != 0)
1842 {
1843 p = frag_more (1);
1844 insn_size += 1;
1845 md_number_to_chars (p, (valueT) FWAIT_OPCODE, 1);
1846 }
1847
1848 /* The prefix bytes. */
|
1801 for (q = i.prefix; q < i.prefix + i.prefixes; q++)
1802 {
1803 p = frag_more (1);
1804 insn_size += 1;
1805 md_number_to_chars (p, (valueT) *q, 1);
1806 }
1807
1808 /* Now the opcode; be careful about word order here! */
| 1849 for (q = i.prefix; q < i.prefix + i.prefixes; q++)
1850 {
1851 p = frag_more (1);
1852 insn_size += 1;
1853 md_number_to_chars (p, (valueT) *q, 1);
1854 }
1855
1856 /* Now the opcode; be careful about word order here! */
|
1809 if (fits_in_unsigned_byte (t->base_opcode))
| 1857 if (fits_in_unsigned_byte (i.tm.base_opcode))
|
1810 {
| 1858 {
|
1811 FRAG_APPEND_1_CHAR (t->base_opcode);
| 1859 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
|
1812 insn_size += 1;
1813 }
| 1860 insn_size += 1;
1861 }
|
1814 else if (fits_in_unsigned_word (t->base_opcode))
| 1862 else if (fits_in_unsigned_word (i.tm.base_opcode))
|
1815 {
1816 p = frag_more (2);
1817 insn_size += 2;
1818 /* put out high byte first: can't use md_number_to_chars! */
| 1863 {
1864 p = frag_more (2);
1865 insn_size += 2;
1866 /* put out high byte first: can't use md_number_to_chars! */
|
1819 *p++ = (t->base_opcode >> 8) & 0xff;
1820 *p = t->base_opcode & 0xff;
| 1867 *p++ = (i.tm.base_opcode >> 8) & 0xff;
1868 *p = i.tm.base_opcode & 0xff;
|
1821 }
1822 else
1823 { /* opcode is either 3 or 4 bytes */
| 1869 }
1870 else
1871 { /* opcode is either 3 or 4 bytes */
|
1824 if (t->base_opcode & 0xff000000)
| 1872 if (i.tm.base_opcode & 0xff000000)
|
1825 {
1826 p = frag_more (4);
1827 insn_size += 4;
| 1873 {
1874 p = frag_more (4);
1875 insn_size += 4;
|
1828 *p++ = (t->base_opcode >> 24) & 0xff;
| 1876 *p++ = (i.tm.base_opcode >> 24) & 0xff;
|
1829 }
1830 else
1831 {
1832 p = frag_more (3);
1833 insn_size += 3;
1834 }
| 1877 }
1878 else
1879 {
1880 p = frag_more (3);
1881 insn_size += 3;
1882 }
|
1835 *p++ = (t->base_opcode >> 16) & 0xff;
1836 *p++ = (t->base_opcode >> 8) & 0xff;
1837 *p = (t->base_opcode) & 0xff;
| 1883 *p++ = (i.tm.base_opcode >> 16) & 0xff;
1884 *p++ = (i.tm.base_opcode >> 8) & 0xff;
1885 *p = (i.tm.base_opcode) & 0xff;
|
1838 }
1839
1840 /* Now the modrm byte and base index byte (if present). */
| 1886 }
1887
1888 /* Now the modrm byte and base index byte (if present). */
|
1841 if (t->opcode_modifier & Modrm)
| 1889 if (i.tm.opcode_modifier & Modrm)
|
1842 {
1843 p = frag_more (1);
1844 insn_size += 1;
1845 /* md_number_to_chars (p, i.rm, 1); */
1846 md_number_to_chars (p,
1847 (valueT) (i.rm.regmem << 0
1848 | i.rm.reg << 3
1849 | i.rm.mode << 6),
1850 1);
1851 /* If i.rm.regmem == ESP (4) && i.rm.mode != Mode 3 (Register mode)
1852 ==> need second modrm byte. */
1853 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING && i.rm.mode != 3)
1854 {
1855 p = frag_more (1);
1856 insn_size += 1;
1857 /* md_number_to_chars (p, i.bi, 1); */
1858 md_number_to_chars (p, (valueT) (i.bi.base << 0
1859 | i.bi.index << 3
1860 | i.bi.scale << 6),
1861 1);
1862 }
1863 }
1864
1865 if (i.disp_operands)
1866 {
1867 register unsigned int n;
1868
1869 for (n = 0; n < i.operands; n++)
1870 {
1871 if (i.disps[n])
1872 {
1873 if (i.disps[n]->X_op == O_constant)
1874 {
1875 if (i.types[n] & (Disp8 | Abs8))
1876 {
1877 p = frag_more (1);
1878 insn_size += 1;
1879 md_number_to_chars (p,
1880 (valueT) i.disps[n]->X_add_number,
1881 1);
1882 }
1883 else if (i.types[n] & (Disp16 | Abs16))
1884 {
1885 p = frag_more (2);
1886 insn_size += 2;
1887 md_number_to_chars (p,
1888 (valueT) i.disps[n]->X_add_number,
1889 2);
1890 }
1891 else
1892 { /* Disp32|Abs32 */
1893 p = frag_more (4);
1894 insn_size += 4;
1895 md_number_to_chars (p,
1896 (valueT) i.disps[n]->X_add_number,
1897 4);
1898 }
1899 }
1900 else
1901 { /* not absolute_section */
1902 /* need a 32-bit fixup (don't support 8bit non-absolute disps) */
1903 p = frag_more (4);
1904 insn_size += 4;
1905 fix_new_exp (frag_now, p - frag_now->fr_literal, 4,
1906 i.disps[n], 0,
1907 TC_RELOC(i.disp_reloc[n], BFD_RELOC_32));
1908 }
1909 }
1910 }
1911 } /* end displacement output */
1912
1913 /* output immediate */
1914 if (i.imm_operands)
1915 {
1916 register unsigned int n;
1917
1918 for (n = 0; n < i.operands; n++)
1919 {
1920 if (i.imms[n])
1921 {
1922 if (i.imms[n]->X_op == O_constant)
1923 {
1924 if (i.types[n] & (Imm8 | Imm8S))
1925 {
1926 p = frag_more (1);
1927 insn_size += 1;
1928 md_number_to_chars (p,
1929 (valueT) i.imms[n]->X_add_number,
1930 1);
1931 }
1932 else if (i.types[n] & Imm16)
1933 {
1934 p = frag_more (2);
1935 insn_size += 2;
1936 md_number_to_chars (p,
1937 (valueT) i.imms[n]->X_add_number,
1938 2);
1939 }
1940 else
1941 {
1942 p = frag_more (4);
1943 insn_size += 4;
1944 md_number_to_chars (p,
1945 (valueT) i.imms[n]->X_add_number,
1946 4);
1947 }
1948 }
1949 else
1950 { /* not absolute_section */
1951 /* Need a 32-bit fixup (don't support 8bit
1952 non-absolute ims). Try to support other
1953 sizes ... */
1954 int r_type;
1955 int size;
1956 int pcrel = 0;
1957
1958 if (i.types[n] & (Imm8 | Imm8S))
1959 size = 1;
1960 else if (i.types[n] & Imm16)
1961 size = 2;
1962 else
1963 size = 4;
1964 r_type = reloc (size, 0, i.disp_reloc[0]);
1965 p = frag_more (size);
1966 insn_size += size;
1967#ifdef BFD_ASSEMBLER
1968 if (r_type == BFD_RELOC_32
1969 && GOT_symbol
1970 && GOT_symbol == i.imms[n]->X_add_symbol
1971 && (i.imms[n]->X_op == O_symbol
1972 || (i.imms[n]->X_op == O_add
1973 && (i.imms[n]->X_op_symbol->sy_value.X_op
1974 == O_subtract))))
1975 {
1976 r_type = BFD_RELOC_386_GOTPC;
1977 i.imms[n]->X_add_number += 3;
1978 }
1979#endif
1980 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
1981 i.imms[n], pcrel, r_type);
1982 }
1983 }
1984 }
1985 } /* end immediate output */
1986 }
1987
1988#ifdef DEBUG386
1989 if (flag_debug)
1990 {
1991 pi (line, &i);
1992 }
1993#endif /* DEBUG386 */
1994 }
1995}
1996
1997/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
1998 on error. */
1999
2000static int
2001i386_operand (operand_string)
2002 char *operand_string;
2003{
2004 register char *op_string = operand_string;
2005
2006 /* Address of '\0' at end of operand_string. */
2007 char *end_of_operand_string = operand_string + strlen (operand_string);
2008
2009 /* Start and end of displacement string expression (if found). */
2010 char *displacement_string_start = NULL;
2011 char *displacement_string_end = NULL;
2012
2013 /* We check for an absolute prefix (differentiating,
2014 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
2015 if (*op_string == ABSOLUTE_PREFIX)
2016 {
2017 op_string++;
2018 i.types[this_operand] |= JumpAbsolute;
2019 }
2020
2021 /* Check if operand is a register. */
2022 if (*op_string == REGISTER_PREFIX)
2023 {
2024 register reg_entry *r;
2025 if (!(r = parse_register (op_string)))
2026 {
2027 as_bad ("bad register name ('%s')", op_string);
2028 return 0;
2029 }
2030 /* Check for segment override, rather than segment register by
2031 searching for ':' after %<x>s where <x> = s, c, d, e, f, g. */
2032 if ((r->reg_type & (SReg2 | SReg3)) && op_string[3] == ':')
2033 {
2034 switch (r->reg_num)
2035 {
2036 case 0:
2037 i.seg = (seg_entry *) & es;
2038 break;
2039 case 1:
2040 i.seg = (seg_entry *) & cs;
2041 break;
2042 case 2:
2043 i.seg = (seg_entry *) & ss;
2044 break;
2045 case 3:
2046 i.seg = (seg_entry *) & ds;
2047 break;
2048 case 4:
2049 i.seg = (seg_entry *) & fs;
2050 break;
2051 case 5:
2052 i.seg = (seg_entry *) & gs;
2053 break;
2054 }
2055 op_string += 4; /* skip % <x> s : */
2056 operand_string = op_string; /* Pretend given string starts here. */
2057 if (!is_digit_char (*op_string) && !is_identifier_char (*op_string)
2058 && *op_string != '(' && *op_string != ABSOLUTE_PREFIX)
2059 {
2060 as_bad ("bad memory operand after segment override");
2061 return 0;
2062 }
2063 /* Handle case of %es:*foo. */
2064 if (*op_string == ABSOLUTE_PREFIX)
2065 {
2066 op_string++;
2067 i.types[this_operand] |= JumpAbsolute;
2068 }
2069 goto do_memory_reference;
2070 }
2071 i.types[this_operand] |= r->reg_type;
2072 i.regs[this_operand] = r;
2073 i.reg_operands++;
2074 }
2075 else if (*op_string == IMMEDIATE_PREFIX)
2076 { /* ... or an immediate */
2077 char *save_input_line_pointer;
2078 segT exp_seg = 0;
2079 expressionS *exp;
2080
2081 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
2082 {
2083 as_bad ("only 1 or 2 immediate operands are allowed");
2084 return 0;
2085 }
2086
2087 exp = &im_expressions[i.imm_operands++];
2088 i.imms[this_operand] = exp;
2089 save_input_line_pointer = input_line_pointer;
2090 input_line_pointer = ++op_string; /* must advance op_string! */
2091 SKIP_WHITESPACE ();
2092 exp_seg = expression (exp);
| 1890 {
1891 p = frag_more (1);
1892 insn_size += 1;
1893 /* md_number_to_chars (p, i.rm, 1); */
1894 md_number_to_chars (p,
1895 (valueT) (i.rm.regmem << 0
1896 | i.rm.reg << 3
1897 | i.rm.mode << 6),
1898 1);
1899 /* If i.rm.regmem == ESP (4) && i.rm.mode != Mode 3 (Register mode)
1900 ==> need second modrm byte. */
1901 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING && i.rm.mode != 3)
1902 {
1903 p = frag_more (1);
1904 insn_size += 1;
1905 /* md_number_to_chars (p, i.bi, 1); */
1906 md_number_to_chars (p, (valueT) (i.bi.base << 0
1907 | i.bi.index << 3
1908 | i.bi.scale << 6),
1909 1);
1910 }
1911 }
1912
1913 if (i.disp_operands)
1914 {
1915 register unsigned int n;
1916
1917 for (n = 0; n < i.operands; n++)
1918 {
1919 if (i.disps[n])
1920 {
1921 if (i.disps[n]->X_op == O_constant)
1922 {
1923 if (i.types[n] & (Disp8 | Abs8))
1924 {
1925 p = frag_more (1);
1926 insn_size += 1;
1927 md_number_to_chars (p,
1928 (valueT) i.disps[n]->X_add_number,
1929 1);
1930 }
1931 else if (i.types[n] & (Disp16 | Abs16))
1932 {
1933 p = frag_more (2);
1934 insn_size += 2;
1935 md_number_to_chars (p,
1936 (valueT) i.disps[n]->X_add_number,
1937 2);
1938 }
1939 else
1940 { /* Disp32|Abs32 */
1941 p = frag_more (4);
1942 insn_size += 4;
1943 md_number_to_chars (p,
1944 (valueT) i.disps[n]->X_add_number,
1945 4);
1946 }
1947 }
1948 else
1949 { /* not absolute_section */
1950 /* need a 32-bit fixup (don't support 8bit non-absolute disps) */
1951 p = frag_more (4);
1952 insn_size += 4;
1953 fix_new_exp (frag_now, p - frag_now->fr_literal, 4,
1954 i.disps[n], 0,
1955 TC_RELOC(i.disp_reloc[n], BFD_RELOC_32));
1956 }
1957 }
1958 }
1959 } /* end displacement output */
1960
1961 /* output immediate */
1962 if (i.imm_operands)
1963 {
1964 register unsigned int n;
1965
1966 for (n = 0; n < i.operands; n++)
1967 {
1968 if (i.imms[n])
1969 {
1970 if (i.imms[n]->X_op == O_constant)
1971 {
1972 if (i.types[n] & (Imm8 | Imm8S))
1973 {
1974 p = frag_more (1);
1975 insn_size += 1;
1976 md_number_to_chars (p,
1977 (valueT) i.imms[n]->X_add_number,
1978 1);
1979 }
1980 else if (i.types[n] & Imm16)
1981 {
1982 p = frag_more (2);
1983 insn_size += 2;
1984 md_number_to_chars (p,
1985 (valueT) i.imms[n]->X_add_number,
1986 2);
1987 }
1988 else
1989 {
1990 p = frag_more (4);
1991 insn_size += 4;
1992 md_number_to_chars (p,
1993 (valueT) i.imms[n]->X_add_number,
1994 4);
1995 }
1996 }
1997 else
1998 { /* not absolute_section */
1999 /* Need a 32-bit fixup (don't support 8bit
2000 non-absolute ims). Try to support other
2001 sizes ... */
2002 int r_type;
2003 int size;
2004 int pcrel = 0;
2005
2006 if (i.types[n] & (Imm8 | Imm8S))
2007 size = 1;
2008 else if (i.types[n] & Imm16)
2009 size = 2;
2010 else
2011 size = 4;
2012 r_type = reloc (size, 0, i.disp_reloc[0]);
2013 p = frag_more (size);
2014 insn_size += size;
2015#ifdef BFD_ASSEMBLER
2016 if (r_type == BFD_RELOC_32
2017 && GOT_symbol
2018 && GOT_symbol == i.imms[n]->X_add_symbol
2019 && (i.imms[n]->X_op == O_symbol
2020 || (i.imms[n]->X_op == O_add
2021 && (i.imms[n]->X_op_symbol->sy_value.X_op
2022 == O_subtract))))
2023 {
2024 r_type = BFD_RELOC_386_GOTPC;
2025 i.imms[n]->X_add_number += 3;
2026 }
2027#endif
2028 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2029 i.imms[n], pcrel, r_type);
2030 }
2031 }
2032 }
2033 } /* end immediate output */
2034 }
2035
2036#ifdef DEBUG386
2037 if (flag_debug)
2038 {
2039 pi (line, &i);
2040 }
2041#endif /* DEBUG386 */
2042 }
2043}
2044
2045/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
2046 on error. */
2047
2048static int
2049i386_operand (operand_string)
2050 char *operand_string;
2051{
2052 register char *op_string = operand_string;
2053
2054 /* Address of '\0' at end of operand_string. */
2055 char *end_of_operand_string = operand_string + strlen (operand_string);
2056
2057 /* Start and end of displacement string expression (if found). */
2058 char *displacement_string_start = NULL;
2059 char *displacement_string_end = NULL;
2060
2061 /* We check for an absolute prefix (differentiating,
2062 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
2063 if (*op_string == ABSOLUTE_PREFIX)
2064 {
2065 op_string++;
2066 i.types[this_operand] |= JumpAbsolute;
2067 }
2068
2069 /* Check if operand is a register. */
2070 if (*op_string == REGISTER_PREFIX)
2071 {
2072 register reg_entry *r;
2073 if (!(r = parse_register (op_string)))
2074 {
2075 as_bad ("bad register name ('%s')", op_string);
2076 return 0;
2077 }
2078 /* Check for segment override, rather than segment register by
2079 searching for ':' after %<x>s where <x> = s, c, d, e, f, g. */
2080 if ((r->reg_type & (SReg2 | SReg3)) && op_string[3] == ':')
2081 {
2082 switch (r->reg_num)
2083 {
2084 case 0:
2085 i.seg = (seg_entry *) & es;
2086 break;
2087 case 1:
2088 i.seg = (seg_entry *) & cs;
2089 break;
2090 case 2:
2091 i.seg = (seg_entry *) & ss;
2092 break;
2093 case 3:
2094 i.seg = (seg_entry *) & ds;
2095 break;
2096 case 4:
2097 i.seg = (seg_entry *) & fs;
2098 break;
2099 case 5:
2100 i.seg = (seg_entry *) & gs;
2101 break;
2102 }
2103 op_string += 4; /* skip % <x> s : */
2104 operand_string = op_string; /* Pretend given string starts here. */
2105 if (!is_digit_char (*op_string) && !is_identifier_char (*op_string)
2106 && *op_string != '(' && *op_string != ABSOLUTE_PREFIX)
2107 {
2108 as_bad ("bad memory operand after segment override");
2109 return 0;
2110 }
2111 /* Handle case of %es:*foo. */
2112 if (*op_string == ABSOLUTE_PREFIX)
2113 {
2114 op_string++;
2115 i.types[this_operand] |= JumpAbsolute;
2116 }
2117 goto do_memory_reference;
2118 }
2119 i.types[this_operand] |= r->reg_type;
2120 i.regs[this_operand] = r;
2121 i.reg_operands++;
2122 }
2123 else if (*op_string == IMMEDIATE_PREFIX)
2124 { /* ... or an immediate */
2125 char *save_input_line_pointer;
2126 segT exp_seg = 0;
2127 expressionS *exp;
2128
2129 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
2130 {
2131 as_bad ("only 1 or 2 immediate operands are allowed");
2132 return 0;
2133 }
2134
2135 exp = &im_expressions[i.imm_operands++];
2136 i.imms[this_operand] = exp;
2137 save_input_line_pointer = input_line_pointer;
2138 input_line_pointer = ++op_string; /* must advance op_string! */
2139 SKIP_WHITESPACE ();
2140 exp_seg = expression (exp);
|
| 2141 if (*input_line_pointer != '\0')
2142 {
2143 /* This should be as_bad, but some versions of gcc, up to
2144 about 2.8 and egcs 1.01, generate a bogus @GOTOFF(%ebx)
2145 in certain cases. Oddly, the code in question turns out
2146 to work correctly anyhow, so we make this just a warning
2147 until those versions of gcc are obsolete. */
2148 as_warn ("warning: unrecognized characters `%s' in expression",
2149 input_line_pointer);
2150 }
|
2093 input_line_pointer = save_input_line_pointer;
2094
2095 if (exp->X_op == O_absent)
2096 {
2097 /* missing or bad expr becomes absolute 0 */
2098 as_bad ("missing or invalid immediate expression '%s' taken as 0",
2099 operand_string);
2100 exp->X_op = O_constant;
2101 exp->X_add_number = 0;
2102 exp->X_add_symbol = (symbolS *) 0;
2103 exp->X_op_symbol = (symbolS *) 0;
2104 i.types[this_operand] |= Imm;
2105 }
2106 else if (exp->X_op == O_constant)
2107 {
2108 i.types[this_operand] |=
2109 smallest_imm_type ((unsigned long) exp->X_add_number);
2110 }
2111#ifdef OBJ_AOUT
2112 else if (exp_seg != text_section
2113 && exp_seg != data_section
2114 && exp_seg != bss_section
2115 && exp_seg != undefined_section
2116#ifdef BFD_ASSEMBLER
2117 && ! bfd_is_com_section (exp_seg)
2118#endif
2119 )
2120 {
2121 seg_unimplemented:
2122 as_bad ("Unimplemented segment type %d in parse_operand", exp_seg);
2123 return 0;
2124 }
2125#endif
2126 else
2127 {
2128 /* this is an address ==> 32bit */
2129 i.types[this_operand] |= Imm32;
2130 }
2131 /* shorten this type of this operand if the instruction wants
2132 * fewer bits than are present in the immediate. The bit field
2133 * code can put out 'andb $0xffffff, %al', for example. pace
2134 * also 'movw $foo,(%eax)'
2135 */
2136 switch (i.suffix)
2137 {
2138 case WORD_OPCODE_SUFFIX:
2139 i.types[this_operand] |= Imm16;
2140 break;
2141 case BYTE_OPCODE_SUFFIX:
2142 i.types[this_operand] |= Imm16 | Imm8 | Imm8S;
2143 break;
2144 }
2145 }
2146 else if (is_digit_char (*op_string) || is_identifier_char (*op_string)
2147 || *op_string == '(')
2148 {
2149 /* This is a memory reference of some sort. */
2150 register char *base_string;
2151 unsigned int found_base_index_form;
2152
2153 do_memory_reference:
2154 if (i.mem_operands == MAX_MEMORY_OPERANDS)
2155 {
2156 as_bad ("more than 1 memory reference in instruction");
2157 return 0;
2158 }
2159 i.mem_operands++;
2160
2161 /* Determine type of memory operand from opcode_suffix;
| 2151 input_line_pointer = save_input_line_pointer;
2152
2153 if (exp->X_op == O_absent)
2154 {
2155 /* missing or bad expr becomes absolute 0 */
2156 as_bad ("missing or invalid immediate expression '%s' taken as 0",
2157 operand_string);
2158 exp->X_op = O_constant;
2159 exp->X_add_number = 0;
2160 exp->X_add_symbol = (symbolS *) 0;
2161 exp->X_op_symbol = (symbolS *) 0;
2162 i.types[this_operand] |= Imm;
2163 }
2164 else if (exp->X_op == O_constant)
2165 {
2166 i.types[this_operand] |=
2167 smallest_imm_type ((unsigned long) exp->X_add_number);
2168 }
2169#ifdef OBJ_AOUT
2170 else if (exp_seg != text_section
2171 && exp_seg != data_section
2172 && exp_seg != bss_section
2173 && exp_seg != undefined_section
2174#ifdef BFD_ASSEMBLER
2175 && ! bfd_is_com_section (exp_seg)
2176#endif
2177 )
2178 {
2179 seg_unimplemented:
2180 as_bad ("Unimplemented segment type %d in parse_operand", exp_seg);
2181 return 0;
2182 }
2183#endif
2184 else
2185 {
2186 /* this is an address ==> 32bit */
2187 i.types[this_operand] |= Imm32;
2188 }
2189 /* shorten this type of this operand if the instruction wants
2190 * fewer bits than are present in the immediate. The bit field
2191 * code can put out 'andb $0xffffff, %al', for example. pace
2192 * also 'movw $foo,(%eax)'
2193 */
2194 switch (i.suffix)
2195 {
2196 case WORD_OPCODE_SUFFIX:
2197 i.types[this_operand] |= Imm16;
2198 break;
2199 case BYTE_OPCODE_SUFFIX:
2200 i.types[this_operand] |= Imm16 | Imm8 | Imm8S;
2201 break;
2202 }
2203 }
2204 else if (is_digit_char (*op_string) || is_identifier_char (*op_string)
2205 || *op_string == '(')
2206 {
2207 /* This is a memory reference of some sort. */
2208 register char *base_string;
2209 unsigned int found_base_index_form;
2210
2211 do_memory_reference:
2212 if (i.mem_operands == MAX_MEMORY_OPERANDS)
2213 {
2214 as_bad ("more than 1 memory reference in instruction");
2215 return 0;
2216 }
2217 i.mem_operands++;
2218
2219 /* Determine type of memory operand from opcode_suffix;
|
2162 no opcode suffix implies general memory references. */
| 2220 no opcode suffix implies general memory references. */
|
2163 switch (i.suffix)
2164 {
2165 case BYTE_OPCODE_SUFFIX:
2166 i.types[this_operand] |= Mem8;
2167 break;
2168 case WORD_OPCODE_SUFFIX:
2169 i.types[this_operand] |= Mem16;
2170 break;
2171 case DWORD_OPCODE_SUFFIX:
2172 default:
2173 i.types[this_operand] |= Mem32;
2174 }
2175
2176 /* Check for base index form. We detect the base index form by
2177 looking for an ')' at the end of the operand, searching
2178 for the '(' matching it, and finding a REGISTER_PREFIX or ','
2179 after it. */
2180 base_string = end_of_operand_string - 1;
2181 found_base_index_form = 0;
2182 if (*base_string == ')')
2183 {
2184 unsigned int parens_balanced = 1;
2185 /* We've already checked that the number of left & right ()'s are
2186 equal, so this loop will not be infinite. */
2187 do
2188 {
2189 base_string--;
2190 if (*base_string == ')')
2191 parens_balanced++;
2192 if (*base_string == '(')
2193 parens_balanced--;
2194 }
2195 while (parens_balanced);
2196 base_string++; /* Skip past '('. */
2197 if (*base_string == REGISTER_PREFIX || *base_string == ',')
2198 found_base_index_form = 1;
2199 }
2200
2201 /* If we can't parse a base index register expression, we've found
2202 a pure displacement expression. We set up displacement_string_start
2203 and displacement_string_end for the code below. */
2204 if (!found_base_index_form)
2205 {
2206 displacement_string_start = op_string;
2207 displacement_string_end = end_of_operand_string;
2208 }
2209 else
2210 {
2211 char *base_reg_name, *index_reg_name, *num_string;
2212 int num;
2213
2214 i.types[this_operand] |= BaseIndex;
2215
2216 /* If there is a displacement set-up for it to be parsed later. */
2217 if (base_string != op_string + 1)
2218 {
2219 displacement_string_start = op_string;
2220 displacement_string_end = base_string - 1;
2221 }
2222
2223 /* Find base register (if any). */
2224 if (*base_string != ',')
2225 {
2226 base_reg_name = base_string++;
2227 /* skip past register name & parse it */
2228 while (isalpha (*base_string))
2229 base_string++;
2230 if (base_string == base_reg_name + 1)
2231 {
2232 as_bad ("can't find base register name after '(%c'",
2233 REGISTER_PREFIX);
2234 return 0;
2235 }
2236 END_STRING_AND_SAVE (base_string);
2237 if (!(i.base_reg = parse_register (base_reg_name)))
2238 {
2239 as_bad ("bad base register name ('%s')", base_reg_name);
2240 return 0;
2241 }
2242 RESTORE_END_STRING (base_string);
2243 }
2244
2245 /* Now check seperator; must be ',' ==> index reg
2246 OR num ==> no index reg. just scale factor
2247 OR ')' ==> end. (scale factor = 1) */
2248 if (*base_string != ',' && *base_string != ')')
2249 {
2250 as_bad ("expecting ',' or ')' after base register in `%s'",
2251 operand_string);
2252 return 0;
2253 }
2254
2255 /* There may index reg here; and there may be a scale factor. */
2256 if (*base_string == ',' && *(base_string + 1) == REGISTER_PREFIX)
2257 {
2258 index_reg_name = ++base_string;
2259 while (isalpha (*++base_string));
2260 END_STRING_AND_SAVE (base_string);
2261 if (!(i.index_reg = parse_register (index_reg_name)))
2262 {
2263 as_bad ("bad index register name ('%s')", index_reg_name);
2264 return 0;
2265 }
2266 RESTORE_END_STRING (base_string);
2267 }
2268
2269 /* Check for scale factor. */
2270 if (*base_string == ',' && isdigit (*(base_string + 1)))
2271 {
2272 num_string = ++base_string;
2273 while (is_digit_char (*base_string))
2274 base_string++;
2275 if (base_string == num_string)
2276 {
2277 as_bad ("can't find a scale factor after ','");
2278 return 0;
2279 }
2280 END_STRING_AND_SAVE (base_string);
2281 /* We've got a scale factor. */
2282 if (!sscanf (num_string, "%d", &num))
2283 {
2284 as_bad ("can't parse scale factor from '%s'", num_string);
2285 return 0;
2286 }
2287 RESTORE_END_STRING (base_string);
2288 switch (num)
2289 { /* must be 1 digit scale */
2290 case 1:
2291 i.log2_scale_factor = 0;
2292 break;
2293 case 2:
2294 i.log2_scale_factor = 1;
2295 break;
2296 case 4:
2297 i.log2_scale_factor = 2;
2298 break;
2299 case 8:
2300 i.log2_scale_factor = 3;
2301 break;
2302 default:
2303 as_bad ("expecting scale factor of 1, 2, 4, 8; got %d", num);
2304 return 0;
2305 }
2306 }
2307 else
2308 {
2309 if (!i.index_reg && *base_string == ',')
2310 {
2311 as_bad ("expecting index register or scale factor after ','; got '%c'",
2312 *(base_string + 1));
2313 return 0;
2314 }
2315 }
2316 }
2317
2318 /* If there's an expression begining the operand, parse it,
2319 assuming displacement_string_start and displacement_string_end
2320 are meaningful. */
2321 if (displacement_string_start)
2322 {
2323 register expressionS *exp;
2324 segT exp_seg = 0;
2325 char *save_input_line_pointer;
2326 exp = &disp_expressions[i.disp_operands];
2327 i.disps[this_operand] = exp;
2328 i.disp_reloc[this_operand] = NO_RELOC;
2329 i.disp_operands++;
2330 save_input_line_pointer = input_line_pointer;
2331 input_line_pointer = displacement_string_start;
2332 END_STRING_AND_SAVE (displacement_string_end);
| 2221 switch (i.suffix)
2222 {
2223 case BYTE_OPCODE_SUFFIX:
2224 i.types[this_operand] |= Mem8;
2225 break;
2226 case WORD_OPCODE_SUFFIX:
2227 i.types[this_operand] |= Mem16;
2228 break;
2229 case DWORD_OPCODE_SUFFIX:
2230 default:
2231 i.types[this_operand] |= Mem32;
2232 }
2233
2234 /* Check for base index form. We detect the base index form by
2235 looking for an ')' at the end of the operand, searching
2236 for the '(' matching it, and finding a REGISTER_PREFIX or ','
2237 after it. */
2238 base_string = end_of_operand_string - 1;
2239 found_base_index_form = 0;
2240 if (*base_string == ')')
2241 {
2242 unsigned int parens_balanced = 1;
2243 /* We've already checked that the number of left & right ()'s are
2244 equal, so this loop will not be infinite. */
2245 do
2246 {
2247 base_string--;
2248 if (*base_string == ')')
2249 parens_balanced++;
2250 if (*base_string == '(')
2251 parens_balanced--;
2252 }
2253 while (parens_balanced);
2254 base_string++; /* Skip past '('. */
2255 if (*base_string == REGISTER_PREFIX || *base_string == ',')
2256 found_base_index_form = 1;
2257 }
2258
2259 /* If we can't parse a base index register expression, we've found
2260 a pure displacement expression. We set up displacement_string_start
2261 and displacement_string_end for the code below. */
2262 if (!found_base_index_form)
2263 {
2264 displacement_string_start = op_string;
2265 displacement_string_end = end_of_operand_string;
2266 }
2267 else
2268 {
2269 char *base_reg_name, *index_reg_name, *num_string;
2270 int num;
2271
2272 i.types[this_operand] |= BaseIndex;
2273
2274 /* If there is a displacement set-up for it to be parsed later. */
2275 if (base_string != op_string + 1)
2276 {
2277 displacement_string_start = op_string;
2278 displacement_string_end = base_string - 1;
2279 }
2280
2281 /* Find base register (if any). */
2282 if (*base_string != ',')
2283 {
2284 base_reg_name = base_string++;
2285 /* skip past register name & parse it */
2286 while (isalpha (*base_string))
2287 base_string++;
2288 if (base_string == base_reg_name + 1)
2289 {
2290 as_bad ("can't find base register name after '(%c'",
2291 REGISTER_PREFIX);
2292 return 0;
2293 }
2294 END_STRING_AND_SAVE (base_string);
2295 if (!(i.base_reg = parse_register (base_reg_name)))
2296 {
2297 as_bad ("bad base register name ('%s')", base_reg_name);
2298 return 0;
2299 }
2300 RESTORE_END_STRING (base_string);
2301 }
2302
2303 /* Now check seperator; must be ',' ==> index reg
2304 OR num ==> no index reg. just scale factor
2305 OR ')' ==> end. (scale factor = 1) */
2306 if (*base_string != ',' && *base_string != ')')
2307 {
2308 as_bad ("expecting ',' or ')' after base register in `%s'",
2309 operand_string);
2310 return 0;
2311 }
2312
2313 /* There may index reg here; and there may be a scale factor. */
2314 if (*base_string == ',' && *(base_string + 1) == REGISTER_PREFIX)
2315 {
2316 index_reg_name = ++base_string;
2317 while (isalpha (*++base_string));
2318 END_STRING_AND_SAVE (base_string);
2319 if (!(i.index_reg = parse_register (index_reg_name)))
2320 {
2321 as_bad ("bad index register name ('%s')", index_reg_name);
2322 return 0;
2323 }
2324 RESTORE_END_STRING (base_string);
2325 }
2326
2327 /* Check for scale factor. */
2328 if (*base_string == ',' && isdigit (*(base_string + 1)))
2329 {
2330 num_string = ++base_string;
2331 while (is_digit_char (*base_string))
2332 base_string++;
2333 if (base_string == num_string)
2334 {
2335 as_bad ("can't find a scale factor after ','");
2336 return 0;
2337 }
2338 END_STRING_AND_SAVE (base_string);
2339 /* We've got a scale factor. */
2340 if (!sscanf (num_string, "%d", &num))
2341 {
2342 as_bad ("can't parse scale factor from '%s'", num_string);
2343 return 0;
2344 }
2345 RESTORE_END_STRING (base_string);
2346 switch (num)
2347 { /* must be 1 digit scale */
2348 case 1:
2349 i.log2_scale_factor = 0;
2350 break;
2351 case 2:
2352 i.log2_scale_factor = 1;
2353 break;
2354 case 4:
2355 i.log2_scale_factor = 2;
2356 break;
2357 case 8:
2358 i.log2_scale_factor = 3;
2359 break;
2360 default:
2361 as_bad ("expecting scale factor of 1, 2, 4, 8; got %d", num);
2362 return 0;
2363 }
2364 }
2365 else
2366 {
2367 if (!i.index_reg && *base_string == ',')
2368 {
2369 as_bad ("expecting index register or scale factor after ','; got '%c'",
2370 *(base_string + 1));
2371 return 0;
2372 }
2373 }
2374 }
2375
2376 /* If there's an expression begining the operand, parse it,
2377 assuming displacement_string_start and displacement_string_end
2378 are meaningful. */
2379 if (displacement_string_start)
2380 {
2381 register expressionS *exp;
2382 segT exp_seg = 0;
2383 char *save_input_line_pointer;
2384 exp = &disp_expressions[i.disp_operands];
2385 i.disps[this_operand] = exp;
2386 i.disp_reloc[this_operand] = NO_RELOC;
2387 i.disp_operands++;
2388 save_input_line_pointer = input_line_pointer;
2389 input_line_pointer = displacement_string_start;
2390 END_STRING_AND_SAVE (displacement_string_end);
|
| 2391
|
2333#ifndef LEX_AT
2334 {
2335 /*
2336 * We can have operands of the form
2337 * <symbol>@GOTOFF+<nnn>
2338 * Take the easy way out here and copy everything
2339 * into a temporary buffer...
2340 */
2341 register char *cp;
| 2392#ifndef LEX_AT
2393 {
2394 /*
2395 * We can have operands of the form
2396 * <symbol>@GOTOFF+<nnn>
2397 * Take the easy way out here and copy everything
2398 * into a temporary buffer...
2399 */
2400 register char *cp;
|
2342 if ((cp = strchr (input_line_pointer,'@')) != NULL) {
2343 char tmpbuf[BUFSIZ];
2344
2345 if(!GOT_symbol)
2346 GOT_symbol = symbol_find_or_make(GLOBAL_OFFSET_TABLE_NAME);
| |
2347
| 2401
|
2348 if (strncmp(cp+1, "PLT", 3) == 0) {
2349 i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32;
2350 *cp = '\0';
2351 strcpy(tmpbuf, input_line_pointer);
2352 strcat(tmpbuf, cp+1+3);
2353 *cp = '@';
2354 } else if (strncmp(cp+1, "GOTOFF", 6) == 0) {
2355 i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF;
2356 *cp = '\0';
2357 strcpy(tmpbuf, input_line_pointer);
2358 strcat(tmpbuf, cp+1+6);
2359 *cp = '@';
2360 } else if (strncmp(cp+1, "GOT", 3) == 0) {
2361 i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32;
2362 *cp = '\0';
2363 strcpy(tmpbuf, input_line_pointer);
2364 strcat(tmpbuf, cp+1+3);
2365 *cp = '@';
2366 } else
2367 as_bad("Bad reloc specifier '%s' in expression", cp+1);
2368 input_line_pointer = tmpbuf;
2369 }
| 2402 cp = strchr (input_line_pointer, '@');
2403 if (cp != NULL)
2404 {
2405 char *tmpbuf;
2406
2407 if (GOT_symbol == NULL)
2408 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
2409
2410 tmpbuf = (char *) alloca ((cp - input_line_pointer) + 20);
2411
2412 if (strncmp (cp + 1, "PLT", 3) == 0)
2413 {
2414 i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32;
2415 *cp = '\0';
2416 strcpy (tmpbuf, input_line_pointer);
2417 strcat (tmpbuf, cp + 1 + 3);
2418 *cp = '@';
2419 }
2420 else if (strncmp (cp + 1, "GOTOFF", 6) == 0)
2421 {
2422 i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF;
2423 *cp = '\0';
2424 strcpy (tmpbuf, input_line_pointer);
2425 strcat (tmpbuf, cp + 1 + 6);
2426 *cp = '@';
2427 }
2428 else if (strncmp (cp + 1, "GOT", 3) == 0)
2429 {
2430 i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32;
2431 *cp = '\0';
2432 strcpy (tmpbuf, input_line_pointer);
2433 strcat (tmpbuf, cp + 1 + 3);
2434 *cp = '@';
2435 }
2436 else
2437 as_bad ("Bad reloc specifier '%s' in expression", cp + 1);
2438
2439 input_line_pointer = tmpbuf;
2440 }
|
2370 }
2371#endif
| 2441 }
2442#endif
|
| 2443
|
2372 exp_seg = expression (exp);
2373
2374#ifdef BFD_ASSEMBLER
2375 /* We do this to make sure that the section symbol is in
2376 the symbol table. We will ultimately change the relocation
2377 to be relative to the beginning of the section */
2378 if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF)
2379 {
2380 if (S_IS_LOCAL(exp->X_add_symbol)
2381 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
2382 section_symbol(exp->X_add_symbol->bsym->section);
2383 assert (exp->X_op == O_symbol);
2384 exp->X_op = O_subtract;
2385 exp->X_op_symbol = GOT_symbol;
2386 i.disp_reloc[this_operand] = BFD_RELOC_32;
2387 }
2388#endif
2389
2390 if (*input_line_pointer)
2391 as_bad ("Ignoring junk '%s' after expression", input_line_pointer);
2392 RESTORE_END_STRING (displacement_string_end);
2393 input_line_pointer = save_input_line_pointer;
2394 if (exp->X_op == O_absent)
2395 {
2396 /* missing expr becomes absolute 0 */
2397 as_bad ("missing or invalid displacement '%s' taken as 0",
2398 operand_string);
2399 i.types[this_operand] |= (Disp | Abs);
2400 exp->X_op = O_constant;
2401 exp->X_add_number = 0;
2402 exp->X_add_symbol = (symbolS *) 0;
2403 exp->X_op_symbol = (symbolS *) 0;
2404 }
2405 else if (exp->X_op == O_constant)
2406 {
2407 i.types[this_operand] |= SMALLEST_DISP_TYPE (exp->X_add_number);
2408 }
2409 else if (exp_seg == text_section
2410 || exp_seg == data_section
2411 || exp_seg == bss_section
2412 || exp_seg == undefined_section)
2413 {
2414 i.types[this_operand] |= Disp32;
2415 }
2416 else
2417 {
2418#ifndef OBJ_AOUT
2419 i.types[this_operand] |= Disp32;
2420#else
2421 goto seg_unimplemented;
2422#endif
2423 }
2424 }
2425
2426 /* Make sure the memory operand we've been dealt is valid. */
2427 if (i.base_reg && i.index_reg &&
2428 !(i.base_reg->reg_type & i.index_reg->reg_type & Reg))
2429 {
2430 as_bad ("register size mismatch in (base,index,scale) expression");
2431 return 0;
2432 }
2433 /*
2434 * special case for (%dx) while doing input/output op
2435 */
2436 if ((i.base_reg &&
2437 (i.base_reg->reg_type == (Reg16 | InOutPortReg)) &&
2438 (i.index_reg == 0)))
2439 {
2440 i.types[this_operand] |= InOutPortReg;
2441 return 1;
2442 }
2443 if ((i.base_reg && (i.base_reg->reg_type & Reg32) == 0) ||
2444 (i.index_reg && (i.index_reg->reg_type & Reg32) == 0))
2445 {
2446 as_bad ("base/index register must be 32 bit register");
2447 return 0;
2448 }
2449 if (i.index_reg && i.index_reg == esp)
2450 {
2451 as_bad ("%s may not be used as an index register", esp->reg_name);
2452 return 0;
2453 }
2454 }
2455 else
2456 { /* it's not a memory operand; argh! */
2457 as_bad ("invalid char %s begining %s operand '%s'",
2458 output_invalid (*op_string), ordinal_names[this_operand],
2459 op_string);
2460 return 0;
2461 }
2462 return 1; /* normal return */
2463}
2464
2465/*
2466 * md_estimate_size_before_relax()
2467 *
2468 * Called just before relax().
2469 * Any symbol that is now undefined will not become defined.
2470 * Return the correct fr_subtype in the frag.
2471 * Return the initial "guess for fr_var" to caller.
2472 * The guess for fr_var is ACTUALLY the growth beyond fr_fix.
2473 * Whatever we do to grow fr_fix or fr_var contributes to our returned value.
2474 * Although it may not be explicit in the frag, pretend fr_var starts with a
2475 * 0 value.
2476 */
2477int
2478md_estimate_size_before_relax (fragP, segment)
2479 register fragS *fragP;
2480 register segT segment;
2481{
2482 register unsigned char *opcode;
2483 register int old_fr_fix;
2484
2485 old_fr_fix = fragP->fr_fix;
2486 opcode = (unsigned char *) fragP->fr_opcode;
2487 /* We've already got fragP->fr_subtype right; all we have to do is check
2488 for un-relaxable symbols. */
2489 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
2490 {
2491 /* symbol is undefined in this segment */
2492 switch (opcode[0])
2493 {
2494 case JUMP_PC_RELATIVE: /* make jmp (0xeb) a dword displacement jump */
2495 opcode[0] = 0xe9; /* dword disp jmp */
2496 fragP->fr_fix += 4;
2497 fix_new (fragP, old_fr_fix, 4,
2498 fragP->fr_symbol,
2499 fragP->fr_offset, 1,
2500 (GOT_symbol && /* Not quite right - we should switch on
2501 presence of @PLT, but I cannot see how
2502 to get to that from here. We should have
2503 done this in md_assemble to really
2504 get it right all of the time, but I
2505 think it does not matter that much, as
2506 this will be right most of the time. ERY*/
2507 S_GET_SEGMENT(fragP->fr_symbol) == undefined_section)?
2508 BFD_RELOC_386_PLT32 : BFD_RELOC_32_PCREL);
2509 break;
2510
2511 default:
2512 /* This changes the byte-displacement jump 0x7N -->
2513 the dword-displacement jump 0x0f8N */
2514 opcode[1] = opcode[0] + 0x10;
2515 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; /* two-byte escape */
2516 fragP->fr_fix += 1 + 4; /* we've added an opcode byte */
2517 fix_new (fragP, old_fr_fix + 1, 4,
2518 fragP->fr_symbol,
2519 fragP->fr_offset, 1,
2520 (GOT_symbol && /* Not quite right - we should switch on
2521 presence of @PLT, but I cannot see how
2522 to get to that from here. ERY */
2523 S_GET_SEGMENT(fragP->fr_symbol) == undefined_section)?
2524 BFD_RELOC_386_PLT32 : BFD_RELOC_32_PCREL);
2525 break;
2526 }
2527 frag_wane (fragP);
2528 }
2529 return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
2530} /* md_estimate_size_before_relax() */
2531
2532/*
2533 * md_convert_frag();
2534 *
2535 * Called after relax() is finished.
2536 * In: Address of frag.
2537 * fr_type == rs_machine_dependent.
2538 * fr_subtype is what the address relaxed to.
2539 *
2540 * Out: Any fixSs and constants are set up.
2541 * Caller will turn frag into a ".space 0".
2542 */
2543#ifndef BFD_ASSEMBLER
2544void
2545md_convert_frag (headers, sec, fragP)
2546 object_headers *headers;
2547 segT sec;
2548 register fragS *fragP;
2549#else
2550void
2551md_convert_frag (abfd, sec, fragP)
2552 bfd *abfd;
2553 segT sec;
2554 register fragS *fragP;
2555#endif
2556{
2557 register unsigned char *opcode;
2558 unsigned char *where_to_put_displacement = NULL;
2559 unsigned int target_address;
2560 unsigned int opcode_address;
2561 unsigned int extension = 0;
2562 int displacement_from_opcode_start;
2563
2564 opcode = (unsigned char *) fragP->fr_opcode;
2565
2566 /* Address we want to reach in file space. */
2567 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
2568#ifdef BFD_ASSEMBLER /* not needed otherwise? */
2569 target_address += fragP->fr_symbol->sy_frag->fr_address;
2570#endif
2571
2572 /* Address opcode resides at in file space. */
2573 opcode_address = fragP->fr_address + fragP->fr_fix;
2574
2575 /* Displacement from opcode start to fill into instruction. */
2576 displacement_from_opcode_start = target_address - opcode_address;
2577
2578 switch (fragP->fr_subtype)
2579 {
2580 case ENCODE_RELAX_STATE (COND_JUMP, BYTE):
2581 case ENCODE_RELAX_STATE (UNCOND_JUMP, BYTE):
2582 /* don't have to change opcode */
2583 extension = 1; /* 1 opcode + 1 displacement */
2584 where_to_put_displacement = &opcode[1];
2585 break;
2586
2587 case ENCODE_RELAX_STATE (COND_JUMP, WORD):
2588 opcode[1] = TWO_BYTE_OPCODE_ESCAPE;
2589 opcode[2] = opcode[0] + 0x10;
2590 opcode[0] = WORD_PREFIX_OPCODE;
2591 extension = 4; /* 3 opcode + 2 displacement */
2592 where_to_put_displacement = &opcode[3];
2593 break;
2594
2595 case ENCODE_RELAX_STATE (UNCOND_JUMP, WORD):
2596 opcode[1] = 0xe9;
2597 opcode[0] = WORD_PREFIX_OPCODE;
2598 extension = 3; /* 2 opcode + 2 displacement */
2599 where_to_put_displacement = &opcode[2];
2600 break;
2601
2602 case ENCODE_RELAX_STATE (COND_JUMP, DWORD):
2603 opcode[1] = opcode[0] + 0x10;
2604 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
2605 extension = 5; /* 2 opcode + 4 displacement */
2606 where_to_put_displacement = &opcode[2];
2607 break;
2608
2609 case ENCODE_RELAX_STATE (UNCOND_JUMP, DWORD):
2610 opcode[0] = 0xe9;
2611 extension = 4; /* 1 opcode + 4 displacement */
2612 where_to_put_displacement = &opcode[1];
2613 break;
2614
2615 default:
2616 BAD_CASE (fragP->fr_subtype);
2617 break;
2618 }
2619 /* now put displacement after opcode */
2620 md_number_to_chars ((char *) where_to_put_displacement,
2621 (valueT) (displacement_from_opcode_start - extension),
2622 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
2623 fragP->fr_fix += extension;
2624}
2625
2626
2627int md_short_jump_size = 2; /* size of byte displacement jmp */
2628int md_long_jump_size = 5; /* size of dword displacement jmp */
2629const int md_reloc_size = 8; /* Size of relocation record */
2630
2631void
2632md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
2633 char *ptr;
2634 addressT from_addr, to_addr;
2635 fragS *frag;
2636 symbolS *to_symbol;
2637{
2638 long offset;
2639
2640 offset = to_addr - (from_addr + 2);
2641 md_number_to_chars (ptr, (valueT) 0xeb, 1); /* opcode for byte-disp jump */
2642 md_number_to_chars (ptr + 1, (valueT) offset, 1);
2643}
2644
2645void
2646md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
2647 char *ptr;
2648 addressT from_addr, to_addr;
2649 fragS *frag;
2650 symbolS *to_symbol;
2651{
2652 long offset;
2653
2654 if (flag_do_long_jump)
2655 {
2656 offset = to_addr - S_GET_VALUE (to_symbol);
2657 md_number_to_chars (ptr, (valueT) 0xe9, 1);/* opcode for long jmp */
2658 md_number_to_chars (ptr + 1, (valueT) offset, 4);
2659 fix_new (frag, (ptr + 1) - frag->fr_literal, 4,
2660 to_symbol, (offsetT) 0, 0, BFD_RELOC_32);
2661 }
2662 else
2663 {
2664 offset = to_addr - (from_addr + 5);
2665 md_number_to_chars (ptr, (valueT) 0xe9, 1);
2666 md_number_to_chars (ptr + 1, (valueT) offset, 4);
2667 }
2668}
2669
2670/* Apply a fixup (fixS) to segment data, once it has been determined
2671 by our caller that we have all the info we need to fix it up.
2672
2673 On the 386, immediates, displacements, and data pointers are all in
2674 the same (little-endian) format, so we don't need to care about which
2675 we are handling. */
2676
2677int
2678md_apply_fix3 (fixP, valp, seg)
2679 fixS *fixP; /* The fix we're to put in. */
2680 valueT *valp; /* Pointer to the value of the bits. */
2681 segT seg; /* Segment fix is from. */
2682{
2683 register char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
2684 valueT value = *valp;
2685
| 2444 exp_seg = expression (exp);
2445
2446#ifdef BFD_ASSEMBLER
2447 /* We do this to make sure that the section symbol is in
2448 the symbol table. We will ultimately change the relocation
2449 to be relative to the beginning of the section */
2450 if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF)
2451 {
2452 if (S_IS_LOCAL(exp->X_add_symbol)
2453 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
2454 section_symbol(exp->X_add_symbol->bsym->section);
2455 assert (exp->X_op == O_symbol);
2456 exp->X_op = O_subtract;
2457 exp->X_op_symbol = GOT_symbol;
2458 i.disp_reloc[this_operand] = BFD_RELOC_32;
2459 }
2460#endif
2461
2462 if (*input_line_pointer)
2463 as_bad ("Ignoring junk '%s' after expression", input_line_pointer);
2464 RESTORE_END_STRING (displacement_string_end);
2465 input_line_pointer = save_input_line_pointer;
2466 if (exp->X_op == O_absent)
2467 {
2468 /* missing expr becomes absolute 0 */
2469 as_bad ("missing or invalid displacement '%s' taken as 0",
2470 operand_string);
2471 i.types[this_operand] |= (Disp | Abs);
2472 exp->X_op = O_constant;
2473 exp->X_add_number = 0;
2474 exp->X_add_symbol = (symbolS *) 0;
2475 exp->X_op_symbol = (symbolS *) 0;
2476 }
2477 else if (exp->X_op == O_constant)
2478 {
2479 i.types[this_operand] |= SMALLEST_DISP_TYPE (exp->X_add_number);
2480 }
2481 else if (exp_seg == text_section
2482 || exp_seg == data_section
2483 || exp_seg == bss_section
2484 || exp_seg == undefined_section)
2485 {
2486 i.types[this_operand] |= Disp32;
2487 }
2488 else
2489 {
2490#ifndef OBJ_AOUT
2491 i.types[this_operand] |= Disp32;
2492#else
2493 goto seg_unimplemented;
2494#endif
2495 }
2496 }
2497
2498 /* Make sure the memory operand we've been dealt is valid. */
2499 if (i.base_reg && i.index_reg &&
2500 !(i.base_reg->reg_type & i.index_reg->reg_type & Reg))
2501 {
2502 as_bad ("register size mismatch in (base,index,scale) expression");
2503 return 0;
2504 }
2505 /*
2506 * special case for (%dx) while doing input/output op
2507 */
2508 if ((i.base_reg &&
2509 (i.base_reg->reg_type == (Reg16 | InOutPortReg)) &&
2510 (i.index_reg == 0)))
2511 {
2512 i.types[this_operand] |= InOutPortReg;
2513 return 1;
2514 }
2515 if ((i.base_reg && (i.base_reg->reg_type & Reg32) == 0) ||
2516 (i.index_reg && (i.index_reg->reg_type & Reg32) == 0))
2517 {
2518 as_bad ("base/index register must be 32 bit register");
2519 return 0;
2520 }
2521 if (i.index_reg && i.index_reg == esp)
2522 {
2523 as_bad ("%s may not be used as an index register", esp->reg_name);
2524 return 0;
2525 }
2526 }
2527 else
2528 { /* it's not a memory operand; argh! */
2529 as_bad ("invalid char %s begining %s operand '%s'",
2530 output_invalid (*op_string), ordinal_names[this_operand],
2531 op_string);
2532 return 0;
2533 }
2534 return 1; /* normal return */
2535}
2536
2537/*
2538 * md_estimate_size_before_relax()
2539 *
2540 * Called just before relax().
2541 * Any symbol that is now undefined will not become defined.
2542 * Return the correct fr_subtype in the frag.
2543 * Return the initial "guess for fr_var" to caller.
2544 * The guess for fr_var is ACTUALLY the growth beyond fr_fix.
2545 * Whatever we do to grow fr_fix or fr_var contributes to our returned value.
2546 * Although it may not be explicit in the frag, pretend fr_var starts with a
2547 * 0 value.
2548 */
2549int
2550md_estimate_size_before_relax (fragP, segment)
2551 register fragS *fragP;
2552 register segT segment;
2553{
2554 register unsigned char *opcode;
2555 register int old_fr_fix;
2556
2557 old_fr_fix = fragP->fr_fix;
2558 opcode = (unsigned char *) fragP->fr_opcode;
2559 /* We've already got fragP->fr_subtype right; all we have to do is check
2560 for un-relaxable symbols. */
2561 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
2562 {
2563 /* symbol is undefined in this segment */
2564 switch (opcode[0])
2565 {
2566 case JUMP_PC_RELATIVE: /* make jmp (0xeb) a dword displacement jump */
2567 opcode[0] = 0xe9; /* dword disp jmp */
2568 fragP->fr_fix += 4;
2569 fix_new (fragP, old_fr_fix, 4,
2570 fragP->fr_symbol,
2571 fragP->fr_offset, 1,
2572 (GOT_symbol && /* Not quite right - we should switch on
2573 presence of @PLT, but I cannot see how
2574 to get to that from here. We should have
2575 done this in md_assemble to really
2576 get it right all of the time, but I
2577 think it does not matter that much, as
2578 this will be right most of the time. ERY*/
2579 S_GET_SEGMENT(fragP->fr_symbol) == undefined_section)?
2580 BFD_RELOC_386_PLT32 : BFD_RELOC_32_PCREL);
2581 break;
2582
2583 default:
2584 /* This changes the byte-displacement jump 0x7N -->
2585 the dword-displacement jump 0x0f8N */
2586 opcode[1] = opcode[0] + 0x10;
2587 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; /* two-byte escape */
2588 fragP->fr_fix += 1 + 4; /* we've added an opcode byte */
2589 fix_new (fragP, old_fr_fix + 1, 4,
2590 fragP->fr_symbol,
2591 fragP->fr_offset, 1,
2592 (GOT_symbol && /* Not quite right - we should switch on
2593 presence of @PLT, but I cannot see how
2594 to get to that from here. ERY */
2595 S_GET_SEGMENT(fragP->fr_symbol) == undefined_section)?
2596 BFD_RELOC_386_PLT32 : BFD_RELOC_32_PCREL);
2597 break;
2598 }
2599 frag_wane (fragP);
2600 }
2601 return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
2602} /* md_estimate_size_before_relax() */
2603
2604/*
2605 * md_convert_frag();
2606 *
2607 * Called after relax() is finished.
2608 * In: Address of frag.
2609 * fr_type == rs_machine_dependent.
2610 * fr_subtype is what the address relaxed to.
2611 *
2612 * Out: Any fixSs and constants are set up.
2613 * Caller will turn frag into a ".space 0".
2614 */
2615#ifndef BFD_ASSEMBLER
2616void
2617md_convert_frag (headers, sec, fragP)
2618 object_headers *headers;
2619 segT sec;
2620 register fragS *fragP;
2621#else
2622void
2623md_convert_frag (abfd, sec, fragP)
2624 bfd *abfd;
2625 segT sec;
2626 register fragS *fragP;
2627#endif
2628{
2629 register unsigned char *opcode;
2630 unsigned char *where_to_put_displacement = NULL;
2631 unsigned int target_address;
2632 unsigned int opcode_address;
2633 unsigned int extension = 0;
2634 int displacement_from_opcode_start;
2635
2636 opcode = (unsigned char *) fragP->fr_opcode;
2637
2638 /* Address we want to reach in file space. */
2639 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
2640#ifdef BFD_ASSEMBLER /* not needed otherwise? */
2641 target_address += fragP->fr_symbol->sy_frag->fr_address;
2642#endif
2643
2644 /* Address opcode resides at in file space. */
2645 opcode_address = fragP->fr_address + fragP->fr_fix;
2646
2647 /* Displacement from opcode start to fill into instruction. */
2648 displacement_from_opcode_start = target_address - opcode_address;
2649
2650 switch (fragP->fr_subtype)
2651 {
2652 case ENCODE_RELAX_STATE (COND_JUMP, BYTE):
2653 case ENCODE_RELAX_STATE (UNCOND_JUMP, BYTE):
2654 /* don't have to change opcode */
2655 extension = 1; /* 1 opcode + 1 displacement */
2656 where_to_put_displacement = &opcode[1];
2657 break;
2658
2659 case ENCODE_RELAX_STATE (COND_JUMP, WORD):
2660 opcode[1] = TWO_BYTE_OPCODE_ESCAPE;
2661 opcode[2] = opcode[0] + 0x10;
2662 opcode[0] = WORD_PREFIX_OPCODE;
2663 extension = 4; /* 3 opcode + 2 displacement */
2664 where_to_put_displacement = &opcode[3];
2665 break;
2666
2667 case ENCODE_RELAX_STATE (UNCOND_JUMP, WORD):
2668 opcode[1] = 0xe9;
2669 opcode[0] = WORD_PREFIX_OPCODE;
2670 extension = 3; /* 2 opcode + 2 displacement */
2671 where_to_put_displacement = &opcode[2];
2672 break;
2673
2674 case ENCODE_RELAX_STATE (COND_JUMP, DWORD):
2675 opcode[1] = opcode[0] + 0x10;
2676 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
2677 extension = 5; /* 2 opcode + 4 displacement */
2678 where_to_put_displacement = &opcode[2];
2679 break;
2680
2681 case ENCODE_RELAX_STATE (UNCOND_JUMP, DWORD):
2682 opcode[0] = 0xe9;
2683 extension = 4; /* 1 opcode + 4 displacement */
2684 where_to_put_displacement = &opcode[1];
2685 break;
2686
2687 default:
2688 BAD_CASE (fragP->fr_subtype);
2689 break;
2690 }
2691 /* now put displacement after opcode */
2692 md_number_to_chars ((char *) where_to_put_displacement,
2693 (valueT) (displacement_from_opcode_start - extension),
2694 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
2695 fragP->fr_fix += extension;
2696}
2697
2698
2699int md_short_jump_size = 2; /* size of byte displacement jmp */
2700int md_long_jump_size = 5; /* size of dword displacement jmp */
2701const int md_reloc_size = 8; /* Size of relocation record */
2702
2703void
2704md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
2705 char *ptr;
2706 addressT from_addr, to_addr;
2707 fragS *frag;
2708 symbolS *to_symbol;
2709{
2710 long offset;
2711
2712 offset = to_addr - (from_addr + 2);
2713 md_number_to_chars (ptr, (valueT) 0xeb, 1); /* opcode for byte-disp jump */
2714 md_number_to_chars (ptr + 1, (valueT) offset, 1);
2715}
2716
2717void
2718md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
2719 char *ptr;
2720 addressT from_addr, to_addr;
2721 fragS *frag;
2722 symbolS *to_symbol;
2723{
2724 long offset;
2725
2726 if (flag_do_long_jump)
2727 {
2728 offset = to_addr - S_GET_VALUE (to_symbol);
2729 md_number_to_chars (ptr, (valueT) 0xe9, 1);/* opcode for long jmp */
2730 md_number_to_chars (ptr + 1, (valueT) offset, 4);
2731 fix_new (frag, (ptr + 1) - frag->fr_literal, 4,
2732 to_symbol, (offsetT) 0, 0, BFD_RELOC_32);
2733 }
2734 else
2735 {
2736 offset = to_addr - (from_addr + 5);
2737 md_number_to_chars (ptr, (valueT) 0xe9, 1);
2738 md_number_to_chars (ptr + 1, (valueT) offset, 4);
2739 }
2740}
2741
2742/* Apply a fixup (fixS) to segment data, once it has been determined
2743 by our caller that we have all the info we need to fix it up.
2744
2745 On the 386, immediates, displacements, and data pointers are all in
2746 the same (little-endian) format, so we don't need to care about which
2747 we are handling. */
2748
2749int
2750md_apply_fix3 (fixP, valp, seg)
2751 fixS *fixP; /* The fix we're to put in. */
2752 valueT *valp; /* Pointer to the value of the bits. */
2753 segT seg; /* Segment fix is from. */
2754{
2755 register char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
2756 valueT value = *valp;
2757
|
| 2758 if (fixP->fx_r_type == BFD_RELOC_32 && fixP->fx_pcrel)
2759 fixP->fx_r_type = BFD_RELOC_32_PCREL;
2760
|
2686#if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
2687 /*
2688 * This is a hack. There should be a better way to
2689 * handle this.
2690 */
2691 if (fixP->fx_r_type == BFD_RELOC_32_PCREL && fixP->fx_addsy)
2692 {
2693#ifndef OBJ_AOUT
| 2761#if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
2762 /*
2763 * This is a hack. There should be a better way to
2764 * handle this.
2765 */
2766 if (fixP->fx_r_type == BFD_RELOC_32_PCREL && fixP->fx_addsy)
2767 {
2768#ifndef OBJ_AOUT
|
2694 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
| 2769 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
2770 || OUTPUT_FLAVOR == bfd_target_coff_flavour)
|
2695 value += fixP->fx_where + fixP->fx_frag->fr_address;
2696#endif
2697#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2698 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
2699 && (S_GET_SEGMENT (fixP->fx_addsy) == seg
2700 || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0))
2701 {
2702 /* Yes, we add the values in twice. This is because
2703 bfd_perform_relocation subtracts them out again. I think
2704 bfd_perform_relocation is broken, but I don't dare change
2705 it. FIXME. */
2706 value += fixP->fx_where + fixP->fx_frag->fr_address;
2707 }
2708#endif
| 2771 value += fixP->fx_where + fixP->fx_frag->fr_address;
2772#endif
2773#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2774 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
2775 && (S_GET_SEGMENT (fixP->fx_addsy) == seg
2776 || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0))
2777 {
2778 /* Yes, we add the values in twice. This is because
2779 bfd_perform_relocation subtracts them out again. I think
2780 bfd_perform_relocation is broken, but I don't dare change
2781 it. FIXME. */
2782 value += fixP->fx_where + fixP->fx_frag->fr_address;
2783 }
2784#endif
|
| 2785#if defined (OBJ_COFF) && defined (TE_PE)
2786 /* For some reason, the PE format does not store a section
2787 address offset for a PC relative symbol. */
2788 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
2789 value += md_pcrel_from (fixP);
2790#endif
|
2709 }
2710
2711 /* Fix a few things - the dynamic linker expects certain values here,
2712 and we must not dissappoint it. */
2713#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2714 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
2715 && fixP->fx_addsy)
2716 switch(fixP->fx_r_type) {
2717 case BFD_RELOC_386_PLT32:
2718 /* Make the jump instruction point to the address of the operand. At
2719 runtime we merely add the offset to the actual PLT entry. */
2720 value = 0xfffffffc;
2721 break;
2722 case BFD_RELOC_386_GOTPC:
2723/*
2724 * This is tough to explain. We end up with this one if we have
2725 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
2726 * here is to obtain the absolute address of the GOT, and it is strongly
2727 * preferable from a performance point of view to avoid using a runtime
2728 * relocation for this. The actual sequence of instructions often look
2729 * something like:
2730 *
2731 * call .L66
2732 * .L66:
2733 * popl %ebx
2734 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
2735 *
2736 * The call and pop essentially return the absolute address of
2737 * the label .L66 and store it in %ebx. The linker itself will
2738 * ultimately change the first operand of the addl so that %ebx points to
2739 * the GOT, but to keep things simple, the .o file must have this operand
2740 * set so that it generates not the absolute address of .L66, but the
2741 * absolute address of itself. This allows the linker itself simply
2742 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
2743 * added in, and the addend of the relocation is stored in the operand
2744 * field for the instruction itself.
2745 *
2746 * Our job here is to fix the operand so that it would add the correct
2747 * offset so that %ebx would point to itself. The thing that is tricky is
2748 * that .-.L66 will point to the beginning of the instruction, so we need
2749 * to further modify the operand so that it will point to itself.
2750 * There are other cases where you have something like:
2751 *
2752 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
2753 *
2754 * and here no correction would be required. Internally in the assembler
2755 * we treat operands of this form as not being pcrel since the '.' is
2756 * explicitly mentioned, and I wonder whether it would simplify matters
2757 * to do it this way. Who knows. In earlier versions of the PIC patches,
2758 * the pcrel_adjust field was used to store the correction, but since the
2759 * expression is not pcrel, I felt it would be confusing to do it this way.
2760 */
2761 value -= 1;
2762 break;
2763 case BFD_RELOC_386_GOT32:
2764 value = 0; /* Fully resolved at runtime. No addend. */
2765 break;
2766 case BFD_RELOC_386_GOTOFF:
2767 break;
2768
2769 default:
2770 break;
2771 }
2772#endif
2773
2774#endif
2775 md_number_to_chars (p, value, fixP->fx_size);
2776
2777 return 1;
2778}
2779
2780#if 0
2781/* This is never used. */
2782long /* Knows about the byte order in a word. */
2783md_chars_to_number (con, nbytes)
2784 unsigned char con[]; /* Low order byte 1st. */
2785 int nbytes; /* Number of bytes in the input. */
2786{
2787 long retval;
2788 for (retval = 0, con += nbytes - 1; nbytes--; con--)
2789 {
2790 retval <<= BITS_PER_CHAR;
2791 retval |= *con;
2792 }
2793 return retval;
2794}
2795#endif /* 0 */
2796
2797
2798#define MAX_LITTLENUMS 6
2799
2800/* Turn the string pointed to by litP into a floating point constant of type
2801 type, and emit the appropriate bytes. The number of LITTLENUMS emitted
2802 is stored in *sizeP . An error message is returned, or NULL on OK. */
2803char *
2804md_atof (type, litP, sizeP)
2805 char type;
2806 char *litP;
2807 int *sizeP;
2808{
2809 int prec;
2810 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2811 LITTLENUM_TYPE *wordP;
2812 char *t;
2813
2814 switch (type)
2815 {
2816 case 'f':
2817 case 'F':
2818 prec = 2;
2819 break;
2820
2821 case 'd':
2822 case 'D':
2823 prec = 4;
2824 break;
2825
2826 case 'x':
2827 case 'X':
2828 prec = 5;
2829 break;
2830
2831 default:
2832 *sizeP = 0;
2833 return "Bad call to md_atof ()";
2834 }
2835 t = atof_ieee (input_line_pointer, type, words);
2836 if (t)
2837 input_line_pointer = t;
2838
2839 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2840 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
2841 the bigendian 386. */
2842 for (wordP = words + prec - 1; prec--;)
2843 {
2844 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
2845 litP += sizeof (LITTLENUM_TYPE);
2846 }
2847 return 0;
2848}
2849
2850char output_invalid_buf[8];
2851
2852static char *
2853output_invalid (c)
2854 char c;
2855{
2856 if (isprint (c))
2857 sprintf (output_invalid_buf, "'%c'", c);
2858 else
2859 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
2860 return output_invalid_buf;
2861}
2862
2863/* reg_string starts *before* REGISTER_PREFIX */
2864static reg_entry *
2865parse_register (reg_string)
2866 char *reg_string;
2867{
2868 register char *s = reg_string;
2869 register char *p;
2870 char reg_name_given[MAX_REG_NAME_SIZE];
2871
2872 s++; /* skip REGISTER_PREFIX */
2873 for (p = reg_name_given; is_register_char (*s); p++, s++)
2874 {
2875 *p = register_chars[(unsigned char) *s];
2876 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
2877 return (reg_entry *) 0;
2878 }
2879 *p = '\0';
2880 return (reg_entry *) hash_find (reg_hash, reg_name_given);
2881}
2882
2883#ifdef OBJ_ELF
2884CONST char *md_shortopts = "kmVQ:";
2885#else
2886CONST char *md_shortopts = "m";
2887#endif
2888struct option md_longopts[] = {
2889 {NULL, no_argument, NULL, 0}
2890};
2891size_t md_longopts_size = sizeof(md_longopts);
2892
2893int
2894md_parse_option (c, arg)
2895 int c;
2896 char *arg;
2897{
2898 switch (c)
2899 {
2900 case 'm':
2901 flag_do_long_jump = 1;
2902 break;
2903
2904#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2905 /* -k: Ignore for FreeBSD compatibility. */
2906 case 'k':
2907 break;
2908
2909 /* -V: SVR4 argument to print version ID. */
2910 case 'V':
2911 print_version_id ();
2912 break;
2913
2914 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
2915 should be emitted or not. FIXME: Not implemented. */
2916 case 'Q':
2917 break;
2918#endif
2919
2920 default:
2921 return 0;
2922 }
2923 return 1;
2924}
2925
2926void
2927md_show_usage (stream)
2928 FILE *stream;
2929{
2930 fprintf (stream, "\
2931-m do long jump\n");
2932}
2933
2934#ifdef BFD_ASSEMBLER
2935#ifdef OBJ_MAYBE_ELF
2936#ifdef OBJ_MAYBE_COFF
2937
2938/* Pick the target format to use. */
2939
2940const char *
2941i386_target_format ()
2942{
2943 switch (OUTPUT_FLAVOR)
2944 {
2945 case bfd_target_coff_flavour:
2946 return "coff-i386";
2947 case bfd_target_elf_flavour:
2948 return "elf32-i386";
2949 default:
2950 abort ();
2951 return NULL;
2952 }
2953}
2954
2955#endif /* OBJ_MAYBE_COFF */
2956#endif /* OBJ_MAYBE_ELF */
2957#endif /* BFD_ASSEMBLER */
2958
2959/* ARGSUSED */
2960symbolS *
2961md_undefined_symbol (name)
2962 char *name;
2963{
2964 if (*name == '_' && *(name+1) == 'G'
2965 && strcmp(name, GLOBAL_OFFSET_TABLE_NAME) == 0)
2966 {
2967 if(!GOT_symbol)
2968 {
2969 if(symbol_find(name))
2970 as_bad("GOT already in symbol table");
2971 GOT_symbol = symbol_new (name, undefined_section,
2972 (valueT) 0, &zero_address_frag);
2973 };
2974 return GOT_symbol;
2975 }
2976 return 0;
2977}
2978
2979/* Round up a section size to the appropriate boundary. */
2980valueT
2981md_section_align (segment, size)
2982 segT segment;
2983 valueT size;
2984{
2985#ifdef OBJ_AOUT
2986#ifdef BFD_ASSEMBLER
2987 /* For a.out, force the section size to be aligned. If we don't do
2988 this, BFD will align it for us, but it will not write out the
2989 final bytes of the section. This may be a bug in BFD, but it is
2990 easier to fix it here since that is how the other a.out targets
2991 work. */
2992 int align;
2993
2994 align = bfd_get_section_alignment (stdoutput, segment);
2995 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
2996#endif
2997#endif
2998
2999 return size;
3000}
3001
3002/* Exactly what point is a PC-relative offset relative TO? On the
3003 i386, they're relative to the address of the offset, plus its
3004 size. (??? Is this right? FIXME-SOON!) */
3005long
3006md_pcrel_from (fixP)
3007 fixS *fixP;
3008{
3009 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
3010}
3011
3012#ifndef I386COFF
3013
3014static void
3015s_bss (ignore)
3016 int ignore;
3017{
3018 register int temp;
3019
3020 temp = get_absolute_expression ();
3021 subseg_set (bss_section, (subsegT) temp);
3022 demand_empty_rest_of_line ();
3023}
3024
3025#endif
3026
3027
3028#ifdef BFD_ASSEMBLER
3029
3030void
3031i386_validate_fix (fixp)
3032 fixS *fixp;
3033{
3034 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
3035 {
3036 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
3037 fixp->fx_subsy = 0;
3038 }
3039}
3040
3041#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
3042#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
3043
3044arelent *
3045tc_gen_reloc (section, fixp)
3046 asection *section;
3047 fixS *fixp;
3048{
3049 arelent *rel;
3050 bfd_reloc_code_real_type code;
3051
3052 switch(fixp->fx_r_type)
3053 {
3054 case BFD_RELOC_386_PLT32:
3055 case BFD_RELOC_386_GOT32:
3056 case BFD_RELOC_386_GOTOFF:
3057 case BFD_RELOC_386_GOTPC:
| 2791 }
2792
2793 /* Fix a few things - the dynamic linker expects certain values here,
2794 and we must not dissappoint it. */
2795#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2796 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
2797 && fixP->fx_addsy)
2798 switch(fixP->fx_r_type) {
2799 case BFD_RELOC_386_PLT32:
2800 /* Make the jump instruction point to the address of the operand. At
2801 runtime we merely add the offset to the actual PLT entry. */
2802 value = 0xfffffffc;
2803 break;
2804 case BFD_RELOC_386_GOTPC:
2805/*
2806 * This is tough to explain. We end up with this one if we have
2807 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
2808 * here is to obtain the absolute address of the GOT, and it is strongly
2809 * preferable from a performance point of view to avoid using a runtime
2810 * relocation for this. The actual sequence of instructions often look
2811 * something like:
2812 *
2813 * call .L66
2814 * .L66:
2815 * popl %ebx
2816 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
2817 *
2818 * The call and pop essentially return the absolute address of
2819 * the label .L66 and store it in %ebx. The linker itself will
2820 * ultimately change the first operand of the addl so that %ebx points to
2821 * the GOT, but to keep things simple, the .o file must have this operand
2822 * set so that it generates not the absolute address of .L66, but the
2823 * absolute address of itself. This allows the linker itself simply
2824 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
2825 * added in, and the addend of the relocation is stored in the operand
2826 * field for the instruction itself.
2827 *
2828 * Our job here is to fix the operand so that it would add the correct
2829 * offset so that %ebx would point to itself. The thing that is tricky is
2830 * that .-.L66 will point to the beginning of the instruction, so we need
2831 * to further modify the operand so that it will point to itself.
2832 * There are other cases where you have something like:
2833 *
2834 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
2835 *
2836 * and here no correction would be required. Internally in the assembler
2837 * we treat operands of this form as not being pcrel since the '.' is
2838 * explicitly mentioned, and I wonder whether it would simplify matters
2839 * to do it this way. Who knows. In earlier versions of the PIC patches,
2840 * the pcrel_adjust field was used to store the correction, but since the
2841 * expression is not pcrel, I felt it would be confusing to do it this way.
2842 */
2843 value -= 1;
2844 break;
2845 case BFD_RELOC_386_GOT32:
2846 value = 0; /* Fully resolved at runtime. No addend. */
2847 break;
2848 case BFD_RELOC_386_GOTOFF:
2849 break;
2850
2851 default:
2852 break;
2853 }
2854#endif
2855
2856#endif
2857 md_number_to_chars (p, value, fixP->fx_size);
2858
2859 return 1;
2860}
2861
2862#if 0
2863/* This is never used. */
2864long /* Knows about the byte order in a word. */
2865md_chars_to_number (con, nbytes)
2866 unsigned char con[]; /* Low order byte 1st. */
2867 int nbytes; /* Number of bytes in the input. */
2868{
2869 long retval;
2870 for (retval = 0, con += nbytes - 1; nbytes--; con--)
2871 {
2872 retval <<= BITS_PER_CHAR;
2873 retval |= *con;
2874 }
2875 return retval;
2876}
2877#endif /* 0 */
2878
2879
2880#define MAX_LITTLENUMS 6
2881
2882/* Turn the string pointed to by litP into a floating point constant of type
2883 type, and emit the appropriate bytes. The number of LITTLENUMS emitted
2884 is stored in *sizeP . An error message is returned, or NULL on OK. */
2885char *
2886md_atof (type, litP, sizeP)
2887 char type;
2888 char *litP;
2889 int *sizeP;
2890{
2891 int prec;
2892 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2893 LITTLENUM_TYPE *wordP;
2894 char *t;
2895
2896 switch (type)
2897 {
2898 case 'f':
2899 case 'F':
2900 prec = 2;
2901 break;
2902
2903 case 'd':
2904 case 'D':
2905 prec = 4;
2906 break;
2907
2908 case 'x':
2909 case 'X':
2910 prec = 5;
2911 break;
2912
2913 default:
2914 *sizeP = 0;
2915 return "Bad call to md_atof ()";
2916 }
2917 t = atof_ieee (input_line_pointer, type, words);
2918 if (t)
2919 input_line_pointer = t;
2920
2921 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2922 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
2923 the bigendian 386. */
2924 for (wordP = words + prec - 1; prec--;)
2925 {
2926 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
2927 litP += sizeof (LITTLENUM_TYPE);
2928 }
2929 return 0;
2930}
2931
2932char output_invalid_buf[8];
2933
2934static char *
2935output_invalid (c)
2936 char c;
2937{
2938 if (isprint (c))
2939 sprintf (output_invalid_buf, "'%c'", c);
2940 else
2941 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
2942 return output_invalid_buf;
2943}
2944
2945/* reg_string starts *before* REGISTER_PREFIX */
2946static reg_entry *
2947parse_register (reg_string)
2948 char *reg_string;
2949{
2950 register char *s = reg_string;
2951 register char *p;
2952 char reg_name_given[MAX_REG_NAME_SIZE];
2953
2954 s++; /* skip REGISTER_PREFIX */
2955 for (p = reg_name_given; is_register_char (*s); p++, s++)
2956 {
2957 *p = register_chars[(unsigned char) *s];
2958 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
2959 return (reg_entry *) 0;
2960 }
2961 *p = '\0';
2962 return (reg_entry *) hash_find (reg_hash, reg_name_given);
2963}
2964
2965#ifdef OBJ_ELF
2966CONST char *md_shortopts = "kmVQ:";
2967#else
2968CONST char *md_shortopts = "m";
2969#endif
2970struct option md_longopts[] = {
2971 {NULL, no_argument, NULL, 0}
2972};
2973size_t md_longopts_size = sizeof(md_longopts);
2974
2975int
2976md_parse_option (c, arg)
2977 int c;
2978 char *arg;
2979{
2980 switch (c)
2981 {
2982 case 'm':
2983 flag_do_long_jump = 1;
2984 break;
2985
2986#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2987 /* -k: Ignore for FreeBSD compatibility. */
2988 case 'k':
2989 break;
2990
2991 /* -V: SVR4 argument to print version ID. */
2992 case 'V':
2993 print_version_id ();
2994 break;
2995
2996 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
2997 should be emitted or not. FIXME: Not implemented. */
2998 case 'Q':
2999 break;
3000#endif
3001
3002 default:
3003 return 0;
3004 }
3005 return 1;
3006}
3007
3008void
3009md_show_usage (stream)
3010 FILE *stream;
3011{
3012 fprintf (stream, "\
3013-m do long jump\n");
3014}
3015
3016#ifdef BFD_ASSEMBLER
3017#ifdef OBJ_MAYBE_ELF
3018#ifdef OBJ_MAYBE_COFF
3019
3020/* Pick the target format to use. */
3021
3022const char *
3023i386_target_format ()
3024{
3025 switch (OUTPUT_FLAVOR)
3026 {
3027 case bfd_target_coff_flavour:
3028 return "coff-i386";
3029 case bfd_target_elf_flavour:
3030 return "elf32-i386";
3031 default:
3032 abort ();
3033 return NULL;
3034 }
3035}
3036
3037#endif /* OBJ_MAYBE_COFF */
3038#endif /* OBJ_MAYBE_ELF */
3039#endif /* BFD_ASSEMBLER */
3040
3041/* ARGSUSED */
3042symbolS *
3043md_undefined_symbol (name)
3044 char *name;
3045{
3046 if (*name == '_' && *(name+1) == 'G'
3047 && strcmp(name, GLOBAL_OFFSET_TABLE_NAME) == 0)
3048 {
3049 if(!GOT_symbol)
3050 {
3051 if(symbol_find(name))
3052 as_bad("GOT already in symbol table");
3053 GOT_symbol = symbol_new (name, undefined_section,
3054 (valueT) 0, &zero_address_frag);
3055 };
3056 return GOT_symbol;
3057 }
3058 return 0;
3059}
3060
3061/* Round up a section size to the appropriate boundary. */
3062valueT
3063md_section_align (segment, size)
3064 segT segment;
3065 valueT size;
3066{
3067#ifdef OBJ_AOUT
3068#ifdef BFD_ASSEMBLER
3069 /* For a.out, force the section size to be aligned. If we don't do
3070 this, BFD will align it for us, but it will not write out the
3071 final bytes of the section. This may be a bug in BFD, but it is
3072 easier to fix it here since that is how the other a.out targets
3073 work. */
3074 int align;
3075
3076 align = bfd_get_section_alignment (stdoutput, segment);
3077 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
3078#endif
3079#endif
3080
3081 return size;
3082}
3083
3084/* Exactly what point is a PC-relative offset relative TO? On the
3085 i386, they're relative to the address of the offset, plus its
3086 size. (??? Is this right? FIXME-SOON!) */
3087long
3088md_pcrel_from (fixP)
3089 fixS *fixP;
3090{
3091 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
3092}
3093
3094#ifndef I386COFF
3095
3096static void
3097s_bss (ignore)
3098 int ignore;
3099{
3100 register int temp;
3101
3102 temp = get_absolute_expression ();
3103 subseg_set (bss_section, (subsegT) temp);
3104 demand_empty_rest_of_line ();
3105}
3106
3107#endif
3108
3109
3110#ifdef BFD_ASSEMBLER
3111
3112void
3113i386_validate_fix (fixp)
3114 fixS *fixp;
3115{
3116 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
3117 {
3118 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
3119 fixp->fx_subsy = 0;
3120 }
3121}
3122
3123#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
3124#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
3125
3126arelent *
3127tc_gen_reloc (section, fixp)
3128 asection *section;
3129 fixS *fixp;
3130{
3131 arelent *rel;
3132 bfd_reloc_code_real_type code;
3133
3134 switch(fixp->fx_r_type)
3135 {
3136 case BFD_RELOC_386_PLT32:
3137 case BFD_RELOC_386_GOT32:
3138 case BFD_RELOC_386_GOTOFF:
3139 case BFD_RELOC_386_GOTPC:
|
| 3140 case BFD_RELOC_RVA:
|
3058 code = fixp->fx_r_type;
3059 break;
3060 default:
3061 switch (F (fixp->fx_size, fixp->fx_pcrel))
3062 {
3063 MAP (1, 0, BFD_RELOC_8);
3064 MAP (2, 0, BFD_RELOC_16);
3065 MAP (4, 0, BFD_RELOC_32);
3066 MAP (1, 1, BFD_RELOC_8_PCREL);
3067 MAP (2, 1, BFD_RELOC_16_PCREL);
3068 MAP (4, 1, BFD_RELOC_32_PCREL);
3069 default:
3070 as_bad ("Can not do %d byte %srelocation", fixp->fx_size,
3071 fixp->fx_pcrel ? "pc-relative " : "");
3072 }
3073 }
3074#undef MAP
3075#undef F
3076
3077 if (code == BFD_RELOC_32
3078 && GOT_symbol
3079 && fixp->fx_addsy == GOT_symbol)
3080 code = BFD_RELOC_386_GOTPC;
3081
3082 rel = (arelent *) xmalloc (sizeof (arelent));
3083 rel->sym_ptr_ptr = &fixp->fx_addsy->bsym;
3084 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
3085 if (fixp->fx_pcrel)
3086 rel->addend = fixp->fx_addnumber;
3087 else
3088 rel->addend = 0;
3089
3090 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
3091 if (rel->howto == NULL)
3092 {
3093 as_bad_where (fixp->fx_file, fixp->fx_line,
3094 "Cannot represent relocation type %s",
3095 bfd_get_reloc_code_name (code));
3096 /* Set howto to a garbage value so that we can keep going. */
3097 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
3098 assert (rel->howto != NULL);
3099 }
3100
3101 return rel;
3102}
3103
3104#else /* ! BFD_ASSEMBLER */
3105
3106#if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
3107void
3108tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
3109 char *where;
3110 fixS *fixP;
3111 relax_addressT segment_address_in_file;
3112{
3113 /*
3114 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3115 * Out: GNU LD relocation length code: 0, 1, or 2.
3116 */
3117
3118 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
3119 long r_symbolnum;
3120
3121 know (fixP->fx_addsy != NULL);
3122
3123 md_number_to_chars (where,
3124 (valueT) (fixP->fx_frag->fr_address
3125 + fixP->fx_where - segment_address_in_file),
3126 4);
3127
3128 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
3129 ? S_GET_TYPE (fixP->fx_addsy)
3130 : fixP->fx_addsy->sy_number);
3131
3132 where[6] = (r_symbolnum >> 16) & 0x0ff;
3133 where[5] = (r_symbolnum >> 8) & 0x0ff;
3134 where[4] = r_symbolnum & 0x0ff;
3135 where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08)
3136 | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06)
3137 | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f));
3138}
3139
3140#endif /* OBJ_AOUT or OBJ_BOUT */
3141
3142#if defined (I386COFF)
3143
3144short
3145tc_coff_fix2rtype (fixP)
3146 fixS *fixP;
3147{
3148 if (fixP->fx_r_type == R_IMAGEBASE)
3149 return R_IMAGEBASE;
3150
3151 return (fixP->fx_pcrel ?
3152 (fixP->fx_size == 1 ? R_PCRBYTE :
3153 fixP->fx_size == 2 ? R_PCRWORD :
3154 R_PCRLONG) :
3155 (fixP->fx_size == 1 ? R_RELBYTE :
3156 fixP->fx_size == 2 ? R_RELWORD :
3157 R_DIR32));
3158}
3159
3160int
3161tc_coff_sizemachdep (frag)
3162 fragS *frag;
3163{
3164 if (frag->fr_next)
3165 return (frag->fr_next->fr_address - frag->fr_address);
3166 else
3167 return 0;
3168}
3169
3170#endif /* I386COFF */
3171
3172#endif /* BFD_ASSEMBLER? */
3173
3174/* end of tc-i386.c */
| 3141 code = fixp->fx_r_type;
3142 break;
3143 default:
3144 switch (F (fixp->fx_size, fixp->fx_pcrel))
3145 {
3146 MAP (1, 0, BFD_RELOC_8);
3147 MAP (2, 0, BFD_RELOC_16);
3148 MAP (4, 0, BFD_RELOC_32);
3149 MAP (1, 1, BFD_RELOC_8_PCREL);
3150 MAP (2, 1, BFD_RELOC_16_PCREL);
3151 MAP (4, 1, BFD_RELOC_32_PCREL);
3152 default:
3153 as_bad ("Can not do %d byte %srelocation", fixp->fx_size,
3154 fixp->fx_pcrel ? "pc-relative " : "");
3155 }
3156 }
3157#undef MAP
3158#undef F
3159
3160 if (code == BFD_RELOC_32
3161 && GOT_symbol
3162 && fixp->fx_addsy == GOT_symbol)
3163 code = BFD_RELOC_386_GOTPC;
3164
3165 rel = (arelent *) xmalloc (sizeof (arelent));
3166 rel->sym_ptr_ptr = &fixp->fx_addsy->bsym;
3167 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
3168 if (fixp->fx_pcrel)
3169 rel->addend = fixp->fx_addnumber;
3170 else
3171 rel->addend = 0;
3172
3173 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
3174 if (rel->howto == NULL)
3175 {
3176 as_bad_where (fixp->fx_file, fixp->fx_line,
3177 "Cannot represent relocation type %s",
3178 bfd_get_reloc_code_name (code));
3179 /* Set howto to a garbage value so that we can keep going. */
3180 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
3181 assert (rel->howto != NULL);
3182 }
3183
3184 return rel;
3185}
3186
3187#else /* ! BFD_ASSEMBLER */
3188
3189#if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
3190void
3191tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
3192 char *where;
3193 fixS *fixP;
3194 relax_addressT segment_address_in_file;
3195{
3196 /*
3197 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3198 * Out: GNU LD relocation length code: 0, 1, or 2.
3199 */
3200
3201 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
3202 long r_symbolnum;
3203
3204 know (fixP->fx_addsy != NULL);
3205
3206 md_number_to_chars (where,
3207 (valueT) (fixP->fx_frag->fr_address
3208 + fixP->fx_where - segment_address_in_file),
3209 4);
3210
3211 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
3212 ? S_GET_TYPE (fixP->fx_addsy)
3213 : fixP->fx_addsy->sy_number);
3214
3215 where[6] = (r_symbolnum >> 16) & 0x0ff;
3216 where[5] = (r_symbolnum >> 8) & 0x0ff;
3217 where[4] = r_symbolnum & 0x0ff;
3218 where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08)
3219 | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06)
3220 | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f));
3221}
3222
3223#endif /* OBJ_AOUT or OBJ_BOUT */
3224
3225#if defined (I386COFF)
3226
3227short
3228tc_coff_fix2rtype (fixP)
3229 fixS *fixP;
3230{
3231 if (fixP->fx_r_type == R_IMAGEBASE)
3232 return R_IMAGEBASE;
3233
3234 return (fixP->fx_pcrel ?
3235 (fixP->fx_size == 1 ? R_PCRBYTE :
3236 fixP->fx_size == 2 ? R_PCRWORD :
3237 R_PCRLONG) :
3238 (fixP->fx_size == 1 ? R_RELBYTE :
3239 fixP->fx_size == 2 ? R_RELWORD :
3240 R_DIR32));
3241}
3242
3243int
3244tc_coff_sizemachdep (frag)
3245 fragS *frag;
3246{
3247 if (frag->fr_next)
3248 return (frag->fr_next->fr_address - frag->fr_address);
3249 else
3250 return 0;
3251}
3252
3253#endif /* I386COFF */
3254
3255#endif /* BFD_ASSEMBLER? */
3256
3257/* end of tc-i386.c */
|